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2a709f28fa
* 0day explit mitigation * Memory corruption prevention * Privilege escalation prevention * Buffer over flow prevention * File System corruption defense * Thread escape prevention This may very well be the most intensive inclusion to BrooklynR. This will not be part of an x86 suite nor it will be released as tool kit. The security core toolkit will remain part of kernel base.
70 lines
2.1 KiB
C
70 lines
2.1 KiB
C
/*
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* intel_bxtwc.h - Header file for Intel Broxton Whiskey Cove PMIC
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*
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* Copyright (C) 2015 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/mfd/intel_soc_pmic.h>
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#ifndef __INTEL_BXTWC_H__
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#define __INTEL_BXTWC_H__
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/* BXT WC devices */
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#define BXTWC_DEVICE1_ADDR 0x4E
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#define BXTWC_DEVICE2_ADDR 0x4F
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#define BXTWC_DEVICE3_ADDR 0x5E
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/* device1 Registers */
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#define BXTWC_CHIPID 0x4E00
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#define BXTWC_CHIPVER 0x4E01
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#define BXTWC_SCHGRIRQ0_ADDR 0x5E1A
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#define BXTWC_CHGRCTRL0_ADDR 0x5E16
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#define BXTWC_CHGRCTRL1_ADDR 0x5E17
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#define BXTWC_CHGRCTRL2_ADDR 0x5E18
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#define BXTWC_CHGRSTATUS_ADDR 0x5E19
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#define BXTWC_THRMBATZONE_ADDR 0x4F22
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#define BXTWC_USBPATH_ADDR 0x5E19
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#define BXTWC_USBPHYCTRL_ADDR 0x5E07
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#define BXTWC_USBIDCTRL_ADDR 0x5E05
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#define BXTWC_USBIDEN_MASK 0x01
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#define BXTWC_USBIDSTAT_ADDR 0x00FF
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#define BXTWC_USBSRCDETSTATUS_ADDR 0x5E29
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#define BXTWC_DBGUSBBC1_ADDR 0x5FE0
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#define BXTWC_DBGUSBBC2_ADDR 0x5FE1
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#define BXTWC_DBGUSBBCSTAT_ADDR 0x5FE2
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#define BXTWC_WAKESRC_ADDR 0x4E22
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#define BXTWC_WAKESRC2_ADDR 0x4EE5
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#define BXTWC_CHRTTADDR_ADDR 0x5E22
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#define BXTWC_CHRTTDATA_ADDR 0x5E23
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#define BXTWC_STHRMIRQ0_ADDR 0x4F19
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#define WC_MTHRMIRQ1_ADDR 0x4E12
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#define WC_STHRMIRQ1_ADDR 0x4F1A
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#define WC_STHRMIRQ2_ADDR 0x4F1B
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#define BXTWC_THRMZN0H_ADDR 0x4F44
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#define BXTWC_THRMZN0L_ADDR 0x4F45
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#define BXTWC_THRMZN1H_ADDR 0x4F46
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#define BXTWC_THRMZN1L_ADDR 0x4F47
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#define BXTWC_THRMZN2H_ADDR 0x4F48
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#define BXTWC_THRMZN2L_ADDR 0x4F49
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#define BXTWC_THRMZN3H_ADDR 0x4F4A
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#define BXTWC_THRMZN3L_ADDR 0x4F4B
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#define BXTWC_THRMZN4H_ADDR 0x4F4C
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#define BXTWC_THRMZN4L_ADDR 0x4F4D
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#endif
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