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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
44 lines
881 B
C
44 lines
881 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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*
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* Microchip PolarFire SoC (MPFS)
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*
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* Copyright (c) 2020 Microchip Corporation. All rights reserved.
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*
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* Author: Conor Dooley <conor.dooley@microchip.com>
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*
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*/
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#ifndef __SOC_MPFS_H__
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#define __SOC_MPFS_H__
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#include <linux/types.h>
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#include <linux/of_device.h>
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struct mpfs_sys_controller;
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struct mpfs_mss_msg {
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u8 cmd_opcode;
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u16 cmd_data_size;
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struct mpfs_mss_response *response;
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u8 *cmd_data;
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u16 mbox_offset;
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u16 resp_offset;
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};
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struct mpfs_mss_response {
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u32 resp_status;
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u32 *resp_msg;
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u16 resp_size;
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};
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#if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL)
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int mpfs_blocking_transaction(struct mpfs_sys_controller *mpfs_client, struct mpfs_mss_msg *msg);
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struct mpfs_sys_controller *mpfs_sys_controller_get(struct device *dev);
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#endif /* if IS_ENABLED(CONFIG_POLARFIRE_SOC_SYS_CTRL) */
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#endif /* __SOC_MPFS_H__ */
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