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https://github.com/Qortal/Brooklyn.git
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334 lines
9.4 KiB
C
334 lines
9.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Clock Driver for HiFiBerry DAC+ HD
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*
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* Author: Joerg Schambacher, i2Audio GmbH for HiFiBerry
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* Copyright 2020
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/clk.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/slab.h>
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#include <linux/platform_device.h>
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#include <linux/i2c.h>
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#include <linux/regmap.h>
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#define NO_PLL_RESET 0
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#define PLL_RESET 1
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#define HIFIBERRY_PLL_MAX_REGISTER 256
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#define DEFAULT_RATE 44100
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static struct reg_default hifiberry_pll_reg_defaults[] = {
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{0x02, 0x53}, {0x03, 0x00}, {0x07, 0x20}, {0x0F, 0x00},
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{0x10, 0x0D}, {0x11, 0x1D}, {0x12, 0x0D}, {0x13, 0x8C},
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{0x14, 0x8C}, {0x15, 0x8C}, {0x16, 0x8C}, {0x17, 0x8C},
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{0x18, 0x2A}, {0x1C, 0x00}, {0x1D, 0x0F}, {0x1F, 0x00},
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{0x2A, 0x00}, {0x2C, 0x00}, {0x2F, 0x00}, {0x30, 0x00},
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{0x31, 0x00}, {0x32, 0x00}, {0x34, 0x00}, {0x37, 0x00},
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{0x38, 0x00}, {0x39, 0x00}, {0x3A, 0x00}, {0x3B, 0x01},
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{0x3E, 0x00}, {0x3F, 0x00}, {0x40, 0x00}, {0x41, 0x00},
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{0x5A, 0x00}, {0x5B, 0x00}, {0x95, 0x00}, {0x96, 0x00},
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{0x97, 0x00}, {0x98, 0x00}, {0x99, 0x00}, {0x9A, 0x00},
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{0x9B, 0x00}, {0xA2, 0x00}, {0xA3, 0x00}, {0xA4, 0x00},
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{0xB7, 0x92},
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{0x1A, 0x3D}, {0x1B, 0x09}, {0x1E, 0xF3}, {0x20, 0x13},
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{0x21, 0x75}, {0x2B, 0x04}, {0x2D, 0x11}, {0x2E, 0xE0},
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{0x3D, 0x7A},
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{0x35, 0x9D}, {0x36, 0x00}, {0x3C, 0x42},
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{ 177, 0xAC},
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};
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static struct reg_default common_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
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static int num_common_pll_regs;
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static struct reg_default dedicated_192k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
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static int num_dedicated_192k_pll_regs;
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static struct reg_default dedicated_96k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
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static int num_dedicated_96k_pll_regs;
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static struct reg_default dedicated_48k_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
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static int num_dedicated_48k_pll_regs;
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static struct reg_default dedicated_176k4_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
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static int num_dedicated_176k4_pll_regs;
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static struct reg_default dedicated_88k2_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
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static int num_dedicated_88k2_pll_regs;
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static struct reg_default dedicated_44k1_pll_regs[HIFIBERRY_PLL_MAX_REGISTER];
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static int num_dedicated_44k1_pll_regs;
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/**
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* struct clk_hifiberry_drvdata - Common struct to the HiFiBerry DAC HD Clk
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* @hw: clk_hw for the common clk framework
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*/
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struct clk_hifiberry_drvdata {
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struct regmap *regmap;
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struct clk *clk;
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struct clk_hw hw;
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unsigned long rate;
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};
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#define to_hifiberry_clk(_hw) \
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container_of(_hw, struct clk_hifiberry_drvdata, hw)
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static int clk_hifiberry_dachd_write_pll_regs(struct regmap *regmap,
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struct reg_default *regs,
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int num, int do_pll_reset)
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{
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int i;
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int ret = 0;
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char pll_soft_reset[] = { 177, 0xAC, };
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for (i = 0; i < num; i++) {
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ret |= regmap_write(regmap, regs[i].reg, regs[i].def);
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if (ret)
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return ret;
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}
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if (do_pll_reset) {
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ret |= regmap_write(regmap, pll_soft_reset[0],
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pll_soft_reset[1]);
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mdelay(10);
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}
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return ret;
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}
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static unsigned long clk_hifiberry_dachd_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return to_hifiberry_clk(hw)->rate;
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}
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static long clk_hifiberry_dachd_round_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long *parent_rate)
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{
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return rate;
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}
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static int clk_hifiberry_dachd_set_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long parent_rate)
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{
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int ret;
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struct clk_hifiberry_drvdata *drvdata = to_hifiberry_clk(hw);
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switch (rate) {
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case 44100:
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ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,
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dedicated_44k1_pll_regs, num_dedicated_44k1_pll_regs,
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PLL_RESET);
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break;
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case 88200:
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ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,
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dedicated_88k2_pll_regs, num_dedicated_88k2_pll_regs,
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PLL_RESET);
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break;
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case 176400:
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ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,
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dedicated_176k4_pll_regs, num_dedicated_176k4_pll_regs,
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PLL_RESET);
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break;
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case 48000:
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ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,
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dedicated_48k_pll_regs, num_dedicated_48k_pll_regs,
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PLL_RESET);
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break;
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case 96000:
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ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,
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dedicated_96k_pll_regs, num_dedicated_96k_pll_regs,
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PLL_RESET);
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break;
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case 192000:
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ret = clk_hifiberry_dachd_write_pll_regs(drvdata->regmap,
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dedicated_192k_pll_regs, num_dedicated_192k_pll_regs,
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PLL_RESET);
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break;
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default:
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ret = -EINVAL;
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break;
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}
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to_hifiberry_clk(hw)->rate = rate;
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return ret;
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}
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const struct clk_ops clk_hifiberry_dachd_rate_ops = {
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.recalc_rate = clk_hifiberry_dachd_recalc_rate,
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.round_rate = clk_hifiberry_dachd_round_rate,
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.set_rate = clk_hifiberry_dachd_set_rate,
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};
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static int clk_hifiberry_get_prop_values(struct device *dev,
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char *prop_name,
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struct reg_default *regs)
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{
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int ret;
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int i;
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u8 tmp[2 * HIFIBERRY_PLL_MAX_REGISTER];
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ret = of_property_read_variable_u8_array(dev->of_node, prop_name,
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tmp, 0, 2 * HIFIBERRY_PLL_MAX_REGISTER);
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if (ret < 0)
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return ret;
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if (ret & 1) {
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dev_err(dev,
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"%s <%s> -> #%i odd number of bytes for reg/val pairs!",
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__func__,
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prop_name,
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ret);
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return -EINVAL;
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}
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ret /= 2;
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for (i = 0; i < ret; i++) {
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regs[i].reg = (u32)tmp[2 * i];
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regs[i].def = (u32)tmp[2 * i + 1];
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}
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return ret;
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}
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static int clk_hifiberry_dachd_dt_parse(struct device *dev)
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{
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num_common_pll_regs = clk_hifiberry_get_prop_values(dev,
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"common_pll_regs", common_pll_regs);
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num_dedicated_44k1_pll_regs = clk_hifiberry_get_prop_values(dev,
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"44k1_pll_regs", dedicated_44k1_pll_regs);
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num_dedicated_88k2_pll_regs = clk_hifiberry_get_prop_values(dev,
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"88k2_pll_regs", dedicated_88k2_pll_regs);
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num_dedicated_176k4_pll_regs = clk_hifiberry_get_prop_values(dev,
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"176k4_pll_regs", dedicated_176k4_pll_regs);
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num_dedicated_48k_pll_regs = clk_hifiberry_get_prop_values(dev,
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"48k_pll_regs", dedicated_48k_pll_regs);
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num_dedicated_96k_pll_regs = clk_hifiberry_get_prop_values(dev,
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"96k_pll_regs", dedicated_96k_pll_regs);
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num_dedicated_192k_pll_regs = clk_hifiberry_get_prop_values(dev,
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"192k_pll_regs", dedicated_192k_pll_regs);
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return 0;
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}
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static int clk_hifiberry_dachd_remove(struct device *dev)
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{
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of_clk_del_provider(dev->of_node);
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return 0;
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}
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const struct regmap_config hifiberry_pll_regmap = {
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.reg_bits = 8,
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.val_bits = 8,
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.max_register = HIFIBERRY_PLL_MAX_REGISTER,
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.reg_defaults = hifiberry_pll_reg_defaults,
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.num_reg_defaults = ARRAY_SIZE(hifiberry_pll_reg_defaults),
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.cache_type = REGCACHE_RBTREE,
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};
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EXPORT_SYMBOL_GPL(hifiberry_pll_regmap);
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static int clk_hifiberry_dachd_i2c_probe(struct i2c_client *i2c,
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const struct i2c_device_id *id)
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{
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struct clk_hifiberry_drvdata *hdclk;
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int ret = 0;
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struct clk_init_data init;
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struct device *dev = &i2c->dev;
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struct device_node *dev_node = dev->of_node;
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struct regmap_config config = hifiberry_pll_regmap;
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hdclk = devm_kzalloc(&i2c->dev,
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sizeof(struct clk_hifiberry_drvdata), GFP_KERNEL);
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if (!hdclk)
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return -ENOMEM;
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i2c_set_clientdata(i2c, hdclk);
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hdclk->regmap = devm_regmap_init_i2c(i2c, &config);
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if (IS_ERR(hdclk->regmap))
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return PTR_ERR(hdclk->regmap);
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/* start PLL to allow detection of DAC */
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ret = clk_hifiberry_dachd_write_pll_regs(hdclk->regmap,
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hifiberry_pll_reg_defaults,
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ARRAY_SIZE(hifiberry_pll_reg_defaults),
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PLL_RESET);
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if (ret)
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return ret;
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clk_hifiberry_dachd_dt_parse(dev);
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/* restart PLL with configs from DTB */
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ret = clk_hifiberry_dachd_write_pll_regs(hdclk->regmap, common_pll_regs,
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num_common_pll_regs, PLL_RESET);
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if (ret)
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return ret;
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init.name = "clk-hifiberry-dachd";
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init.ops = &clk_hifiberry_dachd_rate_ops;
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init.flags = 0;
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init.parent_names = NULL;
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init.num_parents = 0;
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hdclk->hw.init = &init;
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hdclk->clk = devm_clk_register(dev, &hdclk->hw);
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if (IS_ERR(hdclk->clk)) {
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dev_err(dev, "unable to register %s\n", init.name);
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return PTR_ERR(hdclk->clk);
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}
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ret = of_clk_add_provider(dev_node, of_clk_src_simple_get, hdclk->clk);
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if (ret != 0) {
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dev_err(dev, "Cannot of_clk_add_provider");
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return ret;
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}
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ret = clk_set_rate(hdclk->hw.clk, DEFAULT_RATE);
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if (ret != 0) {
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dev_err(dev, "Cannot set rate : %d\n", ret);
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return -EINVAL;
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}
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return ret;
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}
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static int clk_hifiberry_dachd_i2c_remove(struct i2c_client *i2c)
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{
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clk_hifiberry_dachd_remove(&i2c->dev);
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return 0;
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}
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static const struct i2c_device_id clk_hifiberry_dachd_i2c_id[] = {
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{ "dachd-clk", },
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{ }
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};
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MODULE_DEVICE_TABLE(i2c, clk_hifiberry_dachd_i2c_id);
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static const struct of_device_id clk_hifiberry_dachd_of_match[] = {
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{ .compatible = "hifiberry,dachd-clk", },
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{ }
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};
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MODULE_DEVICE_TABLE(of, clk_hifiberry_dachd_of_match);
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static struct i2c_driver clk_hifiberry_dachd_i2c_driver = {
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.probe = clk_hifiberry_dachd_i2c_probe,
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.remove = clk_hifiberry_dachd_i2c_remove,
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.id_table = clk_hifiberry_dachd_i2c_id,
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.driver = {
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.name = "dachd-clk",
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.of_match_table = of_match_ptr(clk_hifiberry_dachd_of_match),
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},
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};
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module_i2c_driver(clk_hifiberry_dachd_i2c_driver);
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MODULE_DESCRIPTION("HiFiBerry DAC+ HD clock driver");
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MODULE_AUTHOR("Joerg Schambacher <joerg@i2audio.com>");
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MODULE_LICENSE("GPL v2");
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MODULE_ALIAS("platform:clk-hifiberry-dachd");
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