mirror of
https://github.com/Qortal/Brooklyn.git
synced 2025-02-15 03:35:55 +00:00
a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
410 lines
20 KiB
JSON
410 lines
20 KiB
JSON
[
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{
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"BriefDescription": "Number of occurrences where a microcode assist is invoked by hardware.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3,4,5,6,7",
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"EventCode": "0xc1",
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"EventName": "ASSISTS.ANY",
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"PEBScounters": "0,1,2,3,4,5,6,7",
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"PublicDescription": "Counts the number of occurrences where a microcode assist is invoked by hardware Examples include AD (page Access Dirty), FP and AVX related assists.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x7"
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},
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{
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"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0x28",
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"EventName": "CORE_POWER.LVL0_TURBO_LICENSE",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.",
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"SampleAfterValue": "200003",
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"Speculative": "1",
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"UMask": "0x7"
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},
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{
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"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0x28",
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"EventName": "CORE_POWER.LVL1_TURBO_LICENSE",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.",
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"SampleAfterValue": "200003",
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"Speculative": "1",
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"UMask": "0x18"
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},
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{
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"BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0x28",
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"EventName": "CORE_POWER.LVL2_TURBO_LICENSE",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchtecture). This includes high current AVX 512-bit instructions.",
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"SampleAfterValue": "200003",
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"Speculative": "1",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10004",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.DEMAND_CODE_RD.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184000004",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184000004",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand data reads that have any type of response.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10001",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand data reads that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.DEMAND_DATA_RD.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184000001",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand data reads that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184000001",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10002",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.DEMAND_RFO.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184000002",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184000002",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10400",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184000400",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184000400",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10010",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184000010",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184000010",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x10020",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.HWPF_L2_RFO.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184000020",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184000020",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.OTHER.ANY_RESPONSE",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x18000",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.OTHER.DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184008000",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
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"SampleAfterValue": "100003",
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"Speculative": "1",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.",
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"CollectPEBSRecord": "2",
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"Counter": "0,1,2,3",
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"EventCode": "0xB7, 0xBB",
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"EventName": "OCR.OTHER.LOCAL_DRAM",
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"MSRIndex": "0x1a6,0x1a7",
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"MSRValue": "0x184008000",
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"Offcore": "1",
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"PEBScounters": "0,1,2,3",
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"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
|
|
"SampleAfterValue": "100003",
|
|
"Speculative": "1",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts streaming stores that have any type of response.",
|
|
"CollectPEBSRecord": "2",
|
|
"Counter": "0,1,2,3",
|
|
"EventCode": "0xB7, 0xBB",
|
|
"EventName": "OCR.STREAMING_WR.ANY_RESPONSE",
|
|
"MSRIndex": "0x1a6,0x1a7",
|
|
"MSRValue": "0x10800",
|
|
"Offcore": "1",
|
|
"PEBScounters": "0,1,2,3",
|
|
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
|
|
"SampleAfterValue": "100003",
|
|
"Speculative": "1",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts streaming stores that DRAM supplied the request.",
|
|
"CollectPEBSRecord": "2",
|
|
"Counter": "0,1,2,3",
|
|
"EventCode": "0xB7, 0xBB",
|
|
"EventName": "OCR.STREAMING_WR.DRAM",
|
|
"MSRIndex": "0x1a6,0x1a7",
|
|
"MSRValue": "0x184000800",
|
|
"Offcore": "1",
|
|
"PEBScounters": "0,1,2,3",
|
|
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
|
|
"SampleAfterValue": "100003",
|
|
"Speculative": "1",
|
|
"UMask": "0x1"
|
|
},
|
|
{
|
|
"BriefDescription": "Counts streaming stores that DRAM supplied the request.",
|
|
"CollectPEBSRecord": "2",
|
|
"Counter": "0,1,2,3",
|
|
"EventCode": "0xB7, 0xBB",
|
|
"EventName": "OCR.STREAMING_WR.LOCAL_DRAM",
|
|
"MSRIndex": "0x1a6,0x1a7",
|
|
"MSRValue": "0x184000800",
|
|
"Offcore": "1",
|
|
"PEBScounters": "0,1,2,3",
|
|
"PublicDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
|
|
"SampleAfterValue": "100003",
|
|
"Speculative": "1",
|
|
"UMask": "0x1"
|
|
}
|
|
] |