Qortal/Brooklyn
3
0
Fork 1
mirror of https://github.com/Qortal/Brooklyn.git synced 2025-02-13 02:35:54 +00:00
Code Issues Projects Releases Wiki Activity
Brooklyn/tools/perf/pmu-events/arch/x86/nehalemep/floating-point.json
crowetic a94b3d14aa Brooklyn+ (PLUS) changes 
Changes included (and more):

1. Dynamic RAM merge

2. Real-time page scan and allocation

3. Cache compression

4. Real-time IRQ checks

5. Dynamic I/O allocation for Java heap

6. Java page migration

7. Contiguous memory allocation

8. Idle pages tracking

9. Per CPU RAM usage tracking

10. ARM NEON scalar multiplication library

11. NEON/ARMv8 crypto extensions

12. NEON SHA, Blake, RIPEMD crypto extensions

13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
2022-05-12 10:47:00 -07:00

229 lines
6.9 KiB
JSON
Raw Blame History

[
{
"BriefDescription": "X87 Floating point assists (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.ALL",
"PEBS": "1",
"SampleAfterValue": "20000",
"UMask": "0x1"
},
{
"BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.INPUT",
"PEBS": "1",
"SampleAfterValue": "20000",
"UMask": "0x4"
},
{
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)",
"Counter": "0,1,2,3",
"EventCode": "0xF7",
"EventName": "FP_ASSIST.OUTPUT",
"PEBS": "1",
"SampleAfterValue": "20000",
"UMask": "0x2"
},
{
"BriefDescription": "MMX Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.MMX",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "SSE2 integer Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
"SampleAfterValue": "2000000",
"UMask": "0x8"
},
{
"BriefDescription": "SSE* FP double precision Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
"SampleAfterValue": "2000000",
"UMask": "0x80"
},
{
"BriefDescription": "SSE and SSE2 FP Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
"SampleAfterValue": "2000000",
"UMask": "0x4"
},
{
"BriefDescription": "SSE FP packed Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
"SampleAfterValue": "2000000",
"UMask": "0x10"
},
{
"BriefDescription": "SSE FP scalar Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
"SampleAfterValue": "2000000",
"UMask": "0x20"
},
{
"BriefDescription": "SSE* FP single precision Uops",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
"SampleAfterValue": "2000000",
"UMask": "0x40"
},
{
"BriefDescription": "Computational floating-point operations executed",
"Counter": "0,1,2,3",
"EventCode": "0x10",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "All Floating Point to and from MMX transitions",
"Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.ANY",
"SampleAfterValue": "2000000",
"UMask": "0x3"
},
{
"BriefDescription": "Transitions from MMX to Floating Point instructions",
"Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_FP",
"SampleAfterValue": "2000000",
"UMask": "0x1"
},
{
"BriefDescription": "Transitions from Floating Point to MMX instructions",
"Counter": "0,1,2,3",
"EventCode": "0xCC",
"EventName": "FP_MMX_TRANS.TO_MMX",
"SampleAfterValue": "2000000",
"UMask": "0x2"
},
{
"BriefDescription": "128 bit SIMD integer pack operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACK",
"SampleAfterValue": "200000",
"UMask": "0x4"
},
{
"BriefDescription": "128 bit SIMD integer arithmetic operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_ARITH",
"SampleAfterValue": "200000",
"UMask": "0x20"
},
{
"BriefDescription": "128 bit SIMD integer logical operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
"SampleAfterValue": "200000",
"UMask": "0x10"
},
{
"BriefDescription": "128 bit SIMD integer multiply operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_MPY",
"SampleAfterValue": "200000",
"UMask": "0x1"
},
{
"BriefDescription": "128 bit SIMD integer shift operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.PACKED_SHIFT",
"SampleAfterValue": "200000",
"UMask": "0x2"
},
{
"BriefDescription": "128 bit SIMD integer shuffle/move operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
"UMask": "0x40"
},
{
"BriefDescription": "128 bit SIMD integer unpack operations",
"Counter": "0,1,2,3",
"EventCode": "0x12",
"EventName": "SIMD_INT_128.UNPACK",
"SampleAfterValue": "200000",
"UMask": "0x8"
},
{
"BriefDescription": "SIMD integer 64 bit pack operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACK",
"SampleAfterValue": "200000",
"UMask": "0x4"
},
{
"BriefDescription": "SIMD integer 64 bit arithmetic operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_ARITH",
"SampleAfterValue": "200000",
"UMask": "0x20"
},
{
"BriefDescription": "SIMD integer 64 bit logical operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
"SampleAfterValue": "200000",
"UMask": "0x10"
},
{
"BriefDescription": "SIMD integer 64 bit packed multiply operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_MPY",
"SampleAfterValue": "200000",
"UMask": "0x1"
},
{
"BriefDescription": "SIMD integer 64 bit shift operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.PACKED_SHIFT",
"SampleAfterValue": "200000",
"UMask": "0x2"
},
{
"BriefDescription": "SIMD integer 64 bit shuffle/move operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
"UMask": "0x40"
},
{
"BriefDescription": "SIMD integer 64 bit unpack operations",
"Counter": "0,1,2,3",
"EventCode": "0xFD",
"EventName": "SIMD_INT_64.UNPACK",
"SampleAfterValue": "200000",
"UMask": "0x8"
}
]
Reference in New Issue View Git Blame Copy Permalink