mirror of
https://github.com/Qortal/Brooklyn.git
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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
173 lines
5.1 KiB
JSON
173 lines
5.1 KiB
JSON
[
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{
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"BriefDescription": "DTLB load misses",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.ANY",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "DTLB load miss large page walks",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
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"SampleAfterValue": "200000",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "DTLB load miss caused by low part of address",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
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"SampleAfterValue": "200000",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "DTLB second level hit",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
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"SampleAfterValue": "2000000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "DTLB load miss page walks complete",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "DTLB load miss page walk cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x8",
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"EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
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"SampleAfterValue": "200000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "DTLB misses",
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"Counter": "0,1,2,3",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.ANY",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "DTLB miss large page walks",
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"Counter": "0,1,2,3",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
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"SampleAfterValue": "200000",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "DTLB misses caused by low part of address. Count also includes 2M page references because 2M pages do not use the PDE.",
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"Counter": "0,1,2,3",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.PDE_MISS",
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"SampleAfterValue": "200000",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "DTLB first level misses but second level hit",
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"Counter": "0,1,2,3",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.STLB_HIT",
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"SampleAfterValue": "200000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "DTLB miss page walks",
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"Counter": "0,1,2,3",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "DTLB miss page walk cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x49",
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"EventName": "DTLB_MISSES.WALK_CYCLES",
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"SampleAfterValue": "2000000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Extended Page Table walk cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x4F",
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"EventName": "EPT.WALK_CYCLES",
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"SampleAfterValue": "2000000",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "ITLB flushes",
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"Counter": "0,1,2,3",
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"EventCode": "0xAE",
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"EventName": "ITLB_FLUSH",
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"SampleAfterValue": "2000000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "ITLB miss",
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"Counter": "0,1,2,3",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.ANY",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "ITLB miss large page walks",
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"Counter": "0,1,2,3",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
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"SampleAfterValue": "200000",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "ITLB miss page walks",
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"Counter": "0,1,2,3",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "200000",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "ITLB miss page walk cycles",
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"Counter": "0,1,2,3",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.WALK_CYCLES",
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"SampleAfterValue": "2000000",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xC8",
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"EventName": "ITLB_MISS_RETIRED",
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"PEBS": "1",
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"SampleAfterValue": "200000",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "Retired loads that miss the DTLB (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xCB",
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"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
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"PEBS": "1",
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"SampleAfterValue": "200000",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "Retired stores that miss the DTLB (Precise Event)",
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"Counter": "0,1,2,3",
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"EventCode": "0xC",
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"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
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"PEBS": "1",
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"SampleAfterValue": "200000",
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"UMask": "0x1"
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}
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] |