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Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
88 lines
2.0 KiB
YAML
88 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,gpucc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Graphics Clock & Reset Controller Binding
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maintainers:
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm graphics clock control module which supports the clocks, resets and
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power domains on Qualcomm SoCs.
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See also:
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dt-bindings/clock/qcom,gpucc-sdm845.h
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dt-bindings/clock/qcom,gpucc-sc7180.h
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dt-bindings/clock/qcom,gpucc-sc7280.h
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dt-bindings/clock/qcom,gpucc-sm6350.h
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dt-bindings/clock/qcom,gpucc-sm8150.h
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dt-bindings/clock/qcom,gpucc-sm8250.h
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properties:
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compatible:
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enum:
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- qcom,sdm845-gpucc
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- qcom,sc7180-gpucc
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- qcom,sc7280-gpucc
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- qcom,sc8180x-gpucc
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- qcom,sm6350-gpucc
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- qcom,sm8150-gpucc
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- qcom,sm8250-gpucc
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clocks:
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items:
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- description: Board XO source
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- description: GPLL0 main branch source
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- description: GPLL0 div branch source
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clock-names:
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items:
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- const: bi_tcxo
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- const: gcc_gpu_gpll0_clk_src
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- const: gcc_gpu_gpll0_div_clk_src
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'#clock-cells':
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const: 1
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'#reset-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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maxItems: 1
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#reset-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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clock-controller@5090000 {
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compatible = "qcom,sdm845-gpucc";
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reg = <0x05090000 0x9000>;
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clocks = <&rpmhcc RPMH_CXO_CLK>,
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<&gcc GCC_GPU_GPLL0_CLK_SRC>,
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<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
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clock-names = "bi_tcxo",
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"gcc_gpu_gpll0_clk_src",
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"gcc_gpu_gpll0_div_clk_src";
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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