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Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
148 lines
3.9 KiB
YAML
148 lines
3.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/spi-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SPI Controller Generic Binding
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maintainers:
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- Mark Brown <broonie@kernel.org>
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description: |
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SPI busses can be described with a node for the SPI controller device
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and a set of child nodes for each SPI slave on the bus. The system SPI
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controller may be described for use in SPI master mode or in SPI slave mode,
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but not for both at the same time.
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properties:
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$nodename:
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pattern: "^spi(@.*|-[0-9a-f])*$"
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"#address-cells":
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enum: [0, 1]
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"#size-cells":
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const: 0
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cs-gpios:
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description: |
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GPIOs used as chip selects.
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If that property is used, the number of chip selects will be
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increased automatically with max(cs-gpios, hardware chip selects).
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So if, for example, the controller has 4 CS lines, and the
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cs-gpios looks like this
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cs-gpios = <&gpio1 0 0>, <0>, <&gpio1 1 0>, <&gpio1 2 0>;
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Then it should be configured so that num_chipselect = 4, with
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the following mapping
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cs0 : &gpio1 0 0
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cs1 : native
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cs2 : &gpio1 1 0
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cs3 : &gpio1 2 0
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The second flag of a gpio descriptor can be GPIO_ACTIVE_HIGH (0)
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or GPIO_ACTIVE_LOW(1). Legacy device trees often use 0.
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There is a special rule set for combining the second flag of an
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cs-gpio with the optional spi-cs-high flag for SPI slaves.
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Each table entry defines how the CS pin is to be physically
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driven (not considering potential gpio inversions by pinmux):
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device node | cs-gpio | CS pin state active | Note
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================+===============+=====================+=====
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spi-cs-high | - | H |
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- | - | L |
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spi-cs-high | ACTIVE_HIGH | H |
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- | ACTIVE_HIGH | L | 1
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spi-cs-high | ACTIVE_LOW | H | 2
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- | ACTIVE_LOW | L |
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Notes:
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1) Should print a warning about polarity inversion.
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Here it would be wise to avoid and define the gpio as
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ACTIVE_LOW.
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2) Should print a warning about polarity inversion
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because ACTIVE_LOW is overridden by spi-cs-high.
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Should be generally avoided and be replaced by
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spi-cs-high + ACTIVE_HIGH.
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num-cs:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Total number of chip selects.
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spi-slave:
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$ref: /schemas/types.yaml#/definitions/flag
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description:
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The SPI controller acts as a slave, instead of a master.
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slave:
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type: object
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properties:
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compatible:
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description:
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Compatible of the SPI device.
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required:
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- compatible
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patternProperties:
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"^.*@[0-9a-f]+$":
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type: object
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$ref: spi-peripheral-props.yaml
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required:
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- compatible
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- reg
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allOf:
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- if:
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not:
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required:
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- spi-slave
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then:
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properties:
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"#address-cells":
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const: 1
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else:
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properties:
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"#address-cells":
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const: 0
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additionalProperties: true
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examples:
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- |
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spi@80010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx28-spi";
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reg = <0x80010000 0x2000>;
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interrupts = <96>;
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dmas = <&dma_apbh 0>;
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dma-names = "rx-tx";
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display@0 {
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compatible = "lg,lg4573";
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spi-max-frequency = <1000000>;
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reg = <0>;
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};
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sensor@1 {
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compatible = "bosch,bme680";
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spi-max-frequency = <100000>;
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reg = <1>;
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};
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flash@2 {
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compatible = "jedec,spi-nor";
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spi-max-frequency = <50000000>;
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reg = <2>, <3>;
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stacked-memories = /bits/ 64 <0x10000000 0x10000000>;
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};
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};
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