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a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
65 lines
1.0 KiB
Plaintext
65 lines
1.0 KiB
Plaintext
// SPDX-License-Identifier: (GPL-2.0 or MIT)
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/*
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* Device Tree Source for the Spider CPU board
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*
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* Copyright (C) 2021 Renesas Electronics Corp.
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*/
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#include "r8a779f0.dtsi"
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/ {
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model = "Renesas Spider CPU board";
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compatible = "renesas,spider-cpu", "renesas,r8a779f0";
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memory@48000000 {
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device_type = "memory";
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/* first 128MB is reserved for secure area. */
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reg = <0x0 0x48000000 0x0 0x78000000>;
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};
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memory@480000000 {
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device_type = "memory";
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reg = <0x4 0x80000000 0x0 0x80000000>;
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};
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};
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&extal_clk {
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clock-frequency = <20000000>;
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};
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&extalr_clk {
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clock-frequency = <32768>;
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};
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&pfc {
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pinctrl-0 = <&scif_clk_pins>;
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pinctrl-names = "default";
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scif3_pins: scif3 {
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groups = "scif3_data", "scif3_ctrl";
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function = "scif3";
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};
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scif_clk_pins: scif_clk {
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groups = "scif_clk";
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function = "scif_clk";
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};
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};
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&rwdt {
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timeout-sec = <60>;
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status = "okay";
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};
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&scif3 {
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pinctrl-0 = <&scif3_pins>;
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pinctrl-names = "default";
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uart-has-rtscts;
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status = "okay";
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};
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&scif_clk {
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clock-frequency = <24000000>;
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};
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