diff --git a/Security Algo Accelerator/docs/Cortex_A72_MPCore_Cryptography_Technical_Reference_Manual-r1p0-00rel0.pdf b/Security Algo Accelerator/docs/Cortex_A72_MPCore_Cryptography_Technical_Reference_Manual-r1p0-00rel0.pdf new file mode 100644 index 0000000000..7866fa35cf Binary files /dev/null and b/Security Algo Accelerator/docs/Cortex_A72_MPCore_Cryptography_Technical_Reference_Manual-r1p0-00rel0.pdf differ diff --git a/Security Algo Accelerator/logical/maia/verilog/MAIA.v b/Security Algo Accelerator/logical/maia/verilog/MAIA.v new file mode 100644 index 0000000000..49910c358c --- /dev/null +++ b/Security Algo Accelerator/logical/maia/verilog/MAIA.v @@ -0,0 +1,4802 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: MAIA.v $ +// Checked In : $Date: 2014-10-14 15:20:06 -0500 (Tue, 14 Oct 2014) $ +// Revision : $Revision: 71806 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// +// This is top-level interconnect layer for the MAIA top-level. +// + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +`define MAIA_CN 3 + +module MAIA ( + CLK, + CLKEN, + nCPUPORESET, + nCORERESET, + nL2RESET, + L2RSTDISABLE, + WARMRSTREQ, + CFGEND, + VINITHI, + CFGTE, + CP15SDISABLE, + CLUSTERIDAFF1, + CLUSTERIDAFF2, + AA64nAA32, + RVBARADDR0, +// BEGIN INCLUDE FOR CPU1 + RVBARADDR1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + RVBARADDR2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + RVBARADDR3, +// END INCLUDE FOR CPU3 + CRYPTODISABLE, + nFIQ, + nIRQ, + nSEI, + nREI, + nVFIQ, + nVIRQ, + nVSEI, +// BEGIN NO-GIC pins + nVCPUMNTIRQ, +// END NO-GIC pins + PERIPHBASE, +// BEGIN NO-GIC pins + GICCDISABLE, + ICDTVALID, + ICDTREADY, + ICDTDATA, + ICDTLAST, + ICDTDEST, + ICCTVALID, + ICCTREADY, + ICCTDATA, + ICCTLAST, + ICCTID, +// END NO-GIC pins + CNTVALUEB, + CNTCLKEN, + nCNTPNSIRQ, + nCNTPSIRQ, + nCNTVIRQ, + nCNTHPIRQ, + CLREXMONREQ, + CLREXMONACK, + EVENTI, + EVENTO, + STANDBYWFI, + STANDBYWFE, + STANDBYWFIL2, + SMPEN, + CPUQACTIVE, + CPUQREQn, + CPUQACCEPTn, + CPUQDENY, + L2QACTIVE, + L2QREQn, + L2QACCEPTn, + L2QDENY, + L2FLUSHREQ, + L2FLUSHDONE, + nINTERRIRQ, + nEXTERRIRQ, + SYSBARDISABLE, + BROADCASTINNER, + BROADCASTOUTER, + BROADCASTCACHEMAINT, + ACLKENM, + ACINACTM, + AWREADYM, + AWVALIDM, + AWIDM, + AWADDRM, + AWLENM, + AWSIZEM, + AWBURSTM, + AWBARM, + AWDOMAINM, + AWLOCKM, + AWCACHEM, + AWPROTM, + AWSNOOPM, + AWUNIQUEM, + WRMEMATTR, + WREADYM, + WVALIDM, + WDATAM, + WSTRBM, + WIDM, + WLASTM, + BREADYM, + BVALIDM, + BIDM, + BRESPM, + ARREADYM, + ARVALIDM, + ARIDM, + ARADDRM, + ARLENM, + ARSIZEM, + ARBURSTM, + ARBARM, + ARDOMAINM, + ARLOCKM, + ARCACHEM, + ARPROTM, + ARSNOOPM, + RDMEMATTR, + RREADYM, + RVALIDM, + RIDM, + RDATAM, + RRESPM, + RLASTM, + ACREADYM, + ACVALIDM, + ACADDRM, + ACPROTM, + ACSNOOPM, + CRREADYM, + CRVALIDM, + CRRESPM, + CDREADYM, + CDVALIDM, + CDDATAM, + CDLASTM, + RACKM, + WACKM, +// BEGIN NO-ACP pins + ACLKENS, + AINACTS, + AWREADYS, + AWVALIDS, + AWIDS, + AWADDRS, + AWLENS, + AWCACHES, + AWUSERS, + AWPROTS, + WREADYS, + WVALIDS, + WDATAS, + WSTRBS, + WLASTS, + BREADYS, + BVALIDS, + BIDS, + BRESPS, + ARREADYS, + ARVALIDS, + ARIDS, + ARADDRS, + ARLENS, + ARCACHES, + ARUSERS, + ARPROTS, + RREADYS, + RVALIDS, + RIDS, + RDATAS, + RRESPS, + RLASTS, +// END NO-ACP pins + DBGROMADDR, + DBGROMADDRV, + DBGACK, + nCOMMIRQ, + COMMRX, + COMMTX, + DBGRSTREQ, + DBGNOPWRDWN, + DBGL1RSTDISABLE, + nPMUIRQ, + PMUEVENT0, +// BEGIN INCLUDE FOR CPU1 + PMUEVENT1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + PMUEVENT2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + PMUEVENT3, +// END INCLUDE FOR CPU3 + ATCLKEN, + TSVALUEB, + ATREADYM0, + AFVALIDM0, + ATDATAM0, + ATVALIDM0, + ATBYTESM0, + AFREADYM0, + ATIDM0, + SYNCREQM0, +// BEGIN INCLUDE FOR CPU1 + ATREADYM1, + AFVALIDM1, + ATDATAM1, + ATVALIDM1, + ATBYTESM1, + AFREADYM1, + ATIDM1, + SYNCREQM1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ATREADYM2, + AFVALIDM2, + ATDATAM2, + ATVALIDM2, + ATBYTESM2, + AFREADYM2, + ATIDM2, + SYNCREQM2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ATREADYM3, + AFVALIDM3, + ATDATAM3, + ATVALIDM3, + ATBYTESM3, + AFREADYM3, + ATIDM3, + SYNCREQM3, +// END INCLUDE FOR CPU3 + PCLKDBG, + PCLKENDBG, + nPRESETDBG, + PSELDBG, + PADDRDBG, + PADDRDBG31, + PENABLEDBG, + PWRITEDBG, + PWDATADBG, + PRDATADBG, + PREADYDBG, + PSLVERRDBG, + EDBGRQ, + PMUSNAPSHOTREQ, + PMUSNAPSHOTACK, + DBGPWRDUP, + DBGPWRUPREQ, + CTICHIN, + CTICHOUTACK, + CTICHOUT, + CTICHINACK, + CISBYPASS, + CIHSBYPASS, + CTIIRQ, + CTIIRQACK, + DBGEN, + NIDEN, + SPIDEN, + SPNIDEN, + DFTSE, + DFTRSTDISABLE, + DFTCRCLKDISABLE, + DFTL2CLKDISABLE, + DFTRAMHOLD, + DFTCLKBYPASS, + DFTMCPHOLD, + nMBISTRESET, + MBISTREQ +); + +//# +//# Interface Signals +//# ================= +//# + +//----------------------------------------------------------------------------- +// Clock and Reset Signals +//----------------------------------------------------------------------------- + input CLK; // Fast Clock + input CLKEN; // Fast Clock Enable + + input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset + input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) + input nL2RESET; // L2 reset + input L2RSTDISABLE; // L2 RAMs hardware reset disable + output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request +//See also nPRESETDBG; // Debug APB reset (PCLK) + +//----------------------------------------------------------------------------- +// Static Configuration Signals +//----------------------------------------------------------------------------- +// Static configuration signals that should be tied off and not change dynamically. +// Many of the initial values specified by these inputs +// may be overridden in software using CP15 registers. + + input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) + input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors + input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) + input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers + + input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] + input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] + + input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) + input [43:2] RVBARADDR0; // RVBAR address +// BEGIN INCLUDE FOR CPU1 + input [43:2] RVBARADDR1; // RVBAR address +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input [43:2] RVBARADDR2; // RVBAR address +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input [43:2] RVBARADDR3; // RVBAR address +// END INCLUDE FOR CPU3 + input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension + +//----------------------------------------------------------------------------- +// Interrupt Controller Signals +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] nFIQ; // Fast Interrupt request + input [`MAIA_CN:0] nIRQ; // Interrupt request + input [`MAIA_CN:0] nSEI; // System Error Interrupt + input [`MAIA_CN:0] nREI; // RAM Error Interrupt + input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request + input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request + input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt +// BEGIN NO-GIC pins + output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output +// END NO-GIC pins + + input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers +// BEGIN NO-GIC pins + input GICCDISABLE; // Put GIC into bypass mode + + input ICDTVALID; // Distrubuter AXI4 SP Message Valid + output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message + input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data + input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet + input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID + + output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid + input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message + output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data + output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet + output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID +// END NO-GIC pins + +//----------------------------------------------------------------------------- +// Timer Signals +//----------------------------------------------------------------------------- + input [63:0] CNTVALUEB; // Counter value in binary + input CNTCLKEN; // Counter clock enable + output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event + output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event + output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event + output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event + +//----------------------------------------------------------------------------- +// Power Management Signals +//----------------------------------------------------------------------------- + input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) + output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) + input EVENTI; // Event input for processor wake-up from WFE state + output EVENTO; // Event output, signal is active when SEV instruction is executed + output [`MAIA_CN:0] STANDBYWFI; // WFI mode + output [`MAIA_CN:0] STANDBYWFE; // WFE mode + output STANDBYWFIL2; // WFI mode for L2 + output [`MAIA_CN:0] SMPEN; // CPU SMP bit + + output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE + input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn + output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn + output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY + + output L2QACTIVE; // L2 Q-channel QACTIVE + input L2QREQn; // L2 Q-channel QREQn + output L2QACCEPTn; // L2 Q-channel QACCEPTn + output L2QDENY; // L2 Q-channel QDENY + + input L2FLUSHREQ; // L2 hardware flush request + output L2FLUSHDONE; // L2 hardware flush done + +//----------------------------------------------------------------------------- +// Asynchronous Error Signals +//----------------------------------------------------------------------------- + output nINTERRIRQ; // L2 RAM dbl-bit ECC error + output nEXTERRIRQ; // Write transaction error + +//----------------------------------------------------------------------------- +// Bus Configuration Signals +//----------------------------------------------------------------------------- + input SYSBARDISABLE; // Disable broadcast of barriers + input BROADCASTINNER; // Extend Inner Shared Domain + input BROADCASTOUTER; // Extend Outer Shared Domain + input BROADCASTCACHEMAINT; // Broadcast cache maint ops + +//----------------------------------------------------------------------------- +// AMBA4 ACE Master (AXI with Coherency extensions) +//----------------------------------------------------------------------------- + input ACLKENM; // AXI Master clock enable + input ACINACTM; // ACE Snoop interface no longer active or accepting requests + +// Write Address channel signals + input AWREADYM; // Write Address ready (slave ready to accept write address) + output AWVALIDM; // Write Address valid + output [6:0] AWIDM; // Write Address ID + output [43:0] AWADDRM; // Write Address + output [7:0] AWLENM; // Write Burst Length + output [2:0] AWSIZEM; // Write Burst Size + output [1:0] AWBURSTM; // Write Burst type + output [1:0] AWBARM; // Barrier + output [1:0] AWDOMAINM; // Domain + output AWLOCKM; // Write Lock type + output [3:0] AWCACHEM; // Write Cache type + output [2:0] AWPROTM; // Write Protection type + output [2:0] AWSNOOPM; // Write Snoop Request type + output AWUNIQUEM; // Write Unique state + output [7:0] WRMEMATTR; // Write raw memory attributes + +// Write Data channel signals + input WREADYM; // Write Data ready (slave ready to accept data) + output WVALIDM; // Write Data valid + output [127:0] WDATAM; // Write Data + output [15:0] WSTRBM; // Write byte-lane strobes + output [6:0] WIDM; // Write id + output WLASTM; // Write Data last transfer indicator + +// Write Response channel signals + output BREADYM; // Write Response ready (master ready to accept response) + input BVALIDM; // Write Response Valid + input [6:0] BIDM; // Write Response ID + input [1:0] BRESPM; // Write Response + +// Read Address channel signals + input ARREADYM; // Read Address ready (slave ready to accept read address) + output ARVALIDM; // Read Address valid + output [6:0] ARIDM; // Read Address ID + output [43:0] ARADDRM; // Read Address + output [7:0] ARLENM; // Read Burst Length + output [2:0] ARSIZEM; // Read Burst Size + output [1:0] ARBURSTM; // Read Burst type + output [1:0] ARBARM; // Barrier + output [1:0] ARDOMAINM; // Domain + output ARLOCKM; // Read Lock type + output [3:0] ARCACHEM; // Read Cache type + output [2:0] ARPROTM; // Read Protection type + output [3:0] ARSNOOPM; // Read Snoop Request type + output [7:0] RDMEMATTR; // Read raw memory attributes + +// Read Data channel signals + output RREADYM; // Read Data ready (master ready to accept data) + input RVALIDM; // Read Data valid + input [6:0] RIDM; // Read Data ID + input [127:0] RDATAM; // Read Data + input [3:0] RRESPM; // Read Data response + input RLASTM; // Read Data last transfer indicator + +// Coherency Address channel signals + output ACREADYM; // master ready to accept snoop address + input ACVALIDM; // Snoop Address valid + input [43:0] ACADDRM; // Snoop Address + input [2:0] ACPROTM; // Snoop Protection type + input [3:0] ACSNOOPM; // Snoop Request type + +// Coherency Response channel signals + input CRREADYM; // slave ready to accept snoop response + output CRVALIDM; // Snoop Response valid + output [4:0] CRRESPM; // Snoop Response + +// Coherency Data handshake channel signals + input CDREADYM; // slave ready to accept snoop data + output CDVALIDM; // Snoop Data valid + output [127:0] CDDATAM; // Snoop Data + output CDLASTM; // Snoop Data last transfer indicator + +// Read/Write Acknowledge signals + output RACKM; // Read Acknowledge + output WACKM; // Write Acknowledge + +// BEGIN NO-ACP pins +//----------------------------------------------------------------------------- +// ACP AXI Slave +//----------------------------------------------------------------------------- + input ACLKENS; // AXI slave clock enable + input AINACTS; // AXI slave interface no longer active or accepting requests +// Write Address channel signals + output AWREADYS; // Write Address ready (slave ready to accept write address) + input AWVALIDS; // Write Address valid + input [4:0] AWIDS; // Write Address ID + input [43:0] AWADDRS; // Write Address + input [7:0] AWLENS; // Write Burst Length + input [3:0] AWCACHES; // Write Cache type + input [1:0] AWUSERS; // Write inner & outer shareability + input [2:0] AWPROTS; // Write Protection type + +// Write Data channel signals + output WREADYS; // Write Data ready (slave ready to accept data) + input WVALIDS; // Write Data valid + input [127:0] WDATAS; // Write Data + input [15:0] WSTRBS; // Write byte-lane strobes + input WLASTS; // Write Data last transfer indicator + +// Write Response channel signals + input BREADYS; // Write Response ready (master ready to accept response) + output BVALIDS; // Write Response Valid + output [4:0] BIDS; // Write Response ID tag + output [1:0] BRESPS; // Write Response + +// Read Address channel signals + output ARREADYS; // Read Address ready (slave ready to accept read address) + input ARVALIDS; // Read Address valid + input [4:0] ARIDS; // Read Address ID + input [43:0] ARADDRS; // Read Address + input [7:0] ARLENS; // Read Burst Length + input [3:0] ARCACHES; // Read Cache type + input [1:0] ARUSERS; // Read inner & outer shareability + input [2:0] ARPROTS; // Read Protection type + +// Read Data channel signals + input RREADYS; // Read Data ready (master ready to accept data) + output RVALIDS; // Read Data valid + output [4:0] RIDS; // Read Data ID + output [127:0] RDATAS; // Read Data + output [1:0] RRESPS; // Read Data response + output RLASTS; // Read Data last transfer indicator +// END NO-ACP pins +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (CLK) +//----------------------------------------------------------------------------- +// Debug CLK interface + input [43:12] DBGROMADDR; // Debug ROM base address + input DBGROMADDRV; // Debug ROM base address valid + + output [`MAIA_CN:0] DBGACK; // Debug acknowledge + output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt + output [`MAIA_CN:0] COMMRX; // Comms channel receive + output [`MAIA_CN:0] COMMTX; // Comms channel transmit + + output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request + output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request + + input DBGL1RSTDISABLE; // L1 DCache hardware reset disable + +// PMU CLK interface + output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request + output [24:0] PMUEVENT0; // PMU Event bus +// BEGIN INCLUDE FOR CPU1 + output [24:0] PMUEVENT1; // PMU Event bus +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + output [24:0] PMUEVENT2; // PMU Event bus +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + output [24:0] PMUEVENT3; // PMU Event bus +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (ATCLK) +//----------------------------------------------------------------------------- +// ETM ATB interface and Misc signals + input ATCLKEN; // ATB Clock Enable + input [63:0] TSVALUEB; // ATB Timestamp in binary + + input ATREADYM0; // ATDATA can be accepted + input AFVALIDM0; // ATB Fifo Flush Request + output [31:0] ATDATAM0; // ATB Data + output ATVALIDM0; // ATB Data Valid + output [1:0] ATBYTESM0; // ATB Data Size + output AFREADYM0; // ATB Fifo Flush Finished + output [6:0] ATIDM0; // ATB Trace Source ID + input SYNCREQM0; // ATB External synchronization request + +// BEGIN INCLUDE FOR CPU1 + input ATREADYM1; // ATDATA can be accepted + input AFVALIDM1; // ATB Fifo Flush Request + output [31:0] ATDATAM1; // ATB Data + output ATVALIDM1; // ATB Data Valid + output [1:0] ATBYTESM1; // ATB Data Size + output AFREADYM1; // ATB Fifo Flush Finished + output [6:0] ATIDM1; // ATB Trace Source ID + input SYNCREQM1; // ATB External synchronization request +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ATREADYM2; // ATDATA can be accepted + input AFVALIDM2; // ATB Fifo Flush Request + output [31:0] ATDATAM2; // ATB Data + output ATVALIDM2; // ATB Data Valid + output [1:0] ATBYTESM2; // ATB Data Size + output AFREADYM2; // ATB Fifo Flush Finished + output [6:0] ATIDM2; // ATB Trace Source ID + input SYNCREQM2; // ATB External synchronization request +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ATREADYM3; // ATDATA can be accepted + input AFVALIDM3; // ATB Fifo Flush Request + output [31:0] ATDATAM3; // ATB Data + output ATVALIDM3; // ATB Data Valid + output [1:0] ATBYTESM3; // ATB Data Size + output AFREADYM3; // ATB Fifo Flush Finished + output [6:0] ATIDM3; // ATB Trace Source ID + input SYNCREQM3; // ATB External synchronization request +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (PCLK) +//----------------------------------------------------------------------------- +// Debug-APBv3 port (APB) + input PCLKDBG; // APB Clock + input PCLKENDBG; // APB Clock Enable + input nPRESETDBG; // APB Reset + input PSELDBG; // Debug bus access + input [21:2] PADDRDBG; // APB address + input PADDRDBG31; // APB address bit[31] + input PENABLEDBG; // APB transfer complete flag + input PWRITEDBG; // APB read/write indicator + input [31:0] PWDATADBG; // APB write data + output [31:0] PRDATADBG; // APB read data + output PREADYDBG; // APB slave ready, used to extend a transfer + output PSLVERRDBG; // APB slave transfer error + +// Misc interface + input [`MAIA_CN:0] EDBGRQ; // External debug request + +// PMU Snapshot interface + input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request + output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge + +// Power-related interface + input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status + output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request + +// CTI interface + input [3:0] CTICHIN; // Channel In + input [3:0] CTICHOUTACK; // Channel Out acknowledge + output [3:0] CTICHOUT; // Channel Out + output [3:0] CTICHINACK; // Channel In acknowledge + input CISBYPASS; // Channel interface sync bypass + input [3:0] CIHSBYPASS; // Channel interface H/S bypass + output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt + input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge + +//----------------------------------------------------------------------------- +// Debug Authentication Interface (CLK & PCLK) +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] DBGEN; // Invasive debug enable + input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable + input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable + input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable + +//----------------------------------------------------------------------------- +// DFT Signals +//----------------------------------------------------------------------------- + input DFTSE; // Scan enable + input DFTRSTDISABLE; // Disable reset to cells during scan shift + input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr + input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 + input DFTRAMHOLD; // Holds data in RAMs + input DFTCLKBYPASS; // L2 RAM strobe clock bypass + input DFTMCPHOLD; // Disable multi-cycle RAM paths + +//----------------------------------------------------------------------------- +// MBIST Interface +//----------------------------------------------------------------------------- + input nMBISTRESET; // MBIST reset + input MBISTREQ; // MBIST mode request + + + // wires + wire aa64naa32_cpu0_o; + wire aa64naa32_cpu1_o; + wire aa64naa32_cpu2_o; + wire aa64naa32_cpu3_o; + wire afreadym_cpu0_i; + wire afreadym_cpu1_i; + wire afreadym_cpu2_i; + wire afreadym_cpu3_i; + wire afvalidm_cpu0_o; + wire afvalidm_cpu1_o; + wire afvalidm_cpu2_o; + wire afvalidm_cpu3_o; + wire [1:0] atbytesm_cpu0_i; + wire [1:0] atbytesm_cpu1_i; + wire [1:0] atbytesm_cpu2_i; + wire [1:0] atbytesm_cpu3_i; + wire atclken_cpu0_o; + wire atclken_cpu1_o; + wire atclken_cpu2_o; + wire atclken_cpu3_o; + wire [31:0] atdatam_cpu0_i; + wire [31:0] atdatam_cpu1_i; + wire [31:0] atdatam_cpu2_i; + wire [31:0] atdatam_cpu3_i; + wire [6:0] atidm_cpu0_i; + wire [6:0] atidm_cpu1_i; + wire [6:0] atidm_cpu2_i; + wire [6:0] atidm_cpu3_i; + wire atreadym_cpu0_o; + wire atreadym_cpu1_o; + wire atreadym_cpu2_o; + wire atreadym_cpu3_o; + wire atvalidm_cpu0_i; + wire atvalidm_cpu1_i; + wire atvalidm_cpu2_i; + wire atvalidm_cpu3_i; + wire cfgend_cpu0_o; + wire cfgend_cpu1_o; + wire cfgend_cpu2_o; + wire cfgend_cpu3_o; + wire cfgte_cpu0_o; + wire cfgte_cpu1_o; + wire cfgte_cpu2_o; + wire cfgte_cpu3_o; + wire ck_cpu0_crcx_clk_en_n; + wire ck_cpu0_event_reg; + wire ck_cpu0_wfe_ack; + wire ck_cpu0_wfi_ack; + wire ck_cpu1_crcx_clk_en_n; + wire ck_cpu1_event_reg; + wire ck_cpu1_wfe_ack; + wire ck_cpu1_wfi_ack; + wire ck_cpu2_crcx_clk_en_n; + wire ck_cpu2_event_reg; + wire ck_cpu2_wfe_ack; + wire ck_cpu2_wfi_ack; + wire ck_cpu3_crcx_clk_en_n; + wire ck_cpu3_event_reg; + wire ck_cpu3_wfe_ack; + wire ck_cpu3_wfi_ack; + wire [`MAIA_CN:0] ck_gclkt; + wire [7:0] clusteridaff1_cpu0_o; + wire [7:0] clusteridaff1_cpu1_o; + wire [7:0] clusteridaff1_cpu2_o; + wire [7:0] clusteridaff1_cpu3_o; + wire [7:0] clusteridaff2_cpu0_o; + wire [7:0] clusteridaff2_cpu1_o; + wire [7:0] clusteridaff2_cpu2_o; + wire [7:0] clusteridaff2_cpu3_o; + wire commrx_cpu0_i; + wire commrx_cpu1_i; + wire commrx_cpu2_i; + wire commrx_cpu3_i; + wire commtx_cpu0_i; + wire commtx_cpu1_i; + wire commtx_cpu2_i; + wire commtx_cpu3_i; + wire cp15sdisable_cpu0_o; + wire cp15sdisable_cpu1_o; + wire cp15sdisable_cpu2_o; + wire cp15sdisable_cpu3_o; + wire [1:0] cpuid_cpu0_o; + wire [1:0] cpuid_cpu1_o; + wire [1:0] cpuid_cpu2_o; + wire [1:0] cpuid_cpu3_o; + wire cryptodisable_cpu0_o; + wire cryptodisable_cpu1_o; + wire cryptodisable_cpu2_o; + wire cryptodisable_cpu3_o; + wire dbgack_cpu0_i; + wire dbgack_cpu1_i; + wire dbgack_cpu2_i; + wire dbgack_cpu3_i; + wire dbgen_cpu0_o; + wire dbgen_cpu1_o; + wire dbgen_cpu2_o; + wire dbgen_cpu3_o; + wire dbgl1rstdisable_cpu0_o; + wire dbgl1rstdisable_cpu1_o; + wire dbgl1rstdisable_cpu2_o; + wire dbgl1rstdisable_cpu3_o; + wire dbgnopwrdwn_cpu0_i; + wire dbgnopwrdwn_cpu1_i; + wire dbgnopwrdwn_cpu2_i; + wire dbgnopwrdwn_cpu3_i; + wire [43:12] dbgromaddr_cpu0_o; + wire [43:12] dbgromaddr_cpu1_o; + wire [43:12] dbgromaddr_cpu2_o; + wire [43:12] dbgromaddr_cpu3_o; + wire dbgromaddrv_cpu0_o; + wire dbgromaddrv_cpu1_o; + wire dbgromaddrv_cpu2_o; + wire dbgromaddrv_cpu3_o; + wire dbgrstreq_cpu0_i; + wire dbgrstreq_cpu1_i; + wire dbgrstreq_cpu2_i; + wire dbgrstreq_cpu3_i; + wire dftcrclkdisable_cpu0_o; + wire dftcrclkdisable_cpu1_o; + wire dftcrclkdisable_cpu2_o; + wire dftcrclkdisable_cpu3_o; + wire dftramhold_cpu0_o; + wire dftramhold_cpu1_o; + wire dftramhold_cpu2_o; + wire dftramhold_cpu3_o; + wire dftrstdisable_cpu0_o; + wire dftrstdisable_cpu1_o; + wire dftrstdisable_cpu2_o; + wire dftrstdisable_cpu3_o; + wire dftse_cpu0_o; + wire dftse_cpu1_o; + wire dftse_cpu2_o; + wire dftse_cpu3_o; + wire [2:0] ds_cpu0_cpuectlr_ret; + wire ds_cpu0_cpuectlr_smp; + wire ds_cpu0_fiq_wfe_qual; + wire ds_cpu0_fiq_wfi_qual; + wire ds_cpu0_flush; + wire [5:0] ds_cpu0_flush_type; + wire ds_cpu0_hcr_va; + wire ds_cpu0_hcr_vf; + wire ds_cpu0_hcr_vi; + wire ds_cpu0_ic_aa64naa32; + wire [4:0] ds_cpu0_ic_cpsr_mode; + wire ds_cpu0_ic_hcr_change; + wire ds_cpu0_ic_sample_spr; + wire ds_cpu0_ic_scr_change; + wire ds_cpu0_imp_abrt_wfe_qual; + wire ds_cpu0_imp_abrt_wfi_qual; + wire ds_cpu0_irq_wfe_qual; + wire ds_cpu0_irq_wfi_qual; + wire [8:0] ds_cpu0_l2_spr_addr; + wire ds_cpu0_l2_spr_dw; + wire ds_cpu0_l2_spr_en; + wire ds_cpu0_l2_spr_rd; + wire ds_cpu0_l2_spr_wr; + wire [63:0] ds_cpu0_l2_spr_wr_data; + wire ds_cpu0_reset_req; + wire ds_cpu0_sev_req; + wire ds_cpu0_sevl_req; + wire ds_cpu0_vfiq_wfe_qual; + wire ds_cpu0_vfiq_wfi_qual; + wire ds_cpu0_vimp_abrt_wfe_qual; + wire ds_cpu0_vimp_abrt_wfi_qual; + wire ds_cpu0_virq_wfe_qual; + wire ds_cpu0_virq_wfi_qual; + wire ds_cpu0_wfe_req; + wire ds_cpu0_wfi_req; + wire [2:0] ds_cpu1_cpuectlr_ret; + wire ds_cpu1_cpuectlr_smp; + wire ds_cpu1_fiq_wfe_qual; + wire ds_cpu1_fiq_wfi_qual; + wire ds_cpu1_flush; + wire [5:0] ds_cpu1_flush_type; + wire ds_cpu1_hcr_va; + wire ds_cpu1_hcr_vf; + wire ds_cpu1_hcr_vi; + wire ds_cpu1_ic_aa64naa32; + wire [4:0] ds_cpu1_ic_cpsr_mode; + wire ds_cpu1_ic_hcr_change; + wire ds_cpu1_ic_sample_spr; + wire ds_cpu1_ic_scr_change; + wire ds_cpu1_imp_abrt_wfe_qual; + wire ds_cpu1_imp_abrt_wfi_qual; + wire ds_cpu1_irq_wfe_qual; + wire ds_cpu1_irq_wfi_qual; + wire [8:0] ds_cpu1_l2_spr_addr; + wire ds_cpu1_l2_spr_dw; + wire ds_cpu1_l2_spr_en; + wire ds_cpu1_l2_spr_rd; + wire ds_cpu1_l2_spr_wr; + wire [63:0] ds_cpu1_l2_spr_wr_data; + wire ds_cpu1_reset_req; + wire ds_cpu1_sev_req; + wire ds_cpu1_sevl_req; + wire ds_cpu1_vfiq_wfe_qual; + wire ds_cpu1_vfiq_wfi_qual; + wire ds_cpu1_vimp_abrt_wfe_qual; + wire ds_cpu1_vimp_abrt_wfi_qual; + wire ds_cpu1_virq_wfe_qual; + wire ds_cpu1_virq_wfi_qual; + wire ds_cpu1_wfe_req; + wire ds_cpu1_wfi_req; + wire [2:0] ds_cpu2_cpuectlr_ret; + wire ds_cpu2_cpuectlr_smp; + wire ds_cpu2_fiq_wfe_qual; + wire ds_cpu2_fiq_wfi_qual; + wire ds_cpu2_flush; + wire [5:0] ds_cpu2_flush_type; + wire ds_cpu2_hcr_va; + wire ds_cpu2_hcr_vf; + wire ds_cpu2_hcr_vi; + wire ds_cpu2_ic_aa64naa32; + wire [4:0] ds_cpu2_ic_cpsr_mode; + wire ds_cpu2_ic_hcr_change; + wire ds_cpu2_ic_sample_spr; + wire ds_cpu2_ic_scr_change; + wire ds_cpu2_imp_abrt_wfe_qual; + wire ds_cpu2_imp_abrt_wfi_qual; + wire ds_cpu2_irq_wfe_qual; + wire ds_cpu2_irq_wfi_qual; + wire [8:0] ds_cpu2_l2_spr_addr; + wire ds_cpu2_l2_spr_dw; + wire ds_cpu2_l2_spr_en; + wire ds_cpu2_l2_spr_rd; + wire ds_cpu2_l2_spr_wr; + wire [63:0] ds_cpu2_l2_spr_wr_data; + wire ds_cpu2_reset_req; + wire ds_cpu2_sev_req; + wire ds_cpu2_sevl_req; + wire ds_cpu2_vfiq_wfe_qual; + wire ds_cpu2_vfiq_wfi_qual; + wire ds_cpu2_vimp_abrt_wfe_qual; + wire ds_cpu2_vimp_abrt_wfi_qual; + wire ds_cpu2_virq_wfe_qual; + wire ds_cpu2_virq_wfi_qual; + wire ds_cpu2_wfe_req; + wire ds_cpu2_wfi_req; + wire [2:0] ds_cpu3_cpuectlr_ret; + wire ds_cpu3_cpuectlr_smp; + wire ds_cpu3_fiq_wfe_qual; + wire ds_cpu3_fiq_wfi_qual; + wire ds_cpu3_flush; + wire [5:0] ds_cpu3_flush_type; + wire ds_cpu3_hcr_va; + wire ds_cpu3_hcr_vf; + wire ds_cpu3_hcr_vi; + wire ds_cpu3_ic_aa64naa32; + wire [4:0] ds_cpu3_ic_cpsr_mode; + wire ds_cpu3_ic_hcr_change; + wire ds_cpu3_ic_sample_spr; + wire ds_cpu3_ic_scr_change; + wire ds_cpu3_imp_abrt_wfe_qual; + wire ds_cpu3_imp_abrt_wfi_qual; + wire ds_cpu3_irq_wfe_qual; + wire ds_cpu3_irq_wfi_qual; + wire [8:0] ds_cpu3_l2_spr_addr; + wire ds_cpu3_l2_spr_dw; + wire ds_cpu3_l2_spr_en; + wire ds_cpu3_l2_spr_rd; + wire ds_cpu3_l2_spr_wr; + wire [63:0] ds_cpu3_l2_spr_wr_data; + wire ds_cpu3_reset_req; + wire ds_cpu3_sev_req; + wire ds_cpu3_sevl_req; + wire ds_cpu3_vfiq_wfe_qual; + wire ds_cpu3_vfiq_wfi_qual; + wire ds_cpu3_vimp_abrt_wfe_qual; + wire ds_cpu3_vimp_abrt_wfi_qual; + wire ds_cpu3_virq_wfe_qual; + wire ds_cpu3_virq_wfi_qual; + wire ds_cpu3_wfe_req; + wire ds_cpu3_wfi_req; + wire dt_cpu0_coredbg_in_reset_gclk; + wire [1:0] dt_cpu0_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu0_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu0_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu0_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu0_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu0_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; + wire dt_cpu0_cti_trigoutack_bit1_gclk; + wire dt_cpu0_dbif_ack_gclk; + wire [14:2] dt_cpu0_dbif_addr_pclk; + wire dt_cpu0_dbif_err_gclk; + wire dt_cpu0_dbif_locked_pclk; + wire [31:0] dt_cpu0_dbif_rddata_gclk; + wire dt_cpu0_dbif_req_pclk; + wire [31:0] dt_cpu0_dbif_wrdata_pclk; + wire dt_cpu0_dbif_write_pclk; + wire dt_cpu0_edacr_frc_idleack_pclk; + wire dt_cpu0_edbgrq_pclk; + wire dt_cpu0_edecr_osuce_pclk; + wire dt_cpu0_edecr_rce_pclk; + wire dt_cpu0_edecr_ss_pclk; + wire dt_cpu0_edprcr_corepurq_pclk; + wire dt_cpu0_et_oslock_gclk; + wire dt_cpu0_halt_ack_gclk; + wire dt_cpu0_hlt_dbgevt_ok_gclk; + wire dt_cpu0_noclkstop_pclk; + wire dt_cpu0_os_double_lock_gclk; + wire dt_cpu0_pmusnapshot_ack_gclk; + wire dt_cpu0_pmusnapshot_req_pclk; + wire dt_cpu0_wfx_dbg_req_gclk; + wire dt_cpu0_wfx_wakeup_pclk; + wire dt_cpu1_coredbg_in_reset_gclk; + wire [1:0] dt_cpu1_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu1_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu1_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu1_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu1_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu1_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; + wire dt_cpu1_cti_trigoutack_bit1_gclk; + wire dt_cpu1_dbif_ack_gclk; + wire [14:2] dt_cpu1_dbif_addr_pclk; + wire dt_cpu1_dbif_err_gclk; + wire dt_cpu1_dbif_locked_pclk; + wire [31:0] dt_cpu1_dbif_rddata_gclk; + wire dt_cpu1_dbif_req_pclk; + wire [31:0] dt_cpu1_dbif_wrdata_pclk; + wire dt_cpu1_dbif_write_pclk; + wire dt_cpu1_edacr_frc_idleack_pclk; + wire dt_cpu1_edbgrq_pclk; + wire dt_cpu1_edecr_osuce_pclk; + wire dt_cpu1_edecr_rce_pclk; + wire dt_cpu1_edecr_ss_pclk; + wire dt_cpu1_edprcr_corepurq_pclk; + wire dt_cpu1_et_oslock_gclk; + wire dt_cpu1_halt_ack_gclk; + wire dt_cpu1_hlt_dbgevt_ok_gclk; + wire dt_cpu1_noclkstop_pclk; + wire dt_cpu1_os_double_lock_gclk; + wire dt_cpu1_pmusnapshot_ack_gclk; + wire dt_cpu1_pmusnapshot_req_pclk; + wire dt_cpu1_wfx_dbg_req_gclk; + wire dt_cpu1_wfx_wakeup_pclk; + wire dt_cpu2_coredbg_in_reset_gclk; + wire [1:0] dt_cpu2_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu2_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu2_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu2_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu2_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu2_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; + wire dt_cpu2_cti_trigoutack_bit1_gclk; + wire dt_cpu2_dbif_ack_gclk; + wire [14:2] dt_cpu2_dbif_addr_pclk; + wire dt_cpu2_dbif_err_gclk; + wire dt_cpu2_dbif_locked_pclk; + wire [31:0] dt_cpu2_dbif_rddata_gclk; + wire dt_cpu2_dbif_req_pclk; + wire [31:0] dt_cpu2_dbif_wrdata_pclk; + wire dt_cpu2_dbif_write_pclk; + wire dt_cpu2_edacr_frc_idleack_pclk; + wire dt_cpu2_edbgrq_pclk; + wire dt_cpu2_edecr_osuce_pclk; + wire dt_cpu2_edecr_rce_pclk; + wire dt_cpu2_edecr_ss_pclk; + wire dt_cpu2_edprcr_corepurq_pclk; + wire dt_cpu2_et_oslock_gclk; + wire dt_cpu2_halt_ack_gclk; + wire dt_cpu2_hlt_dbgevt_ok_gclk; + wire dt_cpu2_noclkstop_pclk; + wire dt_cpu2_os_double_lock_gclk; + wire dt_cpu2_pmusnapshot_ack_gclk; + wire dt_cpu2_pmusnapshot_req_pclk; + wire dt_cpu2_wfx_dbg_req_gclk; + wire dt_cpu2_wfx_wakeup_pclk; + wire dt_cpu3_coredbg_in_reset_gclk; + wire [1:0] dt_cpu3_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu3_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu3_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu3_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu3_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu3_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; + wire dt_cpu3_cti_trigoutack_bit1_gclk; + wire dt_cpu3_dbif_ack_gclk; + wire [14:2] dt_cpu3_dbif_addr_pclk; + wire dt_cpu3_dbif_err_gclk; + wire dt_cpu3_dbif_locked_pclk; + wire [31:0] dt_cpu3_dbif_rddata_gclk; + wire dt_cpu3_dbif_req_pclk; + wire [31:0] dt_cpu3_dbif_wrdata_pclk; + wire dt_cpu3_dbif_write_pclk; + wire dt_cpu3_edacr_frc_idleack_pclk; + wire dt_cpu3_edbgrq_pclk; + wire dt_cpu3_edecr_osuce_pclk; + wire dt_cpu3_edecr_rce_pclk; + wire dt_cpu3_edecr_ss_pclk; + wire dt_cpu3_edprcr_corepurq_pclk; + wire dt_cpu3_et_oslock_gclk; + wire dt_cpu3_halt_ack_gclk; + wire dt_cpu3_hlt_dbgevt_ok_gclk; + wire dt_cpu3_noclkstop_pclk; + wire dt_cpu3_os_double_lock_gclk; + wire dt_cpu3_pmusnapshot_ack_gclk; + wire dt_cpu3_pmusnapshot_req_pclk; + wire dt_cpu3_wfx_dbg_req_gclk; + wire dt_cpu3_wfx_wakeup_pclk; + wire etclken_cpu0_i; + wire etclken_cpu1_i; + wire etclken_cpu2_i; + wire etclken_cpu3_i; + wire giccdisable_cpu0_o; + wire giccdisable_cpu1_o; + wire giccdisable_cpu2_o; + wire giccdisable_cpu3_o; + wire [`MAIA_CN:0] ic_block_eoi_sgi_wr; + wire [`MAIA_CN:0] ic_el_change_complete; + wire [`MAIA_CN:0] ic_hcr_change_complete; + wire [`MAIA_CN:0] ic_ich_el2_tall0; + wire [`MAIA_CN:0] ic_ich_el2_tall1; + wire [`MAIA_CN:0] ic_ich_el2_tc; + wire [`MAIA_CN:0] ic_nfiq; + wire [`MAIA_CN:0] ic_nirq; + wire [`MAIA_CN:0] ic_nsei; + wire [`MAIA_CN:0] ic_nvfiq; + wire [`MAIA_CN:0] ic_nvirq; + wire [`MAIA_CN:0] ic_nvsei; + wire [`MAIA_CN:0] ic_p_valid; + wire [`MAIA_CN:0] ic_sample_spr; + wire [`MAIA_CN:0] ic_scr_change_complete; + wire [`MAIA_CN:0] ic_sra_el1ns_en; + wire [`MAIA_CN:0] ic_sra_el1s_en; + wire [`MAIA_CN:0] ic_sra_el2_en; + wire [`MAIA_CN:0] ic_sra_el3_en; + wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; + wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap; + wire [`MAIA_CN:0] ic_sre_el1s_mon_trap; + wire [`MAIA_CN:0] ic_sre_el2_mon_trap; + wire l2_cpu0_arb_thrshld_timeout_en; + wire l2_cpu0_barrier_done; + wire l2_cpu0_blk_non_evict_wr; + wire l2_cpu0_ccb_dbg_req_c3; + wire [48:0] l2_cpu0_ccb_req_addr_c3; + wire [4:0] l2_cpu0_ccb_req_id_c3; + wire [23:0] l2_cpu0_ccb_req_info_c3; + wire [8:0] l2_cpu0_ccb_req_type_c3; + wire l2_cpu0_cfg_ecc_en; + wire [2:0] l2_cpu0_dbufid_r1; + wire [129:0] l2_cpu0_ddata_r2; + wire l2_cpu0_ddlb_ecc_err_r3; + wire l2_cpu0_dext_err_r2; + wire l2_cpu0_dext_err_type_r2; + wire l2_cpu0_disable_clean_evict_opt; + wire l2_cpu0_dlast_r1; + wire l2_cpu0_dsngl_ecc_err_r3; + wire [3:0] l2_cpu0_dsq_clr_id_q; + wire l2_cpu0_dsq_clr_vld_q; + wire [3:0] l2_cpu0_dsq_rd_buf_id; + wire [15:0] l2_cpu0_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu0_dsq_rd_data_q; + wire l2_cpu0_dsq_rd_en; + wire l2_cpu0_dsq_rd_en_x2; + wire l2_cpu0_dt_pmu_evt_en; + wire l2_cpu0_dvalid_r1; + wire l2_cpu0_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; + wire l2_cpu0_flsh_if_rd_l4_dly; + wire l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; + wire l2_cpu0_flsh_ls_rd_l2_dly; + wire l2_cpu0_flsh_ls_rd_l4_dly; + wire l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; + wire l2_cpu0_flsh_ls_wr_l2_dly; + wire l2_cpu0_flsh_ls_wr_l4_dly; + wire l2_cpu0_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu0_ibufid_r1; + wire [15:0] l2_cpu0_ic_addr_arb_set; + wire l2_cpu0_ic_arb_fast; + wire l2_cpu0_ic_barrier_stall_q; + wire [43:18] l2_cpu0_ic_base; + wire [31:0] l2_cpu0_ic_data_arb_set; + wire [2:0] l2_cpu0_ic_elem_size_arb_set; + wire l2_cpu0_ic_excl_arb_set; + wire [2:0] l2_cpu0_ic_id_arb_set; + wire l2_cpu0_ic_ns_arb_set; + wire l2_cpu0_ic_vld_skid; + wire l2_cpu0_ic_write_arb_set; + wire [127:0] l2_cpu0_idata_r2; + wire l2_cpu0_idlb_ecc_err_r3; + wire l2_cpu0_idle_block_reqs_q; + wire l2_cpu0_idle_wakeup_q; + wire l2_cpu0_iext_err_r2; + wire l2_cpu0_iext_err_type_r2; + wire l2_cpu0_if_ccb_clken_c3; + wire l2_cpu0_if_ccb_req_c3; + wire l2_cpu0_if_ccb_resp; + wire [4:0] l2_cpu0_if_ccb_resp_id; + wire l2_cpu0_if_sync_done_q; + wire l2_cpu0_if_sync_req; + wire l2_cpu0_ifq_haz_pending; + wire l2_cpu0_isngl_ecc_err_r3; + wire l2_cpu0_ivalid_r1; + wire [1:0] l2_cpu0_l2_cache_size; + wire [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; + wire l2_cpu0_lrq_haz_pending; + wire l2_cpu0_ls_ccb_clken_c3; + wire l2_cpu0_ls_ccb_data_wr; + wire l2_cpu0_ls_ccb_req_c3; + wire l2_cpu0_ls_ccb_resp; + wire [4:0] l2_cpu0_ls_ccb_resp_id; + wire l2_cpu0_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu0_ls_rd_haz_id_arb_q; + wire l2_cpu0_ls_rd_haz_vld_arb_q; + wire l2_cpu0_ls_sync_req; + wire [4:0] l2_cpu0_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu0_ls_wr_data_w2a; + wire l2_cpu0_ls_wr_dirty_w2a; + wire l2_cpu0_ls_wr_err_w2a; + wire [2:0] l2_cpu0_ls_wr_haz_id_arb_q; + wire l2_cpu0_ls_wr_haz_vld_arb_q; + wire l2_cpu0_ls_wr_last_w2a; + wire l2_cpu0_ls_wr_req_w2a; + wire [2:0] l2_cpu0_ls_wr_type_w2a; + wire [12:0] l2_cpu0_mbist1_addr_b1; + wire l2_cpu0_mbist1_all_b1; + wire [3:0] l2_cpu0_mbist1_array_b1; + wire [7:0] l2_cpu0_mbist1_be_b1; + wire l2_cpu0_mbist1_en_b1; + wire l2_cpu0_mbist1_rd_en_b1; + wire l2_cpu0_mbist1_wr_en_b1; + wire l2_cpu0_no_intctrl; + wire l2_cpu0_pf_rd_vld_skid_popped; + wire l2_cpu0_pf_throttle_q; + wire [33:0] l2_cpu0_pmu_events; + wire [2:0] l2_cpu0_rbufid; + wire l2_cpu0_rd_aarch64_arb_set; + wire [44:0] l2_cpu0_rd_addr_arb_set; + wire l2_cpu0_rd_arb; + wire l2_cpu0_rd_arb_fast; + wire [15:8] l2_cpu0_rd_asid_arb_set; + wire l2_cpu0_rd_bypass_arb_set; + wire [2:0] l2_cpu0_rd_bypass_bufid_e5; + wire [2:0] l2_cpu0_rd_bypass_lrq_id_e5; + wire l2_cpu0_rd_bypass_req_can_e5; + wire l2_cpu0_rd_bypass_way_e5; + wire [2:0] l2_cpu0_rd_cache_attr_arb_set; + wire [2:0] l2_cpu0_rd_elem_size_arb_set; + wire l2_cpu0_rd_excl_arb_set; + wire [4:0] l2_cpu0_rd_id_arb_set; + wire [2:0] l2_cpu0_rd_lrq_id_arb_set; + wire [7:0] l2_cpu0_rd_page_attr_arb_set; + wire l2_cpu0_rd_prfm_arb_set; + wire l2_cpu0_rd_priv_arb_set; + wire l2_cpu0_rd_replayed_arb_set; + wire [1:0] l2_cpu0_rd_shared_arb_set; + wire [6:0] l2_cpu0_rd_type_arb_set; + wire l2_cpu0_rd_va48_arb_set; + wire l2_cpu0_rd_vld_skid; + wire l2_cpu0_rd_way_arb_set; + wire l2_cpu0_rexfail; + wire [1:0] l2_cpu0_rstate; + wire l2_cpu0_rvalid; + wire [2:0] l2_cpu0_spec_bufid; + wire l2_cpu0_spec_valid; + wire [63:0] l2_cpu0_spr_rd_data; + wire l2_cpu0_tbw_dbl_ecc_err; + wire [63:0] l2_cpu0_tbw_desc_data; + wire l2_cpu0_tbw_desc_vld; + wire l2_cpu0_tbw_ext_err; + wire l2_cpu0_tbw_ext_err_type; + wire l2_cpu0_tlb_ccb_clken_c3; + wire l2_cpu0_tlb_ccb_req_c3; + wire l2_cpu0_tlb_sync_complete; + wire l2_cpu0_tlb_sync_done_q; + wire l2_cpu0_tlb_sync_req; + wire l2_cpu0_trq_haz_pending; + wire l2_cpu0_tw_ccb_resp; + wire [4:0] l2_cpu0_tw_ccb_resp_id; + wire l2_cpu0_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu0_wr_addr_arb_set; + wire l2_cpu0_wr_arb; + wire l2_cpu0_wr_arb_fast; + wire [2:0] l2_cpu0_wr_cache_attr_arb_set; + wire [11:0] l2_cpu0_wr_cl_id_arb_set; + wire l2_cpu0_wr_clean_evict_arb_set; + wire [143:0] l2_cpu0_wr_data; + wire l2_cpu0_wr_data_stall; + wire l2_cpu0_wr_data_vld_x1_q; + wire l2_cpu0_wr_dirty_arb_set; + wire [2:0] l2_cpu0_wr_elem_size_arb_set; + wire l2_cpu0_wr_err_arb_set; + wire l2_cpu0_wr_evict_x1_q; + wire l2_cpu0_wr_ex_fail; + wire l2_cpu0_wr_ex_resp; + wire [3:0] l2_cpu0_wr_id_arb_set; + wire l2_cpu0_wr_last_arb_set; + wire [7:0] l2_cpu0_wr_page_attr_arb_set; + wire [3:0] l2_cpu0_wr_partial_dw_arb_set; + wire l2_cpu0_wr_priv_arb_set; + wire [1:0] l2_cpu0_wr_shared_arb_set; + wire [2:0] l2_cpu0_wr_type_arb_set; + wire l2_cpu0_wr_vld_skid; + wire l2_cpu0_wr_way_arb_set; + wire l2_cpu0_wrq_almost_full; + wire [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; + wire l2_cpu0_wrq_haz_pending; + wire l2_cpu1_arb_thrshld_timeout_en; + wire l2_cpu1_barrier_done; + wire l2_cpu1_blk_non_evict_wr; + wire l2_cpu1_ccb_dbg_req_c3; + wire [48:0] l2_cpu1_ccb_req_addr_c3; + wire [4:0] l2_cpu1_ccb_req_id_c3; + wire [23:0] l2_cpu1_ccb_req_info_c3; + wire [8:0] l2_cpu1_ccb_req_type_c3; + wire l2_cpu1_cfg_ecc_en; + wire [2:0] l2_cpu1_dbufid_r1; + wire [129:0] l2_cpu1_ddata_r2; + wire l2_cpu1_ddlb_ecc_err_r3; + wire l2_cpu1_dext_err_r2; + wire l2_cpu1_dext_err_type_r2; + wire l2_cpu1_disable_clean_evict_opt; + wire l2_cpu1_dlast_r1; + wire l2_cpu1_dsngl_ecc_err_r3; + wire [3:0] l2_cpu1_dsq_clr_id_q; + wire l2_cpu1_dsq_clr_vld_q; + wire [3:0] l2_cpu1_dsq_rd_buf_id; + wire [15:0] l2_cpu1_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu1_dsq_rd_data_q; + wire l2_cpu1_dsq_rd_en; + wire l2_cpu1_dsq_rd_en_x2; + wire l2_cpu1_dt_pmu_evt_en; + wire l2_cpu1_dvalid_r1; + wire l2_cpu1_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; + wire l2_cpu1_flsh_if_rd_l4_dly; + wire l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; + wire l2_cpu1_flsh_ls_rd_l2_dly; + wire l2_cpu1_flsh_ls_rd_l4_dly; + wire l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; + wire l2_cpu1_flsh_ls_wr_l2_dly; + wire l2_cpu1_flsh_ls_wr_l4_dly; + wire l2_cpu1_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu1_ibufid_r1; + wire [15:0] l2_cpu1_ic_addr_arb_set; + wire l2_cpu1_ic_arb_fast; + wire l2_cpu1_ic_barrier_stall_q; + wire [43:18] l2_cpu1_ic_base; + wire [31:0] l2_cpu1_ic_data_arb_set; + wire [2:0] l2_cpu1_ic_elem_size_arb_set; + wire l2_cpu1_ic_excl_arb_set; + wire [2:0] l2_cpu1_ic_id_arb_set; + wire l2_cpu1_ic_ns_arb_set; + wire l2_cpu1_ic_vld_skid; + wire l2_cpu1_ic_write_arb_set; + wire [127:0] l2_cpu1_idata_r2; + wire l2_cpu1_idlb_ecc_err_r3; + wire l2_cpu1_idle_block_reqs_q; + wire l2_cpu1_idle_wakeup_q; + wire l2_cpu1_iext_err_r2; + wire l2_cpu1_iext_err_type_r2; + wire l2_cpu1_if_ccb_clken_c3; + wire l2_cpu1_if_ccb_req_c3; + wire l2_cpu1_if_ccb_resp; + wire [4:0] l2_cpu1_if_ccb_resp_id; + wire l2_cpu1_if_sync_done_q; + wire l2_cpu1_if_sync_req; + wire l2_cpu1_ifq_haz_pending; + wire l2_cpu1_isngl_ecc_err_r3; + wire l2_cpu1_ivalid_r1; + wire [1:0] l2_cpu1_l2_cache_size; + wire [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; + wire l2_cpu1_lrq_haz_pending; + wire l2_cpu1_ls_ccb_clken_c3; + wire l2_cpu1_ls_ccb_data_wr; + wire l2_cpu1_ls_ccb_req_c3; + wire l2_cpu1_ls_ccb_resp; + wire [4:0] l2_cpu1_ls_ccb_resp_id; + wire l2_cpu1_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu1_ls_rd_haz_id_arb_q; + wire l2_cpu1_ls_rd_haz_vld_arb_q; + wire l2_cpu1_ls_sync_req; + wire [4:0] l2_cpu1_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu1_ls_wr_data_w2a; + wire l2_cpu1_ls_wr_dirty_w2a; + wire l2_cpu1_ls_wr_err_w2a; + wire [2:0] l2_cpu1_ls_wr_haz_id_arb_q; + wire l2_cpu1_ls_wr_haz_vld_arb_q; + wire l2_cpu1_ls_wr_last_w2a; + wire l2_cpu1_ls_wr_req_w2a; + wire [2:0] l2_cpu1_ls_wr_type_w2a; + wire [12:0] l2_cpu1_mbist1_addr_b1; + wire l2_cpu1_mbist1_all_b1; + wire [3:0] l2_cpu1_mbist1_array_b1; + wire [7:0] l2_cpu1_mbist1_be_b1; + wire l2_cpu1_mbist1_en_b1; + wire l2_cpu1_mbist1_rd_en_b1; + wire l2_cpu1_mbist1_wr_en_b1; + wire l2_cpu1_no_intctrl; + wire l2_cpu1_pf_rd_vld_skid_popped; + wire l2_cpu1_pf_throttle_q; + wire [33:0] l2_cpu1_pmu_events; + wire [2:0] l2_cpu1_rbufid; + wire l2_cpu1_rd_aarch64_arb_set; + wire [44:0] l2_cpu1_rd_addr_arb_set; + wire l2_cpu1_rd_arb; + wire l2_cpu1_rd_arb_fast; + wire [15:8] l2_cpu1_rd_asid_arb_set; + wire l2_cpu1_rd_bypass_arb_set; + wire [2:0] l2_cpu1_rd_bypass_bufid_e5; + wire [2:0] l2_cpu1_rd_bypass_lrq_id_e5; + wire l2_cpu1_rd_bypass_req_can_e5; + wire l2_cpu1_rd_bypass_way_e5; + wire [2:0] l2_cpu1_rd_cache_attr_arb_set; + wire [2:0] l2_cpu1_rd_elem_size_arb_set; + wire l2_cpu1_rd_excl_arb_set; + wire [4:0] l2_cpu1_rd_id_arb_set; + wire [2:0] l2_cpu1_rd_lrq_id_arb_set; + wire [7:0] l2_cpu1_rd_page_attr_arb_set; + wire l2_cpu1_rd_prfm_arb_set; + wire l2_cpu1_rd_priv_arb_set; + wire l2_cpu1_rd_replayed_arb_set; + wire [1:0] l2_cpu1_rd_shared_arb_set; + wire [6:0] l2_cpu1_rd_type_arb_set; + wire l2_cpu1_rd_va48_arb_set; + wire l2_cpu1_rd_vld_skid; + wire l2_cpu1_rd_way_arb_set; + wire l2_cpu1_rexfail; + wire [1:0] l2_cpu1_rstate; + wire l2_cpu1_rvalid; + wire [2:0] l2_cpu1_spec_bufid; + wire l2_cpu1_spec_valid; + wire [63:0] l2_cpu1_spr_rd_data; + wire l2_cpu1_tbw_dbl_ecc_err; + wire [63:0] l2_cpu1_tbw_desc_data; + wire l2_cpu1_tbw_desc_vld; + wire l2_cpu1_tbw_ext_err; + wire l2_cpu1_tbw_ext_err_type; + wire l2_cpu1_tlb_ccb_clken_c3; + wire l2_cpu1_tlb_ccb_req_c3; + wire l2_cpu1_tlb_sync_complete; + wire l2_cpu1_tlb_sync_done_q; + wire l2_cpu1_tlb_sync_req; + wire l2_cpu1_trq_haz_pending; + wire l2_cpu1_tw_ccb_resp; + wire [4:0] l2_cpu1_tw_ccb_resp_id; + wire l2_cpu1_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu1_wr_addr_arb_set; + wire l2_cpu1_wr_arb; + wire l2_cpu1_wr_arb_fast; + wire [2:0] l2_cpu1_wr_cache_attr_arb_set; + wire [11:0] l2_cpu1_wr_cl_id_arb_set; + wire l2_cpu1_wr_clean_evict_arb_set; + wire [143:0] l2_cpu1_wr_data; + wire l2_cpu1_wr_data_stall; + wire l2_cpu1_wr_data_vld_x1_q; + wire l2_cpu1_wr_dirty_arb_set; + wire [2:0] l2_cpu1_wr_elem_size_arb_set; + wire l2_cpu1_wr_err_arb_set; + wire l2_cpu1_wr_evict_x1_q; + wire l2_cpu1_wr_ex_fail; + wire l2_cpu1_wr_ex_resp; + wire [3:0] l2_cpu1_wr_id_arb_set; + wire l2_cpu1_wr_last_arb_set; + wire [7:0] l2_cpu1_wr_page_attr_arb_set; + wire [3:0] l2_cpu1_wr_partial_dw_arb_set; + wire l2_cpu1_wr_priv_arb_set; + wire [1:0] l2_cpu1_wr_shared_arb_set; + wire [2:0] l2_cpu1_wr_type_arb_set; + wire l2_cpu1_wr_vld_skid; + wire l2_cpu1_wr_way_arb_set; + wire l2_cpu1_wrq_almost_full; + wire [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; + wire l2_cpu1_wrq_haz_pending; + wire l2_cpu2_arb_thrshld_timeout_en; + wire l2_cpu2_barrier_done; + wire l2_cpu2_blk_non_evict_wr; + wire l2_cpu2_ccb_dbg_req_c3; + wire [48:0] l2_cpu2_ccb_req_addr_c3; + wire [4:0] l2_cpu2_ccb_req_id_c3; + wire [23:0] l2_cpu2_ccb_req_info_c3; + wire [8:0] l2_cpu2_ccb_req_type_c3; + wire l2_cpu2_cfg_ecc_en; + wire [2:0] l2_cpu2_dbufid_r1; + wire [129:0] l2_cpu2_ddata_r2; + wire l2_cpu2_ddlb_ecc_err_r3; + wire l2_cpu2_dext_err_r2; + wire l2_cpu2_dext_err_type_r2; + wire l2_cpu2_disable_clean_evict_opt; + wire l2_cpu2_dlast_r1; + wire l2_cpu2_dsngl_ecc_err_r3; + wire [3:0] l2_cpu2_dsq_clr_id_q; + wire l2_cpu2_dsq_clr_vld_q; + wire [3:0] l2_cpu2_dsq_rd_buf_id; + wire [15:0] l2_cpu2_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu2_dsq_rd_data_q; + wire l2_cpu2_dsq_rd_en; + wire l2_cpu2_dsq_rd_en_x2; + wire l2_cpu2_dt_pmu_evt_en; + wire l2_cpu2_dvalid_r1; + wire l2_cpu2_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; + wire l2_cpu2_flsh_if_rd_l4_dly; + wire l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; + wire l2_cpu2_flsh_ls_rd_l2_dly; + wire l2_cpu2_flsh_ls_rd_l4_dly; + wire l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; + wire l2_cpu2_flsh_ls_wr_l2_dly; + wire l2_cpu2_flsh_ls_wr_l4_dly; + wire l2_cpu2_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu2_ibufid_r1; + wire [15:0] l2_cpu2_ic_addr_arb_set; + wire l2_cpu2_ic_arb_fast; + wire l2_cpu2_ic_barrier_stall_q; + wire [43:18] l2_cpu2_ic_base; + wire [31:0] l2_cpu2_ic_data_arb_set; + wire [2:0] l2_cpu2_ic_elem_size_arb_set; + wire l2_cpu2_ic_excl_arb_set; + wire [2:0] l2_cpu2_ic_id_arb_set; + wire l2_cpu2_ic_ns_arb_set; + wire l2_cpu2_ic_vld_skid; + wire l2_cpu2_ic_write_arb_set; + wire [127:0] l2_cpu2_idata_r2; + wire l2_cpu2_idlb_ecc_err_r3; + wire l2_cpu2_idle_block_reqs_q; + wire l2_cpu2_idle_wakeup_q; + wire l2_cpu2_iext_err_r2; + wire l2_cpu2_iext_err_type_r2; + wire l2_cpu2_if_ccb_clken_c3; + wire l2_cpu2_if_ccb_req_c3; + wire l2_cpu2_if_ccb_resp; + wire [4:0] l2_cpu2_if_ccb_resp_id; + wire l2_cpu2_if_sync_done_q; + wire l2_cpu2_if_sync_req; + wire l2_cpu2_ifq_haz_pending; + wire l2_cpu2_isngl_ecc_err_r3; + wire l2_cpu2_ivalid_r1; + wire [1:0] l2_cpu2_l2_cache_size; + wire [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; + wire l2_cpu2_lrq_haz_pending; + wire l2_cpu2_ls_ccb_clken_c3; + wire l2_cpu2_ls_ccb_data_wr; + wire l2_cpu2_ls_ccb_req_c3; + wire l2_cpu2_ls_ccb_resp; + wire [4:0] l2_cpu2_ls_ccb_resp_id; + wire l2_cpu2_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu2_ls_rd_haz_id_arb_q; + wire l2_cpu2_ls_rd_haz_vld_arb_q; + wire l2_cpu2_ls_sync_req; + wire [4:0] l2_cpu2_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu2_ls_wr_data_w2a; + wire l2_cpu2_ls_wr_dirty_w2a; + wire l2_cpu2_ls_wr_err_w2a; + wire [2:0] l2_cpu2_ls_wr_haz_id_arb_q; + wire l2_cpu2_ls_wr_haz_vld_arb_q; + wire l2_cpu2_ls_wr_last_w2a; + wire l2_cpu2_ls_wr_req_w2a; + wire [2:0] l2_cpu2_ls_wr_type_w2a; + wire [12:0] l2_cpu2_mbist1_addr_b1; + wire l2_cpu2_mbist1_all_b1; + wire [3:0] l2_cpu2_mbist1_array_b1; + wire [7:0] l2_cpu2_mbist1_be_b1; + wire l2_cpu2_mbist1_en_b1; + wire l2_cpu2_mbist1_rd_en_b1; + wire l2_cpu2_mbist1_wr_en_b1; + wire l2_cpu2_no_intctrl; + wire l2_cpu2_pf_rd_vld_skid_popped; + wire l2_cpu2_pf_throttle_q; + wire [33:0] l2_cpu2_pmu_events; + wire [2:0] l2_cpu2_rbufid; + wire l2_cpu2_rd_aarch64_arb_set; + wire [44:0] l2_cpu2_rd_addr_arb_set; + wire l2_cpu2_rd_arb; + wire l2_cpu2_rd_arb_fast; + wire [15:8] l2_cpu2_rd_asid_arb_set; + wire l2_cpu2_rd_bypass_arb_set; + wire [2:0] l2_cpu2_rd_bypass_bufid_e5; + wire [2:0] l2_cpu2_rd_bypass_lrq_id_e5; + wire l2_cpu2_rd_bypass_req_can_e5; + wire l2_cpu2_rd_bypass_way_e5; + wire [2:0] l2_cpu2_rd_cache_attr_arb_set; + wire [2:0] l2_cpu2_rd_elem_size_arb_set; + wire l2_cpu2_rd_excl_arb_set; + wire [4:0] l2_cpu2_rd_id_arb_set; + wire [2:0] l2_cpu2_rd_lrq_id_arb_set; + wire [7:0] l2_cpu2_rd_page_attr_arb_set; + wire l2_cpu2_rd_prfm_arb_set; + wire l2_cpu2_rd_priv_arb_set; + wire l2_cpu2_rd_replayed_arb_set; + wire [1:0] l2_cpu2_rd_shared_arb_set; + wire [6:0] l2_cpu2_rd_type_arb_set; + wire l2_cpu2_rd_va48_arb_set; + wire l2_cpu2_rd_vld_skid; + wire l2_cpu2_rd_way_arb_set; + wire l2_cpu2_rexfail; + wire [1:0] l2_cpu2_rstate; + wire l2_cpu2_rvalid; + wire [2:0] l2_cpu2_spec_bufid; + wire l2_cpu2_spec_valid; + wire [63:0] l2_cpu2_spr_rd_data; + wire l2_cpu2_tbw_dbl_ecc_err; + wire [63:0] l2_cpu2_tbw_desc_data; + wire l2_cpu2_tbw_desc_vld; + wire l2_cpu2_tbw_ext_err; + wire l2_cpu2_tbw_ext_err_type; + wire l2_cpu2_tlb_ccb_clken_c3; + wire l2_cpu2_tlb_ccb_req_c3; + wire l2_cpu2_tlb_sync_complete; + wire l2_cpu2_tlb_sync_done_q; + wire l2_cpu2_tlb_sync_req; + wire l2_cpu2_trq_haz_pending; + wire l2_cpu2_tw_ccb_resp; + wire [4:0] l2_cpu2_tw_ccb_resp_id; + wire l2_cpu2_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu2_wr_addr_arb_set; + wire l2_cpu2_wr_arb; + wire l2_cpu2_wr_arb_fast; + wire [2:0] l2_cpu2_wr_cache_attr_arb_set; + wire [11:0] l2_cpu2_wr_cl_id_arb_set; + wire l2_cpu2_wr_clean_evict_arb_set; + wire [143:0] l2_cpu2_wr_data; + wire l2_cpu2_wr_data_stall; + wire l2_cpu2_wr_data_vld_x1_q; + wire l2_cpu2_wr_dirty_arb_set; + wire [2:0] l2_cpu2_wr_elem_size_arb_set; + wire l2_cpu2_wr_err_arb_set; + wire l2_cpu2_wr_evict_x1_q; + wire l2_cpu2_wr_ex_fail; + wire l2_cpu2_wr_ex_resp; + wire [3:0] l2_cpu2_wr_id_arb_set; + wire l2_cpu2_wr_last_arb_set; + wire [7:0] l2_cpu2_wr_page_attr_arb_set; + wire [3:0] l2_cpu2_wr_partial_dw_arb_set; + wire l2_cpu2_wr_priv_arb_set; + wire [1:0] l2_cpu2_wr_shared_arb_set; + wire [2:0] l2_cpu2_wr_type_arb_set; + wire l2_cpu2_wr_vld_skid; + wire l2_cpu2_wr_way_arb_set; + wire l2_cpu2_wrq_almost_full; + wire [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; + wire l2_cpu2_wrq_haz_pending; + wire l2_cpu3_arb_thrshld_timeout_en; + wire l2_cpu3_barrier_done; + wire l2_cpu3_blk_non_evict_wr; + wire l2_cpu3_ccb_dbg_req_c3; + wire [48:0] l2_cpu3_ccb_req_addr_c3; + wire [4:0] l2_cpu3_ccb_req_id_c3; + wire [23:0] l2_cpu3_ccb_req_info_c3; + wire [8:0] l2_cpu3_ccb_req_type_c3; + wire l2_cpu3_cfg_ecc_en; + wire [2:0] l2_cpu3_dbufid_r1; + wire [129:0] l2_cpu3_ddata_r2; + wire l2_cpu3_ddlb_ecc_err_r3; + wire l2_cpu3_dext_err_r2; + wire l2_cpu3_dext_err_type_r2; + wire l2_cpu3_disable_clean_evict_opt; + wire l2_cpu3_dlast_r1; + wire l2_cpu3_dsngl_ecc_err_r3; + wire [3:0] l2_cpu3_dsq_clr_id_q; + wire l2_cpu3_dsq_clr_vld_q; + wire [3:0] l2_cpu3_dsq_rd_buf_id; + wire [15:0] l2_cpu3_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu3_dsq_rd_data_q; + wire l2_cpu3_dsq_rd_en; + wire l2_cpu3_dsq_rd_en_x2; + wire l2_cpu3_dt_pmu_evt_en; + wire l2_cpu3_dvalid_r1; + wire l2_cpu3_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; + wire l2_cpu3_flsh_if_rd_l4_dly; + wire l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; + wire l2_cpu3_flsh_ls_rd_l2_dly; + wire l2_cpu3_flsh_ls_rd_l4_dly; + wire l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; + wire l2_cpu3_flsh_ls_wr_l2_dly; + wire l2_cpu3_flsh_ls_wr_l4_dly; + wire l2_cpu3_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu3_ibufid_r1; + wire [15:0] l2_cpu3_ic_addr_arb_set; + wire l2_cpu3_ic_arb_fast; + wire l2_cpu3_ic_barrier_stall_q; + wire [43:18] l2_cpu3_ic_base; + wire [31:0] l2_cpu3_ic_data_arb_set; + wire [2:0] l2_cpu3_ic_elem_size_arb_set; + wire l2_cpu3_ic_excl_arb_set; + wire [2:0] l2_cpu3_ic_id_arb_set; + wire l2_cpu3_ic_ns_arb_set; + wire l2_cpu3_ic_vld_skid; + wire l2_cpu3_ic_write_arb_set; + wire [127:0] l2_cpu3_idata_r2; + wire l2_cpu3_idlb_ecc_err_r3; + wire l2_cpu3_idle_block_reqs_q; + wire l2_cpu3_idle_wakeup_q; + wire l2_cpu3_iext_err_r2; + wire l2_cpu3_iext_err_type_r2; + wire l2_cpu3_if_ccb_clken_c3; + wire l2_cpu3_if_ccb_req_c3; + wire l2_cpu3_if_ccb_resp; + wire [4:0] l2_cpu3_if_ccb_resp_id; + wire l2_cpu3_if_sync_done_q; + wire l2_cpu3_if_sync_req; + wire l2_cpu3_ifq_haz_pending; + wire l2_cpu3_isngl_ecc_err_r3; + wire l2_cpu3_ivalid_r1; + wire [1:0] l2_cpu3_l2_cache_size; + wire [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; + wire l2_cpu3_lrq_haz_pending; + wire l2_cpu3_ls_ccb_clken_c3; + wire l2_cpu3_ls_ccb_data_wr; + wire l2_cpu3_ls_ccb_req_c3; + wire l2_cpu3_ls_ccb_resp; + wire [4:0] l2_cpu3_ls_ccb_resp_id; + wire l2_cpu3_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu3_ls_rd_haz_id_arb_q; + wire l2_cpu3_ls_rd_haz_vld_arb_q; + wire l2_cpu3_ls_sync_req; + wire [4:0] l2_cpu3_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu3_ls_wr_data_w2a; + wire l2_cpu3_ls_wr_dirty_w2a; + wire l2_cpu3_ls_wr_err_w2a; + wire [2:0] l2_cpu3_ls_wr_haz_id_arb_q; + wire l2_cpu3_ls_wr_haz_vld_arb_q; + wire l2_cpu3_ls_wr_last_w2a; + wire l2_cpu3_ls_wr_req_w2a; + wire [2:0] l2_cpu3_ls_wr_type_w2a; + wire [12:0] l2_cpu3_mbist1_addr_b1; + wire l2_cpu3_mbist1_all_b1; + wire [3:0] l2_cpu3_mbist1_array_b1; + wire [7:0] l2_cpu3_mbist1_be_b1; + wire l2_cpu3_mbist1_en_b1; + wire l2_cpu3_mbist1_rd_en_b1; + wire l2_cpu3_mbist1_wr_en_b1; + wire l2_cpu3_no_intctrl; + wire l2_cpu3_pf_rd_vld_skid_popped; + wire l2_cpu3_pf_throttle_q; + wire [33:0] l2_cpu3_pmu_events; + wire [2:0] l2_cpu3_rbufid; + wire l2_cpu3_rd_aarch64_arb_set; + wire [44:0] l2_cpu3_rd_addr_arb_set; + wire l2_cpu3_rd_arb; + wire l2_cpu3_rd_arb_fast; + wire [15:8] l2_cpu3_rd_asid_arb_set; + wire l2_cpu3_rd_bypass_arb_set; + wire [2:0] l2_cpu3_rd_bypass_bufid_e5; + wire [2:0] l2_cpu3_rd_bypass_lrq_id_e5; + wire l2_cpu3_rd_bypass_req_can_e5; + wire l2_cpu3_rd_bypass_way_e5; + wire [2:0] l2_cpu3_rd_cache_attr_arb_set; + wire [2:0] l2_cpu3_rd_elem_size_arb_set; + wire l2_cpu3_rd_excl_arb_set; + wire [4:0] l2_cpu3_rd_id_arb_set; + wire [2:0] l2_cpu3_rd_lrq_id_arb_set; + wire [7:0] l2_cpu3_rd_page_attr_arb_set; + wire l2_cpu3_rd_prfm_arb_set; + wire l2_cpu3_rd_priv_arb_set; + wire l2_cpu3_rd_replayed_arb_set; + wire [1:0] l2_cpu3_rd_shared_arb_set; + wire [6:0] l2_cpu3_rd_type_arb_set; + wire l2_cpu3_rd_va48_arb_set; + wire l2_cpu3_rd_vld_skid; + wire l2_cpu3_rd_way_arb_set; + wire l2_cpu3_rexfail; + wire [1:0] l2_cpu3_rstate; + wire l2_cpu3_rvalid; + wire [2:0] l2_cpu3_spec_bufid; + wire l2_cpu3_spec_valid; + wire [63:0] l2_cpu3_spr_rd_data; + wire l2_cpu3_tbw_dbl_ecc_err; + wire [63:0] l2_cpu3_tbw_desc_data; + wire l2_cpu3_tbw_desc_vld; + wire l2_cpu3_tbw_ext_err; + wire l2_cpu3_tbw_ext_err_type; + wire l2_cpu3_tlb_ccb_clken_c3; + wire l2_cpu3_tlb_ccb_req_c3; + wire l2_cpu3_tlb_sync_complete; + wire l2_cpu3_tlb_sync_done_q; + wire l2_cpu3_tlb_sync_req; + wire l2_cpu3_trq_haz_pending; + wire l2_cpu3_tw_ccb_resp; + wire [4:0] l2_cpu3_tw_ccb_resp_id; + wire l2_cpu3_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu3_wr_addr_arb_set; + wire l2_cpu3_wr_arb; + wire l2_cpu3_wr_arb_fast; + wire [2:0] l2_cpu3_wr_cache_attr_arb_set; + wire [11:0] l2_cpu3_wr_cl_id_arb_set; + wire l2_cpu3_wr_clean_evict_arb_set; + wire [143:0] l2_cpu3_wr_data; + wire l2_cpu3_wr_data_stall; + wire l2_cpu3_wr_data_vld_x1_q; + wire l2_cpu3_wr_dirty_arb_set; + wire [2:0] l2_cpu3_wr_elem_size_arb_set; + wire l2_cpu3_wr_err_arb_set; + wire l2_cpu3_wr_evict_x1_q; + wire l2_cpu3_wr_ex_fail; + wire l2_cpu3_wr_ex_resp; + wire [3:0] l2_cpu3_wr_id_arb_set; + wire l2_cpu3_wr_last_arb_set; + wire [7:0] l2_cpu3_wr_page_attr_arb_set; + wire [3:0] l2_cpu3_wr_partial_dw_arb_set; + wire l2_cpu3_wr_priv_arb_set; + wire [1:0] l2_cpu3_wr_shared_arb_set; + wire [2:0] l2_cpu3_wr_type_arb_set; + wire l2_cpu3_wr_vld_skid; + wire l2_cpu3_wr_way_arb_set; + wire l2_cpu3_wrq_almost_full; + wire [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; + wire l2_cpu3_wrq_haz_pending; + wire [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu0_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu1_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu2_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu3_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu0_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu1_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu2_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu3_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; + wire ls_cpu0_clrexmon; + wire ls_cpu0_imp_abort_containable; + wire ls_cpu0_imp_abort_dec; + wire ls_cpu0_imp_abort_ecc; + wire ls_cpu0_imp_abort_slv; + wire ls_cpu0_raw_eae_nonsec; + wire ls_cpu0_raw_eae_secure; + wire ls_cpu1_clrexmon; + wire ls_cpu1_imp_abort_containable; + wire ls_cpu1_imp_abort_dec; + wire ls_cpu1_imp_abort_ecc; + wire ls_cpu1_imp_abort_slv; + wire ls_cpu1_raw_eae_nonsec; + wire ls_cpu1_raw_eae_secure; + wire ls_cpu2_clrexmon; + wire ls_cpu2_imp_abort_containable; + wire ls_cpu2_imp_abort_dec; + wire ls_cpu2_imp_abort_ecc; + wire ls_cpu2_imp_abort_slv; + wire ls_cpu2_raw_eae_nonsec; + wire ls_cpu2_raw_eae_secure; + wire ls_cpu3_clrexmon; + wire ls_cpu3_imp_abort_containable; + wire ls_cpu3_imp_abort_dec; + wire ls_cpu3_imp_abort_ecc; + wire ls_cpu3_imp_abort_slv; + wire ls_cpu3_raw_eae_nonsec; + wire ls_cpu3_raw_eae_secure; + wire ncommirq_cpu0_i; + wire ncommirq_cpu1_i; + wire ncommirq_cpu2_i; + wire ncommirq_cpu3_i; + wire ncorereset_cpu0_o; + wire ncorereset_cpu1_o; + wire ncorereset_cpu2_o; + wire ncorereset_cpu3_o; + wire ncpuporeset_cpu0_o; + wire ncpuporeset_cpu1_o; + wire ncpuporeset_cpu2_o; + wire ncpuporeset_cpu3_o; + wire niden_cpu0_o; + wire niden_cpu1_o; + wire niden_cpu2_o; + wire niden_cpu3_o; + wire nmbistreset_cpu0_o; + wire nmbistreset_cpu1_o; + wire nmbistreset_cpu2_o; + wire nmbistreset_cpu3_o; + wire npmuirq_cpu0_i; + wire npmuirq_cpu1_i; + wire npmuirq_cpu2_i; + wire npmuirq_cpu3_i; + wire pm_export_cpu0_i; + wire pm_export_cpu1_i; + wire pm_export_cpu2_i; + wire pm_export_cpu3_i; + wire [24:0] pmuevent_cpu0_i; + wire [24:0] pmuevent_cpu1_i; + wire [24:0] pmuevent_cpu2_i; + wire [24:0] pmuevent_cpu3_i; + wire [43:2] rvbaraddr_cpu0_o; + wire [43:2] rvbaraddr_cpu1_o; + wire [43:2] rvbaraddr_cpu2_o; + wire [43:2] rvbaraddr_cpu3_o; + wire spiden_cpu0_o; + wire spiden_cpu1_o; + wire spiden_cpu2_o; + wire spiden_cpu3_o; + wire spniden_cpu0_o; + wire spniden_cpu1_o; + wire spniden_cpu2_o; + wire spniden_cpu3_o; + wire syncreqm_cpu0_o; + wire syncreqm_cpu1_o; + wire syncreqm_cpu2_o; + wire syncreqm_cpu3_o; + wire [1:0] tm_cpu0_cnthctl_kernel; + wire [3:0] tm_cpu0_cntkctl_usr; + wire [1:0] tm_cpu1_cnthctl_kernel; + wire [3:0] tm_cpu1_cntkctl_usr; + wire [1:0] tm_cpu2_cnthctl_kernel; + wire [3:0] tm_cpu2_cntkctl_usr; + wire [1:0] tm_cpu3_cnthctl_kernel; + wire [3:0] tm_cpu3_cntkctl_usr; + wire [63:0] tsvalueb_cpu0_o; + wire [63:0] tsvalueb_cpu1_o; + wire [63:0] tsvalueb_cpu2_o; + wire [63:0] tsvalueb_cpu3_o; + wire vinithi_cpu0_o; + wire vinithi_cpu1_o; + wire vinithi_cpu2_o; + wire vinithi_cpu3_o; + + maia_cpu ucpu0( // outputs + .afreadym_cpu (afreadym_cpu0_i), + .atbytesm_cpu (atbytesm_cpu0_i[1:0]), + .atdatam_cpu (atdatam_cpu0_i[31:0]), + .atidm_cpu (atidm_cpu0_i[6:0]), + .atvalidm_cpu (atvalidm_cpu0_i), + .commrx_cpu (commrx_cpu0_i), + .commtx_cpu (commtx_cpu0_i), + .dbgack_cpu (dbgack_cpu0_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu0_i), + .dbgrstreq_cpu (dbgrstreq_cpu0_i), + .ds_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_flush (ds_cpu0_flush), + .ds_flush_type (ds_cpu0_flush_type[5:0]), + .ds_hcr_va (ds_cpu0_hcr_va), + .ds_hcr_vf (ds_cpu0_hcr_vf), + .ds_hcr_vi (ds_cpu0_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu0_reset_req), + .ds_sev_req (ds_cpu0_sev_req), + .ds_sevl_req (ds_cpu0_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_wfe_req (ds_cpu0_wfe_req), + .ds_wfi_req (ds_cpu0_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu0_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu0_clrexmon), + .ls_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu0_i), + .npmuirq_cpu (npmuirq_cpu0_i), + .pm_export_cpu (pm_export_cpu0_i), + .pmuevent_cpu (pmuevent_cpu0_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu0_o), + .afvalidm_cpu (afvalidm_cpu0_o), + .atclken_cpu (atclken_cpu0_o), + .atreadym_cpu (atreadym_cpu0_o), + .cfgend_cpu (cfgend_cpu0_o), + .cfgte_cpu (cfgte_cpu0_o), + .ck_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_event_reg (ck_cpu0_event_reg), + .ck_gclkt (ck_gclkt[0]), + .ck_wfe_ack (ck_cpu0_wfe_ack), + .ck_wfi_ack (ck_cpu0_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu0_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu0_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu0_o), + .cpuid (cpuid_cpu0_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu0_o), + .dbgen_cpu (dbgen_cpu0_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu0_o), + .dbgromaddr_cpu (dbgromaddr_cpu0_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu0_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu0_o), + .dftramhold_cpu (dftramhold_cpu0_o), + .dftrstdisable_cpu (dftrstdisable_cpu0_o), + .dftse_cpu (dftse_cpu0_o), + .dt_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu0_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[0]), + .ic_el_change_complete (ic_el_change_complete[0]), + .ic_hcr_change_complete (ic_hcr_change_complete[0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[0]), + .ic_ich_el2_tc (ic_ich_el2_tc[0]), + .ic_nfiq (ic_nfiq[0]), + .ic_nirq (ic_nirq[0]), + .ic_nsei (ic_nsei[0]), + .ic_nvfiq (ic_nvfiq[0]), + .ic_nvirq (ic_nvirq[0]), + .ic_nvsei (ic_nvsei[0]), + .ic_p_valid (ic_p_valid[0]), + .ic_sample_spr (ic_sample_spr[0]), + .ic_scr_change_complete (ic_scr_change_complete[0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[0]), + .ic_sra_el1s_en (ic_sra_el1s_en[0]), + .ic_sra_el2_en (ic_sra_el2_en[0]), + .ic_sra_el3_en (ic_sra_el3_en[0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[0]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu0_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu0_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu0_rexfail), + .l2_cpu_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu0_rvalid), + .l2_cpu_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu0_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu0_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu0_o), + .ncpuporeset_cpu (ncpuporeset_cpu0_o), + .niden_cpu (niden_cpu0_o), + .nmbistreset_cpu (nmbistreset_cpu0_o), + .rvbaraddr_cpu (rvbaraddr_cpu0_o[43:2]), + .spiden_cpu (spiden_cpu0_o), + .spniden_cpu (spniden_cpu0_o), + .syncreqm_cpu (syncreqm_cpu0_o), + .tm_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu0_o[63:0]), + .vinithi_cpu (vinithi_cpu0_o) + ); // ucpu0 + + maia_cpu ucpu1( // outputs + .afreadym_cpu (afreadym_cpu1_i), + .atbytesm_cpu (atbytesm_cpu1_i[1:0]), + .atdatam_cpu (atdatam_cpu1_i[31:0]), + .atidm_cpu (atidm_cpu1_i[6:0]), + .atvalidm_cpu (atvalidm_cpu1_i), + .commrx_cpu (commrx_cpu1_i), + .commtx_cpu (commtx_cpu1_i), + .dbgack_cpu (dbgack_cpu1_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu1_i), + .dbgrstreq_cpu (dbgrstreq_cpu1_i), + .ds_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_flush (ds_cpu1_flush), + .ds_flush_type (ds_cpu1_flush_type[5:0]), + .ds_hcr_va (ds_cpu1_hcr_va), + .ds_hcr_vf (ds_cpu1_hcr_vf), + .ds_hcr_vi (ds_cpu1_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu1_reset_req), + .ds_sev_req (ds_cpu1_sev_req), + .ds_sevl_req (ds_cpu1_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_wfe_req (ds_cpu1_wfe_req), + .ds_wfi_req (ds_cpu1_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu1_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu1_clrexmon), + .ls_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu1_i), + .npmuirq_cpu (npmuirq_cpu1_i), + .pm_export_cpu (pm_export_cpu1_i), + .pmuevent_cpu (pmuevent_cpu1_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu1_o), + .afvalidm_cpu (afvalidm_cpu1_o), + .atclken_cpu (atclken_cpu1_o), + .atreadym_cpu (atreadym_cpu1_o), + .cfgend_cpu (cfgend_cpu1_o), + .cfgte_cpu (cfgte_cpu1_o), + .ck_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_event_reg (ck_cpu1_event_reg), + .ck_gclkt (ck_gclkt[1]), + .ck_wfe_ack (ck_cpu1_wfe_ack), + .ck_wfi_ack (ck_cpu1_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu1_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu1_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu1_o), + .cpuid (cpuid_cpu1_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu1_o), + .dbgen_cpu (dbgen_cpu1_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu1_o), + .dbgromaddr_cpu (dbgromaddr_cpu1_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu1_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu1_o), + .dftramhold_cpu (dftramhold_cpu1_o), + .dftrstdisable_cpu (dftrstdisable_cpu1_o), + .dftse_cpu (dftse_cpu1_o), + .dt_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu1_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[1]), + .ic_el_change_complete (ic_el_change_complete[1]), + .ic_hcr_change_complete (ic_hcr_change_complete[1]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[1]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[1]), + .ic_ich_el2_tc (ic_ich_el2_tc[1]), + .ic_nfiq (ic_nfiq[1]), + .ic_nirq (ic_nirq[1]), + .ic_nsei (ic_nsei[1]), + .ic_nvfiq (ic_nvfiq[1]), + .ic_nvirq (ic_nvirq[1]), + .ic_nvsei (ic_nvsei[1]), + .ic_p_valid (ic_p_valid[1]), + .ic_sample_spr (ic_sample_spr[1]), + .ic_scr_change_complete (ic_scr_change_complete[1]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[1]), + .ic_sra_el1s_en (ic_sra_el1s_en[1]), + .ic_sra_el2_en (ic_sra_el2_en[1]), + .ic_sra_el3_en (ic_sra_el3_en[1]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[1]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[1]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[1]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[1]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu1_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu1_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu1_rexfail), + .l2_cpu_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu1_rvalid), + .l2_cpu_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu1_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu1_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu1_o), + .ncpuporeset_cpu (ncpuporeset_cpu1_o), + .niden_cpu (niden_cpu1_o), + .nmbistreset_cpu (nmbistreset_cpu1_o), + .rvbaraddr_cpu (rvbaraddr_cpu1_o[43:2]), + .spiden_cpu (spiden_cpu1_o), + .spniden_cpu (spniden_cpu1_o), + .syncreqm_cpu (syncreqm_cpu1_o), + .tm_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu1_o[63:0]), + .vinithi_cpu (vinithi_cpu1_o) + ); // ucpu1 + + maia_cpu ucpu2( // outputs + .afreadym_cpu (afreadym_cpu2_i), + .atbytesm_cpu (atbytesm_cpu2_i[1:0]), + .atdatam_cpu (atdatam_cpu2_i[31:0]), + .atidm_cpu (atidm_cpu2_i[6:0]), + .atvalidm_cpu (atvalidm_cpu2_i), + .commrx_cpu (commrx_cpu2_i), + .commtx_cpu (commtx_cpu2_i), + .dbgack_cpu (dbgack_cpu2_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu2_i), + .dbgrstreq_cpu (dbgrstreq_cpu2_i), + .ds_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_flush (ds_cpu2_flush), + .ds_flush_type (ds_cpu2_flush_type[5:0]), + .ds_hcr_va (ds_cpu2_hcr_va), + .ds_hcr_vf (ds_cpu2_hcr_vf), + .ds_hcr_vi (ds_cpu2_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu2_reset_req), + .ds_sev_req (ds_cpu2_sev_req), + .ds_sevl_req (ds_cpu2_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_wfe_req (ds_cpu2_wfe_req), + .ds_wfi_req (ds_cpu2_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu2_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu2_clrexmon), + .ls_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu2_i), + .npmuirq_cpu (npmuirq_cpu2_i), + .pm_export_cpu (pm_export_cpu2_i), + .pmuevent_cpu (pmuevent_cpu2_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu2_o), + .afvalidm_cpu (afvalidm_cpu2_o), + .atclken_cpu (atclken_cpu2_o), + .atreadym_cpu (atreadym_cpu2_o), + .cfgend_cpu (cfgend_cpu2_o), + .cfgte_cpu (cfgte_cpu2_o), + .ck_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_event_reg (ck_cpu2_event_reg), + .ck_gclkt (ck_gclkt[2]), + .ck_wfe_ack (ck_cpu2_wfe_ack), + .ck_wfi_ack (ck_cpu2_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu2_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu2_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu2_o), + .cpuid (cpuid_cpu2_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu2_o), + .dbgen_cpu (dbgen_cpu2_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu2_o), + .dbgromaddr_cpu (dbgromaddr_cpu2_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu2_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu2_o), + .dftramhold_cpu (dftramhold_cpu2_o), + .dftrstdisable_cpu (dftrstdisable_cpu2_o), + .dftse_cpu (dftse_cpu2_o), + .dt_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu2_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[2]), + .ic_el_change_complete (ic_el_change_complete[2]), + .ic_hcr_change_complete (ic_hcr_change_complete[2]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[2]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[2]), + .ic_ich_el2_tc (ic_ich_el2_tc[2]), + .ic_nfiq (ic_nfiq[2]), + .ic_nirq (ic_nirq[2]), + .ic_nsei (ic_nsei[2]), + .ic_nvfiq (ic_nvfiq[2]), + .ic_nvirq (ic_nvirq[2]), + .ic_nvsei (ic_nvsei[2]), + .ic_p_valid (ic_p_valid[2]), + .ic_sample_spr (ic_sample_spr[2]), + .ic_scr_change_complete (ic_scr_change_complete[2]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[2]), + .ic_sra_el1s_en (ic_sra_el1s_en[2]), + .ic_sra_el2_en (ic_sra_el2_en[2]), + .ic_sra_el3_en (ic_sra_el3_en[2]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[2]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[2]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[2]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[2]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu2_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu2_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu2_rexfail), + .l2_cpu_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu2_rvalid), + .l2_cpu_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu2_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu2_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu2_o), + .ncpuporeset_cpu (ncpuporeset_cpu2_o), + .niden_cpu (niden_cpu2_o), + .nmbistreset_cpu (nmbistreset_cpu2_o), + .rvbaraddr_cpu (rvbaraddr_cpu2_o[43:2]), + .spiden_cpu (spiden_cpu2_o), + .spniden_cpu (spniden_cpu2_o), + .syncreqm_cpu (syncreqm_cpu2_o), + .tm_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu2_o[63:0]), + .vinithi_cpu (vinithi_cpu2_o) + ); // ucpu2 + + maia_cpu ucpu3( // outputs + .afreadym_cpu (afreadym_cpu3_i), + .atbytesm_cpu (atbytesm_cpu3_i[1:0]), + .atdatam_cpu (atdatam_cpu3_i[31:0]), + .atidm_cpu (atidm_cpu3_i[6:0]), + .atvalidm_cpu (atvalidm_cpu3_i), + .commrx_cpu (commrx_cpu3_i), + .commtx_cpu (commtx_cpu3_i), + .dbgack_cpu (dbgack_cpu3_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu (dbgrstreq_cpu3_i), + .ds_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_flush (ds_cpu3_flush), + .ds_flush_type (ds_cpu3_flush_type[5:0]), + .ds_hcr_va (ds_cpu3_hcr_va), + .ds_hcr_vf (ds_cpu3_hcr_vf), + .ds_hcr_vi (ds_cpu3_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_ic_scr_change (ds_cpu3_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu3_reset_req), + .ds_sev_req (ds_cpu3_sev_req), + .ds_sevl_req (ds_cpu3_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_wfe_req (ds_cpu3_wfe_req), + .ds_wfi_req (ds_cpu3_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu3_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu3_clrexmon), + .ls_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu3_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu3_i), + .npmuirq_cpu (npmuirq_cpu3_i), + .pm_export_cpu (pm_export_cpu3_i), + .pmuevent_cpu (pmuevent_cpu3_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu3_o), + .afvalidm_cpu (afvalidm_cpu3_o), + .atclken_cpu (atclken_cpu3_o), + .atreadym_cpu (atreadym_cpu3_o), + .cfgend_cpu (cfgend_cpu3_o), + .cfgte_cpu (cfgte_cpu3_o), + .ck_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_event_reg (ck_cpu3_event_reg), + .ck_gclkt (ck_gclkt[3]), + .ck_wfe_ack (ck_cpu3_wfe_ack), + .ck_wfi_ack (ck_cpu3_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu3_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu3_o), + .cpuid (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu3_o), + .dbgen_cpu (dbgen_cpu3_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu3_o), + .dbgromaddr_cpu (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu3_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu3_o), + .dftramhold_cpu (dftramhold_cpu3_o), + .dftrstdisable_cpu (dftrstdisable_cpu3_o), + .dftse_cpu (dftse_cpu3_o), + .dt_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu3_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[3]), + .ic_el_change_complete (ic_el_change_complete[3]), + .ic_hcr_change_complete (ic_hcr_change_complete[3]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[3]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[3]), + .ic_ich_el2_tc (ic_ich_el2_tc[3]), + .ic_nfiq (ic_nfiq[3]), + .ic_nirq (ic_nirq[3]), + .ic_nsei (ic_nsei[3]), + .ic_nvfiq (ic_nvfiq[3]), + .ic_nvirq (ic_nvirq[3]), + .ic_nvsei (ic_nvsei[3]), + .ic_p_valid (ic_p_valid[3]), + .ic_sample_spr (ic_sample_spr[3]), + .ic_scr_change_complete (ic_scr_change_complete[3]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[3]), + .ic_sra_el1s_en (ic_sra_el1s_en[3]), + .ic_sra_el2_en (ic_sra_el2_en[3]), + .ic_sra_el3_en (ic_sra_el3_en[3]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[3]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[3]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[3]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[3]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu3_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu3_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu3_rexfail), + .l2_cpu_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu3_rvalid), + .l2_cpu_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu3_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu3_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu3_o), + .ncpuporeset_cpu (ncpuporeset_cpu3_o), + .niden_cpu (niden_cpu3_o), + .nmbistreset_cpu (nmbistreset_cpu3_o), + .rvbaraddr_cpu (rvbaraddr_cpu3_o[43:2]), + .spiden_cpu (spiden_cpu3_o), + .spniden_cpu (spniden_cpu3_o), + .syncreqm_cpu (syncreqm_cpu3_o), + .tm_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu3_o[63:0]), + .vinithi_cpu (vinithi_cpu3_o) + ); // ucpu3 + + maia_noncpu unoncpu( // outputs + .ACREADYM (ACREADYM), + .AFREADYM0 (AFREADYM0), + .AFREADYM1 (AFREADYM1), + .AFREADYM2 (AFREADYM2), + .AFREADYM3 (AFREADYM3), + .ARADDRM (ARADDRM[43:0]), + .ARBARM (ARBARM[1:0]), + .ARBURSTM (ARBURSTM[1:0]), + .ARCACHEM (ARCACHEM[3:0]), + .ARDOMAINM (ARDOMAINM[1:0]), + .ARIDM (ARIDM[6:0]), + .ARLENM (ARLENM[7:0]), + .ARLOCKM (ARLOCKM), + .ARPROTM (ARPROTM[2:0]), + .ARREADYS (ARREADYS), + .ARSIZEM (ARSIZEM[2:0]), + .ARSNOOPM (ARSNOOPM[3:0]), + .ARVALIDM (ARVALIDM), + .ATBYTESM0 (ATBYTESM0[1:0]), + .ATBYTESM1 (ATBYTESM1[1:0]), + .ATBYTESM2 (ATBYTESM2[1:0]), + .ATBYTESM3 (ATBYTESM3[1:0]), + .ATDATAM0 (ATDATAM0[31:0]), + .ATDATAM1 (ATDATAM1[31:0]), + .ATDATAM2 (ATDATAM2[31:0]), + .ATDATAM3 (ATDATAM3[31:0]), + .ATIDM0 (ATIDM0[6:0]), + .ATIDM1 (ATIDM1[6:0]), + .ATIDM2 (ATIDM2[6:0]), + .ATIDM3 (ATIDM3[6:0]), + .ATVALIDM0 (ATVALIDM0), + .ATVALIDM1 (ATVALIDM1), + .ATVALIDM2 (ATVALIDM2), + .ATVALIDM3 (ATVALIDM3), + .AWADDRM (AWADDRM[43:0]), + .AWBARM (AWBARM[1:0]), + .AWBURSTM (AWBURSTM[1:0]), + .AWCACHEM (AWCACHEM[3:0]), + .AWDOMAINM (AWDOMAINM[1:0]), + .AWIDM (AWIDM[6:0]), + .AWLENM (AWLENM[7:0]), + .AWLOCKM (AWLOCKM), + .AWPROTM (AWPROTM[2:0]), + .AWREADYS (AWREADYS), + .AWSIZEM (AWSIZEM[2:0]), + .AWSNOOPM (AWSNOOPM[2:0]), + .AWUNIQUEM (AWUNIQUEM), + .AWVALIDM (AWVALIDM), + .BIDS (BIDS[4:0]), + .BREADYM (BREADYM), + .BRESPS (BRESPS[1:0]), + .BVALIDS (BVALIDS), + .CDDATAM (CDDATAM[127:0]), + .CDLASTM (CDLASTM), + .CDVALIDM (CDVALIDM), + .CLREXMONACK (CLREXMONACK), + .COMMRX (COMMRX[`MAIA_CN:0]), + .COMMTX (COMMTX[`MAIA_CN:0]), + .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), + .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), + .CPUQDENY (CPUQDENY[`MAIA_CN:0]), + .CRRESPM (CRRESPM[4:0]), + .CRVALIDM (CRVALIDM), + .CTICHINACK (CTICHINACK[3:0]), + .CTICHOUT (CTICHOUT[3:0]), + .CTIIRQ (CTIIRQ[`MAIA_CN:0]), + .DBGACK (DBGACK[`MAIA_CN:0]), + .DBGNOPWRDWN (DBGNOPWRDWN[`MAIA_CN:0]), + .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), + .DBGRSTREQ (DBGRSTREQ[`MAIA_CN:0]), + .EVENTO (EVENTO), + .ICCTDATA (ICCTDATA[15:0]), + .ICCTID (ICCTID[1:0]), + .ICCTLAST (ICCTLAST), + .ICCTVALID (ICCTVALID), + .ICDTREADY (ICDTREADY), + .L2FLUSHDONE (L2FLUSHDONE), + .L2QACCEPTn (L2QACCEPTn), + .L2QACTIVE (L2QACTIVE), + .L2QDENY (L2QDENY), + .PMUEVENT0 (PMUEVENT0[24:0]), + .PMUEVENT1 (PMUEVENT1[24:0]), + .PMUEVENT2 (PMUEVENT2[24:0]), + .PMUEVENT3 (PMUEVENT3[24:0]), + .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), + .PRDATADBG (PRDATADBG[31:0]), + .PREADYDBG (PREADYDBG), + .PSLVERRDBG (PSLVERRDBG), + .RACKM (RACKM), + .RDATAS (RDATAS[127:0]), + .RDMEMATTR (RDMEMATTR[7:0]), + .RIDS (RIDS[4:0]), + .RLASTS (RLASTS), + .RREADYM (RREADYM), + .RRESPS (RRESPS[1:0]), + .RVALIDS (RVALIDS), + .SMPEN (SMPEN[`MAIA_CN:0]), + .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), + .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), + .STANDBYWFIL2 (STANDBYWFIL2), + .WACKM (WACKM), + .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), + .WDATAM (WDATAM[127:0]), + .WIDM (WIDM[6:0]), + .WLASTM (WLASTM), + .WREADYS (WREADYS), + .WRMEMATTR (WRMEMATTR[7:0]), + .WSTRBM (WSTRBM[15:0]), + .WVALIDM (WVALIDM), + .aa64naa32_cpu0_o (aa64naa32_cpu0_o), + .aa64naa32_cpu1_o (aa64naa32_cpu1_o), + .aa64naa32_cpu2_o (aa64naa32_cpu2_o), + .aa64naa32_cpu3_o (aa64naa32_cpu3_o), + .afvalidm_cpu0_o (afvalidm_cpu0_o), + .afvalidm_cpu1_o (afvalidm_cpu1_o), + .afvalidm_cpu2_o (afvalidm_cpu2_o), + .afvalidm_cpu3_o (afvalidm_cpu3_o), + .atclken_cpu0_o (atclken_cpu0_o), + .atclken_cpu1_o (atclken_cpu1_o), + .atclken_cpu2_o (atclken_cpu2_o), + .atclken_cpu3_o (atclken_cpu3_o), + .atreadym_cpu0_o (atreadym_cpu0_o), + .atreadym_cpu1_o (atreadym_cpu1_o), + .atreadym_cpu2_o (atreadym_cpu2_o), + .atreadym_cpu3_o (atreadym_cpu3_o), + .cfgend_cpu0_o (cfgend_cpu0_o), + .cfgend_cpu1_o (cfgend_cpu1_o), + .cfgend_cpu2_o (cfgend_cpu2_o), + .cfgend_cpu3_o (cfgend_cpu3_o), + .cfgte_cpu0_o (cfgte_cpu0_o), + .cfgte_cpu1_o (cfgte_cpu1_o), + .cfgte_cpu2_o (cfgte_cpu2_o), + .cfgte_cpu3_o (cfgte_cpu3_o), + .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_cpu0_event_reg (ck_cpu0_event_reg), + .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), + .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), + .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_cpu1_event_reg (ck_cpu1_event_reg), + .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), + .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), + .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_cpu2_event_reg (ck_cpu2_event_reg), + .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), + .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), + .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_cpu3_event_reg (ck_cpu3_event_reg), + .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), + .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), + .ck_gclkt (ck_gclkt[`MAIA_CN:0]), + .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), + .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), + .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), + .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), + .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), + .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), + .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), + .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), + .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), + .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), + .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), + .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), + .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), + .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), + .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu0_o (cryptodisable_cpu0_o), + .cryptodisable_cpu1_o (cryptodisable_cpu1_o), + .cryptodisable_cpu2_o (cryptodisable_cpu2_o), + .cryptodisable_cpu3_o (cryptodisable_cpu3_o), + .dbgen_cpu0_o (dbgen_cpu0_o), + .dbgen_cpu1_o (dbgen_cpu1_o), + .dbgen_cpu2_o (dbgen_cpu2_o), + .dbgen_cpu3_o (dbgen_cpu3_o), + .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), + .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), + .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), + .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), + .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), + .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), + .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), + .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), + .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), + .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), + .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), + .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), + .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), + .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), + .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), + .dftramhold_cpu0_o (dftramhold_cpu0_o), + .dftramhold_cpu1_o (dftramhold_cpu1_o), + .dftramhold_cpu2_o (dftramhold_cpu2_o), + .dftramhold_cpu3_o (dftramhold_cpu3_o), + .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), + .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), + .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), + .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), + .dftse_cpu0_o (dftse_cpu0_o), + .dftse_cpu1_o (dftse_cpu1_o), + .dftse_cpu2_o (dftse_cpu2_o), + .dftse_cpu3_o (dftse_cpu3_o), + .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .giccdisable_cpu0_o (giccdisable_cpu0_o), + .giccdisable_cpu1_o (giccdisable_cpu1_o), + .giccdisable_cpu2_o (giccdisable_cpu2_o), + .giccdisable_cpu3_o (giccdisable_cpu3_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[`MAIA_CN:0]), + .ic_el_change_complete (ic_el_change_complete[`MAIA_CN:0]), + .ic_hcr_change_complete (ic_hcr_change_complete[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq[`MAIA_CN:0]), + .ic_nirq (ic_nirq[`MAIA_CN:0]), + .ic_nsei (ic_nsei[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei[`MAIA_CN:0]), + .ic_p_valid (ic_p_valid[`MAIA_CN:0]), + .ic_sample_spr (ic_sample_spr[`MAIA_CN:0]), + .ic_scr_change_complete (ic_scr_change_complete[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[`MAIA_CN:0]), + .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu0_barrier_done (l2_cpu0_barrier_done), + .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), + .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), + .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu0_rd_arb (l2_cpu0_rd_arb), + .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu0_rexfail (l2_cpu0_rexfail), + .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu0_rvalid (l2_cpu0_rvalid), + .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu0_spec_valid (l2_cpu0_spec_valid), + .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu0_wr_arb (l2_cpu0_wr_arb), + .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu1_barrier_done (l2_cpu1_barrier_done), + .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), + .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), + .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu1_rd_arb (l2_cpu1_rd_arb), + .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu1_rexfail (l2_cpu1_rexfail), + .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu1_rvalid (l2_cpu1_rvalid), + .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu1_spec_valid (l2_cpu1_spec_valid), + .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu1_wr_arb (l2_cpu1_wr_arb), + .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu2_barrier_done (l2_cpu2_barrier_done), + .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), + .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), + .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu2_rd_arb (l2_cpu2_rd_arb), + .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu2_rexfail (l2_cpu2_rexfail), + .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu2_rvalid (l2_cpu2_rvalid), + .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu2_spec_valid (l2_cpu2_spec_valid), + .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu2_wr_arb (l2_cpu2_wr_arb), + .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu3_barrier_done (l2_cpu3_barrier_done), + .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), + .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), + .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu3_rd_arb (l2_cpu3_rd_arb), + .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu3_rexfail (l2_cpu3_rexfail), + .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu3_rvalid (l2_cpu3_rvalid), + .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu3_spec_valid (l2_cpu3_spec_valid), + .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu3_wr_arb (l2_cpu3_wr_arb), + .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), + .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), + .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), + .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), + .nCOMMIRQ (nCOMMIRQ[`MAIA_CN:0]), + .nEXTERRIRQ (nEXTERRIRQ), + .nINTERRIRQ (nINTERRIRQ), + .nPMUIRQ (nPMUIRQ[`MAIA_CN:0]), + .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), + .ncorereset_cpu0_o (ncorereset_cpu0_o), + .ncorereset_cpu1_o (ncorereset_cpu1_o), + .ncorereset_cpu2_o (ncorereset_cpu2_o), + .ncorereset_cpu3_o (ncorereset_cpu3_o), + .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), + .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), + .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), + .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), + .niden_cpu0_o (niden_cpu0_o), + .niden_cpu1_o (niden_cpu1_o), + .niden_cpu2_o (niden_cpu2_o), + .niden_cpu3_o (niden_cpu3_o), + .nmbistreset_cpu0_o (nmbistreset_cpu0_o), + .nmbistreset_cpu1_o (nmbistreset_cpu1_o), + .nmbistreset_cpu2_o (nmbistreset_cpu2_o), + .nmbistreset_cpu3_o (nmbistreset_cpu3_o), + .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), + .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), + .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), + .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), + .spiden_cpu0_o (spiden_cpu0_o), + .spiden_cpu1_o (spiden_cpu1_o), + .spiden_cpu2_o (spiden_cpu2_o), + .spiden_cpu3_o (spiden_cpu3_o), + .spniden_cpu0_o (spniden_cpu0_o), + .spniden_cpu1_o (spniden_cpu1_o), + .spniden_cpu2_o (spniden_cpu2_o), + .spniden_cpu3_o (spniden_cpu3_o), + .syncreqm_cpu0_o (syncreqm_cpu0_o), + .syncreqm_cpu1_o (syncreqm_cpu1_o), + .syncreqm_cpu2_o (syncreqm_cpu2_o), + .syncreqm_cpu3_o (syncreqm_cpu3_o), + .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), + .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), + .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), + .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), + .vinithi_cpu0_o (vinithi_cpu0_o), + .vinithi_cpu1_o (vinithi_cpu1_o), + .vinithi_cpu2_o (vinithi_cpu2_o), + .vinithi_cpu3_o (vinithi_cpu3_o), + + // inputs + .AA64nAA32 (AA64nAA32[`MAIA_CN:0]), + .ACADDRM (ACADDRM[43:0]), + .ACINACTM (ACINACTM), + .ACLKENM (ACLKENM), + .ACLKENS (ACLKENS), + .ACPROTM (ACPROTM[2:0]), + .ACSNOOPM (ACSNOOPM[3:0]), + .ACVALIDM (ACVALIDM), + .AFVALIDM0 (AFVALIDM0), + .AFVALIDM1 (AFVALIDM1), + .AFVALIDM2 (AFVALIDM2), + .AFVALIDM3 (AFVALIDM3), + .AINACTS (AINACTS), + .ARADDRS (ARADDRS[43:0]), + .ARCACHES (ARCACHES[3:0]), + .ARIDS (ARIDS[4:0]), + .ARLENS (ARLENS[7:0]), + .ARPROTS (ARPROTS[2:0]), + .ARREADYM (ARREADYM), + .ARUSERS (ARUSERS[1:0]), + .ARVALIDS (ARVALIDS), + .ATCLKEN (ATCLKEN), + .ATREADYM0 (ATREADYM0), + .ATREADYM1 (ATREADYM1), + .ATREADYM2 (ATREADYM2), + .ATREADYM3 (ATREADYM3), + .AWADDRS (AWADDRS[43:0]), + .AWCACHES (AWCACHES[3:0]), + .AWIDS (AWIDS[4:0]), + .AWLENS (AWLENS[7:0]), + .AWPROTS (AWPROTS[2:0]), + .AWREADYM (AWREADYM), + .AWUSERS (AWUSERS[1:0]), + .AWVALIDS (AWVALIDS), + .BIDM (BIDM[6:0]), + .BREADYS (BREADYS), + .BRESPM (BRESPM[1:0]), + .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), + .BROADCASTINNER (BROADCASTINNER), + .BROADCASTOUTER (BROADCASTOUTER), + .BVALIDM (BVALIDM), + .CDREADYM (CDREADYM), + .CFGEND (CFGEND[`MAIA_CN:0]), + .CFGTE (CFGTE[`MAIA_CN:0]), + .CIHSBYPASS (CIHSBYPASS[3:0]), + .CISBYPASS (CISBYPASS), + .CLK (CLK), + .CLKEN (CLKEN), + .CLREXMONREQ (CLREXMONREQ), + .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), + .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), + .CNTCLKEN (CNTCLKEN), + .CNTVALUEB (CNTVALUEB[63:0]), + .CP15SDISABLE (CP15SDISABLE[`MAIA_CN:0]), + .CPUQREQn (CPUQREQn[`MAIA_CN:0]), + .CRREADYM (CRREADYM), + .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), + .CTICHIN (CTICHIN[3:0]), + .CTICHOUTACK (CTICHOUTACK[3:0]), + .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), + .DBGEN (DBGEN[`MAIA_CN:0]), + .DBGL1RSTDISABLE (DBGL1RSTDISABLE), + .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), + .DBGROMADDR (DBGROMADDR[43:12]), + .DBGROMADDRV (DBGROMADDRV), + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTCRCLKDISABLE (DFTCRCLKDISABLE[`MAIA_CN:0]), + .DFTL2CLKDISABLE (DFTL2CLKDISABLE), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .EDBGRQ (EDBGRQ[`MAIA_CN:0]), + .EVENTI (EVENTI), + .GICCDISABLE (GICCDISABLE), + .ICCTREADY (ICCTREADY), + .ICDTDATA (ICDTDATA[15:0]), + .ICDTDEST (ICDTDEST[1:0]), + .ICDTLAST (ICDTLAST), + .ICDTVALID (ICDTVALID), + .L2FLUSHREQ (L2FLUSHREQ), + .L2QREQn (L2QREQn), + .L2RSTDISABLE (L2RSTDISABLE), + .MBISTREQ (MBISTREQ), + .NIDEN (NIDEN[`MAIA_CN:0]), + .PADDRDBG (PADDRDBG[21:2]), + .PADDRDBG31 (PADDRDBG31), + .PCLKDBG (PCLKDBG), + .PCLKENDBG (PCLKENDBG), + .PENABLEDBG (PENABLEDBG), + .PERIPHBASE (PERIPHBASE[43:18]), + .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), + .PSELDBG (PSELDBG), + .PWDATADBG (PWDATADBG[31:0]), + .PWRITEDBG (PWRITEDBG), + .RDATAM (RDATAM[127:0]), + .RIDM (RIDM[6:0]), + .RLASTM (RLASTM), + .RREADYS (RREADYS), + .RRESPM (RRESPM[3:0]), + .RVALIDM (RVALIDM), + .RVBARADDR0 (RVBARADDR0[43:2]), + .RVBARADDR1 (RVBARADDR1[43:2]), + .RVBARADDR2 (RVBARADDR2[43:2]), + .RVBARADDR3 (RVBARADDR3[43:2]), + .SPIDEN (SPIDEN[`MAIA_CN:0]), + .SPNIDEN (SPNIDEN[`MAIA_CN:0]), + .SYNCREQM0 (SYNCREQM0), + .SYNCREQM1 (SYNCREQM1), + .SYNCREQM2 (SYNCREQM2), + .SYNCREQM3 (SYNCREQM3), + .SYSBARDISABLE (SYSBARDISABLE), + .TSVALUEB (TSVALUEB[63:0]), + .VINITHI (VINITHI[`MAIA_CN:0]), + .WDATAS (WDATAS[127:0]), + .WLASTS (WLASTS), + .WREADYM (WREADYM), + .WSTRBS (WSTRBS[15:0]), + .WVALIDS (WVALIDS), + .afreadym_cpu0_i (afreadym_cpu0_i), + .afreadym_cpu1_i (afreadym_cpu1_i), + .afreadym_cpu2_i (afreadym_cpu2_i), + .afreadym_cpu3_i (afreadym_cpu3_i), + .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), + .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), + .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), + .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), + .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), + .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), + .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), + .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), + .atidm_cpu0_i (atidm_cpu0_i[6:0]), + .atidm_cpu1_i (atidm_cpu1_i[6:0]), + .atidm_cpu2_i (atidm_cpu2_i[6:0]), + .atidm_cpu3_i (atidm_cpu3_i[6:0]), + .atvalidm_cpu0_i (atvalidm_cpu0_i), + .atvalidm_cpu1_i (atvalidm_cpu1_i), + .atvalidm_cpu2_i (atvalidm_cpu2_i), + .atvalidm_cpu3_i (atvalidm_cpu3_i), + .commrx_cpu0_i (commrx_cpu0_i), + .commrx_cpu1_i (commrx_cpu1_i), + .commrx_cpu2_i (commrx_cpu2_i), + .commrx_cpu3_i (commrx_cpu3_i), + .commtx_cpu0_i (commtx_cpu0_i), + .commtx_cpu1_i (commtx_cpu1_i), + .commtx_cpu2_i (commtx_cpu2_i), + .commtx_cpu3_i (commtx_cpu3_i), + .dbgack_cpu0_i (dbgack_cpu0_i), + .dbgack_cpu1_i (dbgack_cpu1_i), + .dbgack_cpu2_i (dbgack_cpu2_i), + .dbgack_cpu3_i (dbgack_cpu3_i), + .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), + .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), + .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), + .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), + .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), + .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), + .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), + .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_cpu0_flush (ds_cpu0_flush), + .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), + .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), + .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu0_reset_req (ds_cpu0_reset_req), + .ds_cpu0_sev_req (ds_cpu0_sev_req), + .ds_cpu0_sevl_req (ds_cpu0_sevl_req), + .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_cpu0_wfe_req (ds_cpu0_wfe_req), + .ds_cpu0_wfi_req (ds_cpu0_wfi_req), + .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_cpu1_flush (ds_cpu1_flush), + .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), + .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), + .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu1_reset_req (ds_cpu1_reset_req), + .ds_cpu1_sev_req (ds_cpu1_sev_req), + .ds_cpu1_sevl_req (ds_cpu1_sevl_req), + .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_cpu1_wfe_req (ds_cpu1_wfe_req), + .ds_cpu1_wfi_req (ds_cpu1_wfi_req), + .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_cpu2_flush (ds_cpu2_flush), + .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), + .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), + .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu2_reset_req (ds_cpu2_reset_req), + .ds_cpu2_sev_req (ds_cpu2_sev_req), + .ds_cpu2_sevl_req (ds_cpu2_sevl_req), + .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_cpu2_wfe_req (ds_cpu2_wfe_req), + .ds_cpu2_wfi_req (ds_cpu2_wfi_req), + .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_cpu3_flush (ds_cpu3_flush), + .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), + .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), + .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), + .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_cpu3_reset_req (ds_cpu3_reset_req), + .ds_cpu3_sev_req (ds_cpu3_sev_req), + .ds_cpu3_sevl_req (ds_cpu3_sevl_req), + .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_cpu3_wfe_req (ds_cpu3_wfe_req), + .ds_cpu3_wfi_req (ds_cpu3_wfi_req), + .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .etclken_cpu0_i (etclken_cpu0_i), + .etclken_cpu1_i (etclken_cpu1_i), + .etclken_cpu2_i (etclken_cpu2_i), + .etclken_cpu3_i (etclken_cpu3_i), + .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .ls_cpu0_clrexmon (ls_cpu0_clrexmon), + .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ls_cpu1_clrexmon (ls_cpu1_clrexmon), + .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ls_cpu2_clrexmon (ls_cpu2_clrexmon), + .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ls_cpu3_clrexmon (ls_cpu3_clrexmon), + .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), + .nCORERESET (nCORERESET[`MAIA_CN:0]), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nFIQ (nFIQ[`MAIA_CN:0]), + .nIRQ (nIRQ[`MAIA_CN:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .nPRESETDBG (nPRESETDBG), + .nREI (nREI[`MAIA_CN:0]), + .nSEI (nSEI[`MAIA_CN:0]), + .nVFIQ (nVFIQ[`MAIA_CN:0]), + .nVIRQ (nVIRQ[`MAIA_CN:0]), + .nVSEI (nVSEI[`MAIA_CN:0]), + .ncommirq_cpu0_i (ncommirq_cpu0_i), + .ncommirq_cpu1_i (ncommirq_cpu1_i), + .ncommirq_cpu2_i (ncommirq_cpu2_i), + .ncommirq_cpu3_i (ncommirq_cpu3_i), + .npmuirq_cpu0_i (npmuirq_cpu0_i), + .npmuirq_cpu1_i (npmuirq_cpu1_i), + .npmuirq_cpu2_i (npmuirq_cpu2_i), + .npmuirq_cpu3_i (npmuirq_cpu3_i), + .pm_export_cpu0_i (pm_export_cpu0_i), + .pm_export_cpu1_i (pm_export_cpu1_i), + .pm_export_cpu2_i (pm_export_cpu2_i), + .pm_export_cpu3_i (pm_export_cpu3_i), + .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), + .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), + .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), + .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]) + ); // unoncpu +endmodule // MAIA + + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/MAIA_feq20.v b/Security Algo Accelerator/logical/maia/verilog/MAIA_feq20.v new file mode 100644 index 0000000000..e5bfc42be7 --- /dev/null +++ b/Security Algo Accelerator/logical/maia/verilog/MAIA_feq20.v @@ -0,0 +1,4801 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: MAIA_feq20.v $ +// Checked In : $Date: 2014-10-14 15:20:06 -0500 (Tue, 14 Oct 2014) $ +// Revision : $Revision: 71806 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// +// This is top-level interconnect layer for the MAIA_feq20 top-level. +// + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +`define MAIA_CN 3 + +module MAIA_feq20 ( + CLK, + CLKEN, + nCPUPORESET, + nCORERESET, + nL2RESET, + L2RSTDISABLE, + WARMRSTREQ, + CFGEND, + VINITHI, + CFGTE, + CP15SDISABLE, + CLUSTERIDAFF1, + CLUSTERIDAFF2, + AA64nAA32, + RVBARADDR0, +// BEGIN INCLUDE FOR CPU1 + RVBARADDR1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + RVBARADDR2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + RVBARADDR3, +// END INCLUDE FOR CPU3 + CRYPTODISABLE, + nFIQ, + nIRQ, + nSEI, + nREI, + nVFIQ, + nVIRQ, + nVSEI, +// BEGIN NO-GIC pins + nVCPUMNTIRQ, +// END NO-GIC pins + PERIPHBASE, +// BEGIN NO-GIC pins + GICCDISABLE, + ICDTVALID, + ICDTREADY, + ICDTDATA, + ICDTLAST, + ICDTDEST, + ICCTVALID, + ICCTREADY, + ICCTDATA, + ICCTLAST, + ICCTID, +// END NO-GIC pins + CNTVALUEB, + CNTCLKEN, + nCNTPNSIRQ, + nCNTPSIRQ, + nCNTVIRQ, + nCNTHPIRQ, + CLREXMONREQ, + CLREXMONACK, + EVENTI, + EVENTO, + STANDBYWFI, + STANDBYWFE, + STANDBYWFIL2, + SMPEN, + CPUQACTIVE, + CPUQREQn, + CPUQACCEPTn, + CPUQDENY, + L2QACTIVE, + L2QREQn, + L2QACCEPTn, + L2QDENY, + L2FLUSHREQ, + L2FLUSHDONE, + nINTERRIRQ, + nEXTERRIRQ, + SYSBARDISABLE, + BROADCASTINNER, + BROADCASTOUTER, + BROADCASTCACHEMAINT, + ACLKENM, + ACINACTM, + AWREADYM, + AWVALIDM, + AWIDM, + AWADDRM, + AWLENM, + AWSIZEM, + AWBURSTM, + AWBARM, + AWDOMAINM, + AWLOCKM, + AWCACHEM, + AWPROTM, + AWSNOOPM, + AWUNIQUEM, + WRMEMATTR, + WREADYM, + WVALIDM, + WDATAM, + WSTRBM, + WIDM, + WLASTM, + BREADYM, + BVALIDM, + BIDM, + BRESPM, + ARREADYM, + ARVALIDM, + ARIDM, + ARADDRM, + ARLENM, + ARSIZEM, + ARBURSTM, + ARBARM, + ARDOMAINM, + ARLOCKM, + ARCACHEM, + ARPROTM, + ARSNOOPM, + RDMEMATTR, + RREADYM, + RVALIDM, + RIDM, + RDATAM, + RRESPM, + RLASTM, + ACREADYM, + ACVALIDM, + ACADDRM, + ACPROTM, + ACSNOOPM, + CRREADYM, + CRVALIDM, + CRRESPM, + CDREADYM, + CDVALIDM, + CDDATAM, + CDLASTM, + RACKM, + WACKM, +// BEGIN NO-ACP pins + ACLKENS, + AINACTS, + AWREADYS, + AWVALIDS, + AWIDS, + AWADDRS, + AWLENS, + AWCACHES, + AWUSERS, + AWPROTS, + WREADYS, + WVALIDS, + WDATAS, + WSTRBS, + WLASTS, + BREADYS, + BVALIDS, + BIDS, + BRESPS, + ARREADYS, + ARVALIDS, + ARIDS, + ARADDRS, + ARLENS, + ARCACHES, + ARUSERS, + ARPROTS, + RREADYS, + RVALIDS, + RIDS, + RDATAS, + RRESPS, + RLASTS, +// END NO-ACP pins + DBGROMADDR, + DBGROMADDRV, + DBGACK, + nCOMMIRQ, + COMMRX, + COMMTX, + DBGRSTREQ, + DBGNOPWRDWN, + DBGL1RSTDISABLE, + nPMUIRQ, + PMUEVENT0, +// BEGIN INCLUDE FOR CPU1 + PMUEVENT1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + PMUEVENT2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + PMUEVENT3, +// END INCLUDE FOR CPU3 + ATCLKEN, + TSVALUEB, + ATREADYM0, + AFVALIDM0, + ATDATAM0, + ATVALIDM0, + ATBYTESM0, + AFREADYM0, + ATIDM0, + SYNCREQM0, +// BEGIN INCLUDE FOR CPU1 + ATREADYM1, + AFVALIDM1, + ATDATAM1, + ATVALIDM1, + ATBYTESM1, + AFREADYM1, + ATIDM1, + SYNCREQM1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ATREADYM2, + AFVALIDM2, + ATDATAM2, + ATVALIDM2, + ATBYTESM2, + AFREADYM2, + ATIDM2, + SYNCREQM2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ATREADYM3, + AFVALIDM3, + ATDATAM3, + ATVALIDM3, + ATBYTESM3, + AFREADYM3, + ATIDM3, + SYNCREQM3, +// END INCLUDE FOR CPU3 + PCLKDBG, + PCLKENDBG, + nPRESETDBG, + PSELDBG, + PADDRDBG, + PADDRDBG31, + PENABLEDBG, + PWRITEDBG, + PWDATADBG, + PRDATADBG, + PREADYDBG, + PSLVERRDBG, + EDBGRQ, + PMUSNAPSHOTREQ, + PMUSNAPSHOTACK, + DBGPWRDUP, + DBGPWRUPREQ, + CTICHIN, + CTICHOUTACK, + CTICHOUT, + CTICHINACK, + CISBYPASS, + CIHSBYPASS, + CTIIRQ, + CTIIRQACK, + DBGEN, + NIDEN, + SPIDEN, + SPNIDEN, + DFTSE, + DFTRSTDISABLE, + DFTCRCLKDISABLE, + DFTL2CLKDISABLE, + DFTRAMHOLD, + DFTCLKBYPASS, + DFTMCPHOLD, + nMBISTRESET, + MBISTREQ +); + +//# +//# Interface Signals +//# ================= +//# + +//----------------------------------------------------------------------------- +// Clock and Reset Signals +//----------------------------------------------------------------------------- + input CLK; // Fast Clock + input CLKEN; // Fast Clock Enable + + input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset + input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) + input nL2RESET; // L2 reset + input L2RSTDISABLE; // L2 RAMs hardware reset disable + output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request +//See also nPRESETDBG; // Debug APB reset (PCLK) + +//----------------------------------------------------------------------------- +// Static Configuration Signals +//----------------------------------------------------------------------------- +// Static configuration signals that should be tied off and not change dynamically. +// Many of the initial values specified by these inputs +// may be overridden in software using CP15 registers. + + input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) + input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors + input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) + input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers + + input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] + input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] + + input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) + input [43:2] RVBARADDR0; // RVBAR address +// BEGIN INCLUDE FOR CPU1 + input [43:2] RVBARADDR1; // RVBAR address +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input [43:2] RVBARADDR2; // RVBAR address +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input [43:2] RVBARADDR3; // RVBAR address +// END INCLUDE FOR CPU3 + input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension + +//----------------------------------------------------------------------------- +// Interrupt Controller Signals +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] nFIQ; // Fast Interrupt request + input [`MAIA_CN:0] nIRQ; // Interrupt request + input [`MAIA_CN:0] nSEI; // System Error Interrupt + input [`MAIA_CN:0] nREI; // RAM Error Interrupt + input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request + input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request + input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt + + output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output + + input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers + input GICCDISABLE; // Put GIC into bypass mode + + input ICDTVALID; // Distrubuter AXI4 SP Message Valid + output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message + input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data + input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet + input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID + + output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid + input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message + output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data + output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet + output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID + +//----------------------------------------------------------------------------- +// Timer Signals +//----------------------------------------------------------------------------- + input [63:0] CNTVALUEB; // Counter value in binary + input CNTCLKEN; // Counter clock enable + output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event + output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event + output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event + output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event + +//----------------------------------------------------------------------------- +// Power Management Signals +//----------------------------------------------------------------------------- + input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) + output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) + input EVENTI; // Event input for processor wake-up from WFE state + output EVENTO; // Event output, signal is active when SEV instruction is executed + output [`MAIA_CN:0] STANDBYWFI; // WFI mode + output [`MAIA_CN:0] STANDBYWFE; // WFE mode + output STANDBYWFIL2; // WFI mode for L2 + output [`MAIA_CN:0] SMPEN; // CPU SMP bit + + output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE + input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn + output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn + output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY + + output L2QACTIVE; // L2 Q-channel QACTIVE + input L2QREQn; // L2 Q-channel QREQn + output L2QACCEPTn; // L2 Q-channel QACCEPTn + output L2QDENY; // L2 Q-channel QDENY + + input L2FLUSHREQ; // L2 hardware flush request + output L2FLUSHDONE; // L2 hardware flush done + +//----------------------------------------------------------------------------- +// Asynchronous Error Signals +//----------------------------------------------------------------------------- + output nINTERRIRQ; // L2 RAM dbl-bit ECC error + output nEXTERRIRQ; // Write transaction error + +//----------------------------------------------------------------------------- +// Bus Configuration Signals +//----------------------------------------------------------------------------- + input SYSBARDISABLE; // Disable broadcast of barriers + input BROADCASTINNER; // Extend Inner Shared Domain + input BROADCASTOUTER; // Extend Outer Shared Domain + input BROADCASTCACHEMAINT; // Broadcast cache maint ops + +//----------------------------------------------------------------------------- +// AMBA4 ACE Master (AXI with Coherency extensions) +//----------------------------------------------------------------------------- + input ACLKENM; // AXI Master clock enable + input ACINACTM; // ACE Snoop interface no longer active or accepting requests + +// Write Address channel signals + input AWREADYM; // Write Address ready (slave ready to accept write address) + output AWVALIDM; // Write Address valid + output [6:0] AWIDM; // Write Address ID + output [43:0] AWADDRM; // Write Address + output [7:0] AWLENM; // Write Burst Length + output [2:0] AWSIZEM; // Write Burst Size + output [1:0] AWBURSTM; // Write Burst type + output [1:0] AWBARM; // Barrier + output [1:0] AWDOMAINM; // Domain + output AWLOCKM; // Write Lock type + output [3:0] AWCACHEM; // Write Cache type + output [2:0] AWPROTM; // Write Protection type + output [2:0] AWSNOOPM; // Write Snoop Request type + output AWUNIQUEM; // Write Unique state + output [7:0] WRMEMATTR; // Write raw memory attributes + +// Write Data channel signals + input WREADYM; // Write Data ready (slave ready to accept data) + output WVALIDM; // Write Data valid + output [127:0] WDATAM; // Write Data + output [15:0] WSTRBM; // Write byte-lane strobes + output [6:0] WIDM; // Write id + output WLASTM; // Write Data last transfer indicator + +// Write Response channel signals + output BREADYM; // Write Response ready (master ready to accept response) + input BVALIDM; // Write Response Valid + input [6:0] BIDM; // Write Response ID + input [1:0] BRESPM; // Write Response + +// Read Address channel signals + input ARREADYM; // Read Address ready (slave ready to accept read address) + output ARVALIDM; // Read Address valid + output [6:0] ARIDM; // Read Address ID + output [43:0] ARADDRM; // Read Address + output [7:0] ARLENM; // Read Burst Length + output [2:0] ARSIZEM; // Read Burst Size + output [1:0] ARBURSTM; // Read Burst type + output [1:0] ARBARM; // Barrier + output [1:0] ARDOMAINM; // Domain + output ARLOCKM; // Read Lock type + output [3:0] ARCACHEM; // Read Cache type + output [2:0] ARPROTM; // Read Protection type + output [3:0] ARSNOOPM; // Read Snoop Request type + output [7:0] RDMEMATTR; // Read raw memory attributes + +// Read Data channel signals + output RREADYM; // Read Data ready (master ready to accept data) + input RVALIDM; // Read Data valid + input [6:0] RIDM; // Read Data ID + input [127:0] RDATAM; // Read Data + input [3:0] RRESPM; // Read Data response + input RLASTM; // Read Data last transfer indicator + +// Coherency Address channel signals + output ACREADYM; // master ready to accept snoop address + input ACVALIDM; // Snoop Address valid + input [43:0] ACADDRM; // Snoop Address + input [2:0] ACPROTM; // Snoop Protection type + input [3:0] ACSNOOPM; // Snoop Request type + +// Coherency Response channel signals + input CRREADYM; // slave ready to accept snoop response + output CRVALIDM; // Snoop Response valid + output [4:0] CRRESPM; // Snoop Response + +// Coherency Data handshake channel signals + input CDREADYM; // slave ready to accept snoop data + output CDVALIDM; // Snoop Data valid + output [127:0] CDDATAM; // Snoop Data + output CDLASTM; // Snoop Data last transfer indicator + +// Read/Write Acknowledge signals + output RACKM; // Read Acknowledge + output WACKM; // Write Acknowledge + +// BEGIN NO-ACP pins +//----------------------------------------------------------------------------- +// ACP AXI Slave +//----------------------------------------------------------------------------- + input ACLKENS; // AXI slave clock enable + input AINACTS; // AXI slave interface no longer active or accepting requests + +// Write Address channel signals + output AWREADYS; // Write Address ready (slave ready to accept write address) + input AWVALIDS; // Write Address valid + input [4:0] AWIDS; // Write Address ID + input [43:0] AWADDRS; // Write Address + input [7:0] AWLENS; // Write Burst Length + input [3:0] AWCACHES; // Write Cache type + input [1:0] AWUSERS; // Write inner & outer shareability + input [2:0] AWPROTS; // Write Protection type + +// Write Data channel signals + output WREADYS; // Write Data ready (slave ready to accept data) + input WVALIDS; // Write Data valid + input [127:0] WDATAS; // Write Data + input [15:0] WSTRBS; // Write byte-lane strobes + input WLASTS; // Write Data last transfer indicator + +// Write Response channel signals + input BREADYS; // Write Response ready (master ready to accept response) + output BVALIDS; // Write Response Valid + output [4:0] BIDS; // Write Response ID tag + output [1:0] BRESPS; // Write Response + +// Read Address channel signals + output ARREADYS; // Read Address ready (slave ready to accept read address) + input ARVALIDS; // Read Address valid + input [4:0] ARIDS; // Read Address ID + input [43:0] ARADDRS; // Read Address + input [7:0] ARLENS; // Read Burst Length + input [3:0] ARCACHES; // Read Cache type + input [1:0] ARUSERS; // Read inner & outer shareability + input [2:0] ARPROTS; // Read Protection type + +// Read Data channel signals + input RREADYS; // Read Data ready (master ready to accept data) + output RVALIDS; // Read Data valid + output [4:0] RIDS; // Read Data ID + output [127:0] RDATAS; // Read Data + output [1:0] RRESPS; // Read Data response + output RLASTS; // Read Data last transfer indicator +// END NO-ACP pins + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (CLK) +//----------------------------------------------------------------------------- +// Debug CLK interface + input [43:12] DBGROMADDR; // Debug ROM base address + input DBGROMADDRV; // Debug ROM base address valid + + output [`MAIA_CN:0] DBGACK; // Debug acknowledge + output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt + output [`MAIA_CN:0] COMMRX; // Comms channel receive + output [`MAIA_CN:0] COMMTX; // Comms channel transmit + + output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request + output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request + + input DBGL1RSTDISABLE; // L1 DCache hardware reset disable + +// PMU CLK interface + output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request + output [24:0] PMUEVENT0; // PMU Event bus +// BEGIN INCLUDE FOR CPU1 + output [24:0] PMUEVENT1; // PMU Event bus +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + output [24:0] PMUEVENT2; // PMU Event bus +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + output [24:0] PMUEVENT3; // PMU Event bus +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (ATCLK) +//----------------------------------------------------------------------------- +// ETM ATB interface and Misc signals + input ATCLKEN; // ATB Clock Enable + input [63:0] TSVALUEB; // ATB Timestamp in binary + + input ATREADYM0; // ATDATA can be accepted + input AFVALIDM0; // ATB Fifo Flush Request + output [31:0] ATDATAM0; // ATB Data + output ATVALIDM0; // ATB Data Valid + output [1:0] ATBYTESM0; // ATB Data Size + output AFREADYM0; // ATB Fifo Flush Finished + output [6:0] ATIDM0; // ATB Trace Source ID + input SYNCREQM0; // ATB External synchronization request + +// BEGIN INCLUDE FOR CPU1 + input ATREADYM1; // ATDATA can be accepted + input AFVALIDM1; // ATB Fifo Flush Request + output [31:0] ATDATAM1; // ATB Data + output ATVALIDM1; // ATB Data Valid + output [1:0] ATBYTESM1; // ATB Data Size + output AFREADYM1; // ATB Fifo Flush Finished + output [6:0] ATIDM1; // ATB Trace Source ID + input SYNCREQM1; // ATB External synchronization request +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ATREADYM2; // ATDATA can be accepted + input AFVALIDM2; // ATB Fifo Flush Request + output [31:0] ATDATAM2; // ATB Data + output ATVALIDM2; // ATB Data Valid + output [1:0] ATBYTESM2; // ATB Data Size + output AFREADYM2; // ATB Fifo Flush Finished + output [6:0] ATIDM2; // ATB Trace Source ID + input SYNCREQM2; // ATB External synchronization request +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ATREADYM3; // ATDATA can be accepted + input AFVALIDM3; // ATB Fifo Flush Request + output [31:0] ATDATAM3; // ATB Data + output ATVALIDM3; // ATB Data Valid + output [1:0] ATBYTESM3; // ATB Data Size + output AFREADYM3; // ATB Fifo Flush Finished + output [6:0] ATIDM3; // ATB Trace Source ID + input SYNCREQM3; // ATB External synchronization request +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (PCLK) +//----------------------------------------------------------------------------- +// Debug-APBv3 port (APB) + input PCLKDBG; // APB Clock + input PCLKENDBG; // APB Clock Enable + input nPRESETDBG; // APB Reset + input PSELDBG; // Debug bus access + input [21:2] PADDRDBG; // APB address + input PADDRDBG31; // APB address bit[31] + input PENABLEDBG; // APB transfer complete flag + input PWRITEDBG; // APB read/write indicator + input [31:0] PWDATADBG; // APB write data + output [31:0] PRDATADBG; // APB read data + output PREADYDBG; // APB slave ready, used to extend a transfer + output PSLVERRDBG; // APB slave transfer error + +// Misc interface + input [`MAIA_CN:0] EDBGRQ; // External debug request + +// PMU Snapshot interface + input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request + output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge + +// Power-related interface + input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status + output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request + +// CTI interface + input [3:0] CTICHIN; // Channel In + input [3:0] CTICHOUTACK; // Channel Out acknowledge + output [3:0] CTICHOUT; // Channel Out + output [3:0] CTICHINACK; // Channel In acknowledge + input CISBYPASS; // Channel interface sync bypass + input [3:0] CIHSBYPASS; // Channel interface H/S bypass + output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt + input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge + +//----------------------------------------------------------------------------- +// Debug Authentication Interface (CLK & PCLK) +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] DBGEN; // Invasive debug enable + input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable + input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable + input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable + +//----------------------------------------------------------------------------- +// DFT Signals +//----------------------------------------------------------------------------- + input DFTSE; // Scan enable + input DFTRSTDISABLE; // Disable reset to cells during scan shift + input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr + input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 + input DFTRAMHOLD; // Holds data in RAMs + input DFTCLKBYPASS; // L2 RAM strobe clock bypass + input DFTMCPHOLD; // Disable multi-cycle RAM paths + +//----------------------------------------------------------------------------- +// MBIST Interface +//----------------------------------------------------------------------------- + input nMBISTRESET; // MBIST reset + input MBISTREQ; // MBIST mode request + + + // wires + wire aa64naa32_cpu0_o; + wire aa64naa32_cpu1_o; + wire aa64naa32_cpu2_o; + wire aa64naa32_cpu3_o; + wire afreadym_cpu0_i; + wire afreadym_cpu1_i; + wire afreadym_cpu2_i; + wire afreadym_cpu3_i; + wire afvalidm_cpu0_o; + wire afvalidm_cpu1_o; + wire afvalidm_cpu2_o; + wire afvalidm_cpu3_o; + wire [1:0] atbytesm_cpu0_i; + wire [1:0] atbytesm_cpu1_i; + wire [1:0] atbytesm_cpu2_i; + wire [1:0] atbytesm_cpu3_i; + wire atclken_cpu0_o; + wire atclken_cpu1_o; + wire atclken_cpu2_o; + wire atclken_cpu3_o; + wire [31:0] atdatam_cpu0_i; + wire [31:0] atdatam_cpu1_i; + wire [31:0] atdatam_cpu2_i; + wire [31:0] atdatam_cpu3_i; + wire [6:0] atidm_cpu0_i; + wire [6:0] atidm_cpu1_i; + wire [6:0] atidm_cpu2_i; + wire [6:0] atidm_cpu3_i; + wire atreadym_cpu0_o; + wire atreadym_cpu1_o; + wire atreadym_cpu2_o; + wire atreadym_cpu3_o; + wire atvalidm_cpu0_i; + wire atvalidm_cpu1_i; + wire atvalidm_cpu2_i; + wire atvalidm_cpu3_i; + wire cfgend_cpu0_o; + wire cfgend_cpu1_o; + wire cfgend_cpu2_o; + wire cfgend_cpu3_o; + wire cfgte_cpu0_o; + wire cfgte_cpu1_o; + wire cfgte_cpu2_o; + wire cfgte_cpu3_o; + wire ck_cpu0_crcx_clk_en_n; + wire ck_cpu0_event_reg; + wire ck_cpu0_wfe_ack; + wire ck_cpu0_wfi_ack; + wire ck_cpu1_crcx_clk_en_n; + wire ck_cpu1_event_reg; + wire ck_cpu1_wfe_ack; + wire ck_cpu1_wfi_ack; + wire ck_cpu2_crcx_clk_en_n; + wire ck_cpu2_event_reg; + wire ck_cpu2_wfe_ack; + wire ck_cpu2_wfi_ack; + wire ck_cpu3_crcx_clk_en_n; + wire ck_cpu3_event_reg; + wire ck_cpu3_wfe_ack; + wire ck_cpu3_wfi_ack; + wire [`MAIA_CN:0] ck_gclkt; + wire [7:0] clusteridaff1_cpu0_o; + wire [7:0] clusteridaff1_cpu1_o; + wire [7:0] clusteridaff1_cpu2_o; + wire [7:0] clusteridaff1_cpu3_o; + wire [7:0] clusteridaff2_cpu0_o; + wire [7:0] clusteridaff2_cpu1_o; + wire [7:0] clusteridaff2_cpu2_o; + wire [7:0] clusteridaff2_cpu3_o; + wire commrx_cpu0_i; + wire commrx_cpu1_i; + wire commrx_cpu2_i; + wire commrx_cpu3_i; + wire commtx_cpu0_i; + wire commtx_cpu1_i; + wire commtx_cpu2_i; + wire commtx_cpu3_i; + wire cp15sdisable_cpu0_o; + wire cp15sdisable_cpu1_o; + wire cp15sdisable_cpu2_o; + wire cp15sdisable_cpu3_o; + wire [1:0] cpuid_cpu0_o; + wire [1:0] cpuid_cpu1_o; + wire [1:0] cpuid_cpu2_o; + wire [1:0] cpuid_cpu3_o; + wire cryptodisable_cpu0_o; + wire cryptodisable_cpu1_o; + wire cryptodisable_cpu2_o; + wire cryptodisable_cpu3_o; + wire dbgack_cpu0_i; + wire dbgack_cpu1_i; + wire dbgack_cpu2_i; + wire dbgack_cpu3_i; + wire dbgen_cpu0_o; + wire dbgen_cpu1_o; + wire dbgen_cpu2_o; + wire dbgen_cpu3_o; + wire dbgl1rstdisable_cpu0_o; + wire dbgl1rstdisable_cpu1_o; + wire dbgl1rstdisable_cpu2_o; + wire dbgl1rstdisable_cpu3_o; + wire dbgnopwrdwn_cpu0_i; + wire dbgnopwrdwn_cpu1_i; + wire dbgnopwrdwn_cpu2_i; + wire dbgnopwrdwn_cpu3_i; + wire [43:12] dbgromaddr_cpu0_o; + wire [43:12] dbgromaddr_cpu1_o; + wire [43:12] dbgromaddr_cpu2_o; + wire [43:12] dbgromaddr_cpu3_o; + wire dbgromaddrv_cpu0_o; + wire dbgromaddrv_cpu1_o; + wire dbgromaddrv_cpu2_o; + wire dbgromaddrv_cpu3_o; + wire dbgrstreq_cpu0_i; + wire dbgrstreq_cpu1_i; + wire dbgrstreq_cpu2_i; + wire dbgrstreq_cpu3_i; + wire dftcrclkdisable_cpu0_o; + wire dftcrclkdisable_cpu1_o; + wire dftcrclkdisable_cpu2_o; + wire dftcrclkdisable_cpu3_o; + wire dftramhold_cpu0_o; + wire dftramhold_cpu1_o; + wire dftramhold_cpu2_o; + wire dftramhold_cpu3_o; + wire dftrstdisable_cpu0_o; + wire dftrstdisable_cpu1_o; + wire dftrstdisable_cpu2_o; + wire dftrstdisable_cpu3_o; + wire dftse_cpu0_o; + wire dftse_cpu1_o; + wire dftse_cpu2_o; + wire dftse_cpu3_o; + wire [2:0] ds_cpu0_cpuectlr_ret; + wire ds_cpu0_cpuectlr_smp; + wire ds_cpu0_fiq_wfe_qual; + wire ds_cpu0_fiq_wfi_qual; + wire ds_cpu0_flush; + wire [5:0] ds_cpu0_flush_type; + wire ds_cpu0_hcr_va; + wire ds_cpu0_hcr_vf; + wire ds_cpu0_hcr_vi; + wire ds_cpu0_ic_aa64naa32; + wire [4:0] ds_cpu0_ic_cpsr_mode; + wire ds_cpu0_ic_hcr_change; + wire ds_cpu0_ic_sample_spr; + wire ds_cpu0_ic_scr_change; + wire ds_cpu0_imp_abrt_wfe_qual; + wire ds_cpu0_imp_abrt_wfi_qual; + wire ds_cpu0_irq_wfe_qual; + wire ds_cpu0_irq_wfi_qual; + wire [8:0] ds_cpu0_l2_spr_addr; + wire ds_cpu0_l2_spr_dw; + wire ds_cpu0_l2_spr_en; + wire ds_cpu0_l2_spr_rd; + wire ds_cpu0_l2_spr_wr; + wire [63:0] ds_cpu0_l2_spr_wr_data; + wire ds_cpu0_reset_req; + wire ds_cpu0_sev_req; + wire ds_cpu0_sevl_req; + wire ds_cpu0_vfiq_wfe_qual; + wire ds_cpu0_vfiq_wfi_qual; + wire ds_cpu0_vimp_abrt_wfe_qual; + wire ds_cpu0_vimp_abrt_wfi_qual; + wire ds_cpu0_virq_wfe_qual; + wire ds_cpu0_virq_wfi_qual; + wire ds_cpu0_wfe_req; + wire ds_cpu0_wfi_req; + wire [2:0] ds_cpu1_cpuectlr_ret; + wire ds_cpu1_cpuectlr_smp; + wire ds_cpu1_fiq_wfe_qual; + wire ds_cpu1_fiq_wfi_qual; + wire ds_cpu1_flush; + wire [5:0] ds_cpu1_flush_type; + wire ds_cpu1_hcr_va; + wire ds_cpu1_hcr_vf; + wire ds_cpu1_hcr_vi; + wire ds_cpu1_ic_aa64naa32; + wire [4:0] ds_cpu1_ic_cpsr_mode; + wire ds_cpu1_ic_hcr_change; + wire ds_cpu1_ic_sample_spr; + wire ds_cpu1_ic_scr_change; + wire ds_cpu1_imp_abrt_wfe_qual; + wire ds_cpu1_imp_abrt_wfi_qual; + wire ds_cpu1_irq_wfe_qual; + wire ds_cpu1_irq_wfi_qual; + wire [8:0] ds_cpu1_l2_spr_addr; + wire ds_cpu1_l2_spr_dw; + wire ds_cpu1_l2_spr_en; + wire ds_cpu1_l2_spr_rd; + wire ds_cpu1_l2_spr_wr; + wire [63:0] ds_cpu1_l2_spr_wr_data; + wire ds_cpu1_reset_req; + wire ds_cpu1_sev_req; + wire ds_cpu1_sevl_req; + wire ds_cpu1_vfiq_wfe_qual; + wire ds_cpu1_vfiq_wfi_qual; + wire ds_cpu1_vimp_abrt_wfe_qual; + wire ds_cpu1_vimp_abrt_wfi_qual; + wire ds_cpu1_virq_wfe_qual; + wire ds_cpu1_virq_wfi_qual; + wire ds_cpu1_wfe_req; + wire ds_cpu1_wfi_req; + wire [2:0] ds_cpu2_cpuectlr_ret; + wire ds_cpu2_cpuectlr_smp; + wire ds_cpu2_fiq_wfe_qual; + wire ds_cpu2_fiq_wfi_qual; + wire ds_cpu2_flush; + wire [5:0] ds_cpu2_flush_type; + wire ds_cpu2_hcr_va; + wire ds_cpu2_hcr_vf; + wire ds_cpu2_hcr_vi; + wire ds_cpu2_ic_aa64naa32; + wire [4:0] ds_cpu2_ic_cpsr_mode; + wire ds_cpu2_ic_hcr_change; + wire ds_cpu2_ic_sample_spr; + wire ds_cpu2_ic_scr_change; + wire ds_cpu2_imp_abrt_wfe_qual; + wire ds_cpu2_imp_abrt_wfi_qual; + wire ds_cpu2_irq_wfe_qual; + wire ds_cpu2_irq_wfi_qual; + wire [8:0] ds_cpu2_l2_spr_addr; + wire ds_cpu2_l2_spr_dw; + wire ds_cpu2_l2_spr_en; + wire ds_cpu2_l2_spr_rd; + wire ds_cpu2_l2_spr_wr; + wire [63:0] ds_cpu2_l2_spr_wr_data; + wire ds_cpu2_reset_req; + wire ds_cpu2_sev_req; + wire ds_cpu2_sevl_req; + wire ds_cpu2_vfiq_wfe_qual; + wire ds_cpu2_vfiq_wfi_qual; + wire ds_cpu2_vimp_abrt_wfe_qual; + wire ds_cpu2_vimp_abrt_wfi_qual; + wire ds_cpu2_virq_wfe_qual; + wire ds_cpu2_virq_wfi_qual; + wire ds_cpu2_wfe_req; + wire ds_cpu2_wfi_req; + wire [2:0] ds_cpu3_cpuectlr_ret; + wire ds_cpu3_cpuectlr_smp; + wire ds_cpu3_fiq_wfe_qual; + wire ds_cpu3_fiq_wfi_qual; + wire ds_cpu3_flush; + wire [5:0] ds_cpu3_flush_type; + wire ds_cpu3_hcr_va; + wire ds_cpu3_hcr_vf; + wire ds_cpu3_hcr_vi; + wire ds_cpu3_ic_aa64naa32; + wire [4:0] ds_cpu3_ic_cpsr_mode; + wire ds_cpu3_ic_hcr_change; + wire ds_cpu3_ic_sample_spr; + wire ds_cpu3_ic_scr_change; + wire ds_cpu3_imp_abrt_wfe_qual; + wire ds_cpu3_imp_abrt_wfi_qual; + wire ds_cpu3_irq_wfe_qual; + wire ds_cpu3_irq_wfi_qual; + wire [8:0] ds_cpu3_l2_spr_addr; + wire ds_cpu3_l2_spr_dw; + wire ds_cpu3_l2_spr_en; + wire ds_cpu3_l2_spr_rd; + wire ds_cpu3_l2_spr_wr; + wire [63:0] ds_cpu3_l2_spr_wr_data; + wire ds_cpu3_reset_req; + wire ds_cpu3_sev_req; + wire ds_cpu3_sevl_req; + wire ds_cpu3_vfiq_wfe_qual; + wire ds_cpu3_vfiq_wfi_qual; + wire ds_cpu3_vimp_abrt_wfe_qual; + wire ds_cpu3_vimp_abrt_wfi_qual; + wire ds_cpu3_virq_wfe_qual; + wire ds_cpu3_virq_wfi_qual; + wire ds_cpu3_wfe_req; + wire ds_cpu3_wfi_req; + wire dt_cpu0_coredbg_in_reset_gclk; + wire [1:0] dt_cpu0_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu0_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu0_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu0_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu0_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu0_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; + wire dt_cpu0_cti_trigoutack_bit1_gclk; + wire dt_cpu0_dbif_ack_gclk; + wire [14:2] dt_cpu0_dbif_addr_pclk; + wire dt_cpu0_dbif_err_gclk; + wire dt_cpu0_dbif_locked_pclk; + wire [31:0] dt_cpu0_dbif_rddata_gclk; + wire dt_cpu0_dbif_req_pclk; + wire [31:0] dt_cpu0_dbif_wrdata_pclk; + wire dt_cpu0_dbif_write_pclk; + wire dt_cpu0_edacr_frc_idleack_pclk; + wire dt_cpu0_edbgrq_pclk; + wire dt_cpu0_edecr_osuce_pclk; + wire dt_cpu0_edecr_rce_pclk; + wire dt_cpu0_edecr_ss_pclk; + wire dt_cpu0_edprcr_corepurq_pclk; + wire dt_cpu0_et_oslock_gclk; + wire dt_cpu0_halt_ack_gclk; + wire dt_cpu0_hlt_dbgevt_ok_gclk; + wire dt_cpu0_noclkstop_pclk; + wire dt_cpu0_os_double_lock_gclk; + wire dt_cpu0_pmusnapshot_ack_gclk; + wire dt_cpu0_pmusnapshot_req_pclk; + wire dt_cpu0_wfx_dbg_req_gclk; + wire dt_cpu0_wfx_wakeup_pclk; + wire dt_cpu1_coredbg_in_reset_gclk; + wire [1:0] dt_cpu1_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu1_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu1_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu1_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu1_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu1_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; + wire dt_cpu1_cti_trigoutack_bit1_gclk; + wire dt_cpu1_dbif_ack_gclk; + wire [14:2] dt_cpu1_dbif_addr_pclk; + wire dt_cpu1_dbif_err_gclk; + wire dt_cpu1_dbif_locked_pclk; + wire [31:0] dt_cpu1_dbif_rddata_gclk; + wire dt_cpu1_dbif_req_pclk; + wire [31:0] dt_cpu1_dbif_wrdata_pclk; + wire dt_cpu1_dbif_write_pclk; + wire dt_cpu1_edacr_frc_idleack_pclk; + wire dt_cpu1_edbgrq_pclk; + wire dt_cpu1_edecr_osuce_pclk; + wire dt_cpu1_edecr_rce_pclk; + wire dt_cpu1_edecr_ss_pclk; + wire dt_cpu1_edprcr_corepurq_pclk; + wire dt_cpu1_et_oslock_gclk; + wire dt_cpu1_halt_ack_gclk; + wire dt_cpu1_hlt_dbgevt_ok_gclk; + wire dt_cpu1_noclkstop_pclk; + wire dt_cpu1_os_double_lock_gclk; + wire dt_cpu1_pmusnapshot_ack_gclk; + wire dt_cpu1_pmusnapshot_req_pclk; + wire dt_cpu1_wfx_dbg_req_gclk; + wire dt_cpu1_wfx_wakeup_pclk; + wire dt_cpu2_coredbg_in_reset_gclk; + wire [1:0] dt_cpu2_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu2_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu2_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu2_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu2_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu2_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; + wire dt_cpu2_cti_trigoutack_bit1_gclk; + wire dt_cpu2_dbif_ack_gclk; + wire [14:2] dt_cpu2_dbif_addr_pclk; + wire dt_cpu2_dbif_err_gclk; + wire dt_cpu2_dbif_locked_pclk; + wire [31:0] dt_cpu2_dbif_rddata_gclk; + wire dt_cpu2_dbif_req_pclk; + wire [31:0] dt_cpu2_dbif_wrdata_pclk; + wire dt_cpu2_dbif_write_pclk; + wire dt_cpu2_edacr_frc_idleack_pclk; + wire dt_cpu2_edbgrq_pclk; + wire dt_cpu2_edecr_osuce_pclk; + wire dt_cpu2_edecr_rce_pclk; + wire dt_cpu2_edecr_ss_pclk; + wire dt_cpu2_edprcr_corepurq_pclk; + wire dt_cpu2_et_oslock_gclk; + wire dt_cpu2_halt_ack_gclk; + wire dt_cpu2_hlt_dbgevt_ok_gclk; + wire dt_cpu2_noclkstop_pclk; + wire dt_cpu2_os_double_lock_gclk; + wire dt_cpu2_pmusnapshot_ack_gclk; + wire dt_cpu2_pmusnapshot_req_pclk; + wire dt_cpu2_wfx_dbg_req_gclk; + wire dt_cpu2_wfx_wakeup_pclk; + wire dt_cpu3_coredbg_in_reset_gclk; + wire [1:0] dt_cpu3_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu3_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu3_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu3_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu3_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu3_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; + wire dt_cpu3_cti_trigoutack_bit1_gclk; + wire dt_cpu3_dbif_ack_gclk; + wire [14:2] dt_cpu3_dbif_addr_pclk; + wire dt_cpu3_dbif_err_gclk; + wire dt_cpu3_dbif_locked_pclk; + wire [31:0] dt_cpu3_dbif_rddata_gclk; + wire dt_cpu3_dbif_req_pclk; + wire [31:0] dt_cpu3_dbif_wrdata_pclk; + wire dt_cpu3_dbif_write_pclk; + wire dt_cpu3_edacr_frc_idleack_pclk; + wire dt_cpu3_edbgrq_pclk; + wire dt_cpu3_edecr_osuce_pclk; + wire dt_cpu3_edecr_rce_pclk; + wire dt_cpu3_edecr_ss_pclk; + wire dt_cpu3_edprcr_corepurq_pclk; + wire dt_cpu3_et_oslock_gclk; + wire dt_cpu3_halt_ack_gclk; + wire dt_cpu3_hlt_dbgevt_ok_gclk; + wire dt_cpu3_noclkstop_pclk; + wire dt_cpu3_os_double_lock_gclk; + wire dt_cpu3_pmusnapshot_ack_gclk; + wire dt_cpu3_pmusnapshot_req_pclk; + wire dt_cpu3_wfx_dbg_req_gclk; + wire dt_cpu3_wfx_wakeup_pclk; + wire etclken_cpu0_i; + wire etclken_cpu1_i; + wire etclken_cpu2_i; + wire etclken_cpu3_i; + wire giccdisable_cpu0_o; + wire giccdisable_cpu1_o; + wire giccdisable_cpu2_o; + wire giccdisable_cpu3_o; + wire [`MAIA_CN:0] ic_block_eoi_sgi_wr; + wire [`MAIA_CN:0] ic_el_change_complete; + wire [`MAIA_CN:0] ic_hcr_change_complete; + wire [`MAIA_CN:0] ic_ich_el2_tall0; + wire [`MAIA_CN:0] ic_ich_el2_tall1; + wire [`MAIA_CN:0] ic_ich_el2_tc; + wire [`MAIA_CN:0] ic_nfiq; + wire [`MAIA_CN:0] ic_nirq; + wire [`MAIA_CN:0] ic_nsei; + wire [`MAIA_CN:0] ic_nvfiq; + wire [`MAIA_CN:0] ic_nvirq; + wire [`MAIA_CN:0] ic_nvsei; + wire [`MAIA_CN:0] ic_p_valid; + wire [`MAIA_CN:0] ic_sample_spr; + wire [`MAIA_CN:0] ic_scr_change_complete; + wire [`MAIA_CN:0] ic_sra_el1ns_en; + wire [`MAIA_CN:0] ic_sra_el1s_en; + wire [`MAIA_CN:0] ic_sra_el2_en; + wire [`MAIA_CN:0] ic_sra_el3_en; + wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; + wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap; + wire [`MAIA_CN:0] ic_sre_el1s_mon_trap; + wire [`MAIA_CN:0] ic_sre_el2_mon_trap; + wire l2_cpu0_arb_thrshld_timeout_en; + wire l2_cpu0_barrier_done; + wire l2_cpu0_blk_non_evict_wr; + wire l2_cpu0_ccb_dbg_req_c3; + wire [48:0] l2_cpu0_ccb_req_addr_c3; + wire [4:0] l2_cpu0_ccb_req_id_c3; + wire [23:0] l2_cpu0_ccb_req_info_c3; + wire [8:0] l2_cpu0_ccb_req_type_c3; + wire l2_cpu0_cfg_ecc_en; + wire [2:0] l2_cpu0_dbufid_r1; + wire [129:0] l2_cpu0_ddata_r2; + wire l2_cpu0_ddlb_ecc_err_r3; + wire l2_cpu0_dext_err_r2; + wire l2_cpu0_dext_err_type_r2; + wire l2_cpu0_disable_clean_evict_opt; + wire l2_cpu0_dlast_r1; + wire l2_cpu0_dsngl_ecc_err_r3; + wire [3:0] l2_cpu0_dsq_clr_id_q; + wire l2_cpu0_dsq_clr_vld_q; + wire [3:0] l2_cpu0_dsq_rd_buf_id; + wire [15:0] l2_cpu0_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu0_dsq_rd_data_q; + wire l2_cpu0_dsq_rd_en; + wire l2_cpu0_dsq_rd_en_x2; + wire l2_cpu0_dt_pmu_evt_en; + wire l2_cpu0_dvalid_r1; + wire l2_cpu0_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; + wire l2_cpu0_flsh_if_rd_l4_dly; + wire l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; + wire l2_cpu0_flsh_ls_rd_l2_dly; + wire l2_cpu0_flsh_ls_rd_l4_dly; + wire l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; + wire l2_cpu0_flsh_ls_wr_l2_dly; + wire l2_cpu0_flsh_ls_wr_l4_dly; + wire l2_cpu0_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu0_ibufid_r1; + wire [15:0] l2_cpu0_ic_addr_arb_set; + wire l2_cpu0_ic_arb_fast; + wire l2_cpu0_ic_barrier_stall_q; + wire [43:18] l2_cpu0_ic_base; + wire [31:0] l2_cpu0_ic_data_arb_set; + wire [2:0] l2_cpu0_ic_elem_size_arb_set; + wire l2_cpu0_ic_excl_arb_set; + wire [2:0] l2_cpu0_ic_id_arb_set; + wire l2_cpu0_ic_ns_arb_set; + wire l2_cpu0_ic_vld_skid; + wire l2_cpu0_ic_write_arb_set; + wire [127:0] l2_cpu0_idata_r2; + wire l2_cpu0_idlb_ecc_err_r3; + wire l2_cpu0_idle_block_reqs_q; + wire l2_cpu0_idle_wakeup_q; + wire l2_cpu0_iext_err_r2; + wire l2_cpu0_iext_err_type_r2; + wire l2_cpu0_if_ccb_clken_c3; + wire l2_cpu0_if_ccb_req_c3; + wire l2_cpu0_if_ccb_resp; + wire [4:0] l2_cpu0_if_ccb_resp_id; + wire l2_cpu0_if_sync_done_q; + wire l2_cpu0_if_sync_req; + wire l2_cpu0_ifq_haz_pending; + wire l2_cpu0_isngl_ecc_err_r3; + wire l2_cpu0_ivalid_r1; + wire [1:0] l2_cpu0_l2_cache_size; + wire [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; + wire l2_cpu0_lrq_haz_pending; + wire l2_cpu0_ls_ccb_clken_c3; + wire l2_cpu0_ls_ccb_data_wr; + wire l2_cpu0_ls_ccb_req_c3; + wire l2_cpu0_ls_ccb_resp; + wire [4:0] l2_cpu0_ls_ccb_resp_id; + wire l2_cpu0_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu0_ls_rd_haz_id_arb_q; + wire l2_cpu0_ls_rd_haz_vld_arb_q; + wire l2_cpu0_ls_sync_req; + wire [4:0] l2_cpu0_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu0_ls_wr_data_w2a; + wire l2_cpu0_ls_wr_dirty_w2a; + wire l2_cpu0_ls_wr_err_w2a; + wire [2:0] l2_cpu0_ls_wr_haz_id_arb_q; + wire l2_cpu0_ls_wr_haz_vld_arb_q; + wire l2_cpu0_ls_wr_last_w2a; + wire l2_cpu0_ls_wr_req_w2a; + wire [2:0] l2_cpu0_ls_wr_type_w2a; + wire [12:0] l2_cpu0_mbist1_addr_b1; + wire l2_cpu0_mbist1_all_b1; + wire [3:0] l2_cpu0_mbist1_array_b1; + wire [7:0] l2_cpu0_mbist1_be_b1; + wire l2_cpu0_mbist1_en_b1; + wire l2_cpu0_mbist1_rd_en_b1; + wire l2_cpu0_mbist1_wr_en_b1; + wire l2_cpu0_no_intctrl; + wire l2_cpu0_pf_rd_vld_skid_popped; + wire l2_cpu0_pf_throttle_q; + wire [33:0] l2_cpu0_pmu_events; + wire [2:0] l2_cpu0_rbufid; + wire l2_cpu0_rd_aarch64_arb_set; + wire [44:0] l2_cpu0_rd_addr_arb_set; + wire l2_cpu0_rd_arb; + wire l2_cpu0_rd_arb_fast; + wire [15:8] l2_cpu0_rd_asid_arb_set; + wire l2_cpu0_rd_bypass_arb_set; + wire [2:0] l2_cpu0_rd_bypass_bufid_e5; + wire [2:0] l2_cpu0_rd_bypass_lrq_id_e5; + wire l2_cpu0_rd_bypass_req_can_e5; + wire l2_cpu0_rd_bypass_way_e5; + wire [2:0] l2_cpu0_rd_cache_attr_arb_set; + wire [2:0] l2_cpu0_rd_elem_size_arb_set; + wire l2_cpu0_rd_excl_arb_set; + wire [4:0] l2_cpu0_rd_id_arb_set; + wire [2:0] l2_cpu0_rd_lrq_id_arb_set; + wire [7:0] l2_cpu0_rd_page_attr_arb_set; + wire l2_cpu0_rd_prfm_arb_set; + wire l2_cpu0_rd_priv_arb_set; + wire l2_cpu0_rd_replayed_arb_set; + wire [1:0] l2_cpu0_rd_shared_arb_set; + wire [6:0] l2_cpu0_rd_type_arb_set; + wire l2_cpu0_rd_va48_arb_set; + wire l2_cpu0_rd_vld_skid; + wire l2_cpu0_rd_way_arb_set; + wire l2_cpu0_rexfail; + wire [1:0] l2_cpu0_rstate; + wire l2_cpu0_rvalid; + wire [2:0] l2_cpu0_spec_bufid; + wire l2_cpu0_spec_valid; + wire [63:0] l2_cpu0_spr_rd_data; + wire l2_cpu0_tbw_dbl_ecc_err; + wire [63:0] l2_cpu0_tbw_desc_data; + wire l2_cpu0_tbw_desc_vld; + wire l2_cpu0_tbw_ext_err; + wire l2_cpu0_tbw_ext_err_type; + wire l2_cpu0_tlb_ccb_clken_c3; + wire l2_cpu0_tlb_ccb_req_c3; + wire l2_cpu0_tlb_sync_complete; + wire l2_cpu0_tlb_sync_done_q; + wire l2_cpu0_tlb_sync_req; + wire l2_cpu0_trq_haz_pending; + wire l2_cpu0_tw_ccb_resp; + wire [4:0] l2_cpu0_tw_ccb_resp_id; + wire l2_cpu0_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu0_wr_addr_arb_set; + wire l2_cpu0_wr_arb; + wire l2_cpu0_wr_arb_fast; + wire [2:0] l2_cpu0_wr_cache_attr_arb_set; + wire [11:0] l2_cpu0_wr_cl_id_arb_set; + wire l2_cpu0_wr_clean_evict_arb_set; + wire [143:0] l2_cpu0_wr_data; + wire l2_cpu0_wr_data_stall; + wire l2_cpu0_wr_data_vld_x1_q; + wire l2_cpu0_wr_dirty_arb_set; + wire [2:0] l2_cpu0_wr_elem_size_arb_set; + wire l2_cpu0_wr_err_arb_set; + wire l2_cpu0_wr_evict_x1_q; + wire l2_cpu0_wr_ex_fail; + wire l2_cpu0_wr_ex_resp; + wire [3:0] l2_cpu0_wr_id_arb_set; + wire l2_cpu0_wr_last_arb_set; + wire [7:0] l2_cpu0_wr_page_attr_arb_set; + wire [3:0] l2_cpu0_wr_partial_dw_arb_set; + wire l2_cpu0_wr_priv_arb_set; + wire [1:0] l2_cpu0_wr_shared_arb_set; + wire [2:0] l2_cpu0_wr_type_arb_set; + wire l2_cpu0_wr_vld_skid; + wire l2_cpu0_wr_way_arb_set; + wire l2_cpu0_wrq_almost_full; + wire [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; + wire l2_cpu0_wrq_haz_pending; + wire l2_cpu1_arb_thrshld_timeout_en; + wire l2_cpu1_barrier_done; + wire l2_cpu1_blk_non_evict_wr; + wire l2_cpu1_ccb_dbg_req_c3; + wire [48:0] l2_cpu1_ccb_req_addr_c3; + wire [4:0] l2_cpu1_ccb_req_id_c3; + wire [23:0] l2_cpu1_ccb_req_info_c3; + wire [8:0] l2_cpu1_ccb_req_type_c3; + wire l2_cpu1_cfg_ecc_en; + wire [2:0] l2_cpu1_dbufid_r1; + wire [129:0] l2_cpu1_ddata_r2; + wire l2_cpu1_ddlb_ecc_err_r3; + wire l2_cpu1_dext_err_r2; + wire l2_cpu1_dext_err_type_r2; + wire l2_cpu1_disable_clean_evict_opt; + wire l2_cpu1_dlast_r1; + wire l2_cpu1_dsngl_ecc_err_r3; + wire [3:0] l2_cpu1_dsq_clr_id_q; + wire l2_cpu1_dsq_clr_vld_q; + wire [3:0] l2_cpu1_dsq_rd_buf_id; + wire [15:0] l2_cpu1_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu1_dsq_rd_data_q; + wire l2_cpu1_dsq_rd_en; + wire l2_cpu1_dsq_rd_en_x2; + wire l2_cpu1_dt_pmu_evt_en; + wire l2_cpu1_dvalid_r1; + wire l2_cpu1_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; + wire l2_cpu1_flsh_if_rd_l4_dly; + wire l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; + wire l2_cpu1_flsh_ls_rd_l2_dly; + wire l2_cpu1_flsh_ls_rd_l4_dly; + wire l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; + wire l2_cpu1_flsh_ls_wr_l2_dly; + wire l2_cpu1_flsh_ls_wr_l4_dly; + wire l2_cpu1_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu1_ibufid_r1; + wire [15:0] l2_cpu1_ic_addr_arb_set; + wire l2_cpu1_ic_arb_fast; + wire l2_cpu1_ic_barrier_stall_q; + wire [43:18] l2_cpu1_ic_base; + wire [31:0] l2_cpu1_ic_data_arb_set; + wire [2:0] l2_cpu1_ic_elem_size_arb_set; + wire l2_cpu1_ic_excl_arb_set; + wire [2:0] l2_cpu1_ic_id_arb_set; + wire l2_cpu1_ic_ns_arb_set; + wire l2_cpu1_ic_vld_skid; + wire l2_cpu1_ic_write_arb_set; + wire [127:0] l2_cpu1_idata_r2; + wire l2_cpu1_idlb_ecc_err_r3; + wire l2_cpu1_idle_block_reqs_q; + wire l2_cpu1_idle_wakeup_q; + wire l2_cpu1_iext_err_r2; + wire l2_cpu1_iext_err_type_r2; + wire l2_cpu1_if_ccb_clken_c3; + wire l2_cpu1_if_ccb_req_c3; + wire l2_cpu1_if_ccb_resp; + wire [4:0] l2_cpu1_if_ccb_resp_id; + wire l2_cpu1_if_sync_done_q; + wire l2_cpu1_if_sync_req; + wire l2_cpu1_ifq_haz_pending; + wire l2_cpu1_isngl_ecc_err_r3; + wire l2_cpu1_ivalid_r1; + wire [1:0] l2_cpu1_l2_cache_size; + wire [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; + wire l2_cpu1_lrq_haz_pending; + wire l2_cpu1_ls_ccb_clken_c3; + wire l2_cpu1_ls_ccb_data_wr; + wire l2_cpu1_ls_ccb_req_c3; + wire l2_cpu1_ls_ccb_resp; + wire [4:0] l2_cpu1_ls_ccb_resp_id; + wire l2_cpu1_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu1_ls_rd_haz_id_arb_q; + wire l2_cpu1_ls_rd_haz_vld_arb_q; + wire l2_cpu1_ls_sync_req; + wire [4:0] l2_cpu1_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu1_ls_wr_data_w2a; + wire l2_cpu1_ls_wr_dirty_w2a; + wire l2_cpu1_ls_wr_err_w2a; + wire [2:0] l2_cpu1_ls_wr_haz_id_arb_q; + wire l2_cpu1_ls_wr_haz_vld_arb_q; + wire l2_cpu1_ls_wr_last_w2a; + wire l2_cpu1_ls_wr_req_w2a; + wire [2:0] l2_cpu1_ls_wr_type_w2a; + wire [12:0] l2_cpu1_mbist1_addr_b1; + wire l2_cpu1_mbist1_all_b1; + wire [3:0] l2_cpu1_mbist1_array_b1; + wire [7:0] l2_cpu1_mbist1_be_b1; + wire l2_cpu1_mbist1_en_b1; + wire l2_cpu1_mbist1_rd_en_b1; + wire l2_cpu1_mbist1_wr_en_b1; + wire l2_cpu1_no_intctrl; + wire l2_cpu1_pf_rd_vld_skid_popped; + wire l2_cpu1_pf_throttle_q; + wire [33:0] l2_cpu1_pmu_events; + wire [2:0] l2_cpu1_rbufid; + wire l2_cpu1_rd_aarch64_arb_set; + wire [44:0] l2_cpu1_rd_addr_arb_set; + wire l2_cpu1_rd_arb; + wire l2_cpu1_rd_arb_fast; + wire [15:8] l2_cpu1_rd_asid_arb_set; + wire l2_cpu1_rd_bypass_arb_set; + wire [2:0] l2_cpu1_rd_bypass_bufid_e5; + wire [2:0] l2_cpu1_rd_bypass_lrq_id_e5; + wire l2_cpu1_rd_bypass_req_can_e5; + wire l2_cpu1_rd_bypass_way_e5; + wire [2:0] l2_cpu1_rd_cache_attr_arb_set; + wire [2:0] l2_cpu1_rd_elem_size_arb_set; + wire l2_cpu1_rd_excl_arb_set; + wire [4:0] l2_cpu1_rd_id_arb_set; + wire [2:0] l2_cpu1_rd_lrq_id_arb_set; + wire [7:0] l2_cpu1_rd_page_attr_arb_set; + wire l2_cpu1_rd_prfm_arb_set; + wire l2_cpu1_rd_priv_arb_set; + wire l2_cpu1_rd_replayed_arb_set; + wire [1:0] l2_cpu1_rd_shared_arb_set; + wire [6:0] l2_cpu1_rd_type_arb_set; + wire l2_cpu1_rd_va48_arb_set; + wire l2_cpu1_rd_vld_skid; + wire l2_cpu1_rd_way_arb_set; + wire l2_cpu1_rexfail; + wire [1:0] l2_cpu1_rstate; + wire l2_cpu1_rvalid; + wire [2:0] l2_cpu1_spec_bufid; + wire l2_cpu1_spec_valid; + wire [63:0] l2_cpu1_spr_rd_data; + wire l2_cpu1_tbw_dbl_ecc_err; + wire [63:0] l2_cpu1_tbw_desc_data; + wire l2_cpu1_tbw_desc_vld; + wire l2_cpu1_tbw_ext_err; + wire l2_cpu1_tbw_ext_err_type; + wire l2_cpu1_tlb_ccb_clken_c3; + wire l2_cpu1_tlb_ccb_req_c3; + wire l2_cpu1_tlb_sync_complete; + wire l2_cpu1_tlb_sync_done_q; + wire l2_cpu1_tlb_sync_req; + wire l2_cpu1_trq_haz_pending; + wire l2_cpu1_tw_ccb_resp; + wire [4:0] l2_cpu1_tw_ccb_resp_id; + wire l2_cpu1_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu1_wr_addr_arb_set; + wire l2_cpu1_wr_arb; + wire l2_cpu1_wr_arb_fast; + wire [2:0] l2_cpu1_wr_cache_attr_arb_set; + wire [11:0] l2_cpu1_wr_cl_id_arb_set; + wire l2_cpu1_wr_clean_evict_arb_set; + wire [143:0] l2_cpu1_wr_data; + wire l2_cpu1_wr_data_stall; + wire l2_cpu1_wr_data_vld_x1_q; + wire l2_cpu1_wr_dirty_arb_set; + wire [2:0] l2_cpu1_wr_elem_size_arb_set; + wire l2_cpu1_wr_err_arb_set; + wire l2_cpu1_wr_evict_x1_q; + wire l2_cpu1_wr_ex_fail; + wire l2_cpu1_wr_ex_resp; + wire [3:0] l2_cpu1_wr_id_arb_set; + wire l2_cpu1_wr_last_arb_set; + wire [7:0] l2_cpu1_wr_page_attr_arb_set; + wire [3:0] l2_cpu1_wr_partial_dw_arb_set; + wire l2_cpu1_wr_priv_arb_set; + wire [1:0] l2_cpu1_wr_shared_arb_set; + wire [2:0] l2_cpu1_wr_type_arb_set; + wire l2_cpu1_wr_vld_skid; + wire l2_cpu1_wr_way_arb_set; + wire l2_cpu1_wrq_almost_full; + wire [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; + wire l2_cpu1_wrq_haz_pending; + wire l2_cpu2_arb_thrshld_timeout_en; + wire l2_cpu2_barrier_done; + wire l2_cpu2_blk_non_evict_wr; + wire l2_cpu2_ccb_dbg_req_c3; + wire [48:0] l2_cpu2_ccb_req_addr_c3; + wire [4:0] l2_cpu2_ccb_req_id_c3; + wire [23:0] l2_cpu2_ccb_req_info_c3; + wire [8:0] l2_cpu2_ccb_req_type_c3; + wire l2_cpu2_cfg_ecc_en; + wire [2:0] l2_cpu2_dbufid_r1; + wire [129:0] l2_cpu2_ddata_r2; + wire l2_cpu2_ddlb_ecc_err_r3; + wire l2_cpu2_dext_err_r2; + wire l2_cpu2_dext_err_type_r2; + wire l2_cpu2_disable_clean_evict_opt; + wire l2_cpu2_dlast_r1; + wire l2_cpu2_dsngl_ecc_err_r3; + wire [3:0] l2_cpu2_dsq_clr_id_q; + wire l2_cpu2_dsq_clr_vld_q; + wire [3:0] l2_cpu2_dsq_rd_buf_id; + wire [15:0] l2_cpu2_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu2_dsq_rd_data_q; + wire l2_cpu2_dsq_rd_en; + wire l2_cpu2_dsq_rd_en_x2; + wire l2_cpu2_dt_pmu_evt_en; + wire l2_cpu2_dvalid_r1; + wire l2_cpu2_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; + wire l2_cpu2_flsh_if_rd_l4_dly; + wire l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; + wire l2_cpu2_flsh_ls_rd_l2_dly; + wire l2_cpu2_flsh_ls_rd_l4_dly; + wire l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; + wire l2_cpu2_flsh_ls_wr_l2_dly; + wire l2_cpu2_flsh_ls_wr_l4_dly; + wire l2_cpu2_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu2_ibufid_r1; + wire [15:0] l2_cpu2_ic_addr_arb_set; + wire l2_cpu2_ic_arb_fast; + wire l2_cpu2_ic_barrier_stall_q; + wire [43:18] l2_cpu2_ic_base; + wire [31:0] l2_cpu2_ic_data_arb_set; + wire [2:0] l2_cpu2_ic_elem_size_arb_set; + wire l2_cpu2_ic_excl_arb_set; + wire [2:0] l2_cpu2_ic_id_arb_set; + wire l2_cpu2_ic_ns_arb_set; + wire l2_cpu2_ic_vld_skid; + wire l2_cpu2_ic_write_arb_set; + wire [127:0] l2_cpu2_idata_r2; + wire l2_cpu2_idlb_ecc_err_r3; + wire l2_cpu2_idle_block_reqs_q; + wire l2_cpu2_idle_wakeup_q; + wire l2_cpu2_iext_err_r2; + wire l2_cpu2_iext_err_type_r2; + wire l2_cpu2_if_ccb_clken_c3; + wire l2_cpu2_if_ccb_req_c3; + wire l2_cpu2_if_ccb_resp; + wire [4:0] l2_cpu2_if_ccb_resp_id; + wire l2_cpu2_if_sync_done_q; + wire l2_cpu2_if_sync_req; + wire l2_cpu2_ifq_haz_pending; + wire l2_cpu2_isngl_ecc_err_r3; + wire l2_cpu2_ivalid_r1; + wire [1:0] l2_cpu2_l2_cache_size; + wire [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; + wire l2_cpu2_lrq_haz_pending; + wire l2_cpu2_ls_ccb_clken_c3; + wire l2_cpu2_ls_ccb_data_wr; + wire l2_cpu2_ls_ccb_req_c3; + wire l2_cpu2_ls_ccb_resp; + wire [4:0] l2_cpu2_ls_ccb_resp_id; + wire l2_cpu2_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu2_ls_rd_haz_id_arb_q; + wire l2_cpu2_ls_rd_haz_vld_arb_q; + wire l2_cpu2_ls_sync_req; + wire [4:0] l2_cpu2_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu2_ls_wr_data_w2a; + wire l2_cpu2_ls_wr_dirty_w2a; + wire l2_cpu2_ls_wr_err_w2a; + wire [2:0] l2_cpu2_ls_wr_haz_id_arb_q; + wire l2_cpu2_ls_wr_haz_vld_arb_q; + wire l2_cpu2_ls_wr_last_w2a; + wire l2_cpu2_ls_wr_req_w2a; + wire [2:0] l2_cpu2_ls_wr_type_w2a; + wire [12:0] l2_cpu2_mbist1_addr_b1; + wire l2_cpu2_mbist1_all_b1; + wire [3:0] l2_cpu2_mbist1_array_b1; + wire [7:0] l2_cpu2_mbist1_be_b1; + wire l2_cpu2_mbist1_en_b1; + wire l2_cpu2_mbist1_rd_en_b1; + wire l2_cpu2_mbist1_wr_en_b1; + wire l2_cpu2_no_intctrl; + wire l2_cpu2_pf_rd_vld_skid_popped; + wire l2_cpu2_pf_throttle_q; + wire [33:0] l2_cpu2_pmu_events; + wire [2:0] l2_cpu2_rbufid; + wire l2_cpu2_rd_aarch64_arb_set; + wire [44:0] l2_cpu2_rd_addr_arb_set; + wire l2_cpu2_rd_arb; + wire l2_cpu2_rd_arb_fast; + wire [15:8] l2_cpu2_rd_asid_arb_set; + wire l2_cpu2_rd_bypass_arb_set; + wire [2:0] l2_cpu2_rd_bypass_bufid_e5; + wire [2:0] l2_cpu2_rd_bypass_lrq_id_e5; + wire l2_cpu2_rd_bypass_req_can_e5; + wire l2_cpu2_rd_bypass_way_e5; + wire [2:0] l2_cpu2_rd_cache_attr_arb_set; + wire [2:0] l2_cpu2_rd_elem_size_arb_set; + wire l2_cpu2_rd_excl_arb_set; + wire [4:0] l2_cpu2_rd_id_arb_set; + wire [2:0] l2_cpu2_rd_lrq_id_arb_set; + wire [7:0] l2_cpu2_rd_page_attr_arb_set; + wire l2_cpu2_rd_prfm_arb_set; + wire l2_cpu2_rd_priv_arb_set; + wire l2_cpu2_rd_replayed_arb_set; + wire [1:0] l2_cpu2_rd_shared_arb_set; + wire [6:0] l2_cpu2_rd_type_arb_set; + wire l2_cpu2_rd_va48_arb_set; + wire l2_cpu2_rd_vld_skid; + wire l2_cpu2_rd_way_arb_set; + wire l2_cpu2_rexfail; + wire [1:0] l2_cpu2_rstate; + wire l2_cpu2_rvalid; + wire [2:0] l2_cpu2_spec_bufid; + wire l2_cpu2_spec_valid; + wire [63:0] l2_cpu2_spr_rd_data; + wire l2_cpu2_tbw_dbl_ecc_err; + wire [63:0] l2_cpu2_tbw_desc_data; + wire l2_cpu2_tbw_desc_vld; + wire l2_cpu2_tbw_ext_err; + wire l2_cpu2_tbw_ext_err_type; + wire l2_cpu2_tlb_ccb_clken_c3; + wire l2_cpu2_tlb_ccb_req_c3; + wire l2_cpu2_tlb_sync_complete; + wire l2_cpu2_tlb_sync_done_q; + wire l2_cpu2_tlb_sync_req; + wire l2_cpu2_trq_haz_pending; + wire l2_cpu2_tw_ccb_resp; + wire [4:0] l2_cpu2_tw_ccb_resp_id; + wire l2_cpu2_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu2_wr_addr_arb_set; + wire l2_cpu2_wr_arb; + wire l2_cpu2_wr_arb_fast; + wire [2:0] l2_cpu2_wr_cache_attr_arb_set; + wire [11:0] l2_cpu2_wr_cl_id_arb_set; + wire l2_cpu2_wr_clean_evict_arb_set; + wire [143:0] l2_cpu2_wr_data; + wire l2_cpu2_wr_data_stall; + wire l2_cpu2_wr_data_vld_x1_q; + wire l2_cpu2_wr_dirty_arb_set; + wire [2:0] l2_cpu2_wr_elem_size_arb_set; + wire l2_cpu2_wr_err_arb_set; + wire l2_cpu2_wr_evict_x1_q; + wire l2_cpu2_wr_ex_fail; + wire l2_cpu2_wr_ex_resp; + wire [3:0] l2_cpu2_wr_id_arb_set; + wire l2_cpu2_wr_last_arb_set; + wire [7:0] l2_cpu2_wr_page_attr_arb_set; + wire [3:0] l2_cpu2_wr_partial_dw_arb_set; + wire l2_cpu2_wr_priv_arb_set; + wire [1:0] l2_cpu2_wr_shared_arb_set; + wire [2:0] l2_cpu2_wr_type_arb_set; + wire l2_cpu2_wr_vld_skid; + wire l2_cpu2_wr_way_arb_set; + wire l2_cpu2_wrq_almost_full; + wire [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; + wire l2_cpu2_wrq_haz_pending; + wire l2_cpu3_arb_thrshld_timeout_en; + wire l2_cpu3_barrier_done; + wire l2_cpu3_blk_non_evict_wr; + wire l2_cpu3_ccb_dbg_req_c3; + wire [48:0] l2_cpu3_ccb_req_addr_c3; + wire [4:0] l2_cpu3_ccb_req_id_c3; + wire [23:0] l2_cpu3_ccb_req_info_c3; + wire [8:0] l2_cpu3_ccb_req_type_c3; + wire l2_cpu3_cfg_ecc_en; + wire [2:0] l2_cpu3_dbufid_r1; + wire [129:0] l2_cpu3_ddata_r2; + wire l2_cpu3_ddlb_ecc_err_r3; + wire l2_cpu3_dext_err_r2; + wire l2_cpu3_dext_err_type_r2; + wire l2_cpu3_disable_clean_evict_opt; + wire l2_cpu3_dlast_r1; + wire l2_cpu3_dsngl_ecc_err_r3; + wire [3:0] l2_cpu3_dsq_clr_id_q; + wire l2_cpu3_dsq_clr_vld_q; + wire [3:0] l2_cpu3_dsq_rd_buf_id; + wire [15:0] l2_cpu3_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu3_dsq_rd_data_q; + wire l2_cpu3_dsq_rd_en; + wire l2_cpu3_dsq_rd_en_x2; + wire l2_cpu3_dt_pmu_evt_en; + wire l2_cpu3_dvalid_r1; + wire l2_cpu3_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; + wire l2_cpu3_flsh_if_rd_l4_dly; + wire l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; + wire l2_cpu3_flsh_ls_rd_l2_dly; + wire l2_cpu3_flsh_ls_rd_l4_dly; + wire l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; + wire l2_cpu3_flsh_ls_wr_l2_dly; + wire l2_cpu3_flsh_ls_wr_l4_dly; + wire l2_cpu3_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu3_ibufid_r1; + wire [15:0] l2_cpu3_ic_addr_arb_set; + wire l2_cpu3_ic_arb_fast; + wire l2_cpu3_ic_barrier_stall_q; + wire [43:18] l2_cpu3_ic_base; + wire [31:0] l2_cpu3_ic_data_arb_set; + wire [2:0] l2_cpu3_ic_elem_size_arb_set; + wire l2_cpu3_ic_excl_arb_set; + wire [2:0] l2_cpu3_ic_id_arb_set; + wire l2_cpu3_ic_ns_arb_set; + wire l2_cpu3_ic_vld_skid; + wire l2_cpu3_ic_write_arb_set; + wire [127:0] l2_cpu3_idata_r2; + wire l2_cpu3_idlb_ecc_err_r3; + wire l2_cpu3_idle_block_reqs_q; + wire l2_cpu3_idle_wakeup_q; + wire l2_cpu3_iext_err_r2; + wire l2_cpu3_iext_err_type_r2; + wire l2_cpu3_if_ccb_clken_c3; + wire l2_cpu3_if_ccb_req_c3; + wire l2_cpu3_if_ccb_resp; + wire [4:0] l2_cpu3_if_ccb_resp_id; + wire l2_cpu3_if_sync_done_q; + wire l2_cpu3_if_sync_req; + wire l2_cpu3_ifq_haz_pending; + wire l2_cpu3_isngl_ecc_err_r3; + wire l2_cpu3_ivalid_r1; + wire [1:0] l2_cpu3_l2_cache_size; + wire [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; + wire l2_cpu3_lrq_haz_pending; + wire l2_cpu3_ls_ccb_clken_c3; + wire l2_cpu3_ls_ccb_data_wr; + wire l2_cpu3_ls_ccb_req_c3; + wire l2_cpu3_ls_ccb_resp; + wire [4:0] l2_cpu3_ls_ccb_resp_id; + wire l2_cpu3_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu3_ls_rd_haz_id_arb_q; + wire l2_cpu3_ls_rd_haz_vld_arb_q; + wire l2_cpu3_ls_sync_req; + wire [4:0] l2_cpu3_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu3_ls_wr_data_w2a; + wire l2_cpu3_ls_wr_dirty_w2a; + wire l2_cpu3_ls_wr_err_w2a; + wire [2:0] l2_cpu3_ls_wr_haz_id_arb_q; + wire l2_cpu3_ls_wr_haz_vld_arb_q; + wire l2_cpu3_ls_wr_last_w2a; + wire l2_cpu3_ls_wr_req_w2a; + wire [2:0] l2_cpu3_ls_wr_type_w2a; + wire [12:0] l2_cpu3_mbist1_addr_b1; + wire l2_cpu3_mbist1_all_b1; + wire [3:0] l2_cpu3_mbist1_array_b1; + wire [7:0] l2_cpu3_mbist1_be_b1; + wire l2_cpu3_mbist1_en_b1; + wire l2_cpu3_mbist1_rd_en_b1; + wire l2_cpu3_mbist1_wr_en_b1; + wire l2_cpu3_no_intctrl; + wire l2_cpu3_pf_rd_vld_skid_popped; + wire l2_cpu3_pf_throttle_q; + wire [33:0] l2_cpu3_pmu_events; + wire [2:0] l2_cpu3_rbufid; + wire l2_cpu3_rd_aarch64_arb_set; + wire [44:0] l2_cpu3_rd_addr_arb_set; + wire l2_cpu3_rd_arb; + wire l2_cpu3_rd_arb_fast; + wire [15:8] l2_cpu3_rd_asid_arb_set; + wire l2_cpu3_rd_bypass_arb_set; + wire [2:0] l2_cpu3_rd_bypass_bufid_e5; + wire [2:0] l2_cpu3_rd_bypass_lrq_id_e5; + wire l2_cpu3_rd_bypass_req_can_e5; + wire l2_cpu3_rd_bypass_way_e5; + wire [2:0] l2_cpu3_rd_cache_attr_arb_set; + wire [2:0] l2_cpu3_rd_elem_size_arb_set; + wire l2_cpu3_rd_excl_arb_set; + wire [4:0] l2_cpu3_rd_id_arb_set; + wire [2:0] l2_cpu3_rd_lrq_id_arb_set; + wire [7:0] l2_cpu3_rd_page_attr_arb_set; + wire l2_cpu3_rd_prfm_arb_set; + wire l2_cpu3_rd_priv_arb_set; + wire l2_cpu3_rd_replayed_arb_set; + wire [1:0] l2_cpu3_rd_shared_arb_set; + wire [6:0] l2_cpu3_rd_type_arb_set; + wire l2_cpu3_rd_va48_arb_set; + wire l2_cpu3_rd_vld_skid; + wire l2_cpu3_rd_way_arb_set; + wire l2_cpu3_rexfail; + wire [1:0] l2_cpu3_rstate; + wire l2_cpu3_rvalid; + wire [2:0] l2_cpu3_spec_bufid; + wire l2_cpu3_spec_valid; + wire [63:0] l2_cpu3_spr_rd_data; + wire l2_cpu3_tbw_dbl_ecc_err; + wire [63:0] l2_cpu3_tbw_desc_data; + wire l2_cpu3_tbw_desc_vld; + wire l2_cpu3_tbw_ext_err; + wire l2_cpu3_tbw_ext_err_type; + wire l2_cpu3_tlb_ccb_clken_c3; + wire l2_cpu3_tlb_ccb_req_c3; + wire l2_cpu3_tlb_sync_complete; + wire l2_cpu3_tlb_sync_done_q; + wire l2_cpu3_tlb_sync_req; + wire l2_cpu3_trq_haz_pending; + wire l2_cpu3_tw_ccb_resp; + wire [4:0] l2_cpu3_tw_ccb_resp_id; + wire l2_cpu3_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu3_wr_addr_arb_set; + wire l2_cpu3_wr_arb; + wire l2_cpu3_wr_arb_fast; + wire [2:0] l2_cpu3_wr_cache_attr_arb_set; + wire [11:0] l2_cpu3_wr_cl_id_arb_set; + wire l2_cpu3_wr_clean_evict_arb_set; + wire [143:0] l2_cpu3_wr_data; + wire l2_cpu3_wr_data_stall; + wire l2_cpu3_wr_data_vld_x1_q; + wire l2_cpu3_wr_dirty_arb_set; + wire [2:0] l2_cpu3_wr_elem_size_arb_set; + wire l2_cpu3_wr_err_arb_set; + wire l2_cpu3_wr_evict_x1_q; + wire l2_cpu3_wr_ex_fail; + wire l2_cpu3_wr_ex_resp; + wire [3:0] l2_cpu3_wr_id_arb_set; + wire l2_cpu3_wr_last_arb_set; + wire [7:0] l2_cpu3_wr_page_attr_arb_set; + wire [3:0] l2_cpu3_wr_partial_dw_arb_set; + wire l2_cpu3_wr_priv_arb_set; + wire [1:0] l2_cpu3_wr_shared_arb_set; + wire [2:0] l2_cpu3_wr_type_arb_set; + wire l2_cpu3_wr_vld_skid; + wire l2_cpu3_wr_way_arb_set; + wire l2_cpu3_wrq_almost_full; + wire [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; + wire l2_cpu3_wrq_haz_pending; + wire [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu0_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu1_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu2_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu3_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu0_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu1_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu2_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu3_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; + wire ls_cpu0_clrexmon; + wire ls_cpu0_imp_abort_containable; + wire ls_cpu0_imp_abort_dec; + wire ls_cpu0_imp_abort_ecc; + wire ls_cpu0_imp_abort_slv; + wire ls_cpu0_raw_eae_nonsec; + wire ls_cpu0_raw_eae_secure; + wire ls_cpu1_clrexmon; + wire ls_cpu1_imp_abort_containable; + wire ls_cpu1_imp_abort_dec; + wire ls_cpu1_imp_abort_ecc; + wire ls_cpu1_imp_abort_slv; + wire ls_cpu1_raw_eae_nonsec; + wire ls_cpu1_raw_eae_secure; + wire ls_cpu2_clrexmon; + wire ls_cpu2_imp_abort_containable; + wire ls_cpu2_imp_abort_dec; + wire ls_cpu2_imp_abort_ecc; + wire ls_cpu2_imp_abort_slv; + wire ls_cpu2_raw_eae_nonsec; + wire ls_cpu2_raw_eae_secure; + wire ls_cpu3_clrexmon; + wire ls_cpu3_imp_abort_containable; + wire ls_cpu3_imp_abort_dec; + wire ls_cpu3_imp_abort_ecc; + wire ls_cpu3_imp_abort_slv; + wire ls_cpu3_raw_eae_nonsec; + wire ls_cpu3_raw_eae_secure; + wire ncommirq_cpu0_i; + wire ncommirq_cpu1_i; + wire ncommirq_cpu2_i; + wire ncommirq_cpu3_i; + wire ncorereset_cpu0_o; + wire ncorereset_cpu1_o; + wire ncorereset_cpu2_o; + wire ncorereset_cpu3_o; + wire ncpuporeset_cpu0_o; + wire ncpuporeset_cpu1_o; + wire ncpuporeset_cpu2_o; + wire ncpuporeset_cpu3_o; + wire niden_cpu0_o; + wire niden_cpu1_o; + wire niden_cpu2_o; + wire niden_cpu3_o; + wire nmbistreset_cpu0_o; + wire nmbistreset_cpu1_o; + wire nmbistreset_cpu2_o; + wire nmbistreset_cpu3_o; + wire npmuirq_cpu0_i; + wire npmuirq_cpu1_i; + wire npmuirq_cpu2_i; + wire npmuirq_cpu3_i; + wire pm_export_cpu0_i; + wire pm_export_cpu1_i; + wire pm_export_cpu2_i; + wire pm_export_cpu3_i; + wire [24:0] pmuevent_cpu0_i; + wire [24:0] pmuevent_cpu1_i; + wire [24:0] pmuevent_cpu2_i; + wire [24:0] pmuevent_cpu3_i; + wire [43:2] rvbaraddr_cpu0_o; + wire [43:2] rvbaraddr_cpu1_o; + wire [43:2] rvbaraddr_cpu2_o; + wire [43:2] rvbaraddr_cpu3_o; + wire spiden_cpu0_o; + wire spiden_cpu1_o; + wire spiden_cpu2_o; + wire spiden_cpu3_o; + wire spniden_cpu0_o; + wire spniden_cpu1_o; + wire spniden_cpu2_o; + wire spniden_cpu3_o; + wire syncreqm_cpu0_o; + wire syncreqm_cpu1_o; + wire syncreqm_cpu2_o; + wire syncreqm_cpu3_o; + wire [1:0] tm_cpu0_cnthctl_kernel; + wire [3:0] tm_cpu0_cntkctl_usr; + wire [1:0] tm_cpu1_cnthctl_kernel; + wire [3:0] tm_cpu1_cntkctl_usr; + wire [1:0] tm_cpu2_cnthctl_kernel; + wire [3:0] tm_cpu2_cntkctl_usr; + wire [1:0] tm_cpu3_cnthctl_kernel; + wire [3:0] tm_cpu3_cntkctl_usr; + wire [63:0] tsvalueb_cpu0_o; + wire [63:0] tsvalueb_cpu1_o; + wire [63:0] tsvalueb_cpu2_o; + wire [63:0] tsvalueb_cpu3_o; + wire vinithi_cpu0_o; + wire vinithi_cpu1_o; + wire vinithi_cpu2_o; + wire vinithi_cpu3_o; + + maia_cpu ucpu0( // outputs + .afreadym_cpu (afreadym_cpu0_i), + .atbytesm_cpu (atbytesm_cpu0_i[1:0]), + .atdatam_cpu (atdatam_cpu0_i[31:0]), + .atidm_cpu (atidm_cpu0_i[6:0]), + .atvalidm_cpu (atvalidm_cpu0_i), + .commrx_cpu (commrx_cpu0_i), + .commtx_cpu (commtx_cpu0_i), + .dbgack_cpu (dbgack_cpu0_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu0_i), + .dbgrstreq_cpu (dbgrstreq_cpu0_i), + .ds_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_flush (ds_cpu0_flush), + .ds_flush_type (ds_cpu0_flush_type[5:0]), + .ds_hcr_va (ds_cpu0_hcr_va), + .ds_hcr_vf (ds_cpu0_hcr_vf), + .ds_hcr_vi (ds_cpu0_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu0_reset_req), + .ds_sev_req (ds_cpu0_sev_req), + .ds_sevl_req (ds_cpu0_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_wfe_req (ds_cpu0_wfe_req), + .ds_wfi_req (ds_cpu0_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu0_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu0_clrexmon), + .ls_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu0_i), + .npmuirq_cpu (npmuirq_cpu0_i), + .pm_export_cpu (pm_export_cpu0_i), + .pmuevent_cpu (pmuevent_cpu0_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu0_o), + .afvalidm_cpu (afvalidm_cpu0_o), + .atclken_cpu (atclken_cpu0_o), + .atreadym_cpu (atreadym_cpu0_o), + .cfgend_cpu (cfgend_cpu0_o), + .cfgte_cpu (cfgte_cpu0_o), + .ck_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_event_reg (ck_cpu0_event_reg), + .ck_gclkt (ck_gclkt[0]), + .ck_wfe_ack (ck_cpu0_wfe_ack), + .ck_wfi_ack (ck_cpu0_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu0_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu0_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu0_o), + .cpuid (cpuid_cpu0_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu0_o), + .dbgen_cpu (dbgen_cpu0_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu0_o), + .dbgromaddr_cpu (dbgromaddr_cpu0_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu0_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu0_o), + .dftramhold_cpu (dftramhold_cpu0_o), + .dftrstdisable_cpu (dftrstdisable_cpu0_o), + .dftse_cpu (dftse_cpu0_o), + .dt_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu0_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[0]), + .ic_el_change_complete (ic_el_change_complete[0]), + .ic_hcr_change_complete (ic_hcr_change_complete[0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[0]), + .ic_ich_el2_tc (ic_ich_el2_tc[0]), + .ic_nfiq (ic_nfiq[0]), + .ic_nirq (ic_nirq[0]), + .ic_nsei (ic_nsei[0]), + .ic_nvfiq (ic_nvfiq[0]), + .ic_nvirq (ic_nvirq[0]), + .ic_nvsei (ic_nvsei[0]), + .ic_p_valid (ic_p_valid[0]), + .ic_sample_spr (ic_sample_spr[0]), + .ic_scr_change_complete (ic_scr_change_complete[0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[0]), + .ic_sra_el1s_en (ic_sra_el1s_en[0]), + .ic_sra_el2_en (ic_sra_el2_en[0]), + .ic_sra_el3_en (ic_sra_el3_en[0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[0]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu0_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu0_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu0_rexfail), + .l2_cpu_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu0_rvalid), + .l2_cpu_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu0_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu0_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu0_o), + .ncpuporeset_cpu (ncpuporeset_cpu0_o), + .niden_cpu (niden_cpu0_o), + .nmbistreset_cpu (nmbistreset_cpu0_o), + .rvbaraddr_cpu (rvbaraddr_cpu0_o[43:2]), + .spiden_cpu (spiden_cpu0_o), + .spniden_cpu (spniden_cpu0_o), + .syncreqm_cpu (syncreqm_cpu0_o), + .tm_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu0_o[63:0]), + .vinithi_cpu (vinithi_cpu0_o) + ); // ucpu0 + + maia_cpu ucpu1( // outputs + .afreadym_cpu (afreadym_cpu1_i), + .atbytesm_cpu (atbytesm_cpu1_i[1:0]), + .atdatam_cpu (atdatam_cpu1_i[31:0]), + .atidm_cpu (atidm_cpu1_i[6:0]), + .atvalidm_cpu (atvalidm_cpu1_i), + .commrx_cpu (commrx_cpu1_i), + .commtx_cpu (commtx_cpu1_i), + .dbgack_cpu (dbgack_cpu1_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu1_i), + .dbgrstreq_cpu (dbgrstreq_cpu1_i), + .ds_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_flush (ds_cpu1_flush), + .ds_flush_type (ds_cpu1_flush_type[5:0]), + .ds_hcr_va (ds_cpu1_hcr_va), + .ds_hcr_vf (ds_cpu1_hcr_vf), + .ds_hcr_vi (ds_cpu1_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu1_reset_req), + .ds_sev_req (ds_cpu1_sev_req), + .ds_sevl_req (ds_cpu1_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_wfe_req (ds_cpu1_wfe_req), + .ds_wfi_req (ds_cpu1_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu1_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu1_clrexmon), + .ls_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu1_i), + .npmuirq_cpu (npmuirq_cpu1_i), + .pm_export_cpu (pm_export_cpu1_i), + .pmuevent_cpu (pmuevent_cpu1_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu1_o), + .afvalidm_cpu (afvalidm_cpu1_o), + .atclken_cpu (atclken_cpu1_o), + .atreadym_cpu (atreadym_cpu1_o), + .cfgend_cpu (cfgend_cpu1_o), + .cfgte_cpu (cfgte_cpu1_o), + .ck_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_event_reg (ck_cpu1_event_reg), + .ck_gclkt (ck_gclkt[1]), + .ck_wfe_ack (ck_cpu1_wfe_ack), + .ck_wfi_ack (ck_cpu1_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu1_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu1_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu1_o), + .cpuid (cpuid_cpu1_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu1_o), + .dbgen_cpu (dbgen_cpu1_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu1_o), + .dbgromaddr_cpu (dbgromaddr_cpu1_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu1_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu1_o), + .dftramhold_cpu (dftramhold_cpu1_o), + .dftrstdisable_cpu (dftrstdisable_cpu1_o), + .dftse_cpu (dftse_cpu1_o), + .dt_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu1_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[1]), + .ic_el_change_complete (ic_el_change_complete[1]), + .ic_hcr_change_complete (ic_hcr_change_complete[1]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[1]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[1]), + .ic_ich_el2_tc (ic_ich_el2_tc[1]), + .ic_nfiq (ic_nfiq[1]), + .ic_nirq (ic_nirq[1]), + .ic_nsei (ic_nsei[1]), + .ic_nvfiq (ic_nvfiq[1]), + .ic_nvirq (ic_nvirq[1]), + .ic_nvsei (ic_nvsei[1]), + .ic_p_valid (ic_p_valid[1]), + .ic_sample_spr (ic_sample_spr[1]), + .ic_scr_change_complete (ic_scr_change_complete[1]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[1]), + .ic_sra_el1s_en (ic_sra_el1s_en[1]), + .ic_sra_el2_en (ic_sra_el2_en[1]), + .ic_sra_el3_en (ic_sra_el3_en[1]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[1]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[1]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[1]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[1]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu1_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu1_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu1_rexfail), + .l2_cpu_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu1_rvalid), + .l2_cpu_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu1_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu1_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu1_o), + .ncpuporeset_cpu (ncpuporeset_cpu1_o), + .niden_cpu (niden_cpu1_o), + .nmbistreset_cpu (nmbistreset_cpu1_o), + .rvbaraddr_cpu (rvbaraddr_cpu1_o[43:2]), + .spiden_cpu (spiden_cpu1_o), + .spniden_cpu (spniden_cpu1_o), + .syncreqm_cpu (syncreqm_cpu1_o), + .tm_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu1_o[63:0]), + .vinithi_cpu (vinithi_cpu1_o) + ); // ucpu1 + + maia_cpu ucpu2( // outputs + .afreadym_cpu (afreadym_cpu2_i), + .atbytesm_cpu (atbytesm_cpu2_i[1:0]), + .atdatam_cpu (atdatam_cpu2_i[31:0]), + .atidm_cpu (atidm_cpu2_i[6:0]), + .atvalidm_cpu (atvalidm_cpu2_i), + .commrx_cpu (commrx_cpu2_i), + .commtx_cpu (commtx_cpu2_i), + .dbgack_cpu (dbgack_cpu2_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu2_i), + .dbgrstreq_cpu (dbgrstreq_cpu2_i), + .ds_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_flush (ds_cpu2_flush), + .ds_flush_type (ds_cpu2_flush_type[5:0]), + .ds_hcr_va (ds_cpu2_hcr_va), + .ds_hcr_vf (ds_cpu2_hcr_vf), + .ds_hcr_vi (ds_cpu2_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu2_reset_req), + .ds_sev_req (ds_cpu2_sev_req), + .ds_sevl_req (ds_cpu2_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_wfe_req (ds_cpu2_wfe_req), + .ds_wfi_req (ds_cpu2_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu2_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu2_clrexmon), + .ls_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu2_i), + .npmuirq_cpu (npmuirq_cpu2_i), + .pm_export_cpu (pm_export_cpu2_i), + .pmuevent_cpu (pmuevent_cpu2_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu2_o), + .afvalidm_cpu (afvalidm_cpu2_o), + .atclken_cpu (atclken_cpu2_o), + .atreadym_cpu (atreadym_cpu2_o), + .cfgend_cpu (cfgend_cpu2_o), + .cfgte_cpu (cfgte_cpu2_o), + .ck_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_event_reg (ck_cpu2_event_reg), + .ck_gclkt (ck_gclkt[2]), + .ck_wfe_ack (ck_cpu2_wfe_ack), + .ck_wfi_ack (ck_cpu2_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu2_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu2_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu2_o), + .cpuid (cpuid_cpu2_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu2_o), + .dbgen_cpu (dbgen_cpu2_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu2_o), + .dbgromaddr_cpu (dbgromaddr_cpu2_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu2_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu2_o), + .dftramhold_cpu (dftramhold_cpu2_o), + .dftrstdisable_cpu (dftrstdisable_cpu2_o), + .dftse_cpu (dftse_cpu2_o), + .dt_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu2_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[2]), + .ic_el_change_complete (ic_el_change_complete[2]), + .ic_hcr_change_complete (ic_hcr_change_complete[2]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[2]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[2]), + .ic_ich_el2_tc (ic_ich_el2_tc[2]), + .ic_nfiq (ic_nfiq[2]), + .ic_nirq (ic_nirq[2]), + .ic_nsei (ic_nsei[2]), + .ic_nvfiq (ic_nvfiq[2]), + .ic_nvirq (ic_nvirq[2]), + .ic_nvsei (ic_nvsei[2]), + .ic_p_valid (ic_p_valid[2]), + .ic_sample_spr (ic_sample_spr[2]), + .ic_scr_change_complete (ic_scr_change_complete[2]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[2]), + .ic_sra_el1s_en (ic_sra_el1s_en[2]), + .ic_sra_el2_en (ic_sra_el2_en[2]), + .ic_sra_el3_en (ic_sra_el3_en[2]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[2]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[2]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[2]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[2]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu2_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu2_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu2_rexfail), + .l2_cpu_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu2_rvalid), + .l2_cpu_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu2_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu2_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu2_o), + .ncpuporeset_cpu (ncpuporeset_cpu2_o), + .niden_cpu (niden_cpu2_o), + .nmbistreset_cpu (nmbistreset_cpu2_o), + .rvbaraddr_cpu (rvbaraddr_cpu2_o[43:2]), + .spiden_cpu (spiden_cpu2_o), + .spniden_cpu (spniden_cpu2_o), + .syncreqm_cpu (syncreqm_cpu2_o), + .tm_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu2_o[63:0]), + .vinithi_cpu (vinithi_cpu2_o) + ); // ucpu2 + + maia_cpu ucpu3( // outputs + .afreadym_cpu (afreadym_cpu3_i), + .atbytesm_cpu (atbytesm_cpu3_i[1:0]), + .atdatam_cpu (atdatam_cpu3_i[31:0]), + .atidm_cpu (atidm_cpu3_i[6:0]), + .atvalidm_cpu (atvalidm_cpu3_i), + .commrx_cpu (commrx_cpu3_i), + .commtx_cpu (commtx_cpu3_i), + .dbgack_cpu (dbgack_cpu3_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu (dbgrstreq_cpu3_i), + .ds_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_flush (ds_cpu3_flush), + .ds_flush_type (ds_cpu3_flush_type[5:0]), + .ds_hcr_va (ds_cpu3_hcr_va), + .ds_hcr_vf (ds_cpu3_hcr_vf), + .ds_hcr_vi (ds_cpu3_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_ic_scr_change (ds_cpu3_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu3_reset_req), + .ds_sev_req (ds_cpu3_sev_req), + .ds_sevl_req (ds_cpu3_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_wfe_req (ds_cpu3_wfe_req), + .ds_wfi_req (ds_cpu3_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu3_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu3_clrexmon), + .ls_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu3_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu3_i), + .npmuirq_cpu (npmuirq_cpu3_i), + .pm_export_cpu (pm_export_cpu3_i), + .pmuevent_cpu (pmuevent_cpu3_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu3_o), + .afvalidm_cpu (afvalidm_cpu3_o), + .atclken_cpu (atclken_cpu3_o), + .atreadym_cpu (atreadym_cpu3_o), + .cfgend_cpu (cfgend_cpu3_o), + .cfgte_cpu (cfgte_cpu3_o), + .ck_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_event_reg (ck_cpu3_event_reg), + .ck_gclkt (ck_gclkt[3]), + .ck_wfe_ack (ck_cpu3_wfe_ack), + .ck_wfi_ack (ck_cpu3_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu3_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu3_o), + .cpuid (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu3_o), + .dbgen_cpu (dbgen_cpu3_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu3_o), + .dbgromaddr_cpu (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu3_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu3_o), + .dftramhold_cpu (dftramhold_cpu3_o), + .dftrstdisable_cpu (dftrstdisable_cpu3_o), + .dftse_cpu (dftse_cpu3_o), + .dt_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu3_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[3]), + .ic_el_change_complete (ic_el_change_complete[3]), + .ic_hcr_change_complete (ic_hcr_change_complete[3]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[3]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[3]), + .ic_ich_el2_tc (ic_ich_el2_tc[3]), + .ic_nfiq (ic_nfiq[3]), + .ic_nirq (ic_nirq[3]), + .ic_nsei (ic_nsei[3]), + .ic_nvfiq (ic_nvfiq[3]), + .ic_nvirq (ic_nvirq[3]), + .ic_nvsei (ic_nvsei[3]), + .ic_p_valid (ic_p_valid[3]), + .ic_sample_spr (ic_sample_spr[3]), + .ic_scr_change_complete (ic_scr_change_complete[3]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[3]), + .ic_sra_el1s_en (ic_sra_el1s_en[3]), + .ic_sra_el2_en (ic_sra_el2_en[3]), + .ic_sra_el3_en (ic_sra_el3_en[3]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[3]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[3]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[3]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[3]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu3_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu3_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu3_rexfail), + .l2_cpu_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu3_rvalid), + .l2_cpu_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu3_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu3_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu3_o), + .ncpuporeset_cpu (ncpuporeset_cpu3_o), + .niden_cpu (niden_cpu3_o), + .nmbistreset_cpu (nmbistreset_cpu3_o), + .rvbaraddr_cpu (rvbaraddr_cpu3_o[43:2]), + .spiden_cpu (spiden_cpu3_o), + .spniden_cpu (spniden_cpu3_o), + .syncreqm_cpu (syncreqm_cpu3_o), + .tm_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu3_o[63:0]), + .vinithi_cpu (vinithi_cpu3_o) + ); // ucpu3 + + maia_noncpu_feq20 unoncpu( // outputs + .ACREADYM (ACREADYM), + .AFREADYM0 (AFREADYM0), + .AFREADYM1 (AFREADYM1), + .AFREADYM2 (AFREADYM2), + .AFREADYM3 (AFREADYM3), + .ARADDRM (ARADDRM[43:0]), + .ARBARM (ARBARM[1:0]), + .ARBURSTM (ARBURSTM[1:0]), + .ARCACHEM (ARCACHEM[3:0]), + .ARDOMAINM (ARDOMAINM[1:0]), + .ARIDM (ARIDM[6:0]), + .ARLENM (ARLENM[7:0]), + .ARLOCKM (ARLOCKM), + .ARPROTM (ARPROTM[2:0]), + .ARREADYS (ARREADYS), + .ARSIZEM (ARSIZEM[2:0]), + .ARSNOOPM (ARSNOOPM[3:0]), + .ARVALIDM (ARVALIDM), + .ATBYTESM0 (ATBYTESM0[1:0]), + .ATBYTESM1 (ATBYTESM1[1:0]), + .ATBYTESM2 (ATBYTESM2[1:0]), + .ATBYTESM3 (ATBYTESM3[1:0]), + .ATDATAM0 (ATDATAM0[31:0]), + .ATDATAM1 (ATDATAM1[31:0]), + .ATDATAM2 (ATDATAM2[31:0]), + .ATDATAM3 (ATDATAM3[31:0]), + .ATIDM0 (ATIDM0[6:0]), + .ATIDM1 (ATIDM1[6:0]), + .ATIDM2 (ATIDM2[6:0]), + .ATIDM3 (ATIDM3[6:0]), + .ATVALIDM0 (ATVALIDM0), + .ATVALIDM1 (ATVALIDM1), + .ATVALIDM2 (ATVALIDM2), + .ATVALIDM3 (ATVALIDM3), + .AWADDRM (AWADDRM[43:0]), + .AWBARM (AWBARM[1:0]), + .AWBURSTM (AWBURSTM[1:0]), + .AWCACHEM (AWCACHEM[3:0]), + .AWDOMAINM (AWDOMAINM[1:0]), + .AWIDM (AWIDM[6:0]), + .AWLENM (AWLENM[7:0]), + .AWLOCKM (AWLOCKM), + .AWPROTM (AWPROTM[2:0]), + .AWREADYS (AWREADYS), + .AWSIZEM (AWSIZEM[2:0]), + .AWSNOOPM (AWSNOOPM[2:0]), + .AWUNIQUEM (AWUNIQUEM), + .AWVALIDM (AWVALIDM), + .BIDS (BIDS[4:0]), + .BREADYM (BREADYM), + .BRESPS (BRESPS[1:0]), + .BVALIDS (BVALIDS), + .CDDATAM (CDDATAM[127:0]), + .CDLASTM (CDLASTM), + .CDVALIDM (CDVALIDM), + .CLREXMONACK (CLREXMONACK), + .COMMRX (COMMRX[`MAIA_CN:0]), + .COMMTX (COMMTX[`MAIA_CN:0]), + .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), + .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), + .CPUQDENY (CPUQDENY[`MAIA_CN:0]), + .CRRESPM (CRRESPM[4:0]), + .CRVALIDM (CRVALIDM), + .CTICHINACK (CTICHINACK[3:0]), + .CTICHOUT (CTICHOUT[3:0]), + .CTIIRQ (CTIIRQ[`MAIA_CN:0]), + .DBGACK (DBGACK[`MAIA_CN:0]), + .DBGNOPWRDWN (DBGNOPWRDWN[`MAIA_CN:0]), + .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), + .DBGRSTREQ (DBGRSTREQ[`MAIA_CN:0]), + .EVENTO (EVENTO), + .ICCTDATA (ICCTDATA[15:0]), + .ICCTID (ICCTID[1:0]), + .ICCTLAST (ICCTLAST), + .ICCTVALID (ICCTVALID), + .ICDTREADY (ICDTREADY), + .L2FLUSHDONE (L2FLUSHDONE), + .L2QACCEPTn (L2QACCEPTn), + .L2QACTIVE (L2QACTIVE), + .L2QDENY (L2QDENY), + .PMUEVENT0 (PMUEVENT0[24:0]), + .PMUEVENT1 (PMUEVENT1[24:0]), + .PMUEVENT2 (PMUEVENT2[24:0]), + .PMUEVENT3 (PMUEVENT3[24:0]), + .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), + .PRDATADBG (PRDATADBG[31:0]), + .PREADYDBG (PREADYDBG), + .PSLVERRDBG (PSLVERRDBG), + .RACKM (RACKM), + .RDATAS (RDATAS[127:0]), + .RDMEMATTR (RDMEMATTR[7:0]), + .RIDS (RIDS[4:0]), + .RLASTS (RLASTS), + .RREADYM (RREADYM), + .RRESPS (RRESPS[1:0]), + .RVALIDS (RVALIDS), + .SMPEN (SMPEN[`MAIA_CN:0]), + .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), + .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), + .STANDBYWFIL2 (STANDBYWFIL2), + .WACKM (WACKM), + .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), + .WDATAM (WDATAM[127:0]), + .WIDM (WIDM[6:0]), + .WLASTM (WLASTM), + .WREADYS (WREADYS), + .WRMEMATTR (WRMEMATTR[7:0]), + .WSTRBM (WSTRBM[15:0]), + .WVALIDM (WVALIDM), + .aa64naa32_cpu0_o (aa64naa32_cpu0_o), + .aa64naa32_cpu1_o (aa64naa32_cpu1_o), + .aa64naa32_cpu2_o (aa64naa32_cpu2_o), + .aa64naa32_cpu3_o (aa64naa32_cpu3_o), + .afvalidm_cpu0_o (afvalidm_cpu0_o), + .afvalidm_cpu1_o (afvalidm_cpu1_o), + .afvalidm_cpu2_o (afvalidm_cpu2_o), + .afvalidm_cpu3_o (afvalidm_cpu3_o), + .atclken_cpu0_o (atclken_cpu0_o), + .atclken_cpu1_o (atclken_cpu1_o), + .atclken_cpu2_o (atclken_cpu2_o), + .atclken_cpu3_o (atclken_cpu3_o), + .atreadym_cpu0_o (atreadym_cpu0_o), + .atreadym_cpu1_o (atreadym_cpu1_o), + .atreadym_cpu2_o (atreadym_cpu2_o), + .atreadym_cpu3_o (atreadym_cpu3_o), + .cfgend_cpu0_o (cfgend_cpu0_o), + .cfgend_cpu1_o (cfgend_cpu1_o), + .cfgend_cpu2_o (cfgend_cpu2_o), + .cfgend_cpu3_o (cfgend_cpu3_o), + .cfgte_cpu0_o (cfgte_cpu0_o), + .cfgte_cpu1_o (cfgte_cpu1_o), + .cfgte_cpu2_o (cfgte_cpu2_o), + .cfgte_cpu3_o (cfgte_cpu3_o), + .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_cpu0_event_reg (ck_cpu0_event_reg), + .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), + .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), + .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_cpu1_event_reg (ck_cpu1_event_reg), + .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), + .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), + .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_cpu2_event_reg (ck_cpu2_event_reg), + .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), + .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), + .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_cpu3_event_reg (ck_cpu3_event_reg), + .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), + .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), + .ck_gclkt (ck_gclkt[`MAIA_CN:0]), + .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), + .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), + .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), + .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), + .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), + .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), + .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), + .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), + .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), + .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), + .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), + .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), + .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), + .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), + .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu0_o (cryptodisable_cpu0_o), + .cryptodisable_cpu1_o (cryptodisable_cpu1_o), + .cryptodisable_cpu2_o (cryptodisable_cpu2_o), + .cryptodisable_cpu3_o (cryptodisable_cpu3_o), + .dbgen_cpu0_o (dbgen_cpu0_o), + .dbgen_cpu1_o (dbgen_cpu1_o), + .dbgen_cpu2_o (dbgen_cpu2_o), + .dbgen_cpu3_o (dbgen_cpu3_o), + .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), + .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), + .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), + .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), + .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), + .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), + .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), + .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), + .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), + .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), + .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), + .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), + .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), + .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), + .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), + .dftramhold_cpu0_o (dftramhold_cpu0_o), + .dftramhold_cpu1_o (dftramhold_cpu1_o), + .dftramhold_cpu2_o (dftramhold_cpu2_o), + .dftramhold_cpu3_o (dftramhold_cpu3_o), + .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), + .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), + .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), + .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), + .dftse_cpu0_o (dftse_cpu0_o), + .dftse_cpu1_o (dftse_cpu1_o), + .dftse_cpu2_o (dftse_cpu2_o), + .dftse_cpu3_o (dftse_cpu3_o), + .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .giccdisable_cpu0_o (giccdisable_cpu0_o), + .giccdisable_cpu1_o (giccdisable_cpu1_o), + .giccdisable_cpu2_o (giccdisable_cpu2_o), + .giccdisable_cpu3_o (giccdisable_cpu3_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[`MAIA_CN:0]), + .ic_el_change_complete (ic_el_change_complete[`MAIA_CN:0]), + .ic_hcr_change_complete (ic_hcr_change_complete[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq[`MAIA_CN:0]), + .ic_nirq (ic_nirq[`MAIA_CN:0]), + .ic_nsei (ic_nsei[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei[`MAIA_CN:0]), + .ic_p_valid (ic_p_valid[`MAIA_CN:0]), + .ic_sample_spr (ic_sample_spr[`MAIA_CN:0]), + .ic_scr_change_complete (ic_scr_change_complete[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[`MAIA_CN:0]), + .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu0_barrier_done (l2_cpu0_barrier_done), + .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), + .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), + .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu0_rd_arb (l2_cpu0_rd_arb), + .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu0_rexfail (l2_cpu0_rexfail), + .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu0_rvalid (l2_cpu0_rvalid), + .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu0_spec_valid (l2_cpu0_spec_valid), + .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu0_wr_arb (l2_cpu0_wr_arb), + .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu1_barrier_done (l2_cpu1_barrier_done), + .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), + .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), + .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu1_rd_arb (l2_cpu1_rd_arb), + .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu1_rexfail (l2_cpu1_rexfail), + .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu1_rvalid (l2_cpu1_rvalid), + .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu1_spec_valid (l2_cpu1_spec_valid), + .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu1_wr_arb (l2_cpu1_wr_arb), + .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu2_barrier_done (l2_cpu2_barrier_done), + .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), + .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), + .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu2_rd_arb (l2_cpu2_rd_arb), + .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu2_rexfail (l2_cpu2_rexfail), + .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu2_rvalid (l2_cpu2_rvalid), + .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu2_spec_valid (l2_cpu2_spec_valid), + .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu2_wr_arb (l2_cpu2_wr_arb), + .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu3_barrier_done (l2_cpu3_barrier_done), + .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), + .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), + .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu3_rd_arb (l2_cpu3_rd_arb), + .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu3_rexfail (l2_cpu3_rexfail), + .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu3_rvalid (l2_cpu3_rvalid), + .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu3_spec_valid (l2_cpu3_spec_valid), + .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu3_wr_arb (l2_cpu3_wr_arb), + .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), + .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), + .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), + .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), + .nCOMMIRQ (nCOMMIRQ[`MAIA_CN:0]), + .nEXTERRIRQ (nEXTERRIRQ), + .nINTERRIRQ (nINTERRIRQ), + .nPMUIRQ (nPMUIRQ[`MAIA_CN:0]), + .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), + .ncorereset_cpu0_o (ncorereset_cpu0_o), + .ncorereset_cpu1_o (ncorereset_cpu1_o), + .ncorereset_cpu2_o (ncorereset_cpu2_o), + .ncorereset_cpu3_o (ncorereset_cpu3_o), + .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), + .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), + .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), + .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), + .niden_cpu0_o (niden_cpu0_o), + .niden_cpu1_o (niden_cpu1_o), + .niden_cpu2_o (niden_cpu2_o), + .niden_cpu3_o (niden_cpu3_o), + .nmbistreset_cpu0_o (nmbistreset_cpu0_o), + .nmbistreset_cpu1_o (nmbistreset_cpu1_o), + .nmbistreset_cpu2_o (nmbistreset_cpu2_o), + .nmbistreset_cpu3_o (nmbistreset_cpu3_o), + .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), + .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), + .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), + .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), + .spiden_cpu0_o (spiden_cpu0_o), + .spiden_cpu1_o (spiden_cpu1_o), + .spiden_cpu2_o (spiden_cpu2_o), + .spiden_cpu3_o (spiden_cpu3_o), + .spniden_cpu0_o (spniden_cpu0_o), + .spniden_cpu1_o (spniden_cpu1_o), + .spniden_cpu2_o (spniden_cpu2_o), + .spniden_cpu3_o (spniden_cpu3_o), + .syncreqm_cpu0_o (syncreqm_cpu0_o), + .syncreqm_cpu1_o (syncreqm_cpu1_o), + .syncreqm_cpu2_o (syncreqm_cpu2_o), + .syncreqm_cpu3_o (syncreqm_cpu3_o), + .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), + .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), + .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), + .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), + .vinithi_cpu0_o (vinithi_cpu0_o), + .vinithi_cpu1_o (vinithi_cpu1_o), + .vinithi_cpu2_o (vinithi_cpu2_o), + .vinithi_cpu3_o (vinithi_cpu3_o), + + // inputs + .AA64nAA32 (AA64nAA32[`MAIA_CN:0]), + .ACADDRM (ACADDRM[43:0]), + .ACINACTM (ACINACTM), + .ACLKENM (ACLKENM), + .ACLKENS (ACLKENS), + .ACPROTM (ACPROTM[2:0]), + .ACSNOOPM (ACSNOOPM[3:0]), + .ACVALIDM (ACVALIDM), + .AFVALIDM0 (AFVALIDM0), + .AFVALIDM1 (AFVALIDM1), + .AFVALIDM2 (AFVALIDM2), + .AFVALIDM3 (AFVALIDM3), + .AINACTS (AINACTS), + .ARADDRS (ARADDRS[43:0]), + .ARCACHES (ARCACHES[3:0]), + .ARIDS (ARIDS[4:0]), + .ARLENS (ARLENS[7:0]), + .ARPROTS (ARPROTS[2:0]), + .ARREADYM (ARREADYM), + .ARUSERS (ARUSERS[1:0]), + .ARVALIDS (ARVALIDS), + .ATCLKEN (ATCLKEN), + .ATREADYM0 (ATREADYM0), + .ATREADYM1 (ATREADYM1), + .ATREADYM2 (ATREADYM2), + .ATREADYM3 (ATREADYM3), + .AWADDRS (AWADDRS[43:0]), + .AWCACHES (AWCACHES[3:0]), + .AWIDS (AWIDS[4:0]), + .AWLENS (AWLENS[7:0]), + .AWPROTS (AWPROTS[2:0]), + .AWREADYM (AWREADYM), + .AWUSERS (AWUSERS[1:0]), + .AWVALIDS (AWVALIDS), + .BIDM (BIDM[6:0]), + .BREADYS (BREADYS), + .BRESPM (BRESPM[1:0]), + .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), + .BROADCASTINNER (BROADCASTINNER), + .BROADCASTOUTER (BROADCASTOUTER), + .BVALIDM (BVALIDM), + .CDREADYM (CDREADYM), + .CFGEND (CFGEND[`MAIA_CN:0]), + .CFGTE (CFGTE[`MAIA_CN:0]), + .CIHSBYPASS (CIHSBYPASS[3:0]), + .CISBYPASS (CISBYPASS), + .CLK (CLK), + .CLKEN (CLKEN), + .CLREXMONREQ (CLREXMONREQ), + .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), + .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), + .CNTCLKEN (CNTCLKEN), + .CNTVALUEB (CNTVALUEB[63:0]), + .CP15SDISABLE (CP15SDISABLE[`MAIA_CN:0]), + .CPUQREQn (CPUQREQn[`MAIA_CN:0]), + .CRREADYM (CRREADYM), + .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), + .CTICHIN (CTICHIN[3:0]), + .CTICHOUTACK (CTICHOUTACK[3:0]), + .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), + .DBGEN (DBGEN[`MAIA_CN:0]), + .DBGL1RSTDISABLE (DBGL1RSTDISABLE), + .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), + .DBGROMADDR (DBGROMADDR[43:12]), + .DBGROMADDRV (DBGROMADDRV), + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTCRCLKDISABLE (DFTCRCLKDISABLE[`MAIA_CN:0]), + .DFTL2CLKDISABLE (DFTL2CLKDISABLE), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .EDBGRQ (EDBGRQ[`MAIA_CN:0]), + .EVENTI (EVENTI), + .GICCDISABLE (GICCDISABLE), + .ICCTREADY (ICCTREADY), + .ICDTDATA (ICDTDATA[15:0]), + .ICDTDEST (ICDTDEST[1:0]), + .ICDTLAST (ICDTLAST), + .ICDTVALID (ICDTVALID), + .L2FLUSHREQ (L2FLUSHREQ), + .L2QREQn (L2QREQn), + .L2RSTDISABLE (L2RSTDISABLE), + .MBISTREQ (MBISTREQ), + .NIDEN (NIDEN[`MAIA_CN:0]), + .PADDRDBG (PADDRDBG[21:2]), + .PADDRDBG31 (PADDRDBG31), + .PCLKDBG (PCLKDBG), + .PCLKENDBG (PCLKENDBG), + .PENABLEDBG (PENABLEDBG), + .PERIPHBASE (PERIPHBASE[43:18]), + .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), + .PSELDBG (PSELDBG), + .PWDATADBG (PWDATADBG[31:0]), + .PWRITEDBG (PWRITEDBG), + .RDATAM (RDATAM[127:0]), + .RIDM (RIDM[6:0]), + .RLASTM (RLASTM), + .RREADYS (RREADYS), + .RRESPM (RRESPM[3:0]), + .RVALIDM (RVALIDM), + .RVBARADDR0 (RVBARADDR0[43:2]), + .RVBARADDR1 (RVBARADDR1[43:2]), + .RVBARADDR2 (RVBARADDR2[43:2]), + .RVBARADDR3 (RVBARADDR3[43:2]), + .SPIDEN (SPIDEN[`MAIA_CN:0]), + .SPNIDEN (SPNIDEN[`MAIA_CN:0]), + .SYNCREQM0 (SYNCREQM0), + .SYNCREQM1 (SYNCREQM1), + .SYNCREQM2 (SYNCREQM2), + .SYNCREQM3 (SYNCREQM3), + .SYSBARDISABLE (SYSBARDISABLE), + .TSVALUEB (TSVALUEB[63:0]), + .VINITHI (VINITHI[`MAIA_CN:0]), + .WDATAS (WDATAS[127:0]), + .WLASTS (WLASTS), + .WREADYM (WREADYM), + .WSTRBS (WSTRBS[15:0]), + .WVALIDS (WVALIDS), + .afreadym_cpu0_i (afreadym_cpu0_i), + .afreadym_cpu1_i (afreadym_cpu1_i), + .afreadym_cpu2_i (afreadym_cpu2_i), + .afreadym_cpu3_i (afreadym_cpu3_i), + .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), + .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), + .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), + .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), + .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), + .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), + .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), + .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), + .atidm_cpu0_i (atidm_cpu0_i[6:0]), + .atidm_cpu1_i (atidm_cpu1_i[6:0]), + .atidm_cpu2_i (atidm_cpu2_i[6:0]), + .atidm_cpu3_i (atidm_cpu3_i[6:0]), + .atvalidm_cpu0_i (atvalidm_cpu0_i), + .atvalidm_cpu1_i (atvalidm_cpu1_i), + .atvalidm_cpu2_i (atvalidm_cpu2_i), + .atvalidm_cpu3_i (atvalidm_cpu3_i), + .commrx_cpu0_i (commrx_cpu0_i), + .commrx_cpu1_i (commrx_cpu1_i), + .commrx_cpu2_i (commrx_cpu2_i), + .commrx_cpu3_i (commrx_cpu3_i), + .commtx_cpu0_i (commtx_cpu0_i), + .commtx_cpu1_i (commtx_cpu1_i), + .commtx_cpu2_i (commtx_cpu2_i), + .commtx_cpu3_i (commtx_cpu3_i), + .dbgack_cpu0_i (dbgack_cpu0_i), + .dbgack_cpu1_i (dbgack_cpu1_i), + .dbgack_cpu2_i (dbgack_cpu2_i), + .dbgack_cpu3_i (dbgack_cpu3_i), + .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), + .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), + .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), + .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), + .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), + .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), + .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), + .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_cpu0_flush (ds_cpu0_flush), + .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), + .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), + .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu0_reset_req (ds_cpu0_reset_req), + .ds_cpu0_sev_req (ds_cpu0_sev_req), + .ds_cpu0_sevl_req (ds_cpu0_sevl_req), + .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_cpu0_wfe_req (ds_cpu0_wfe_req), + .ds_cpu0_wfi_req (ds_cpu0_wfi_req), + .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_cpu1_flush (ds_cpu1_flush), + .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), + .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), + .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu1_reset_req (ds_cpu1_reset_req), + .ds_cpu1_sev_req (ds_cpu1_sev_req), + .ds_cpu1_sevl_req (ds_cpu1_sevl_req), + .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_cpu1_wfe_req (ds_cpu1_wfe_req), + .ds_cpu1_wfi_req (ds_cpu1_wfi_req), + .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_cpu2_flush (ds_cpu2_flush), + .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), + .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), + .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu2_reset_req (ds_cpu2_reset_req), + .ds_cpu2_sev_req (ds_cpu2_sev_req), + .ds_cpu2_sevl_req (ds_cpu2_sevl_req), + .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_cpu2_wfe_req (ds_cpu2_wfe_req), + .ds_cpu2_wfi_req (ds_cpu2_wfi_req), + .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_cpu3_flush (ds_cpu3_flush), + .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), + .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), + .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), + .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_cpu3_reset_req (ds_cpu3_reset_req), + .ds_cpu3_sev_req (ds_cpu3_sev_req), + .ds_cpu3_sevl_req (ds_cpu3_sevl_req), + .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_cpu3_wfe_req (ds_cpu3_wfe_req), + .ds_cpu3_wfi_req (ds_cpu3_wfi_req), + .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .etclken_cpu0_i (etclken_cpu0_i), + .etclken_cpu1_i (etclken_cpu1_i), + .etclken_cpu2_i (etclken_cpu2_i), + .etclken_cpu3_i (etclken_cpu3_i), + .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .ls_cpu0_clrexmon (ls_cpu0_clrexmon), + .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ls_cpu1_clrexmon (ls_cpu1_clrexmon), + .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ls_cpu2_clrexmon (ls_cpu2_clrexmon), + .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ls_cpu3_clrexmon (ls_cpu3_clrexmon), + .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), + .nCORERESET (nCORERESET[`MAIA_CN:0]), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nFIQ (nFIQ[`MAIA_CN:0]), + .nIRQ (nIRQ[`MAIA_CN:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .nPRESETDBG (nPRESETDBG), + .nREI (nREI[`MAIA_CN:0]), + .nSEI (nSEI[`MAIA_CN:0]), + .nVFIQ (nVFIQ[`MAIA_CN:0]), + .nVIRQ (nVIRQ[`MAIA_CN:0]), + .nVSEI (nVSEI[`MAIA_CN:0]), + .ncommirq_cpu0_i (ncommirq_cpu0_i), + .ncommirq_cpu1_i (ncommirq_cpu1_i), + .ncommirq_cpu2_i (ncommirq_cpu2_i), + .ncommirq_cpu3_i (ncommirq_cpu3_i), + .npmuirq_cpu0_i (npmuirq_cpu0_i), + .npmuirq_cpu1_i (npmuirq_cpu1_i), + .npmuirq_cpu2_i (npmuirq_cpu2_i), + .npmuirq_cpu3_i (npmuirq_cpu3_i), + .pm_export_cpu0_i (pm_export_cpu0_i), + .pm_export_cpu1_i (pm_export_cpu1_i), + .pm_export_cpu2_i (pm_export_cpu2_i), + .pm_export_cpu3_i (pm_export_cpu3_i), + .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), + .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), + .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), + .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]) + ); // unoncpu +endmodule // MAIA_feq20 + + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/MAIA_feq20_s.v b/Security Algo Accelerator/logical/maia/verilog/MAIA_feq20_s.v new file mode 100644 index 0000000000..4f3003bd3f --- /dev/null +++ b/Security Algo Accelerator/logical/maia/verilog/MAIA_feq20_s.v @@ -0,0 +1,4821 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: MAIA_feq20.v $ +// Checked In : $Date: 2014-10-14 15:20:06 -0500 (Tue, 14 Oct 2014) $ +// Revision : $Revision: 71806 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// +// This is top-level interconnect layer for the MAIA_feq20 top-level. +// + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +`define MAIA_CN 3 + +module MAIA_feq20_s ( + CLK, + CLKEN, + nCPUPORESET, + nCORERESET, + nL2RESET, + L2RSTDISABLE, + WARMRSTREQ, + CFGEND, + VINITHI, + CFGTE, + CP15SDISABLE, + CLUSTERIDAFF1, + CLUSTERIDAFF2, + AA64nAA32, + RVBARADDR0, +// BEGIN INCLUDE FOR CPU1 + RVBARADDR1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + RVBARADDR2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + RVBARADDR3, +// END INCLUDE FOR CPU3 + CRYPTODISABLE, + nFIQ, + nIRQ, + nSEI, + nREI, + nVFIQ, + nVIRQ, + nVSEI, +// BEGIN NO-GIC pins + nVCPUMNTIRQ, +// END NO-GIC pins + PERIPHBASE, +// BEGIN NO-GIC pins + GICCDISABLE, + ICDTVALID, + ICDTREADY, + ICDTDATA, + ICDTLAST, + ICDTDEST, + ICCTVALID, + ICCTREADY, + ICCTDATA, + ICCTLAST, + ICCTID, +// END NO-GIC pins + CNTVALUEB, + CNTCLKEN, + nCNTPNSIRQ, + nCNTPSIRQ, + nCNTVIRQ, + nCNTHPIRQ, + CLREXMONREQ, + CLREXMONACK, + EVENTI, + EVENTO, + STANDBYWFI, + STANDBYWFE, + STANDBYWFIL2, + SMPEN, + CPUQACTIVE, + CPUQREQn, + CPUQACCEPTn, + CPUQDENY, + L2QACTIVE, + L2QREQn, + L2QACCEPTn, + L2QDENY, + L2FLUSHREQ, + L2FLUSHDONE, + nINTERRIRQ, + nEXTERRIRQ, + SYSBARDISABLE, + BROADCASTINNER, + BROADCASTOUTER, + BROADCASTCACHEMAINT, + SCLKEN, + SINACT, + NODEID, + TXSACTIVE, + RXSACTIVE, + TXLINKACTIVEREQ, + TXLINKACTIVEACK, + RXLINKACTIVEREQ, + RXLINKACTIVEACK, + TXREQFLITPEND, + TXREQFLITV, + TXREQFLIT, + REQMEMATTR, + TXREQLCRDV, + TXRSPFLITPEND, + TXRSPFLITV, + TXRSPFLIT, + TXRSPLCRDV, + TXDATFLITPEND, + TXDATFLITV, + TXDATFLIT, + TXDATLCRDV, + RXSNPFLITPEND, + RXSNPFLITV, + RXSNPFLIT, + RXSNPLCRDV, + RXRSPFLITPEND, + RXRSPFLITV, + RXRSPFLIT, + RXRSPLCRDV, + RXDATFLITPEND, + RXDATFLITV, + RXDATFLIT, + RXDATLCRDV, + SAMMNBASE, + SAMADDRMAP0, + SAMADDRMAP1, + SAMADDRMAP2, + SAMADDRMAP3, + SAMADDRMAP4, + SAMADDRMAP5, + SAMADDRMAP6, + SAMADDRMAP7, + SAMADDRMAP8, + SAMADDRMAP9, + SAMADDRMAP10, + SAMADDRMAP11, + SAMADDRMAP12, + SAMADDRMAP13, + SAMADDRMAP14, + SAMADDRMAP15, + SAMADDRMAP16, + SAMADDRMAP17, + SAMADDRMAP18, + SAMADDRMAP19, + SAMMNNODEID, + SAMHNI0NODEID, + SAMHNI1NODEID, + SAMHNF0NODEID, + SAMHNF1NODEID, + SAMHNF2NODEID, + SAMHNF3NODEID, + SAMHNF4NODEID, + SAMHNF5NODEID, + SAMHNF6NODEID, + SAMHNF7NODEID, + SAMHNFMODE, +// BEGIN NO-ACP pins + ACLKENS, + AINACTS, + AWREADYS, + AWVALIDS, + AWIDS, + AWADDRS, + AWLENS, + AWCACHES, + AWUSERS, + AWPROTS, + WREADYS, + WVALIDS, + WDATAS, + WSTRBS, + WLASTS, + BREADYS, + BVALIDS, + BIDS, + BRESPS, + ARREADYS, + ARVALIDS, + ARIDS, + ARADDRS, + ARLENS, + ARCACHES, + ARUSERS, + ARPROTS, + RREADYS, + RVALIDS, + RIDS, + RDATAS, + RRESPS, + RLASTS, +// END NO-ACP pins + DBGROMADDR, + DBGROMADDRV, + DBGACK, + nCOMMIRQ, + COMMRX, + COMMTX, + DBGRSTREQ, + DBGNOPWRDWN, + DBGL1RSTDISABLE, + nPMUIRQ, + PMUEVENT0, +// BEGIN INCLUDE FOR CPU1 + PMUEVENT1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + PMUEVENT2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + PMUEVENT3, +// END INCLUDE FOR CPU3 + ATCLKEN, + TSVALUEB, + ATREADYM0, + AFVALIDM0, + ATDATAM0, + ATVALIDM0, + ATBYTESM0, + AFREADYM0, + ATIDM0, + SYNCREQM0, +// BEGIN INCLUDE FOR CPU1 + ATREADYM1, + AFVALIDM1, + ATDATAM1, + ATVALIDM1, + ATBYTESM1, + AFREADYM1, + ATIDM1, + SYNCREQM1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ATREADYM2, + AFVALIDM2, + ATDATAM2, + ATVALIDM2, + ATBYTESM2, + AFREADYM2, + ATIDM2, + SYNCREQM2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ATREADYM3, + AFVALIDM3, + ATDATAM3, + ATVALIDM3, + ATBYTESM3, + AFREADYM3, + ATIDM3, + SYNCREQM3, +// END INCLUDE FOR CPU3 + PCLKDBG, + PCLKENDBG, + nPRESETDBG, + PSELDBG, + PADDRDBG, + PADDRDBG31, + PENABLEDBG, + PWRITEDBG, + PWDATADBG, + PRDATADBG, + PREADYDBG, + PSLVERRDBG, + EDBGRQ, + PMUSNAPSHOTREQ, + PMUSNAPSHOTACK, + DBGPWRDUP, + DBGPWRUPREQ, + CTICHIN, + CTICHOUTACK, + CTICHOUT, + CTICHINACK, + CISBYPASS, + CIHSBYPASS, + CTIIRQ, + CTIIRQACK, + DBGEN, + NIDEN, + SPIDEN, + SPNIDEN, + DFTSE, + DFTRSTDISABLE, + DFTCRCLKDISABLE, + DFTL2CLKDISABLE, + DFTRAMHOLD, + DFTCLKBYPASS, + DFTMCPHOLD, + nMBISTRESET, + MBISTREQ +); + +//# +//# Interface Signals +//# ================= +//# + +//----------------------------------------------------------------------------- +// Clock and Reset Signals +//----------------------------------------------------------------------------- + input CLK; // Fast Clock + input CLKEN; // Fast Clock Enable + + input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset + input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) + input nL2RESET; // L2 reset + input L2RSTDISABLE; // L2 RAMs hardware reset disable + output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request +//See also nPRESETDBG; // Debug APB reset (PCLK) + +//----------------------------------------------------------------------------- +// Static Configuration Signals +//----------------------------------------------------------------------------- +// Static configuration signals that should be tied off and not change dynamically. +// Many of the initial values specified by these inputs +// may be overridden in software using CP15 registers. + + input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) + input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors + input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) + input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers + + input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] + input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] + + input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) + input [43:2] RVBARADDR0; // RVBAR address +// BEGIN INCLUDE FOR CPU1 + input [43:2] RVBARADDR1; // RVBAR address +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input [43:2] RVBARADDR2; // RVBAR address +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input [43:2] RVBARADDR3; // RVBAR address +// END INCLUDE FOR CPU3 + input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension + +//----------------------------------------------------------------------------- +// Interrupt Controller Signals +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] nFIQ; // Fast Interrupt request + input [`MAIA_CN:0] nIRQ; // Interrupt request + input [`MAIA_CN:0] nSEI; // System Error Interrupt + input [`MAIA_CN:0] nREI; // RAM Error Interrupt + input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request + input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request + input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt + +// BEGIN NO-GIC pins + output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output +// END NO-GIC pins + + input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers +// BEGIN NO-GIC pins + input GICCDISABLE; // Put GIC into bypass mode + + input ICDTVALID; // Distrubuter AXI4 SP Message Valid + output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message + input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data + input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet + input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID + + output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid + input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message + output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data + output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet + output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID +// END NO-GIC pins + +//----------------------------------------------------------------------------- +// Timer Signals +//----------------------------------------------------------------------------- + input [63:0] CNTVALUEB; // Counter value in binary + input CNTCLKEN; // Counter clock enable + output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event + output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event + output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event + output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event + +//----------------------------------------------------------------------------- +// Power Management Signals +//----------------------------------------------------------------------------- + input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) + output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) + input EVENTI; // Event input for processor wake-up from WFE state + output EVENTO; // Event output, signal is active when SEV instruction is executed + output [`MAIA_CN:0] STANDBYWFI; // WFI mode + output [`MAIA_CN:0] STANDBYWFE; // WFE mode + output STANDBYWFIL2; // WFI mode for L2 + output [`MAIA_CN:0] SMPEN; // CPU SMP bit + + output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE + input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn + output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn + output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY + + output L2QACTIVE; // L2 Q-channel QACTIVE + input L2QREQn; // L2 Q-channel QREQn + output L2QACCEPTn; // L2 Q-channel QACCEPTn + output L2QDENY; // L2 Q-channel QDENY + + input L2FLUSHREQ; // L2 hardware flush request + output L2FLUSHDONE; // L2 hardware flush done + +//----------------------------------------------------------------------------- +// Asynchronous Error Signals +//----------------------------------------------------------------------------- + output nINTERRIRQ; // L2 RAM dbl-bit ECC error + output nEXTERRIRQ; // Write transaction error + +//----------------------------------------------------------------------------- +// Bus Configuration Signals +//----------------------------------------------------------------------------- + input SYSBARDISABLE; // Disable broadcast of barriers + input BROADCASTINNER; // Extend Inner Shared Domain + input BROADCASTOUTER; // Extend Outer Shared Domain + input BROADCASTCACHEMAINT; // Broadcast cache maint ops + +//----------------------------------------------------------------------------- +// Skyros RN-F Interface +//----------------------------------------------------------------------------- + input SCLKEN; // Skyros clock enable + input SINACT; // Skyros snoop inactive + + input [6:0] NODEID; // Skyros requestor NodeID + + output TXSACTIVE; // Skyros active - indicates pending activity on pins + input RXSACTIVE; // Skyros active - indicates pending activity on pins + + output TXLINKACTIVEREQ; // Skyros transmit link active request + input TXLINKACTIVEACK; // SKyros transmit link active acknowledge + + input RXLINKACTIVEREQ; // SKyros receive link active request + output RXLINKACTIVEACK; // Skyros receive link active acknowledge + +// TXREQ - outbound requests + output TXREQFLITPEND; // Skyros TXREQ FLIT pending + output TXREQFLITV; // Skyros TXREQ FLIT valid + output [99:0] TXREQFLIT; // Skyros TXREQ FLIT payload + output [7:0] REQMEMATTR; // Skyros TXREQ raw memory attributes + input TXREQLCRDV; // Skyros TXREQ link-layer credit valid + +// TXRSP - outbound response + output TXRSPFLITPEND; // Skyros TXRSP FLIT pending + output TXRSPFLITV; // Skyros TXRSP FLIT valid + output [44:0] TXRSPFLIT; // Skyros TXRSP FLIT payload + input TXRSPLCRDV; // Skyros TXRSP link-layer credit valid + +// TXDAT - outbound data + output TXDATFLITPEND; // Skyros TXDAT FLIT pending + output TXDATFLITV; // Skyros TXDAT FLIT valid + output [193:0] TXDATFLIT; // Skyros TXDAT FLIT payload + input TXDATLCRDV; // Skyros TXDAT link-layer credit valid + +// RXSNP - inbound snoops + input RXSNPFLITPEND; // Skyros RXSNP FLIT pending + input RXSNPFLITV; // Skyros RXSNP FLIT valid + input [64:0] RXSNPFLIT; // Skyros RXSNP FLIT payload + output RXSNPLCRDV; // Skyros RXSNP link-layer credit valid + +// RXRSP - inbound response + input RXRSPFLITPEND; // Skyros RXRSP FLIT pending + input RXRSPFLITV; // Skyros RXRSP FLIT valid + input [44:0] RXRSPFLIT; // Skyros RXRSP FLIT payload + output RXRSPLCRDV; // Skyros RXRSP link-layer credit valid + +// RXDAT - inbound data + input RXDATFLITPEND; // Skyros RXDAT FLIT pending + input RXDATFLITV; // Skyros RXDAT FLIT valid + input [193:0] RXDATFLIT; // Skyros RXDAT FLIT payload + output RXDATLCRDV; // Skyros RXDAT link-layer credit valid + + input [43:24] SAMMNBASE; // Skyros SAM MN base address + input [1:0] SAMADDRMAP0; // Skyros SAM address region 0 mapping + input [1:0] SAMADDRMAP1; // Skyros SAM address region 1 mapping + input [1:0] SAMADDRMAP2; // Skyros SAM address region 2 mapping + input [1:0] SAMADDRMAP3; // Skyros SAM address region 3 mapping + input [1:0] SAMADDRMAP4; // Skyros SAM address region 4 mapping + input [1:0] SAMADDRMAP5; // Skyros SAM address region 5 mapping + input [1:0] SAMADDRMAP6; // Skyros SAM address region 6 mapping + input [1:0] SAMADDRMAP7; // Skyros SAM address region 7 mapping + input [1:0] SAMADDRMAP8; // Skyros SAM address region 8 mapping + input [1:0] SAMADDRMAP9; // Skyros SAM address region 9 mapping + input [1:0] SAMADDRMAP10; // Skyros SAM address region 10 mapping + input [1:0] SAMADDRMAP11; // Skyros SAM address region 11 mapping + input [1:0] SAMADDRMAP12; // Skyros SAM address region 12 mapping + input [1:0] SAMADDRMAP13; // Skyros SAM address region 13 mapping + input [1:0] SAMADDRMAP14; // Skyros SAM address region 14 mapping + input [1:0] SAMADDRMAP15; // Skyros SAM address region 15 mapping + input [1:0] SAMADDRMAP16; // Skyros SAM address region 16 mapping + input [1:0] SAMADDRMAP17; // Skyros SAM address region 17 mapping + input [1:0] SAMADDRMAP18; // Skyros SAM address region 18 mapping + input [1:0] SAMADDRMAP19; // Skyros SAM address region 19 mapping + input [6:0] SAMMNNODEID; // Skyros SAM MN target ID + input [6:0] SAMHNI0NODEID; // Skyros SAM HNI0 target ID + input [6:0] SAMHNI1NODEID; // Skyros SAM HNI1 target ID + input [6:0] SAMHNF0NODEID; // Skyros SAM HNF0 target ID + input [6:0] SAMHNF1NODEID; // Skyros SAM HNF1 target ID + input [6:0] SAMHNF2NODEID; // Skyros SAM HNF2 target ID + input [6:0] SAMHNF3NODEID; // Skyros SAM HNF3 target ID + input [6:0] SAMHNF4NODEID; // Skyros SAM HNF4 target ID + input [6:0] SAMHNF5NODEID; // Skyros SAM HNF5 target ID + input [6:0] SAMHNF6NODEID; // Skyros SAM HNF6 target ID + input [6:0] SAMHNF7NODEID; // Skyros SAM HNF7 target ID + input [2:0] SAMHNFMODE; // Skyros SAM HNF interleaving mode + +// BEGIN NO-ACP pins +//----------------------------------------------------------------------------- +// ACP AXI Slave +//----------------------------------------------------------------------------- + input ACLKENS; // AXI slave clock enable + input AINACTS; // AXI slave interface no longer active or accepting requests + +// Write Address channel signals + output AWREADYS; // Write Address ready (slave ready to accept write address) + input AWVALIDS; // Write Address valid + input [4:0] AWIDS; // Write Address ID + input [43:0] AWADDRS; // Write Address + input [7:0] AWLENS; // Write Burst Length + input [3:0] AWCACHES; // Write Cache type + input [1:0] AWUSERS; // Write inner & outer shareability + input [2:0] AWPROTS; // Write Protection type + +// Write Data channel signals + output WREADYS; // Write Data ready (slave ready to accept data) + input WVALIDS; // Write Data valid + input [127:0] WDATAS; // Write Data + input [15:0] WSTRBS; // Write byte-lane strobes + input WLASTS; // Write Data last transfer indicator + +// Write Response channel signals + input BREADYS; // Write Response ready (master ready to accept response) + output BVALIDS; // Write Response Valid + output [4:0] BIDS; // Write Response ID tag + output [1:0] BRESPS; // Write Response + +// Read Address channel signals + output ARREADYS; // Read Address ready (slave ready to accept read address) + input ARVALIDS; // Read Address valid + input [4:0] ARIDS; // Read Address ID + input [43:0] ARADDRS; // Read Address + input [7:0] ARLENS; // Read Burst Length + input [3:0] ARCACHES; // Read Cache type + input [1:0] ARUSERS; // Read inner & outer shareability + input [2:0] ARPROTS; // Read Protection type + +// Read Data channel signals + input RREADYS; // Read Data ready (master ready to accept data) + output RVALIDS; // Read Data valid + output [4:0] RIDS; // Read Data ID + output [127:0] RDATAS; // Read Data + output [1:0] RRESPS; // Read Data response + output RLASTS; // Read Data last transfer indicator +// END NO-ACP pins +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (CLK) +//----------------------------------------------------------------------------- +// Debug CLK interface + input [43:12] DBGROMADDR; // Debug ROM base address + input DBGROMADDRV; // Debug ROM base address valid + + output [`MAIA_CN:0] DBGACK; // Debug acknowledge + output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt + output [`MAIA_CN:0] COMMRX; // Comms channel receive + output [`MAIA_CN:0] COMMTX; // Comms channel transmit + + output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request + output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request + + input DBGL1RSTDISABLE; // L1 DCache hardware reset disable + +// PMU CLK interface + output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request + output [24:0] PMUEVENT0; // PMU Event bus +// BEGIN INCLUDE FOR CPU1 + output [24:0] PMUEVENT1; // PMU Event bus +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + output [24:0] PMUEVENT2; // PMU Event bus +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + output [24:0] PMUEVENT3; // PMU Event bus +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (ATCLK) +//----------------------------------------------------------------------------- +// ETM ATB interface and Misc signals + input ATCLKEN; // ATB Clock Enable + input [63:0] TSVALUEB; // ATB Timestamp in binary + + input ATREADYM0; // ATDATA can be accepted + input AFVALIDM0; // ATB Fifo Flush Request + output [31:0] ATDATAM0; // ATB Data + output ATVALIDM0; // ATB Data Valid + output [1:0] ATBYTESM0; // ATB Data Size + output AFREADYM0; // ATB Fifo Flush Finished + output [6:0] ATIDM0; // ATB Trace Source ID + input SYNCREQM0; // ATB External synchronization request + +// BEGIN INCLUDE FOR CPU1 + input ATREADYM1; // ATDATA can be accepted + input AFVALIDM1; // ATB Fifo Flush Request + output [31:0] ATDATAM1; // ATB Data + output ATVALIDM1; // ATB Data Valid + output [1:0] ATBYTESM1; // ATB Data Size + output AFREADYM1; // ATB Fifo Flush Finished + output [6:0] ATIDM1; // ATB Trace Source ID + input SYNCREQM1; // ATB External synchronization request +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ATREADYM2; // ATDATA can be accepted + input AFVALIDM2; // ATB Fifo Flush Request + output [31:0] ATDATAM2; // ATB Data + output ATVALIDM2; // ATB Data Valid + output [1:0] ATBYTESM2; // ATB Data Size + output AFREADYM2; // ATB Fifo Flush Finished + output [6:0] ATIDM2; // ATB Trace Source ID + input SYNCREQM2; // ATB External synchronization request +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ATREADYM3; // ATDATA can be accepted + input AFVALIDM3; // ATB Fifo Flush Request + output [31:0] ATDATAM3; // ATB Data + output ATVALIDM3; // ATB Data Valid + output [1:0] ATBYTESM3; // ATB Data Size + output AFREADYM3; // ATB Fifo Flush Finished + output [6:0] ATIDM3; // ATB Trace Source ID + input SYNCREQM3; // ATB External synchronization request +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (PCLK) +//----------------------------------------------------------------------------- +// Debug-APBv3 port (APB) + input PCLKDBG; // APB Clock + input PCLKENDBG; // APB Clock Enable + input nPRESETDBG; // APB Reset + input PSELDBG; // Debug bus access + input [21:2] PADDRDBG; // APB address + input PADDRDBG31; // APB address bit[31] + input PENABLEDBG; // APB transfer complete flag + input PWRITEDBG; // APB read/write indicator + input [31:0] PWDATADBG; // APB write data + output [31:0] PRDATADBG; // APB read data + output PREADYDBG; // APB slave ready, used to extend a transfer + output PSLVERRDBG; // APB slave transfer error + +// Misc interface + input [`MAIA_CN:0] EDBGRQ; // External debug request + +// PMU Snapshot interface + input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request + output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge + +// Power-related interface + input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status + output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request + +// CTI interface + input [3:0] CTICHIN; // Channel In + input [3:0] CTICHOUTACK; // Channel Out acknowledge + output [3:0] CTICHOUT; // Channel Out + output [3:0] CTICHINACK; // Channel In acknowledge + input CISBYPASS; // Channel interface sync bypass + input [3:0] CIHSBYPASS; // Channel interface H/S bypass + output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt + input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge + +//----------------------------------------------------------------------------- +// Debug Authentication Interface (CLK & PCLK) +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] DBGEN; // Invasive debug enable + input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable + input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable + input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable + +//----------------------------------------------------------------------------- +// DFT Signals +//----------------------------------------------------------------------------- + input DFTSE; // Scan enable + input DFTRSTDISABLE; // Disable reset to cells during scan shift + input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr + input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 + input DFTRAMHOLD; // Holds data in RAMs + input DFTCLKBYPASS; // L2 RAM strobe clock bypass + input DFTMCPHOLD; // Disable multi-cycle RAM paths + +//----------------------------------------------------------------------------- +// MBIST Interface +//----------------------------------------------------------------------------- + input nMBISTRESET; // MBIST reset + input MBISTREQ; // MBIST mode request + + + // wires + wire aa64naa32_cpu0_o; + wire aa64naa32_cpu1_o; + wire aa64naa32_cpu2_o; + wire aa64naa32_cpu3_o; + wire afreadym_cpu0_i; + wire afreadym_cpu1_i; + wire afreadym_cpu2_i; + wire afreadym_cpu3_i; + wire afvalidm_cpu0_o; + wire afvalidm_cpu1_o; + wire afvalidm_cpu2_o; + wire afvalidm_cpu3_o; + wire [1:0] atbytesm_cpu0_i; + wire [1:0] atbytesm_cpu1_i; + wire [1:0] atbytesm_cpu2_i; + wire [1:0] atbytesm_cpu3_i; + wire atclken_cpu0_o; + wire atclken_cpu1_o; + wire atclken_cpu2_o; + wire atclken_cpu3_o; + wire [31:0] atdatam_cpu0_i; + wire [31:0] atdatam_cpu1_i; + wire [31:0] atdatam_cpu2_i; + wire [31:0] atdatam_cpu3_i; + wire [6:0] atidm_cpu0_i; + wire [6:0] atidm_cpu1_i; + wire [6:0] atidm_cpu2_i; + wire [6:0] atidm_cpu3_i; + wire atreadym_cpu0_o; + wire atreadym_cpu1_o; + wire atreadym_cpu2_o; + wire atreadym_cpu3_o; + wire atvalidm_cpu0_i; + wire atvalidm_cpu1_i; + wire atvalidm_cpu2_i; + wire atvalidm_cpu3_i; + wire cfgend_cpu0_o; + wire cfgend_cpu1_o; + wire cfgend_cpu2_o; + wire cfgend_cpu3_o; + wire cfgte_cpu0_o; + wire cfgte_cpu1_o; + wire cfgte_cpu2_o; + wire cfgte_cpu3_o; + wire ck_cpu0_crcx_clk_en_n; + wire ck_cpu0_event_reg; + wire ck_cpu0_wfe_ack; + wire ck_cpu0_wfi_ack; + wire ck_cpu1_crcx_clk_en_n; + wire ck_cpu1_event_reg; + wire ck_cpu1_wfe_ack; + wire ck_cpu1_wfi_ack; + wire ck_cpu2_crcx_clk_en_n; + wire ck_cpu2_event_reg; + wire ck_cpu2_wfe_ack; + wire ck_cpu2_wfi_ack; + wire ck_cpu3_crcx_clk_en_n; + wire ck_cpu3_event_reg; + wire ck_cpu3_wfe_ack; + wire ck_cpu3_wfi_ack; + wire [`MAIA_CN:0] ck_gclkt; + wire [7:0] clusteridaff1_cpu0_o; + wire [7:0] clusteridaff1_cpu1_o; + wire [7:0] clusteridaff1_cpu2_o; + wire [7:0] clusteridaff1_cpu3_o; + wire [7:0] clusteridaff2_cpu0_o; + wire [7:0] clusteridaff2_cpu1_o; + wire [7:0] clusteridaff2_cpu2_o; + wire [7:0] clusteridaff2_cpu3_o; + wire commrx_cpu0_i; + wire commrx_cpu1_i; + wire commrx_cpu2_i; + wire commrx_cpu3_i; + wire commtx_cpu0_i; + wire commtx_cpu1_i; + wire commtx_cpu2_i; + wire commtx_cpu3_i; + wire cp15sdisable_cpu0_o; + wire cp15sdisable_cpu1_o; + wire cp15sdisable_cpu2_o; + wire cp15sdisable_cpu3_o; + wire [1:0] cpuid_cpu0_o; + wire [1:0] cpuid_cpu1_o; + wire [1:0] cpuid_cpu2_o; + wire [1:0] cpuid_cpu3_o; + wire cryptodisable_cpu0_o; + wire cryptodisable_cpu1_o; + wire cryptodisable_cpu2_o; + wire cryptodisable_cpu3_o; + wire dbgack_cpu0_i; + wire dbgack_cpu1_i; + wire dbgack_cpu2_i; + wire dbgack_cpu3_i; + wire dbgen_cpu0_o; + wire dbgen_cpu1_o; + wire dbgen_cpu2_o; + wire dbgen_cpu3_o; + wire dbgl1rstdisable_cpu0_o; + wire dbgl1rstdisable_cpu1_o; + wire dbgl1rstdisable_cpu2_o; + wire dbgl1rstdisable_cpu3_o; + wire dbgnopwrdwn_cpu0_i; + wire dbgnopwrdwn_cpu1_i; + wire dbgnopwrdwn_cpu2_i; + wire dbgnopwrdwn_cpu3_i; + wire [43:12] dbgromaddr_cpu0_o; + wire [43:12] dbgromaddr_cpu1_o; + wire [43:12] dbgromaddr_cpu2_o; + wire [43:12] dbgromaddr_cpu3_o; + wire dbgromaddrv_cpu0_o; + wire dbgromaddrv_cpu1_o; + wire dbgromaddrv_cpu2_o; + wire dbgromaddrv_cpu3_o; + wire dbgrstreq_cpu0_i; + wire dbgrstreq_cpu1_i; + wire dbgrstreq_cpu2_i; + wire dbgrstreq_cpu3_i; + wire dftcrclkdisable_cpu0_o; + wire dftcrclkdisable_cpu1_o; + wire dftcrclkdisable_cpu2_o; + wire dftcrclkdisable_cpu3_o; + wire dftramhold_cpu0_o; + wire dftramhold_cpu1_o; + wire dftramhold_cpu2_o; + wire dftramhold_cpu3_o; + wire dftrstdisable_cpu0_o; + wire dftrstdisable_cpu1_o; + wire dftrstdisable_cpu2_o; + wire dftrstdisable_cpu3_o; + wire dftse_cpu0_o; + wire dftse_cpu1_o; + wire dftse_cpu2_o; + wire dftse_cpu3_o; + wire [2:0] ds_cpu0_cpuectlr_ret; + wire ds_cpu0_cpuectlr_smp; + wire ds_cpu0_fiq_wfe_qual; + wire ds_cpu0_fiq_wfi_qual; + wire ds_cpu0_flush; + wire [5:0] ds_cpu0_flush_type; + wire ds_cpu0_hcr_va; + wire ds_cpu0_hcr_vf; + wire ds_cpu0_hcr_vi; + wire ds_cpu0_ic_aa64naa32; + wire [4:0] ds_cpu0_ic_cpsr_mode; + wire ds_cpu0_ic_hcr_change; + wire ds_cpu0_ic_sample_spr; + wire ds_cpu0_ic_scr_change; + wire ds_cpu0_imp_abrt_wfe_qual; + wire ds_cpu0_imp_abrt_wfi_qual; + wire ds_cpu0_irq_wfe_qual; + wire ds_cpu0_irq_wfi_qual; + wire [8:0] ds_cpu0_l2_spr_addr; + wire ds_cpu0_l2_spr_dw; + wire ds_cpu0_l2_spr_en; + wire ds_cpu0_l2_spr_rd; + wire ds_cpu0_l2_spr_wr; + wire [63:0] ds_cpu0_l2_spr_wr_data; + wire ds_cpu0_reset_req; + wire ds_cpu0_sev_req; + wire ds_cpu0_sevl_req; + wire ds_cpu0_vfiq_wfe_qual; + wire ds_cpu0_vfiq_wfi_qual; + wire ds_cpu0_vimp_abrt_wfe_qual; + wire ds_cpu0_vimp_abrt_wfi_qual; + wire ds_cpu0_virq_wfe_qual; + wire ds_cpu0_virq_wfi_qual; + wire ds_cpu0_wfe_req; + wire ds_cpu0_wfi_req; + wire [2:0] ds_cpu1_cpuectlr_ret; + wire ds_cpu1_cpuectlr_smp; + wire ds_cpu1_fiq_wfe_qual; + wire ds_cpu1_fiq_wfi_qual; + wire ds_cpu1_flush; + wire [5:0] ds_cpu1_flush_type; + wire ds_cpu1_hcr_va; + wire ds_cpu1_hcr_vf; + wire ds_cpu1_hcr_vi; + wire ds_cpu1_ic_aa64naa32; + wire [4:0] ds_cpu1_ic_cpsr_mode; + wire ds_cpu1_ic_hcr_change; + wire ds_cpu1_ic_sample_spr; + wire ds_cpu1_ic_scr_change; + wire ds_cpu1_imp_abrt_wfe_qual; + wire ds_cpu1_imp_abrt_wfi_qual; + wire ds_cpu1_irq_wfe_qual; + wire ds_cpu1_irq_wfi_qual; + wire [8:0] ds_cpu1_l2_spr_addr; + wire ds_cpu1_l2_spr_dw; + wire ds_cpu1_l2_spr_en; + wire ds_cpu1_l2_spr_rd; + wire ds_cpu1_l2_spr_wr; + wire [63:0] ds_cpu1_l2_spr_wr_data; + wire ds_cpu1_reset_req; + wire ds_cpu1_sev_req; + wire ds_cpu1_sevl_req; + wire ds_cpu1_vfiq_wfe_qual; + wire ds_cpu1_vfiq_wfi_qual; + wire ds_cpu1_vimp_abrt_wfe_qual; + wire ds_cpu1_vimp_abrt_wfi_qual; + wire ds_cpu1_virq_wfe_qual; + wire ds_cpu1_virq_wfi_qual; + wire ds_cpu1_wfe_req; + wire ds_cpu1_wfi_req; + wire [2:0] ds_cpu2_cpuectlr_ret; + wire ds_cpu2_cpuectlr_smp; + wire ds_cpu2_fiq_wfe_qual; + wire ds_cpu2_fiq_wfi_qual; + wire ds_cpu2_flush; + wire [5:0] ds_cpu2_flush_type; + wire ds_cpu2_hcr_va; + wire ds_cpu2_hcr_vf; + wire ds_cpu2_hcr_vi; + wire ds_cpu2_ic_aa64naa32; + wire [4:0] ds_cpu2_ic_cpsr_mode; + wire ds_cpu2_ic_hcr_change; + wire ds_cpu2_ic_sample_spr; + wire ds_cpu2_ic_scr_change; + wire ds_cpu2_imp_abrt_wfe_qual; + wire ds_cpu2_imp_abrt_wfi_qual; + wire ds_cpu2_irq_wfe_qual; + wire ds_cpu2_irq_wfi_qual; + wire [8:0] ds_cpu2_l2_spr_addr; + wire ds_cpu2_l2_spr_dw; + wire ds_cpu2_l2_spr_en; + wire ds_cpu2_l2_spr_rd; + wire ds_cpu2_l2_spr_wr; + wire [63:0] ds_cpu2_l2_spr_wr_data; + wire ds_cpu2_reset_req; + wire ds_cpu2_sev_req; + wire ds_cpu2_sevl_req; + wire ds_cpu2_vfiq_wfe_qual; + wire ds_cpu2_vfiq_wfi_qual; + wire ds_cpu2_vimp_abrt_wfe_qual; + wire ds_cpu2_vimp_abrt_wfi_qual; + wire ds_cpu2_virq_wfe_qual; + wire ds_cpu2_virq_wfi_qual; + wire ds_cpu2_wfe_req; + wire ds_cpu2_wfi_req; + wire [2:0] ds_cpu3_cpuectlr_ret; + wire ds_cpu3_cpuectlr_smp; + wire ds_cpu3_fiq_wfe_qual; + wire ds_cpu3_fiq_wfi_qual; + wire ds_cpu3_flush; + wire [5:0] ds_cpu3_flush_type; + wire ds_cpu3_hcr_va; + wire ds_cpu3_hcr_vf; + wire ds_cpu3_hcr_vi; + wire ds_cpu3_ic_aa64naa32; + wire [4:0] ds_cpu3_ic_cpsr_mode; + wire ds_cpu3_ic_hcr_change; + wire ds_cpu3_ic_sample_spr; + wire ds_cpu3_ic_scr_change; + wire ds_cpu3_imp_abrt_wfe_qual; + wire ds_cpu3_imp_abrt_wfi_qual; + wire ds_cpu3_irq_wfe_qual; + wire ds_cpu3_irq_wfi_qual; + wire [8:0] ds_cpu3_l2_spr_addr; + wire ds_cpu3_l2_spr_dw; + wire ds_cpu3_l2_spr_en; + wire ds_cpu3_l2_spr_rd; + wire ds_cpu3_l2_spr_wr; + wire [63:0] ds_cpu3_l2_spr_wr_data; + wire ds_cpu3_reset_req; + wire ds_cpu3_sev_req; + wire ds_cpu3_sevl_req; + wire ds_cpu3_vfiq_wfe_qual; + wire ds_cpu3_vfiq_wfi_qual; + wire ds_cpu3_vimp_abrt_wfe_qual; + wire ds_cpu3_vimp_abrt_wfi_qual; + wire ds_cpu3_virq_wfe_qual; + wire ds_cpu3_virq_wfi_qual; + wire ds_cpu3_wfe_req; + wire ds_cpu3_wfi_req; + wire dt_cpu0_coredbg_in_reset_gclk; + wire [1:0] dt_cpu0_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu0_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu0_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu0_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu0_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu0_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; + wire dt_cpu0_cti_trigoutack_bit1_gclk; + wire dt_cpu0_dbif_ack_gclk; + wire [14:2] dt_cpu0_dbif_addr_pclk; + wire dt_cpu0_dbif_err_gclk; + wire dt_cpu0_dbif_locked_pclk; + wire [31:0] dt_cpu0_dbif_rddata_gclk; + wire dt_cpu0_dbif_req_pclk; + wire [31:0] dt_cpu0_dbif_wrdata_pclk; + wire dt_cpu0_dbif_write_pclk; + wire dt_cpu0_edacr_frc_idleack_pclk; + wire dt_cpu0_edbgrq_pclk; + wire dt_cpu0_edecr_osuce_pclk; + wire dt_cpu0_edecr_rce_pclk; + wire dt_cpu0_edecr_ss_pclk; + wire dt_cpu0_edprcr_corepurq_pclk; + wire dt_cpu0_et_oslock_gclk; + wire dt_cpu0_halt_ack_gclk; + wire dt_cpu0_hlt_dbgevt_ok_gclk; + wire dt_cpu0_noclkstop_pclk; + wire dt_cpu0_os_double_lock_gclk; + wire dt_cpu0_pmusnapshot_ack_gclk; + wire dt_cpu0_pmusnapshot_req_pclk; + wire dt_cpu0_wfx_dbg_req_gclk; + wire dt_cpu0_wfx_wakeup_pclk; + wire dt_cpu1_coredbg_in_reset_gclk; + wire [1:0] dt_cpu1_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu1_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu1_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu1_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu1_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu1_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; + wire dt_cpu1_cti_trigoutack_bit1_gclk; + wire dt_cpu1_dbif_ack_gclk; + wire [14:2] dt_cpu1_dbif_addr_pclk; + wire dt_cpu1_dbif_err_gclk; + wire dt_cpu1_dbif_locked_pclk; + wire [31:0] dt_cpu1_dbif_rddata_gclk; + wire dt_cpu1_dbif_req_pclk; + wire [31:0] dt_cpu1_dbif_wrdata_pclk; + wire dt_cpu1_dbif_write_pclk; + wire dt_cpu1_edacr_frc_idleack_pclk; + wire dt_cpu1_edbgrq_pclk; + wire dt_cpu1_edecr_osuce_pclk; + wire dt_cpu1_edecr_rce_pclk; + wire dt_cpu1_edecr_ss_pclk; + wire dt_cpu1_edprcr_corepurq_pclk; + wire dt_cpu1_et_oslock_gclk; + wire dt_cpu1_halt_ack_gclk; + wire dt_cpu1_hlt_dbgevt_ok_gclk; + wire dt_cpu1_noclkstop_pclk; + wire dt_cpu1_os_double_lock_gclk; + wire dt_cpu1_pmusnapshot_ack_gclk; + wire dt_cpu1_pmusnapshot_req_pclk; + wire dt_cpu1_wfx_dbg_req_gclk; + wire dt_cpu1_wfx_wakeup_pclk; + wire dt_cpu2_coredbg_in_reset_gclk; + wire [1:0] dt_cpu2_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu2_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu2_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu2_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu2_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu2_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; + wire dt_cpu2_cti_trigoutack_bit1_gclk; + wire dt_cpu2_dbif_ack_gclk; + wire [14:2] dt_cpu2_dbif_addr_pclk; + wire dt_cpu2_dbif_err_gclk; + wire dt_cpu2_dbif_locked_pclk; + wire [31:0] dt_cpu2_dbif_rddata_gclk; + wire dt_cpu2_dbif_req_pclk; + wire [31:0] dt_cpu2_dbif_wrdata_pclk; + wire dt_cpu2_dbif_write_pclk; + wire dt_cpu2_edacr_frc_idleack_pclk; + wire dt_cpu2_edbgrq_pclk; + wire dt_cpu2_edecr_osuce_pclk; + wire dt_cpu2_edecr_rce_pclk; + wire dt_cpu2_edecr_ss_pclk; + wire dt_cpu2_edprcr_corepurq_pclk; + wire dt_cpu2_et_oslock_gclk; + wire dt_cpu2_halt_ack_gclk; + wire dt_cpu2_hlt_dbgevt_ok_gclk; + wire dt_cpu2_noclkstop_pclk; + wire dt_cpu2_os_double_lock_gclk; + wire dt_cpu2_pmusnapshot_ack_gclk; + wire dt_cpu2_pmusnapshot_req_pclk; + wire dt_cpu2_wfx_dbg_req_gclk; + wire dt_cpu2_wfx_wakeup_pclk; + wire dt_cpu3_coredbg_in_reset_gclk; + wire [1:0] dt_cpu3_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu3_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu3_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu3_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu3_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu3_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; + wire dt_cpu3_cti_trigoutack_bit1_gclk; + wire dt_cpu3_dbif_ack_gclk; + wire [14:2] dt_cpu3_dbif_addr_pclk; + wire dt_cpu3_dbif_err_gclk; + wire dt_cpu3_dbif_locked_pclk; + wire [31:0] dt_cpu3_dbif_rddata_gclk; + wire dt_cpu3_dbif_req_pclk; + wire [31:0] dt_cpu3_dbif_wrdata_pclk; + wire dt_cpu3_dbif_write_pclk; + wire dt_cpu3_edacr_frc_idleack_pclk; + wire dt_cpu3_edbgrq_pclk; + wire dt_cpu3_edecr_osuce_pclk; + wire dt_cpu3_edecr_rce_pclk; + wire dt_cpu3_edecr_ss_pclk; + wire dt_cpu3_edprcr_corepurq_pclk; + wire dt_cpu3_et_oslock_gclk; + wire dt_cpu3_halt_ack_gclk; + wire dt_cpu3_hlt_dbgevt_ok_gclk; + wire dt_cpu3_noclkstop_pclk; + wire dt_cpu3_os_double_lock_gclk; + wire dt_cpu3_pmusnapshot_ack_gclk; + wire dt_cpu3_pmusnapshot_req_pclk; + wire dt_cpu3_wfx_dbg_req_gclk; + wire dt_cpu3_wfx_wakeup_pclk; + wire etclken_cpu0_i; + wire etclken_cpu1_i; + wire etclken_cpu2_i; + wire etclken_cpu3_i; + wire giccdisable_cpu0_o; + wire giccdisable_cpu1_o; + wire giccdisable_cpu2_o; + wire giccdisable_cpu3_o; + wire [`MAIA_CN:0] ic_block_eoi_sgi_wr; + wire [`MAIA_CN:0] ic_el_change_complete; + wire [`MAIA_CN:0] ic_hcr_change_complete; + wire [`MAIA_CN:0] ic_ich_el2_tall0; + wire [`MAIA_CN:0] ic_ich_el2_tall1; + wire [`MAIA_CN:0] ic_ich_el2_tc; + wire [`MAIA_CN:0] ic_nfiq; + wire [`MAIA_CN:0] ic_nirq; + wire [`MAIA_CN:0] ic_nsei; + wire [`MAIA_CN:0] ic_nvfiq; + wire [`MAIA_CN:0] ic_nvirq; + wire [`MAIA_CN:0] ic_nvsei; + wire [`MAIA_CN:0] ic_p_valid; + wire [`MAIA_CN:0] ic_sample_spr; + wire [`MAIA_CN:0] ic_scr_change_complete; + wire [`MAIA_CN:0] ic_sra_el1ns_en; + wire [`MAIA_CN:0] ic_sra_el1s_en; + wire [`MAIA_CN:0] ic_sra_el2_en; + wire [`MAIA_CN:0] ic_sra_el3_en; + wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; + wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap; + wire [`MAIA_CN:0] ic_sre_el1s_mon_trap; + wire [`MAIA_CN:0] ic_sre_el2_mon_trap; + wire l2_cpu0_arb_thrshld_timeout_en; + wire l2_cpu0_barrier_done; + wire l2_cpu0_blk_non_evict_wr; + wire l2_cpu0_ccb_dbg_req_c3; + wire [48:0] l2_cpu0_ccb_req_addr_c3; + wire [4:0] l2_cpu0_ccb_req_id_c3; + wire [23:0] l2_cpu0_ccb_req_info_c3; + wire [8:0] l2_cpu0_ccb_req_type_c3; + wire l2_cpu0_cfg_ecc_en; + wire [2:0] l2_cpu0_dbufid_r1; + wire [129:0] l2_cpu0_ddata_r2; + wire l2_cpu0_ddlb_ecc_err_r3; + wire l2_cpu0_dext_err_r2; + wire l2_cpu0_dext_err_type_r2; + wire l2_cpu0_disable_clean_evict_opt; + wire l2_cpu0_dlast_r1; + wire l2_cpu0_dsngl_ecc_err_r3; + wire [3:0] l2_cpu0_dsq_clr_id_q; + wire l2_cpu0_dsq_clr_vld_q; + wire [3:0] l2_cpu0_dsq_rd_buf_id; + wire [15:0] l2_cpu0_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu0_dsq_rd_data_q; + wire l2_cpu0_dsq_rd_en; + wire l2_cpu0_dsq_rd_en_x2; + wire l2_cpu0_dt_pmu_evt_en; + wire l2_cpu0_dvalid_r1; + wire l2_cpu0_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; + wire l2_cpu0_flsh_if_rd_l4_dly; + wire l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; + wire l2_cpu0_flsh_ls_rd_l2_dly; + wire l2_cpu0_flsh_ls_rd_l4_dly; + wire l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; + wire l2_cpu0_flsh_ls_wr_l2_dly; + wire l2_cpu0_flsh_ls_wr_l4_dly; + wire l2_cpu0_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu0_ibufid_r1; + wire [15:0] l2_cpu0_ic_addr_arb_set; + wire l2_cpu0_ic_arb_fast; + wire l2_cpu0_ic_barrier_stall_q; + wire [43:18] l2_cpu0_ic_base; + wire [31:0] l2_cpu0_ic_data_arb_set; + wire [2:0] l2_cpu0_ic_elem_size_arb_set; + wire l2_cpu0_ic_excl_arb_set; + wire [2:0] l2_cpu0_ic_id_arb_set; + wire l2_cpu0_ic_ns_arb_set; + wire l2_cpu0_ic_vld_skid; + wire l2_cpu0_ic_write_arb_set; + wire [127:0] l2_cpu0_idata_r2; + wire l2_cpu0_idlb_ecc_err_r3; + wire l2_cpu0_idle_block_reqs_q; + wire l2_cpu0_idle_wakeup_q; + wire l2_cpu0_iext_err_r2; + wire l2_cpu0_iext_err_type_r2; + wire l2_cpu0_if_ccb_clken_c3; + wire l2_cpu0_if_ccb_req_c3; + wire l2_cpu0_if_ccb_resp; + wire [4:0] l2_cpu0_if_ccb_resp_id; + wire l2_cpu0_if_sync_done_q; + wire l2_cpu0_if_sync_req; + wire l2_cpu0_ifq_haz_pending; + wire l2_cpu0_isngl_ecc_err_r3; + wire l2_cpu0_ivalid_r1; + wire [1:0] l2_cpu0_l2_cache_size; + wire [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; + wire l2_cpu0_lrq_haz_pending; + wire l2_cpu0_ls_ccb_clken_c3; + wire l2_cpu0_ls_ccb_data_wr; + wire l2_cpu0_ls_ccb_req_c3; + wire l2_cpu0_ls_ccb_resp; + wire [4:0] l2_cpu0_ls_ccb_resp_id; + wire l2_cpu0_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu0_ls_rd_haz_id_arb_q; + wire l2_cpu0_ls_rd_haz_vld_arb_q; + wire l2_cpu0_ls_sync_req; + wire [4:0] l2_cpu0_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu0_ls_wr_data_w2a; + wire l2_cpu0_ls_wr_dirty_w2a; + wire l2_cpu0_ls_wr_err_w2a; + wire [2:0] l2_cpu0_ls_wr_haz_id_arb_q; + wire l2_cpu0_ls_wr_haz_vld_arb_q; + wire l2_cpu0_ls_wr_last_w2a; + wire l2_cpu0_ls_wr_req_w2a; + wire [2:0] l2_cpu0_ls_wr_type_w2a; + wire [12:0] l2_cpu0_mbist1_addr_b1; + wire l2_cpu0_mbist1_all_b1; + wire [3:0] l2_cpu0_mbist1_array_b1; + wire [7:0] l2_cpu0_mbist1_be_b1; + wire l2_cpu0_mbist1_en_b1; + wire l2_cpu0_mbist1_rd_en_b1; + wire l2_cpu0_mbist1_wr_en_b1; + wire l2_cpu0_no_intctrl; + wire l2_cpu0_pf_rd_vld_skid_popped; + wire l2_cpu0_pf_throttle_q; + wire [33:0] l2_cpu0_pmu_events; + wire [2:0] l2_cpu0_rbufid; + wire l2_cpu0_rd_aarch64_arb_set; + wire [44:0] l2_cpu0_rd_addr_arb_set; + wire l2_cpu0_rd_arb; + wire l2_cpu0_rd_arb_fast; + wire [15:8] l2_cpu0_rd_asid_arb_set; + wire l2_cpu0_rd_bypass_arb_set; + wire [2:0] l2_cpu0_rd_bypass_bufid_e5; + wire [2:0] l2_cpu0_rd_bypass_lrq_id_e5; + wire l2_cpu0_rd_bypass_req_can_e5; + wire l2_cpu0_rd_bypass_way_e5; + wire [2:0] l2_cpu0_rd_cache_attr_arb_set; + wire [2:0] l2_cpu0_rd_elem_size_arb_set; + wire l2_cpu0_rd_excl_arb_set; + wire [4:0] l2_cpu0_rd_id_arb_set; + wire [2:0] l2_cpu0_rd_lrq_id_arb_set; + wire [7:0] l2_cpu0_rd_page_attr_arb_set; + wire l2_cpu0_rd_prfm_arb_set; + wire l2_cpu0_rd_priv_arb_set; + wire l2_cpu0_rd_replayed_arb_set; + wire [1:0] l2_cpu0_rd_shared_arb_set; + wire [6:0] l2_cpu0_rd_type_arb_set; + wire l2_cpu0_rd_va48_arb_set; + wire l2_cpu0_rd_vld_skid; + wire l2_cpu0_rd_way_arb_set; + wire l2_cpu0_rexfail; + wire [1:0] l2_cpu0_rstate; + wire l2_cpu0_rvalid; + wire [2:0] l2_cpu0_spec_bufid; + wire l2_cpu0_spec_valid; + wire [63:0] l2_cpu0_spr_rd_data; + wire l2_cpu0_tbw_dbl_ecc_err; + wire [63:0] l2_cpu0_tbw_desc_data; + wire l2_cpu0_tbw_desc_vld; + wire l2_cpu0_tbw_ext_err; + wire l2_cpu0_tbw_ext_err_type; + wire l2_cpu0_tlb_ccb_clken_c3; + wire l2_cpu0_tlb_ccb_req_c3; + wire l2_cpu0_tlb_sync_complete; + wire l2_cpu0_tlb_sync_done_q; + wire l2_cpu0_tlb_sync_req; + wire l2_cpu0_trq_haz_pending; + wire l2_cpu0_tw_ccb_resp; + wire [4:0] l2_cpu0_tw_ccb_resp_id; + wire l2_cpu0_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu0_wr_addr_arb_set; + wire l2_cpu0_wr_arb; + wire l2_cpu0_wr_arb_fast; + wire [2:0] l2_cpu0_wr_cache_attr_arb_set; + wire [11:0] l2_cpu0_wr_cl_id_arb_set; + wire l2_cpu0_wr_clean_evict_arb_set; + wire [143:0] l2_cpu0_wr_data; + wire l2_cpu0_wr_data_stall; + wire l2_cpu0_wr_data_vld_x1_q; + wire l2_cpu0_wr_dirty_arb_set; + wire [2:0] l2_cpu0_wr_elem_size_arb_set; + wire l2_cpu0_wr_err_arb_set; + wire l2_cpu0_wr_evict_x1_q; + wire l2_cpu0_wr_ex_fail; + wire l2_cpu0_wr_ex_resp; + wire [3:0] l2_cpu0_wr_id_arb_set; + wire l2_cpu0_wr_last_arb_set; + wire [7:0] l2_cpu0_wr_page_attr_arb_set; + wire [3:0] l2_cpu0_wr_partial_dw_arb_set; + wire l2_cpu0_wr_priv_arb_set; + wire [1:0] l2_cpu0_wr_shared_arb_set; + wire [2:0] l2_cpu0_wr_type_arb_set; + wire l2_cpu0_wr_vld_skid; + wire l2_cpu0_wr_way_arb_set; + wire l2_cpu0_wrq_almost_full; + wire [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; + wire l2_cpu0_wrq_haz_pending; + wire l2_cpu1_arb_thrshld_timeout_en; + wire l2_cpu1_barrier_done; + wire l2_cpu1_blk_non_evict_wr; + wire l2_cpu1_ccb_dbg_req_c3; + wire [48:0] l2_cpu1_ccb_req_addr_c3; + wire [4:0] l2_cpu1_ccb_req_id_c3; + wire [23:0] l2_cpu1_ccb_req_info_c3; + wire [8:0] l2_cpu1_ccb_req_type_c3; + wire l2_cpu1_cfg_ecc_en; + wire [2:0] l2_cpu1_dbufid_r1; + wire [129:0] l2_cpu1_ddata_r2; + wire l2_cpu1_ddlb_ecc_err_r3; + wire l2_cpu1_dext_err_r2; + wire l2_cpu1_dext_err_type_r2; + wire l2_cpu1_disable_clean_evict_opt; + wire l2_cpu1_dlast_r1; + wire l2_cpu1_dsngl_ecc_err_r3; + wire [3:0] l2_cpu1_dsq_clr_id_q; + wire l2_cpu1_dsq_clr_vld_q; + wire [3:0] l2_cpu1_dsq_rd_buf_id; + wire [15:0] l2_cpu1_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu1_dsq_rd_data_q; + wire l2_cpu1_dsq_rd_en; + wire l2_cpu1_dsq_rd_en_x2; + wire l2_cpu1_dt_pmu_evt_en; + wire l2_cpu1_dvalid_r1; + wire l2_cpu1_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; + wire l2_cpu1_flsh_if_rd_l4_dly; + wire l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; + wire l2_cpu1_flsh_ls_rd_l2_dly; + wire l2_cpu1_flsh_ls_rd_l4_dly; + wire l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; + wire l2_cpu1_flsh_ls_wr_l2_dly; + wire l2_cpu1_flsh_ls_wr_l4_dly; + wire l2_cpu1_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu1_ibufid_r1; + wire [15:0] l2_cpu1_ic_addr_arb_set; + wire l2_cpu1_ic_arb_fast; + wire l2_cpu1_ic_barrier_stall_q; + wire [43:18] l2_cpu1_ic_base; + wire [31:0] l2_cpu1_ic_data_arb_set; + wire [2:0] l2_cpu1_ic_elem_size_arb_set; + wire l2_cpu1_ic_excl_arb_set; + wire [2:0] l2_cpu1_ic_id_arb_set; + wire l2_cpu1_ic_ns_arb_set; + wire l2_cpu1_ic_vld_skid; + wire l2_cpu1_ic_write_arb_set; + wire [127:0] l2_cpu1_idata_r2; + wire l2_cpu1_idlb_ecc_err_r3; + wire l2_cpu1_idle_block_reqs_q; + wire l2_cpu1_idle_wakeup_q; + wire l2_cpu1_iext_err_r2; + wire l2_cpu1_iext_err_type_r2; + wire l2_cpu1_if_ccb_clken_c3; + wire l2_cpu1_if_ccb_req_c3; + wire l2_cpu1_if_ccb_resp; + wire [4:0] l2_cpu1_if_ccb_resp_id; + wire l2_cpu1_if_sync_done_q; + wire l2_cpu1_if_sync_req; + wire l2_cpu1_ifq_haz_pending; + wire l2_cpu1_isngl_ecc_err_r3; + wire l2_cpu1_ivalid_r1; + wire [1:0] l2_cpu1_l2_cache_size; + wire [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; + wire l2_cpu1_lrq_haz_pending; + wire l2_cpu1_ls_ccb_clken_c3; + wire l2_cpu1_ls_ccb_data_wr; + wire l2_cpu1_ls_ccb_req_c3; + wire l2_cpu1_ls_ccb_resp; + wire [4:0] l2_cpu1_ls_ccb_resp_id; + wire l2_cpu1_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu1_ls_rd_haz_id_arb_q; + wire l2_cpu1_ls_rd_haz_vld_arb_q; + wire l2_cpu1_ls_sync_req; + wire [4:0] l2_cpu1_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu1_ls_wr_data_w2a; + wire l2_cpu1_ls_wr_dirty_w2a; + wire l2_cpu1_ls_wr_err_w2a; + wire [2:0] l2_cpu1_ls_wr_haz_id_arb_q; + wire l2_cpu1_ls_wr_haz_vld_arb_q; + wire l2_cpu1_ls_wr_last_w2a; + wire l2_cpu1_ls_wr_req_w2a; + wire [2:0] l2_cpu1_ls_wr_type_w2a; + wire [12:0] l2_cpu1_mbist1_addr_b1; + wire l2_cpu1_mbist1_all_b1; + wire [3:0] l2_cpu1_mbist1_array_b1; + wire [7:0] l2_cpu1_mbist1_be_b1; + wire l2_cpu1_mbist1_en_b1; + wire l2_cpu1_mbist1_rd_en_b1; + wire l2_cpu1_mbist1_wr_en_b1; + wire l2_cpu1_no_intctrl; + wire l2_cpu1_pf_rd_vld_skid_popped; + wire l2_cpu1_pf_throttle_q; + wire [33:0] l2_cpu1_pmu_events; + wire [2:0] l2_cpu1_rbufid; + wire l2_cpu1_rd_aarch64_arb_set; + wire [44:0] l2_cpu1_rd_addr_arb_set; + wire l2_cpu1_rd_arb; + wire l2_cpu1_rd_arb_fast; + wire [15:8] l2_cpu1_rd_asid_arb_set; + wire l2_cpu1_rd_bypass_arb_set; + wire [2:0] l2_cpu1_rd_bypass_bufid_e5; + wire [2:0] l2_cpu1_rd_bypass_lrq_id_e5; + wire l2_cpu1_rd_bypass_req_can_e5; + wire l2_cpu1_rd_bypass_way_e5; + wire [2:0] l2_cpu1_rd_cache_attr_arb_set; + wire [2:0] l2_cpu1_rd_elem_size_arb_set; + wire l2_cpu1_rd_excl_arb_set; + wire [4:0] l2_cpu1_rd_id_arb_set; + wire [2:0] l2_cpu1_rd_lrq_id_arb_set; + wire [7:0] l2_cpu1_rd_page_attr_arb_set; + wire l2_cpu1_rd_prfm_arb_set; + wire l2_cpu1_rd_priv_arb_set; + wire l2_cpu1_rd_replayed_arb_set; + wire [1:0] l2_cpu1_rd_shared_arb_set; + wire [6:0] l2_cpu1_rd_type_arb_set; + wire l2_cpu1_rd_va48_arb_set; + wire l2_cpu1_rd_vld_skid; + wire l2_cpu1_rd_way_arb_set; + wire l2_cpu1_rexfail; + wire [1:0] l2_cpu1_rstate; + wire l2_cpu1_rvalid; + wire [2:0] l2_cpu1_spec_bufid; + wire l2_cpu1_spec_valid; + wire [63:0] l2_cpu1_spr_rd_data; + wire l2_cpu1_tbw_dbl_ecc_err; + wire [63:0] l2_cpu1_tbw_desc_data; + wire l2_cpu1_tbw_desc_vld; + wire l2_cpu1_tbw_ext_err; + wire l2_cpu1_tbw_ext_err_type; + wire l2_cpu1_tlb_ccb_clken_c3; + wire l2_cpu1_tlb_ccb_req_c3; + wire l2_cpu1_tlb_sync_complete; + wire l2_cpu1_tlb_sync_done_q; + wire l2_cpu1_tlb_sync_req; + wire l2_cpu1_trq_haz_pending; + wire l2_cpu1_tw_ccb_resp; + wire [4:0] l2_cpu1_tw_ccb_resp_id; + wire l2_cpu1_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu1_wr_addr_arb_set; + wire l2_cpu1_wr_arb; + wire l2_cpu1_wr_arb_fast; + wire [2:0] l2_cpu1_wr_cache_attr_arb_set; + wire [11:0] l2_cpu1_wr_cl_id_arb_set; + wire l2_cpu1_wr_clean_evict_arb_set; + wire [143:0] l2_cpu1_wr_data; + wire l2_cpu1_wr_data_stall; + wire l2_cpu1_wr_data_vld_x1_q; + wire l2_cpu1_wr_dirty_arb_set; + wire [2:0] l2_cpu1_wr_elem_size_arb_set; + wire l2_cpu1_wr_err_arb_set; + wire l2_cpu1_wr_evict_x1_q; + wire l2_cpu1_wr_ex_fail; + wire l2_cpu1_wr_ex_resp; + wire [3:0] l2_cpu1_wr_id_arb_set; + wire l2_cpu1_wr_last_arb_set; + wire [7:0] l2_cpu1_wr_page_attr_arb_set; + wire [3:0] l2_cpu1_wr_partial_dw_arb_set; + wire l2_cpu1_wr_priv_arb_set; + wire [1:0] l2_cpu1_wr_shared_arb_set; + wire [2:0] l2_cpu1_wr_type_arb_set; + wire l2_cpu1_wr_vld_skid; + wire l2_cpu1_wr_way_arb_set; + wire l2_cpu1_wrq_almost_full; + wire [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; + wire l2_cpu1_wrq_haz_pending; + wire l2_cpu2_arb_thrshld_timeout_en; + wire l2_cpu2_barrier_done; + wire l2_cpu2_blk_non_evict_wr; + wire l2_cpu2_ccb_dbg_req_c3; + wire [48:0] l2_cpu2_ccb_req_addr_c3; + wire [4:0] l2_cpu2_ccb_req_id_c3; + wire [23:0] l2_cpu2_ccb_req_info_c3; + wire [8:0] l2_cpu2_ccb_req_type_c3; + wire l2_cpu2_cfg_ecc_en; + wire [2:0] l2_cpu2_dbufid_r1; + wire [129:0] l2_cpu2_ddata_r2; + wire l2_cpu2_ddlb_ecc_err_r3; + wire l2_cpu2_dext_err_r2; + wire l2_cpu2_dext_err_type_r2; + wire l2_cpu2_disable_clean_evict_opt; + wire l2_cpu2_dlast_r1; + wire l2_cpu2_dsngl_ecc_err_r3; + wire [3:0] l2_cpu2_dsq_clr_id_q; + wire l2_cpu2_dsq_clr_vld_q; + wire [3:0] l2_cpu2_dsq_rd_buf_id; + wire [15:0] l2_cpu2_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu2_dsq_rd_data_q; + wire l2_cpu2_dsq_rd_en; + wire l2_cpu2_dsq_rd_en_x2; + wire l2_cpu2_dt_pmu_evt_en; + wire l2_cpu2_dvalid_r1; + wire l2_cpu2_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; + wire l2_cpu2_flsh_if_rd_l4_dly; + wire l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; + wire l2_cpu2_flsh_ls_rd_l2_dly; + wire l2_cpu2_flsh_ls_rd_l4_dly; + wire l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; + wire l2_cpu2_flsh_ls_wr_l2_dly; + wire l2_cpu2_flsh_ls_wr_l4_dly; + wire l2_cpu2_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu2_ibufid_r1; + wire [15:0] l2_cpu2_ic_addr_arb_set; + wire l2_cpu2_ic_arb_fast; + wire l2_cpu2_ic_barrier_stall_q; + wire [43:18] l2_cpu2_ic_base; + wire [31:0] l2_cpu2_ic_data_arb_set; + wire [2:0] l2_cpu2_ic_elem_size_arb_set; + wire l2_cpu2_ic_excl_arb_set; + wire [2:0] l2_cpu2_ic_id_arb_set; + wire l2_cpu2_ic_ns_arb_set; + wire l2_cpu2_ic_vld_skid; + wire l2_cpu2_ic_write_arb_set; + wire [127:0] l2_cpu2_idata_r2; + wire l2_cpu2_idlb_ecc_err_r3; + wire l2_cpu2_idle_block_reqs_q; + wire l2_cpu2_idle_wakeup_q; + wire l2_cpu2_iext_err_r2; + wire l2_cpu2_iext_err_type_r2; + wire l2_cpu2_if_ccb_clken_c3; + wire l2_cpu2_if_ccb_req_c3; + wire l2_cpu2_if_ccb_resp; + wire [4:0] l2_cpu2_if_ccb_resp_id; + wire l2_cpu2_if_sync_done_q; + wire l2_cpu2_if_sync_req; + wire l2_cpu2_ifq_haz_pending; + wire l2_cpu2_isngl_ecc_err_r3; + wire l2_cpu2_ivalid_r1; + wire [1:0] l2_cpu2_l2_cache_size; + wire [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; + wire l2_cpu2_lrq_haz_pending; + wire l2_cpu2_ls_ccb_clken_c3; + wire l2_cpu2_ls_ccb_data_wr; + wire l2_cpu2_ls_ccb_req_c3; + wire l2_cpu2_ls_ccb_resp; + wire [4:0] l2_cpu2_ls_ccb_resp_id; + wire l2_cpu2_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu2_ls_rd_haz_id_arb_q; + wire l2_cpu2_ls_rd_haz_vld_arb_q; + wire l2_cpu2_ls_sync_req; + wire [4:0] l2_cpu2_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu2_ls_wr_data_w2a; + wire l2_cpu2_ls_wr_dirty_w2a; + wire l2_cpu2_ls_wr_err_w2a; + wire [2:0] l2_cpu2_ls_wr_haz_id_arb_q; + wire l2_cpu2_ls_wr_haz_vld_arb_q; + wire l2_cpu2_ls_wr_last_w2a; + wire l2_cpu2_ls_wr_req_w2a; + wire [2:0] l2_cpu2_ls_wr_type_w2a; + wire [12:0] l2_cpu2_mbist1_addr_b1; + wire l2_cpu2_mbist1_all_b1; + wire [3:0] l2_cpu2_mbist1_array_b1; + wire [7:0] l2_cpu2_mbist1_be_b1; + wire l2_cpu2_mbist1_en_b1; + wire l2_cpu2_mbist1_rd_en_b1; + wire l2_cpu2_mbist1_wr_en_b1; + wire l2_cpu2_no_intctrl; + wire l2_cpu2_pf_rd_vld_skid_popped; + wire l2_cpu2_pf_throttle_q; + wire [33:0] l2_cpu2_pmu_events; + wire [2:0] l2_cpu2_rbufid; + wire l2_cpu2_rd_aarch64_arb_set; + wire [44:0] l2_cpu2_rd_addr_arb_set; + wire l2_cpu2_rd_arb; + wire l2_cpu2_rd_arb_fast; + wire [15:8] l2_cpu2_rd_asid_arb_set; + wire l2_cpu2_rd_bypass_arb_set; + wire [2:0] l2_cpu2_rd_bypass_bufid_e5; + wire [2:0] l2_cpu2_rd_bypass_lrq_id_e5; + wire l2_cpu2_rd_bypass_req_can_e5; + wire l2_cpu2_rd_bypass_way_e5; + wire [2:0] l2_cpu2_rd_cache_attr_arb_set; + wire [2:0] l2_cpu2_rd_elem_size_arb_set; + wire l2_cpu2_rd_excl_arb_set; + wire [4:0] l2_cpu2_rd_id_arb_set; + wire [2:0] l2_cpu2_rd_lrq_id_arb_set; + wire [7:0] l2_cpu2_rd_page_attr_arb_set; + wire l2_cpu2_rd_prfm_arb_set; + wire l2_cpu2_rd_priv_arb_set; + wire l2_cpu2_rd_replayed_arb_set; + wire [1:0] l2_cpu2_rd_shared_arb_set; + wire [6:0] l2_cpu2_rd_type_arb_set; + wire l2_cpu2_rd_va48_arb_set; + wire l2_cpu2_rd_vld_skid; + wire l2_cpu2_rd_way_arb_set; + wire l2_cpu2_rexfail; + wire [1:0] l2_cpu2_rstate; + wire l2_cpu2_rvalid; + wire [2:0] l2_cpu2_spec_bufid; + wire l2_cpu2_spec_valid; + wire [63:0] l2_cpu2_spr_rd_data; + wire l2_cpu2_tbw_dbl_ecc_err; + wire [63:0] l2_cpu2_tbw_desc_data; + wire l2_cpu2_tbw_desc_vld; + wire l2_cpu2_tbw_ext_err; + wire l2_cpu2_tbw_ext_err_type; + wire l2_cpu2_tlb_ccb_clken_c3; + wire l2_cpu2_tlb_ccb_req_c3; + wire l2_cpu2_tlb_sync_complete; + wire l2_cpu2_tlb_sync_done_q; + wire l2_cpu2_tlb_sync_req; + wire l2_cpu2_trq_haz_pending; + wire l2_cpu2_tw_ccb_resp; + wire [4:0] l2_cpu2_tw_ccb_resp_id; + wire l2_cpu2_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu2_wr_addr_arb_set; + wire l2_cpu2_wr_arb; + wire l2_cpu2_wr_arb_fast; + wire [2:0] l2_cpu2_wr_cache_attr_arb_set; + wire [11:0] l2_cpu2_wr_cl_id_arb_set; + wire l2_cpu2_wr_clean_evict_arb_set; + wire [143:0] l2_cpu2_wr_data; + wire l2_cpu2_wr_data_stall; + wire l2_cpu2_wr_data_vld_x1_q; + wire l2_cpu2_wr_dirty_arb_set; + wire [2:0] l2_cpu2_wr_elem_size_arb_set; + wire l2_cpu2_wr_err_arb_set; + wire l2_cpu2_wr_evict_x1_q; + wire l2_cpu2_wr_ex_fail; + wire l2_cpu2_wr_ex_resp; + wire [3:0] l2_cpu2_wr_id_arb_set; + wire l2_cpu2_wr_last_arb_set; + wire [7:0] l2_cpu2_wr_page_attr_arb_set; + wire [3:0] l2_cpu2_wr_partial_dw_arb_set; + wire l2_cpu2_wr_priv_arb_set; + wire [1:0] l2_cpu2_wr_shared_arb_set; + wire [2:0] l2_cpu2_wr_type_arb_set; + wire l2_cpu2_wr_vld_skid; + wire l2_cpu2_wr_way_arb_set; + wire l2_cpu2_wrq_almost_full; + wire [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; + wire l2_cpu2_wrq_haz_pending; + wire l2_cpu3_arb_thrshld_timeout_en; + wire l2_cpu3_barrier_done; + wire l2_cpu3_blk_non_evict_wr; + wire l2_cpu3_ccb_dbg_req_c3; + wire [48:0] l2_cpu3_ccb_req_addr_c3; + wire [4:0] l2_cpu3_ccb_req_id_c3; + wire [23:0] l2_cpu3_ccb_req_info_c3; + wire [8:0] l2_cpu3_ccb_req_type_c3; + wire l2_cpu3_cfg_ecc_en; + wire [2:0] l2_cpu3_dbufid_r1; + wire [129:0] l2_cpu3_ddata_r2; + wire l2_cpu3_ddlb_ecc_err_r3; + wire l2_cpu3_dext_err_r2; + wire l2_cpu3_dext_err_type_r2; + wire l2_cpu3_disable_clean_evict_opt; + wire l2_cpu3_dlast_r1; + wire l2_cpu3_dsngl_ecc_err_r3; + wire [3:0] l2_cpu3_dsq_clr_id_q; + wire l2_cpu3_dsq_clr_vld_q; + wire [3:0] l2_cpu3_dsq_rd_buf_id; + wire [15:0] l2_cpu3_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu3_dsq_rd_data_q; + wire l2_cpu3_dsq_rd_en; + wire l2_cpu3_dsq_rd_en_x2; + wire l2_cpu3_dt_pmu_evt_en; + wire l2_cpu3_dvalid_r1; + wire l2_cpu3_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; + wire l2_cpu3_flsh_if_rd_l4_dly; + wire l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; + wire l2_cpu3_flsh_ls_rd_l2_dly; + wire l2_cpu3_flsh_ls_rd_l4_dly; + wire l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; + wire l2_cpu3_flsh_ls_wr_l2_dly; + wire l2_cpu3_flsh_ls_wr_l4_dly; + wire l2_cpu3_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu3_ibufid_r1; + wire [15:0] l2_cpu3_ic_addr_arb_set; + wire l2_cpu3_ic_arb_fast; + wire l2_cpu3_ic_barrier_stall_q; + wire [43:18] l2_cpu3_ic_base; + wire [31:0] l2_cpu3_ic_data_arb_set; + wire [2:0] l2_cpu3_ic_elem_size_arb_set; + wire l2_cpu3_ic_excl_arb_set; + wire [2:0] l2_cpu3_ic_id_arb_set; + wire l2_cpu3_ic_ns_arb_set; + wire l2_cpu3_ic_vld_skid; + wire l2_cpu3_ic_write_arb_set; + wire [127:0] l2_cpu3_idata_r2; + wire l2_cpu3_idlb_ecc_err_r3; + wire l2_cpu3_idle_block_reqs_q; + wire l2_cpu3_idle_wakeup_q; + wire l2_cpu3_iext_err_r2; + wire l2_cpu3_iext_err_type_r2; + wire l2_cpu3_if_ccb_clken_c3; + wire l2_cpu3_if_ccb_req_c3; + wire l2_cpu3_if_ccb_resp; + wire [4:0] l2_cpu3_if_ccb_resp_id; + wire l2_cpu3_if_sync_done_q; + wire l2_cpu3_if_sync_req; + wire l2_cpu3_ifq_haz_pending; + wire l2_cpu3_isngl_ecc_err_r3; + wire l2_cpu3_ivalid_r1; + wire [1:0] l2_cpu3_l2_cache_size; + wire [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; + wire l2_cpu3_lrq_haz_pending; + wire l2_cpu3_ls_ccb_clken_c3; + wire l2_cpu3_ls_ccb_data_wr; + wire l2_cpu3_ls_ccb_req_c3; + wire l2_cpu3_ls_ccb_resp; + wire [4:0] l2_cpu3_ls_ccb_resp_id; + wire l2_cpu3_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu3_ls_rd_haz_id_arb_q; + wire l2_cpu3_ls_rd_haz_vld_arb_q; + wire l2_cpu3_ls_sync_req; + wire [4:0] l2_cpu3_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu3_ls_wr_data_w2a; + wire l2_cpu3_ls_wr_dirty_w2a; + wire l2_cpu3_ls_wr_err_w2a; + wire [2:0] l2_cpu3_ls_wr_haz_id_arb_q; + wire l2_cpu3_ls_wr_haz_vld_arb_q; + wire l2_cpu3_ls_wr_last_w2a; + wire l2_cpu3_ls_wr_req_w2a; + wire [2:0] l2_cpu3_ls_wr_type_w2a; + wire [12:0] l2_cpu3_mbist1_addr_b1; + wire l2_cpu3_mbist1_all_b1; + wire [3:0] l2_cpu3_mbist1_array_b1; + wire [7:0] l2_cpu3_mbist1_be_b1; + wire l2_cpu3_mbist1_en_b1; + wire l2_cpu3_mbist1_rd_en_b1; + wire l2_cpu3_mbist1_wr_en_b1; + wire l2_cpu3_no_intctrl; + wire l2_cpu3_pf_rd_vld_skid_popped; + wire l2_cpu3_pf_throttle_q; + wire [33:0] l2_cpu3_pmu_events; + wire [2:0] l2_cpu3_rbufid; + wire l2_cpu3_rd_aarch64_arb_set; + wire [44:0] l2_cpu3_rd_addr_arb_set; + wire l2_cpu3_rd_arb; + wire l2_cpu3_rd_arb_fast; + wire [15:8] l2_cpu3_rd_asid_arb_set; + wire l2_cpu3_rd_bypass_arb_set; + wire [2:0] l2_cpu3_rd_bypass_bufid_e5; + wire [2:0] l2_cpu3_rd_bypass_lrq_id_e5; + wire l2_cpu3_rd_bypass_req_can_e5; + wire l2_cpu3_rd_bypass_way_e5; + wire [2:0] l2_cpu3_rd_cache_attr_arb_set; + wire [2:0] l2_cpu3_rd_elem_size_arb_set; + wire l2_cpu3_rd_excl_arb_set; + wire [4:0] l2_cpu3_rd_id_arb_set; + wire [2:0] l2_cpu3_rd_lrq_id_arb_set; + wire [7:0] l2_cpu3_rd_page_attr_arb_set; + wire l2_cpu3_rd_prfm_arb_set; + wire l2_cpu3_rd_priv_arb_set; + wire l2_cpu3_rd_replayed_arb_set; + wire [1:0] l2_cpu3_rd_shared_arb_set; + wire [6:0] l2_cpu3_rd_type_arb_set; + wire l2_cpu3_rd_va48_arb_set; + wire l2_cpu3_rd_vld_skid; + wire l2_cpu3_rd_way_arb_set; + wire l2_cpu3_rexfail; + wire [1:0] l2_cpu3_rstate; + wire l2_cpu3_rvalid; + wire [2:0] l2_cpu3_spec_bufid; + wire l2_cpu3_spec_valid; + wire [63:0] l2_cpu3_spr_rd_data; + wire l2_cpu3_tbw_dbl_ecc_err; + wire [63:0] l2_cpu3_tbw_desc_data; + wire l2_cpu3_tbw_desc_vld; + wire l2_cpu3_tbw_ext_err; + wire l2_cpu3_tbw_ext_err_type; + wire l2_cpu3_tlb_ccb_clken_c3; + wire l2_cpu3_tlb_ccb_req_c3; + wire l2_cpu3_tlb_sync_complete; + wire l2_cpu3_tlb_sync_done_q; + wire l2_cpu3_tlb_sync_req; + wire l2_cpu3_trq_haz_pending; + wire l2_cpu3_tw_ccb_resp; + wire [4:0] l2_cpu3_tw_ccb_resp_id; + wire l2_cpu3_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu3_wr_addr_arb_set; + wire l2_cpu3_wr_arb; + wire l2_cpu3_wr_arb_fast; + wire [2:0] l2_cpu3_wr_cache_attr_arb_set; + wire [11:0] l2_cpu3_wr_cl_id_arb_set; + wire l2_cpu3_wr_clean_evict_arb_set; + wire [143:0] l2_cpu3_wr_data; + wire l2_cpu3_wr_data_stall; + wire l2_cpu3_wr_data_vld_x1_q; + wire l2_cpu3_wr_dirty_arb_set; + wire [2:0] l2_cpu3_wr_elem_size_arb_set; + wire l2_cpu3_wr_err_arb_set; + wire l2_cpu3_wr_evict_x1_q; + wire l2_cpu3_wr_ex_fail; + wire l2_cpu3_wr_ex_resp; + wire [3:0] l2_cpu3_wr_id_arb_set; + wire l2_cpu3_wr_last_arb_set; + wire [7:0] l2_cpu3_wr_page_attr_arb_set; + wire [3:0] l2_cpu3_wr_partial_dw_arb_set; + wire l2_cpu3_wr_priv_arb_set; + wire [1:0] l2_cpu3_wr_shared_arb_set; + wire [2:0] l2_cpu3_wr_type_arb_set; + wire l2_cpu3_wr_vld_skid; + wire l2_cpu3_wr_way_arb_set; + wire l2_cpu3_wrq_almost_full; + wire [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; + wire l2_cpu3_wrq_haz_pending; + wire [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu0_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu1_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu2_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu3_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu0_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu1_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu2_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu3_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; + wire ls_cpu0_clrexmon; + wire ls_cpu0_imp_abort_containable; + wire ls_cpu0_imp_abort_dec; + wire ls_cpu0_imp_abort_ecc; + wire ls_cpu0_imp_abort_slv; + wire ls_cpu0_raw_eae_nonsec; + wire ls_cpu0_raw_eae_secure; + wire ls_cpu1_clrexmon; + wire ls_cpu1_imp_abort_containable; + wire ls_cpu1_imp_abort_dec; + wire ls_cpu1_imp_abort_ecc; + wire ls_cpu1_imp_abort_slv; + wire ls_cpu1_raw_eae_nonsec; + wire ls_cpu1_raw_eae_secure; + wire ls_cpu2_clrexmon; + wire ls_cpu2_imp_abort_containable; + wire ls_cpu2_imp_abort_dec; + wire ls_cpu2_imp_abort_ecc; + wire ls_cpu2_imp_abort_slv; + wire ls_cpu2_raw_eae_nonsec; + wire ls_cpu2_raw_eae_secure; + wire ls_cpu3_clrexmon; + wire ls_cpu3_imp_abort_containable; + wire ls_cpu3_imp_abort_dec; + wire ls_cpu3_imp_abort_ecc; + wire ls_cpu3_imp_abort_slv; + wire ls_cpu3_raw_eae_nonsec; + wire ls_cpu3_raw_eae_secure; + wire ncommirq_cpu0_i; + wire ncommirq_cpu1_i; + wire ncommirq_cpu2_i; + wire ncommirq_cpu3_i; + wire ncorereset_cpu0_o; + wire ncorereset_cpu1_o; + wire ncorereset_cpu2_o; + wire ncorereset_cpu3_o; + wire ncpuporeset_cpu0_o; + wire ncpuporeset_cpu1_o; + wire ncpuporeset_cpu2_o; + wire ncpuporeset_cpu3_o; + wire niden_cpu0_o; + wire niden_cpu1_o; + wire niden_cpu2_o; + wire niden_cpu3_o; + wire nmbistreset_cpu0_o; + wire nmbistreset_cpu1_o; + wire nmbistreset_cpu2_o; + wire nmbistreset_cpu3_o; + wire npmuirq_cpu0_i; + wire npmuirq_cpu1_i; + wire npmuirq_cpu2_i; + wire npmuirq_cpu3_i; + wire pm_export_cpu0_i; + wire pm_export_cpu1_i; + wire pm_export_cpu2_i; + wire pm_export_cpu3_i; + wire [24:0] pmuevent_cpu0_i; + wire [24:0] pmuevent_cpu1_i; + wire [24:0] pmuevent_cpu2_i; + wire [24:0] pmuevent_cpu3_i; + wire [43:2] rvbaraddr_cpu0_o; + wire [43:2] rvbaraddr_cpu1_o; + wire [43:2] rvbaraddr_cpu2_o; + wire [43:2] rvbaraddr_cpu3_o; + wire spiden_cpu0_o; + wire spiden_cpu1_o; + wire spiden_cpu2_o; + wire spiden_cpu3_o; + wire spniden_cpu0_o; + wire spniden_cpu1_o; + wire spniden_cpu2_o; + wire spniden_cpu3_o; + wire syncreqm_cpu0_o; + wire syncreqm_cpu1_o; + wire syncreqm_cpu2_o; + wire syncreqm_cpu3_o; + wire [1:0] tm_cpu0_cnthctl_kernel; + wire [3:0] tm_cpu0_cntkctl_usr; + wire [1:0] tm_cpu1_cnthctl_kernel; + wire [3:0] tm_cpu1_cntkctl_usr; + wire [1:0] tm_cpu2_cnthctl_kernel; + wire [3:0] tm_cpu2_cntkctl_usr; + wire [1:0] tm_cpu3_cnthctl_kernel; + wire [3:0] tm_cpu3_cntkctl_usr; + wire [63:0] tsvalueb_cpu0_o; + wire [63:0] tsvalueb_cpu1_o; + wire [63:0] tsvalueb_cpu2_o; + wire [63:0] tsvalueb_cpu3_o; + wire vinithi_cpu0_o; + wire vinithi_cpu1_o; + wire vinithi_cpu2_o; + wire vinithi_cpu3_o; + + maia_cpu ucpu0( // outputs + .afreadym_cpu (afreadym_cpu0_i), + .atbytesm_cpu (atbytesm_cpu0_i[1:0]), + .atdatam_cpu (atdatam_cpu0_i[31:0]), + .atidm_cpu (atidm_cpu0_i[6:0]), + .atvalidm_cpu (atvalidm_cpu0_i), + .commrx_cpu (commrx_cpu0_i), + .commtx_cpu (commtx_cpu0_i), + .dbgack_cpu (dbgack_cpu0_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu0_i), + .dbgrstreq_cpu (dbgrstreq_cpu0_i), + .ds_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_flush (ds_cpu0_flush), + .ds_flush_type (ds_cpu0_flush_type[5:0]), + .ds_hcr_va (ds_cpu0_hcr_va), + .ds_hcr_vf (ds_cpu0_hcr_vf), + .ds_hcr_vi (ds_cpu0_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu0_reset_req), + .ds_sev_req (ds_cpu0_sev_req), + .ds_sevl_req (ds_cpu0_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_wfe_req (ds_cpu0_wfe_req), + .ds_wfi_req (ds_cpu0_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu0_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu0_clrexmon), + .ls_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu0_i), + .npmuirq_cpu (npmuirq_cpu0_i), + .pm_export_cpu (pm_export_cpu0_i), + .pmuevent_cpu (pmuevent_cpu0_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu0_o), + .afvalidm_cpu (afvalidm_cpu0_o), + .atclken_cpu (atclken_cpu0_o), + .atreadym_cpu (atreadym_cpu0_o), + .cfgend_cpu (cfgend_cpu0_o), + .cfgte_cpu (cfgte_cpu0_o), + .ck_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_event_reg (ck_cpu0_event_reg), + .ck_gclkt (ck_gclkt[0]), + .ck_wfe_ack (ck_cpu0_wfe_ack), + .ck_wfi_ack (ck_cpu0_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu0_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu0_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu0_o), + .cpuid (cpuid_cpu0_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu0_o), + .dbgen_cpu (dbgen_cpu0_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu0_o), + .dbgromaddr_cpu (dbgromaddr_cpu0_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu0_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu0_o), + .dftramhold_cpu (dftramhold_cpu0_o), + .dftrstdisable_cpu (dftrstdisable_cpu0_o), + .dftse_cpu (dftse_cpu0_o), + .dt_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu0_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[0]), + .ic_el_change_complete (ic_el_change_complete[0]), + .ic_hcr_change_complete (ic_hcr_change_complete[0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[0]), + .ic_ich_el2_tc (ic_ich_el2_tc[0]), + .ic_nfiq (ic_nfiq[0]), + .ic_nirq (ic_nirq[0]), + .ic_nsei (ic_nsei[0]), + .ic_nvfiq (ic_nvfiq[0]), + .ic_nvirq (ic_nvirq[0]), + .ic_nvsei (ic_nvsei[0]), + .ic_p_valid (ic_p_valid[0]), + .ic_sample_spr (ic_sample_spr[0]), + .ic_scr_change_complete (ic_scr_change_complete[0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[0]), + .ic_sra_el1s_en (ic_sra_el1s_en[0]), + .ic_sra_el2_en (ic_sra_el2_en[0]), + .ic_sra_el3_en (ic_sra_el3_en[0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[0]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu0_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu0_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu0_rexfail), + .l2_cpu_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu0_rvalid), + .l2_cpu_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu0_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu0_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu0_o), + .ncpuporeset_cpu (ncpuporeset_cpu0_o), + .niden_cpu (niden_cpu0_o), + .nmbistreset_cpu (nmbistreset_cpu0_o), + .rvbaraddr_cpu (rvbaraddr_cpu0_o[43:2]), + .spiden_cpu (spiden_cpu0_o), + .spniden_cpu (spniden_cpu0_o), + .syncreqm_cpu (syncreqm_cpu0_o), + .tm_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu0_o[63:0]), + .vinithi_cpu (vinithi_cpu0_o) + ); // ucpu0 + + maia_cpu ucpu1( // outputs + .afreadym_cpu (afreadym_cpu1_i), + .atbytesm_cpu (atbytesm_cpu1_i[1:0]), + .atdatam_cpu (atdatam_cpu1_i[31:0]), + .atidm_cpu (atidm_cpu1_i[6:0]), + .atvalidm_cpu (atvalidm_cpu1_i), + .commrx_cpu (commrx_cpu1_i), + .commtx_cpu (commtx_cpu1_i), + .dbgack_cpu (dbgack_cpu1_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu1_i), + .dbgrstreq_cpu (dbgrstreq_cpu1_i), + .ds_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_flush (ds_cpu1_flush), + .ds_flush_type (ds_cpu1_flush_type[5:0]), + .ds_hcr_va (ds_cpu1_hcr_va), + .ds_hcr_vf (ds_cpu1_hcr_vf), + .ds_hcr_vi (ds_cpu1_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu1_reset_req), + .ds_sev_req (ds_cpu1_sev_req), + .ds_sevl_req (ds_cpu1_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_wfe_req (ds_cpu1_wfe_req), + .ds_wfi_req (ds_cpu1_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu1_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu1_clrexmon), + .ls_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu1_i), + .npmuirq_cpu (npmuirq_cpu1_i), + .pm_export_cpu (pm_export_cpu1_i), + .pmuevent_cpu (pmuevent_cpu1_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu1_o), + .afvalidm_cpu (afvalidm_cpu1_o), + .atclken_cpu (atclken_cpu1_o), + .atreadym_cpu (atreadym_cpu1_o), + .cfgend_cpu (cfgend_cpu1_o), + .cfgte_cpu (cfgte_cpu1_o), + .ck_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_event_reg (ck_cpu1_event_reg), + .ck_gclkt (ck_gclkt[1]), + .ck_wfe_ack (ck_cpu1_wfe_ack), + .ck_wfi_ack (ck_cpu1_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu1_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu1_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu1_o), + .cpuid (cpuid_cpu1_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu1_o), + .dbgen_cpu (dbgen_cpu1_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu1_o), + .dbgromaddr_cpu (dbgromaddr_cpu1_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu1_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu1_o), + .dftramhold_cpu (dftramhold_cpu1_o), + .dftrstdisable_cpu (dftrstdisable_cpu1_o), + .dftse_cpu (dftse_cpu1_o), + .dt_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu1_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[1]), + .ic_el_change_complete (ic_el_change_complete[1]), + .ic_hcr_change_complete (ic_hcr_change_complete[1]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[1]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[1]), + .ic_ich_el2_tc (ic_ich_el2_tc[1]), + .ic_nfiq (ic_nfiq[1]), + .ic_nirq (ic_nirq[1]), + .ic_nsei (ic_nsei[1]), + .ic_nvfiq (ic_nvfiq[1]), + .ic_nvirq (ic_nvirq[1]), + .ic_nvsei (ic_nvsei[1]), + .ic_p_valid (ic_p_valid[1]), + .ic_sample_spr (ic_sample_spr[1]), + .ic_scr_change_complete (ic_scr_change_complete[1]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[1]), + .ic_sra_el1s_en (ic_sra_el1s_en[1]), + .ic_sra_el2_en (ic_sra_el2_en[1]), + .ic_sra_el3_en (ic_sra_el3_en[1]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[1]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[1]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[1]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[1]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu1_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu1_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu1_rexfail), + .l2_cpu_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu1_rvalid), + .l2_cpu_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu1_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu1_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu1_o), + .ncpuporeset_cpu (ncpuporeset_cpu1_o), + .niden_cpu (niden_cpu1_o), + .nmbistreset_cpu (nmbistreset_cpu1_o), + .rvbaraddr_cpu (rvbaraddr_cpu1_o[43:2]), + .spiden_cpu (spiden_cpu1_o), + .spniden_cpu (spniden_cpu1_o), + .syncreqm_cpu (syncreqm_cpu1_o), + .tm_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu1_o[63:0]), + .vinithi_cpu (vinithi_cpu1_o) + ); // ucpu1 + + maia_cpu ucpu2( // outputs + .afreadym_cpu (afreadym_cpu2_i), + .atbytesm_cpu (atbytesm_cpu2_i[1:0]), + .atdatam_cpu (atdatam_cpu2_i[31:0]), + .atidm_cpu (atidm_cpu2_i[6:0]), + .atvalidm_cpu (atvalidm_cpu2_i), + .commrx_cpu (commrx_cpu2_i), + .commtx_cpu (commtx_cpu2_i), + .dbgack_cpu (dbgack_cpu2_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu2_i), + .dbgrstreq_cpu (dbgrstreq_cpu2_i), + .ds_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_flush (ds_cpu2_flush), + .ds_flush_type (ds_cpu2_flush_type[5:0]), + .ds_hcr_va (ds_cpu2_hcr_va), + .ds_hcr_vf (ds_cpu2_hcr_vf), + .ds_hcr_vi (ds_cpu2_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu2_reset_req), + .ds_sev_req (ds_cpu2_sev_req), + .ds_sevl_req (ds_cpu2_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_wfe_req (ds_cpu2_wfe_req), + .ds_wfi_req (ds_cpu2_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu2_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu2_clrexmon), + .ls_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu2_i), + .npmuirq_cpu (npmuirq_cpu2_i), + .pm_export_cpu (pm_export_cpu2_i), + .pmuevent_cpu (pmuevent_cpu2_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu2_o), + .afvalidm_cpu (afvalidm_cpu2_o), + .atclken_cpu (atclken_cpu2_o), + .atreadym_cpu (atreadym_cpu2_o), + .cfgend_cpu (cfgend_cpu2_o), + .cfgte_cpu (cfgte_cpu2_o), + .ck_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_event_reg (ck_cpu2_event_reg), + .ck_gclkt (ck_gclkt[2]), + .ck_wfe_ack (ck_cpu2_wfe_ack), + .ck_wfi_ack (ck_cpu2_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu2_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu2_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu2_o), + .cpuid (cpuid_cpu2_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu2_o), + .dbgen_cpu (dbgen_cpu2_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu2_o), + .dbgromaddr_cpu (dbgromaddr_cpu2_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu2_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu2_o), + .dftramhold_cpu (dftramhold_cpu2_o), + .dftrstdisable_cpu (dftrstdisable_cpu2_o), + .dftse_cpu (dftse_cpu2_o), + .dt_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu2_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[2]), + .ic_el_change_complete (ic_el_change_complete[2]), + .ic_hcr_change_complete (ic_hcr_change_complete[2]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[2]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[2]), + .ic_ich_el2_tc (ic_ich_el2_tc[2]), + .ic_nfiq (ic_nfiq[2]), + .ic_nirq (ic_nirq[2]), + .ic_nsei (ic_nsei[2]), + .ic_nvfiq (ic_nvfiq[2]), + .ic_nvirq (ic_nvirq[2]), + .ic_nvsei (ic_nvsei[2]), + .ic_p_valid (ic_p_valid[2]), + .ic_sample_spr (ic_sample_spr[2]), + .ic_scr_change_complete (ic_scr_change_complete[2]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[2]), + .ic_sra_el1s_en (ic_sra_el1s_en[2]), + .ic_sra_el2_en (ic_sra_el2_en[2]), + .ic_sra_el3_en (ic_sra_el3_en[2]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[2]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[2]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[2]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[2]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu2_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu2_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu2_rexfail), + .l2_cpu_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu2_rvalid), + .l2_cpu_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu2_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu2_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu2_o), + .ncpuporeset_cpu (ncpuporeset_cpu2_o), + .niden_cpu (niden_cpu2_o), + .nmbistreset_cpu (nmbistreset_cpu2_o), + .rvbaraddr_cpu (rvbaraddr_cpu2_o[43:2]), + .spiden_cpu (spiden_cpu2_o), + .spniden_cpu (spniden_cpu2_o), + .syncreqm_cpu (syncreqm_cpu2_o), + .tm_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu2_o[63:0]), + .vinithi_cpu (vinithi_cpu2_o) + ); // ucpu2 + + maia_cpu ucpu3( // outputs + .afreadym_cpu (afreadym_cpu3_i), + .atbytesm_cpu (atbytesm_cpu3_i[1:0]), + .atdatam_cpu (atdatam_cpu3_i[31:0]), + .atidm_cpu (atidm_cpu3_i[6:0]), + .atvalidm_cpu (atvalidm_cpu3_i), + .commrx_cpu (commrx_cpu3_i), + .commtx_cpu (commtx_cpu3_i), + .dbgack_cpu (dbgack_cpu3_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu (dbgrstreq_cpu3_i), + .ds_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_flush (ds_cpu3_flush), + .ds_flush_type (ds_cpu3_flush_type[5:0]), + .ds_hcr_va (ds_cpu3_hcr_va), + .ds_hcr_vf (ds_cpu3_hcr_vf), + .ds_hcr_vi (ds_cpu3_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_ic_scr_change (ds_cpu3_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu3_reset_req), + .ds_sev_req (ds_cpu3_sev_req), + .ds_sevl_req (ds_cpu3_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_wfe_req (ds_cpu3_wfe_req), + .ds_wfi_req (ds_cpu3_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu3_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu3_clrexmon), + .ls_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu3_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu3_i), + .npmuirq_cpu (npmuirq_cpu3_i), + .pm_export_cpu (pm_export_cpu3_i), + .pmuevent_cpu (pmuevent_cpu3_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu3_o), + .afvalidm_cpu (afvalidm_cpu3_o), + .atclken_cpu (atclken_cpu3_o), + .atreadym_cpu (atreadym_cpu3_o), + .cfgend_cpu (cfgend_cpu3_o), + .cfgte_cpu (cfgte_cpu3_o), + .ck_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_event_reg (ck_cpu3_event_reg), + .ck_gclkt (ck_gclkt[3]), + .ck_wfe_ack (ck_cpu3_wfe_ack), + .ck_wfi_ack (ck_cpu3_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu3_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu3_o), + .cpuid (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu3_o), + .dbgen_cpu (dbgen_cpu3_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu3_o), + .dbgromaddr_cpu (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu3_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu3_o), + .dftramhold_cpu (dftramhold_cpu3_o), + .dftrstdisable_cpu (dftrstdisable_cpu3_o), + .dftse_cpu (dftse_cpu3_o), + .dt_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu3_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[3]), + .ic_el_change_complete (ic_el_change_complete[3]), + .ic_hcr_change_complete (ic_hcr_change_complete[3]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[3]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[3]), + .ic_ich_el2_tc (ic_ich_el2_tc[3]), + .ic_nfiq (ic_nfiq[3]), + .ic_nirq (ic_nirq[3]), + .ic_nsei (ic_nsei[3]), + .ic_nvfiq (ic_nvfiq[3]), + .ic_nvirq (ic_nvirq[3]), + .ic_nvsei (ic_nvsei[3]), + .ic_p_valid (ic_p_valid[3]), + .ic_sample_spr (ic_sample_spr[3]), + .ic_scr_change_complete (ic_scr_change_complete[3]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[3]), + .ic_sra_el1s_en (ic_sra_el1s_en[3]), + .ic_sra_el2_en (ic_sra_el2_en[3]), + .ic_sra_el3_en (ic_sra_el3_en[3]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[3]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[3]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[3]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[3]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu3_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu3_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu3_rexfail), + .l2_cpu_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu3_rvalid), + .l2_cpu_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu3_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu3_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu3_o), + .ncpuporeset_cpu (ncpuporeset_cpu3_o), + .niden_cpu (niden_cpu3_o), + .nmbistreset_cpu (nmbistreset_cpu3_o), + .rvbaraddr_cpu (rvbaraddr_cpu3_o[43:2]), + .spiden_cpu (spiden_cpu3_o), + .spniden_cpu (spniden_cpu3_o), + .syncreqm_cpu (syncreqm_cpu3_o), + .tm_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu3_o[63:0]), + .vinithi_cpu (vinithi_cpu3_o) + ); // ucpu3 + + maia_noncpu_feq20_s unoncpu( // outputs + .AFREADYM0 (AFREADYM0), + .AFREADYM1 (AFREADYM1), + .AFREADYM2 (AFREADYM2), + .AFREADYM3 (AFREADYM3), + .ARREADYS (ARREADYS), + .ATBYTESM0 (ATBYTESM0[1:0]), + .ATBYTESM1 (ATBYTESM1[1:0]), + .ATBYTESM2 (ATBYTESM2[1:0]), + .ATBYTESM3 (ATBYTESM3[1:0]), + .ATDATAM0 (ATDATAM0[31:0]), + .ATDATAM1 (ATDATAM1[31:0]), + .ATDATAM2 (ATDATAM2[31:0]), + .ATDATAM3 (ATDATAM3[31:0]), + .ATIDM0 (ATIDM0[6:0]), + .ATIDM1 (ATIDM1[6:0]), + .ATIDM2 (ATIDM2[6:0]), + .ATIDM3 (ATIDM3[6:0]), + .ATVALIDM0 (ATVALIDM0), + .ATVALIDM1 (ATVALIDM1), + .ATVALIDM2 (ATVALIDM2), + .ATVALIDM3 (ATVALIDM3), + .AWREADYS (AWREADYS), + .BIDS (BIDS[4:0]), + .BRESPS (BRESPS[1:0]), + .BVALIDS (BVALIDS), + .CLREXMONACK (CLREXMONACK), + .COMMRX (COMMRX[`MAIA_CN:0]), + .COMMTX (COMMTX[`MAIA_CN:0]), + .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), + .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), + .CPUQDENY (CPUQDENY[`MAIA_CN:0]), + .CTICHINACK (CTICHINACK[3:0]), + .CTICHOUT (CTICHOUT[3:0]), + .CTIIRQ (CTIIRQ[`MAIA_CN:0]), + .DBGACK (DBGACK[`MAIA_CN:0]), + .DBGNOPWRDWN (DBGNOPWRDWN[`MAIA_CN:0]), + .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), + .DBGRSTREQ (DBGRSTREQ[`MAIA_CN:0]), + .EVENTO (EVENTO), + .ICCTDATA (ICCTDATA[15:0]), + .ICCTID (ICCTID[1:0]), + .ICCTLAST (ICCTLAST), + .ICCTVALID (ICCTVALID), + .ICDTREADY (ICDTREADY), + .L2FLUSHDONE (L2FLUSHDONE), + .L2QACCEPTn (L2QACCEPTn), + .L2QACTIVE (L2QACTIVE), + .L2QDENY (L2QDENY), + .PMUEVENT0 (PMUEVENT0[24:0]), + .PMUEVENT1 (PMUEVENT1[24:0]), + .PMUEVENT2 (PMUEVENT2[24:0]), + .PMUEVENT3 (PMUEVENT3[24:0]), + .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), + .PRDATADBG (PRDATADBG[31:0]), + .PREADYDBG (PREADYDBG), + .PSLVERRDBG (PSLVERRDBG), + .RDATAS (RDATAS[127:0]), + .REQMEMATTR (REQMEMATTR[7:0]), + .RIDS (RIDS[4:0]), + .RLASTS (RLASTS), + .RRESPS (RRESPS[1:0]), + .RVALIDS (RVALIDS), + .RXDATLCRDV (RXDATLCRDV), + .RXLINKACTIVEACK (RXLINKACTIVEACK), + .RXRSPLCRDV (RXRSPLCRDV), + .RXSNPLCRDV (RXSNPLCRDV), + .SMPEN (SMPEN[`MAIA_CN:0]), + .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), + .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), + .STANDBYWFIL2 (STANDBYWFIL2), + .TXDATFLIT (TXDATFLIT[193:0]), + .TXDATFLITPEND (TXDATFLITPEND), + .TXDATFLITV (TXDATFLITV), + .TXLINKACTIVEREQ (TXLINKACTIVEREQ), + .TXREQFLIT (TXREQFLIT[99:0]), + .TXREQFLITPEND (TXREQFLITPEND), + .TXREQFLITV (TXREQFLITV), + .TXRSPFLIT (TXRSPFLIT[44:0]), + .TXRSPFLITPEND (TXRSPFLITPEND), + .TXRSPFLITV (TXRSPFLITV), + .TXSACTIVE (TXSACTIVE), + .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), + .WREADYS (WREADYS), + .aa64naa32_cpu0_o (aa64naa32_cpu0_o), + .aa64naa32_cpu1_o (aa64naa32_cpu1_o), + .aa64naa32_cpu2_o (aa64naa32_cpu2_o), + .aa64naa32_cpu3_o (aa64naa32_cpu3_o), + .afvalidm_cpu0_o (afvalidm_cpu0_o), + .afvalidm_cpu1_o (afvalidm_cpu1_o), + .afvalidm_cpu2_o (afvalidm_cpu2_o), + .afvalidm_cpu3_o (afvalidm_cpu3_o), + .atclken_cpu0_o (atclken_cpu0_o), + .atclken_cpu1_o (atclken_cpu1_o), + .atclken_cpu2_o (atclken_cpu2_o), + .atclken_cpu3_o (atclken_cpu3_o), + .atreadym_cpu0_o (atreadym_cpu0_o), + .atreadym_cpu1_o (atreadym_cpu1_o), + .atreadym_cpu2_o (atreadym_cpu2_o), + .atreadym_cpu3_o (atreadym_cpu3_o), + .cfgend_cpu0_o (cfgend_cpu0_o), + .cfgend_cpu1_o (cfgend_cpu1_o), + .cfgend_cpu2_o (cfgend_cpu2_o), + .cfgend_cpu3_o (cfgend_cpu3_o), + .cfgte_cpu0_o (cfgte_cpu0_o), + .cfgte_cpu1_o (cfgte_cpu1_o), + .cfgte_cpu2_o (cfgte_cpu2_o), + .cfgte_cpu3_o (cfgte_cpu3_o), + .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_cpu0_event_reg (ck_cpu0_event_reg), + .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), + .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), + .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_cpu1_event_reg (ck_cpu1_event_reg), + .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), + .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), + .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_cpu2_event_reg (ck_cpu2_event_reg), + .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), + .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), + .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_cpu3_event_reg (ck_cpu3_event_reg), + .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), + .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), + .ck_gclkt (ck_gclkt[`MAIA_CN:0]), + .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), + .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), + .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), + .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), + .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), + .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), + .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), + .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), + .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), + .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), + .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), + .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), + .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), + .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), + .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu0_o (cryptodisable_cpu0_o), + .cryptodisable_cpu1_o (cryptodisable_cpu1_o), + .cryptodisable_cpu2_o (cryptodisable_cpu2_o), + .cryptodisable_cpu3_o (cryptodisable_cpu3_o), + .dbgen_cpu0_o (dbgen_cpu0_o), + .dbgen_cpu1_o (dbgen_cpu1_o), + .dbgen_cpu2_o (dbgen_cpu2_o), + .dbgen_cpu3_o (dbgen_cpu3_o), + .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), + .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), + .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), + .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), + .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), + .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), + .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), + .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), + .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), + .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), + .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), + .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), + .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), + .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), + .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), + .dftramhold_cpu0_o (dftramhold_cpu0_o), + .dftramhold_cpu1_o (dftramhold_cpu1_o), + .dftramhold_cpu2_o (dftramhold_cpu2_o), + .dftramhold_cpu3_o (dftramhold_cpu3_o), + .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), + .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), + .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), + .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), + .dftse_cpu0_o (dftse_cpu0_o), + .dftse_cpu1_o (dftse_cpu1_o), + .dftse_cpu2_o (dftse_cpu2_o), + .dftse_cpu3_o (dftse_cpu3_o), + .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .giccdisable_cpu0_o (giccdisable_cpu0_o), + .giccdisable_cpu1_o (giccdisable_cpu1_o), + .giccdisable_cpu2_o (giccdisable_cpu2_o), + .giccdisable_cpu3_o (giccdisable_cpu3_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[`MAIA_CN:0]), + .ic_el_change_complete (ic_el_change_complete[`MAIA_CN:0]), + .ic_hcr_change_complete (ic_hcr_change_complete[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq[`MAIA_CN:0]), + .ic_nirq (ic_nirq[`MAIA_CN:0]), + .ic_nsei (ic_nsei[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei[`MAIA_CN:0]), + .ic_p_valid (ic_p_valid[`MAIA_CN:0]), + .ic_sample_spr (ic_sample_spr[`MAIA_CN:0]), + .ic_scr_change_complete (ic_scr_change_complete[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[`MAIA_CN:0]), + .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu0_barrier_done (l2_cpu0_barrier_done), + .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), + .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), + .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu0_rd_arb (l2_cpu0_rd_arb), + .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu0_rexfail (l2_cpu0_rexfail), + .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu0_rvalid (l2_cpu0_rvalid), + .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu0_spec_valid (l2_cpu0_spec_valid), + .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu0_wr_arb (l2_cpu0_wr_arb), + .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu1_barrier_done (l2_cpu1_barrier_done), + .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), + .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), + .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu1_rd_arb (l2_cpu1_rd_arb), + .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu1_rexfail (l2_cpu1_rexfail), + .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu1_rvalid (l2_cpu1_rvalid), + .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu1_spec_valid (l2_cpu1_spec_valid), + .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu1_wr_arb (l2_cpu1_wr_arb), + .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu2_barrier_done (l2_cpu2_barrier_done), + .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), + .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), + .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu2_rd_arb (l2_cpu2_rd_arb), + .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu2_rexfail (l2_cpu2_rexfail), + .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu2_rvalid (l2_cpu2_rvalid), + .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu2_spec_valid (l2_cpu2_spec_valid), + .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu2_wr_arb (l2_cpu2_wr_arb), + .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu3_barrier_done (l2_cpu3_barrier_done), + .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), + .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), + .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu3_rd_arb (l2_cpu3_rd_arb), + .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu3_rexfail (l2_cpu3_rexfail), + .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu3_rvalid (l2_cpu3_rvalid), + .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu3_spec_valid (l2_cpu3_spec_valid), + .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu3_wr_arb (l2_cpu3_wr_arb), + .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), + .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), + .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), + .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), + .nCOMMIRQ (nCOMMIRQ[`MAIA_CN:0]), + .nEXTERRIRQ (nEXTERRIRQ), + .nINTERRIRQ (nINTERRIRQ), + .nPMUIRQ (nPMUIRQ[`MAIA_CN:0]), + .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), + .ncorereset_cpu0_o (ncorereset_cpu0_o), + .ncorereset_cpu1_o (ncorereset_cpu1_o), + .ncorereset_cpu2_o (ncorereset_cpu2_o), + .ncorereset_cpu3_o (ncorereset_cpu3_o), + .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), + .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), + .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), + .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), + .niden_cpu0_o (niden_cpu0_o), + .niden_cpu1_o (niden_cpu1_o), + .niden_cpu2_o (niden_cpu2_o), + .niden_cpu3_o (niden_cpu3_o), + .nmbistreset_cpu0_o (nmbistreset_cpu0_o), + .nmbistreset_cpu1_o (nmbistreset_cpu1_o), + .nmbistreset_cpu2_o (nmbistreset_cpu2_o), + .nmbistreset_cpu3_o (nmbistreset_cpu3_o), + .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), + .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), + .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), + .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), + .spiden_cpu0_o (spiden_cpu0_o), + .spiden_cpu1_o (spiden_cpu1_o), + .spiden_cpu2_o (spiden_cpu2_o), + .spiden_cpu3_o (spiden_cpu3_o), + .spniden_cpu0_o (spniden_cpu0_o), + .spniden_cpu1_o (spniden_cpu1_o), + .spniden_cpu2_o (spniden_cpu2_o), + .spniden_cpu3_o (spniden_cpu3_o), + .syncreqm_cpu0_o (syncreqm_cpu0_o), + .syncreqm_cpu1_o (syncreqm_cpu1_o), + .syncreqm_cpu2_o (syncreqm_cpu2_o), + .syncreqm_cpu3_o (syncreqm_cpu3_o), + .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), + .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), + .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), + .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), + .vinithi_cpu0_o (vinithi_cpu0_o), + .vinithi_cpu1_o (vinithi_cpu1_o), + .vinithi_cpu2_o (vinithi_cpu2_o), + .vinithi_cpu3_o (vinithi_cpu3_o), + + // inputs + .AA64nAA32 (AA64nAA32[`MAIA_CN:0]), + .ACLKENS (ACLKENS), + .AFVALIDM0 (AFVALIDM0), + .AFVALIDM1 (AFVALIDM1), + .AFVALIDM2 (AFVALIDM2), + .AFVALIDM3 (AFVALIDM3), + .AINACTS (AINACTS), + .ARADDRS (ARADDRS[43:0]), + .ARCACHES (ARCACHES[3:0]), + .ARIDS (ARIDS[4:0]), + .ARLENS (ARLENS[7:0]), + .ARPROTS (ARPROTS[2:0]), + .ARUSERS (ARUSERS[1:0]), + .ARVALIDS (ARVALIDS), + .ATCLKEN (ATCLKEN), + .ATREADYM0 (ATREADYM0), + .ATREADYM1 (ATREADYM1), + .ATREADYM2 (ATREADYM2), + .ATREADYM3 (ATREADYM3), + .AWADDRS (AWADDRS[43:0]), + .AWCACHES (AWCACHES[3:0]), + .AWIDS (AWIDS[4:0]), + .AWLENS (AWLENS[7:0]), + .AWPROTS (AWPROTS[2:0]), + .AWUSERS (AWUSERS[1:0]), + .AWVALIDS (AWVALIDS), + .BREADYS (BREADYS), + .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), + .BROADCASTINNER (BROADCASTINNER), + .BROADCASTOUTER (BROADCASTOUTER), + .CFGEND (CFGEND[`MAIA_CN:0]), + .CFGTE (CFGTE[`MAIA_CN:0]), + .CIHSBYPASS (CIHSBYPASS[3:0]), + .CISBYPASS (CISBYPASS), + .CLK (CLK), + .CLKEN (CLKEN), + .CLREXMONREQ (CLREXMONREQ), + .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), + .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), + .CNTCLKEN (CNTCLKEN), + .CNTVALUEB (CNTVALUEB[63:0]), + .CP15SDISABLE (CP15SDISABLE[`MAIA_CN:0]), + .CPUQREQn (CPUQREQn[`MAIA_CN:0]), + .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), + .CTICHIN (CTICHIN[3:0]), + .CTICHOUTACK (CTICHOUTACK[3:0]), + .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), + .DBGEN (DBGEN[`MAIA_CN:0]), + .DBGL1RSTDISABLE (DBGL1RSTDISABLE), + .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), + .DBGROMADDR (DBGROMADDR[43:12]), + .DBGROMADDRV (DBGROMADDRV), + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTCRCLKDISABLE (DFTCRCLKDISABLE[`MAIA_CN:0]), + .DFTL2CLKDISABLE (DFTL2CLKDISABLE), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .EDBGRQ (EDBGRQ[`MAIA_CN:0]), + .EVENTI (EVENTI), + .GICCDISABLE (GICCDISABLE), + .ICCTREADY (ICCTREADY), + .ICDTDATA (ICDTDATA[15:0]), + .ICDTDEST (ICDTDEST[1:0]), + .ICDTLAST (ICDTLAST), + .ICDTVALID (ICDTVALID), + .L2FLUSHREQ (L2FLUSHREQ), + .L2QREQn (L2QREQn), + .L2RSTDISABLE (L2RSTDISABLE), + .MBISTREQ (MBISTREQ), + .NIDEN (NIDEN[`MAIA_CN:0]), + .NODEID (NODEID[6:0]), + .PADDRDBG (PADDRDBG[21:2]), + .PADDRDBG31 (PADDRDBG31), + .PCLKDBG (PCLKDBG), + .PCLKENDBG (PCLKENDBG), + .PENABLEDBG (PENABLEDBG), + .PERIPHBASE (PERIPHBASE[43:18]), + .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), + .PSELDBG (PSELDBG), + .PWDATADBG (PWDATADBG[31:0]), + .PWRITEDBG (PWRITEDBG), + .RREADYS (RREADYS), + .RVBARADDR0 (RVBARADDR0[43:2]), + .RVBARADDR1 (RVBARADDR1[43:2]), + .RVBARADDR2 (RVBARADDR2[43:2]), + .RVBARADDR3 (RVBARADDR3[43:2]), + .RXDATFLIT (RXDATFLIT[193:0]), + .RXDATFLITPEND (RXDATFLITPEND), + .RXDATFLITV (RXDATFLITV), + .RXLINKACTIVEREQ (RXLINKACTIVEREQ), + .RXRSPFLIT (RXRSPFLIT[44:0]), + .RXRSPFLITPEND (RXRSPFLITPEND), + .RXRSPFLITV (RXRSPFLITV), + .RXSACTIVE (RXSACTIVE), + .RXSNPFLIT (RXSNPFLIT[64:0]), + .RXSNPFLITPEND (RXSNPFLITPEND), + .RXSNPFLITV (RXSNPFLITV), + .SAMADDRMAP0 (SAMADDRMAP0[1:0]), + .SAMADDRMAP1 (SAMADDRMAP1[1:0]), + .SAMADDRMAP10 (SAMADDRMAP10[1:0]), + .SAMADDRMAP11 (SAMADDRMAP11[1:0]), + .SAMADDRMAP12 (SAMADDRMAP12[1:0]), + .SAMADDRMAP13 (SAMADDRMAP13[1:0]), + .SAMADDRMAP14 (SAMADDRMAP14[1:0]), + .SAMADDRMAP15 (SAMADDRMAP15[1:0]), + .SAMADDRMAP16 (SAMADDRMAP16[1:0]), + .SAMADDRMAP17 (SAMADDRMAP17[1:0]), + .SAMADDRMAP18 (SAMADDRMAP18[1:0]), + .SAMADDRMAP19 (SAMADDRMAP19[1:0]), + .SAMADDRMAP2 (SAMADDRMAP2[1:0]), + .SAMADDRMAP3 (SAMADDRMAP3[1:0]), + .SAMADDRMAP4 (SAMADDRMAP4[1:0]), + .SAMADDRMAP5 (SAMADDRMAP5[1:0]), + .SAMADDRMAP6 (SAMADDRMAP6[1:0]), + .SAMADDRMAP7 (SAMADDRMAP7[1:0]), + .SAMADDRMAP8 (SAMADDRMAP8[1:0]), + .SAMADDRMAP9 (SAMADDRMAP9[1:0]), + .SAMHNF0NODEID (SAMHNF0NODEID[6:0]), + .SAMHNF1NODEID (SAMHNF1NODEID[6:0]), + .SAMHNF2NODEID (SAMHNF2NODEID[6:0]), + .SAMHNF3NODEID (SAMHNF3NODEID[6:0]), + .SAMHNF4NODEID (SAMHNF4NODEID[6:0]), + .SAMHNF5NODEID (SAMHNF5NODEID[6:0]), + .SAMHNF6NODEID (SAMHNF6NODEID[6:0]), + .SAMHNF7NODEID (SAMHNF7NODEID[6:0]), + .SAMHNFMODE (SAMHNFMODE[2:0]), + .SAMHNI0NODEID (SAMHNI0NODEID[6:0]), + .SAMHNI1NODEID (SAMHNI1NODEID[6:0]), + .SAMMNBASE (SAMMNBASE[43:24]), + .SAMMNNODEID (SAMMNNODEID[6:0]), + .SCLKEN (SCLKEN), + .SINACT (SINACT), + .SPIDEN (SPIDEN[`MAIA_CN:0]), + .SPNIDEN (SPNIDEN[`MAIA_CN:0]), + .SYNCREQM0 (SYNCREQM0), + .SYNCREQM1 (SYNCREQM1), + .SYNCREQM2 (SYNCREQM2), + .SYNCREQM3 (SYNCREQM3), + .SYSBARDISABLE (SYSBARDISABLE), + .TSVALUEB (TSVALUEB[63:0]), + .TXDATLCRDV (TXDATLCRDV), + .TXLINKACTIVEACK (TXLINKACTIVEACK), + .TXREQLCRDV (TXREQLCRDV), + .TXRSPLCRDV (TXRSPLCRDV), + .VINITHI (VINITHI[`MAIA_CN:0]), + .WDATAS (WDATAS[127:0]), + .WLASTS (WLASTS), + .WSTRBS (WSTRBS[15:0]), + .WVALIDS (WVALIDS), + .afreadym_cpu0_i (afreadym_cpu0_i), + .afreadym_cpu1_i (afreadym_cpu1_i), + .afreadym_cpu2_i (afreadym_cpu2_i), + .afreadym_cpu3_i (afreadym_cpu3_i), + .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), + .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), + .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), + .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), + .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), + .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), + .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), + .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), + .atidm_cpu0_i (atidm_cpu0_i[6:0]), + .atidm_cpu1_i (atidm_cpu1_i[6:0]), + .atidm_cpu2_i (atidm_cpu2_i[6:0]), + .atidm_cpu3_i (atidm_cpu3_i[6:0]), + .atvalidm_cpu0_i (atvalidm_cpu0_i), + .atvalidm_cpu1_i (atvalidm_cpu1_i), + .atvalidm_cpu2_i (atvalidm_cpu2_i), + .atvalidm_cpu3_i (atvalidm_cpu3_i), + .commrx_cpu0_i (commrx_cpu0_i), + .commrx_cpu1_i (commrx_cpu1_i), + .commrx_cpu2_i (commrx_cpu2_i), + .commrx_cpu3_i (commrx_cpu3_i), + .commtx_cpu0_i (commtx_cpu0_i), + .commtx_cpu1_i (commtx_cpu1_i), + .commtx_cpu2_i (commtx_cpu2_i), + .commtx_cpu3_i (commtx_cpu3_i), + .dbgack_cpu0_i (dbgack_cpu0_i), + .dbgack_cpu1_i (dbgack_cpu1_i), + .dbgack_cpu2_i (dbgack_cpu2_i), + .dbgack_cpu3_i (dbgack_cpu3_i), + .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), + .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), + .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), + .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), + .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), + .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), + .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), + .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_cpu0_flush (ds_cpu0_flush), + .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), + .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), + .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu0_reset_req (ds_cpu0_reset_req), + .ds_cpu0_sev_req (ds_cpu0_sev_req), + .ds_cpu0_sevl_req (ds_cpu0_sevl_req), + .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_cpu0_wfe_req (ds_cpu0_wfe_req), + .ds_cpu0_wfi_req (ds_cpu0_wfi_req), + .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_cpu1_flush (ds_cpu1_flush), + .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), + .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), + .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu1_reset_req (ds_cpu1_reset_req), + .ds_cpu1_sev_req (ds_cpu1_sev_req), + .ds_cpu1_sevl_req (ds_cpu1_sevl_req), + .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_cpu1_wfe_req (ds_cpu1_wfe_req), + .ds_cpu1_wfi_req (ds_cpu1_wfi_req), + .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_cpu2_flush (ds_cpu2_flush), + .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), + .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), + .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu2_reset_req (ds_cpu2_reset_req), + .ds_cpu2_sev_req (ds_cpu2_sev_req), + .ds_cpu2_sevl_req (ds_cpu2_sevl_req), + .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_cpu2_wfe_req (ds_cpu2_wfe_req), + .ds_cpu2_wfi_req (ds_cpu2_wfi_req), + .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_cpu3_flush (ds_cpu3_flush), + .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), + .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), + .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), + .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_cpu3_reset_req (ds_cpu3_reset_req), + .ds_cpu3_sev_req (ds_cpu3_sev_req), + .ds_cpu3_sevl_req (ds_cpu3_sevl_req), + .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_cpu3_wfe_req (ds_cpu3_wfe_req), + .ds_cpu3_wfi_req (ds_cpu3_wfi_req), + .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .etclken_cpu0_i (etclken_cpu0_i), + .etclken_cpu1_i (etclken_cpu1_i), + .etclken_cpu2_i (etclken_cpu2_i), + .etclken_cpu3_i (etclken_cpu3_i), + .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .ls_cpu0_clrexmon (ls_cpu0_clrexmon), + .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ls_cpu1_clrexmon (ls_cpu1_clrexmon), + .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ls_cpu2_clrexmon (ls_cpu2_clrexmon), + .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ls_cpu3_clrexmon (ls_cpu3_clrexmon), + .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), + .nCORERESET (nCORERESET[`MAIA_CN:0]), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nFIQ (nFIQ[`MAIA_CN:0]), + .nIRQ (nIRQ[`MAIA_CN:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .nPRESETDBG (nPRESETDBG), + .nREI (nREI[`MAIA_CN:0]), + .nSEI (nSEI[`MAIA_CN:0]), + .nVFIQ (nVFIQ[`MAIA_CN:0]), + .nVIRQ (nVIRQ[`MAIA_CN:0]), + .nVSEI (nVSEI[`MAIA_CN:0]), + .ncommirq_cpu0_i (ncommirq_cpu0_i), + .ncommirq_cpu1_i (ncommirq_cpu1_i), + .ncommirq_cpu2_i (ncommirq_cpu2_i), + .ncommirq_cpu3_i (ncommirq_cpu3_i), + .npmuirq_cpu0_i (npmuirq_cpu0_i), + .npmuirq_cpu1_i (npmuirq_cpu1_i), + .npmuirq_cpu2_i (npmuirq_cpu2_i), + .npmuirq_cpu3_i (npmuirq_cpu3_i), + .pm_export_cpu0_i (pm_export_cpu0_i), + .pm_export_cpu1_i (pm_export_cpu1_i), + .pm_export_cpu2_i (pm_export_cpu2_i), + .pm_export_cpu3_i (pm_export_cpu3_i), + .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), + .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), + .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), + .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]) + ); // unoncpu +endmodule // MAIA_feq20_s + + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/MAIA_feq28.v b/Security Algo Accelerator/logical/maia/verilog/MAIA_feq28.v new file mode 100644 index 0000000000..8295b03241 --- /dev/null +++ b/Security Algo Accelerator/logical/maia/verilog/MAIA_feq28.v @@ -0,0 +1,4801 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: MAIA_feq28.v $ +// Checked In : $Date: 2014-10-14 15:20:06 -0500 (Tue, 14 Oct 2014) $ +// Revision : $Revision: 71806 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// +// This is top-level interconnect layer for the MAIA_feq28 top-level. +// + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +`define MAIA_CN 3 + +module MAIA_feq28 ( + CLK, + CLKEN, + nCPUPORESET, + nCORERESET, + nL2RESET, + L2RSTDISABLE, + WARMRSTREQ, + CFGEND, + VINITHI, + CFGTE, + CP15SDISABLE, + CLUSTERIDAFF1, + CLUSTERIDAFF2, + AA64nAA32, + RVBARADDR0, +// BEGIN INCLUDE FOR CPU1 + RVBARADDR1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + RVBARADDR2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + RVBARADDR3, +// END INCLUDE FOR CPU3 + CRYPTODISABLE, + nFIQ, + nIRQ, + nSEI, + nREI, + nVFIQ, + nVIRQ, + nVSEI, +// BEGIN NO-GIC pins + nVCPUMNTIRQ, +// END NO-GIC pins + PERIPHBASE, +// BEGIN NO-GIC pins + GICCDISABLE, + ICDTVALID, + ICDTREADY, + ICDTDATA, + ICDTLAST, + ICDTDEST, + ICCTVALID, + ICCTREADY, + ICCTDATA, + ICCTLAST, + ICCTID, +// END NO-GIC pins + CNTVALUEB, + CNTCLKEN, + nCNTPNSIRQ, + nCNTPSIRQ, + nCNTVIRQ, + nCNTHPIRQ, + CLREXMONREQ, + CLREXMONACK, + EVENTI, + EVENTO, + STANDBYWFI, + STANDBYWFE, + STANDBYWFIL2, + SMPEN, + CPUQACTIVE, + CPUQREQn, + CPUQACCEPTn, + CPUQDENY, + L2QACTIVE, + L2QREQn, + L2QACCEPTn, + L2QDENY, + L2FLUSHREQ, + L2FLUSHDONE, + nINTERRIRQ, + nEXTERRIRQ, + SYSBARDISABLE, + BROADCASTINNER, + BROADCASTOUTER, + BROADCASTCACHEMAINT, + ACLKENM, + ACINACTM, + AWREADYM, + AWVALIDM, + AWIDM, + AWADDRM, + AWLENM, + AWSIZEM, + AWBURSTM, + AWBARM, + AWDOMAINM, + AWLOCKM, + AWCACHEM, + AWPROTM, + AWSNOOPM, + AWUNIQUEM, + WRMEMATTR, + WREADYM, + WVALIDM, + WDATAM, + WSTRBM, + WIDM, + WLASTM, + BREADYM, + BVALIDM, + BIDM, + BRESPM, + ARREADYM, + ARVALIDM, + ARIDM, + ARADDRM, + ARLENM, + ARSIZEM, + ARBURSTM, + ARBARM, + ARDOMAINM, + ARLOCKM, + ARCACHEM, + ARPROTM, + ARSNOOPM, + RDMEMATTR, + RREADYM, + RVALIDM, + RIDM, + RDATAM, + RRESPM, + RLASTM, + ACREADYM, + ACVALIDM, + ACADDRM, + ACPROTM, + ACSNOOPM, + CRREADYM, + CRVALIDM, + CRRESPM, + CDREADYM, + CDVALIDM, + CDDATAM, + CDLASTM, + RACKM, + WACKM, +// BEGIN NO-ACP pins + ACLKENS, + AINACTS, + AWREADYS, + AWVALIDS, + AWIDS, + AWADDRS, + AWLENS, + AWCACHES, + AWUSERS, + AWPROTS, + WREADYS, + WVALIDS, + WDATAS, + WSTRBS, + WLASTS, + BREADYS, + BVALIDS, + BIDS, + BRESPS, + ARREADYS, + ARVALIDS, + ARIDS, + ARADDRS, + ARLENS, + ARCACHES, + ARUSERS, + ARPROTS, + RREADYS, + RVALIDS, + RIDS, + RDATAS, + RRESPS, + RLASTS, +// END NO-ACP pins + DBGROMADDR, + DBGROMADDRV, + DBGACK, + nCOMMIRQ, + COMMRX, + COMMTX, + DBGRSTREQ, + DBGNOPWRDWN, + DBGL1RSTDISABLE, + nPMUIRQ, + PMUEVENT0, +// BEGIN INCLUDE FOR CPU1 + PMUEVENT1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + PMUEVENT2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + PMUEVENT3, +// END INCLUDE FOR CPU3 + ATCLKEN, + TSVALUEB, + ATREADYM0, + AFVALIDM0, + ATDATAM0, + ATVALIDM0, + ATBYTESM0, + AFREADYM0, + ATIDM0, + SYNCREQM0, +// BEGIN INCLUDE FOR CPU1 + ATREADYM1, + AFVALIDM1, + ATDATAM1, + ATVALIDM1, + ATBYTESM1, + AFREADYM1, + ATIDM1, + SYNCREQM1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ATREADYM2, + AFVALIDM2, + ATDATAM2, + ATVALIDM2, + ATBYTESM2, + AFREADYM2, + ATIDM2, + SYNCREQM2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ATREADYM3, + AFVALIDM3, + ATDATAM3, + ATVALIDM3, + ATBYTESM3, + AFREADYM3, + ATIDM3, + SYNCREQM3, +// END INCLUDE FOR CPU3 + PCLKDBG, + PCLKENDBG, + nPRESETDBG, + PSELDBG, + PADDRDBG, + PADDRDBG31, + PENABLEDBG, + PWRITEDBG, + PWDATADBG, + PRDATADBG, + PREADYDBG, + PSLVERRDBG, + EDBGRQ, + PMUSNAPSHOTREQ, + PMUSNAPSHOTACK, + DBGPWRDUP, + DBGPWRUPREQ, + CTICHIN, + CTICHOUTACK, + CTICHOUT, + CTICHINACK, + CISBYPASS, + CIHSBYPASS, + CTIIRQ, + CTIIRQACK, + DBGEN, + NIDEN, + SPIDEN, + SPNIDEN, + DFTSE, + DFTRSTDISABLE, + DFTCRCLKDISABLE, + DFTL2CLKDISABLE, + DFTRAMHOLD, + DFTCLKBYPASS, + DFTMCPHOLD, + nMBISTRESET, + MBISTREQ +); + +//# +//# Interface Signals +//# ================= +//# + +//----------------------------------------------------------------------------- +// Clock and Reset Signals +//----------------------------------------------------------------------------- + input CLK; // Fast Clock + input CLKEN; // Fast Clock Enable + + input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset + input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) + input nL2RESET; // L2 reset + input L2RSTDISABLE; // L2 RAMs hardware reset disable + output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request +//See also nPRESETDBG; // Debug APB reset (PCLK) + +//----------------------------------------------------------------------------- +// Static Configuration Signals +//----------------------------------------------------------------------------- +// Static configuration signals that should be tied off and not change dynamically. +// Many of the initial values specified by these inputs +// may be overridden in software using CP15 registers. + + input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) + input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors + input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) + input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers + + input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] + input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] + + input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) + input [43:2] RVBARADDR0; // RVBAR address +// BEGIN INCLUDE FOR CPU1 + input [43:2] RVBARADDR1; // RVBAR address +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input [43:2] RVBARADDR2; // RVBAR address +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input [43:2] RVBARADDR3; // RVBAR address +// END INCLUDE FOR CPU3 + input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension + +//----------------------------------------------------------------------------- +// Interrupt Controller Signals +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] nFIQ; // Fast Interrupt request + input [`MAIA_CN:0] nIRQ; // Interrupt request + input [`MAIA_CN:0] nSEI; // System Error Interrupt + input [`MAIA_CN:0] nREI; // RAM Error Interrupt + input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request + input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request + input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt + + output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output + + input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers + input GICCDISABLE; // Put GIC into bypass mode + + input ICDTVALID; // Distrubuter AXI4 SP Message Valid + output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message + input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data + input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet + input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID + + output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid + input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message + output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data + output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet + output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID + +//----------------------------------------------------------------------------- +// Timer Signals +//----------------------------------------------------------------------------- + input [63:0] CNTVALUEB; // Counter value in binary + input CNTCLKEN; // Counter clock enable + output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event + output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event + output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event + output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event + +//----------------------------------------------------------------------------- +// Power Management Signals +//----------------------------------------------------------------------------- + input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) + output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) + input EVENTI; // Event input for processor wake-up from WFE state + output EVENTO; // Event output, signal is active when SEV instruction is executed + output [`MAIA_CN:0] STANDBYWFI; // WFI mode + output [`MAIA_CN:0] STANDBYWFE; // WFE mode + output STANDBYWFIL2; // WFI mode for L2 + output [`MAIA_CN:0] SMPEN; // CPU SMP bit + + output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE + input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn + output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn + output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY + + output L2QACTIVE; // L2 Q-channel QACTIVE + input L2QREQn; // L2 Q-channel QREQn + output L2QACCEPTn; // L2 Q-channel QACCEPTn + output L2QDENY; // L2 Q-channel QDENY + + input L2FLUSHREQ; // L2 hardware flush request + output L2FLUSHDONE; // L2 hardware flush done + +//----------------------------------------------------------------------------- +// Asynchronous Error Signals +//----------------------------------------------------------------------------- + output nINTERRIRQ; // L2 RAM dbl-bit ECC error + output nEXTERRIRQ; // Write transaction error + +//----------------------------------------------------------------------------- +// Bus Configuration Signals +//----------------------------------------------------------------------------- + input SYSBARDISABLE; // Disable broadcast of barriers + input BROADCASTINNER; // Extend Inner Shared Domain + input BROADCASTOUTER; // Extend Outer Shared Domain + input BROADCASTCACHEMAINT; // Broadcast cache maint ops + +//----------------------------------------------------------------------------- +// AMBA4 ACE Master (AXI with Coherency extensions) +//----------------------------------------------------------------------------- + input ACLKENM; // AXI Master clock enable + input ACINACTM; // ACE Snoop interface no longer active or accepting requests + +// Write Address channel signals + input AWREADYM; // Write Address ready (slave ready to accept write address) + output AWVALIDM; // Write Address valid + output [6:0] AWIDM; // Write Address ID + output [43:0] AWADDRM; // Write Address + output [7:0] AWLENM; // Write Burst Length + output [2:0] AWSIZEM; // Write Burst Size + output [1:0] AWBURSTM; // Write Burst type + output [1:0] AWBARM; // Barrier + output [1:0] AWDOMAINM; // Domain + output AWLOCKM; // Write Lock type + output [3:0] AWCACHEM; // Write Cache type + output [2:0] AWPROTM; // Write Protection type + output [2:0] AWSNOOPM; // Write Snoop Request type + output AWUNIQUEM; // Write Unique state + output [7:0] WRMEMATTR; // Write raw memory attributes + +// Write Data channel signals + input WREADYM; // Write Data ready (slave ready to accept data) + output WVALIDM; // Write Data valid + output [127:0] WDATAM; // Write Data + output [15:0] WSTRBM; // Write byte-lane strobes + output [6:0] WIDM; // Write id + output WLASTM; // Write Data last transfer indicator + +// Write Response channel signals + output BREADYM; // Write Response ready (master ready to accept response) + input BVALIDM; // Write Response Valid + input [6:0] BIDM; // Write Response ID + input [1:0] BRESPM; // Write Response + +// Read Address channel signals + input ARREADYM; // Read Address ready (slave ready to accept read address) + output ARVALIDM; // Read Address valid + output [6:0] ARIDM; // Read Address ID + output [43:0] ARADDRM; // Read Address + output [7:0] ARLENM; // Read Burst Length + output [2:0] ARSIZEM; // Read Burst Size + output [1:0] ARBURSTM; // Read Burst type + output [1:0] ARBARM; // Barrier + output [1:0] ARDOMAINM; // Domain + output ARLOCKM; // Read Lock type + output [3:0] ARCACHEM; // Read Cache type + output [2:0] ARPROTM; // Read Protection type + output [3:0] ARSNOOPM; // Read Snoop Request type + output [7:0] RDMEMATTR; // Read raw memory attributes + +// Read Data channel signals + output RREADYM; // Read Data ready (master ready to accept data) + input RVALIDM; // Read Data valid + input [6:0] RIDM; // Read Data ID + input [127:0] RDATAM; // Read Data + input [3:0] RRESPM; // Read Data response + input RLASTM; // Read Data last transfer indicator + +// Coherency Address channel signals + output ACREADYM; // master ready to accept snoop address + input ACVALIDM; // Snoop Address valid + input [43:0] ACADDRM; // Snoop Address + input [2:0] ACPROTM; // Snoop Protection type + input [3:0] ACSNOOPM; // Snoop Request type + +// Coherency Response channel signals + input CRREADYM; // slave ready to accept snoop response + output CRVALIDM; // Snoop Response valid + output [4:0] CRRESPM; // Snoop Response + +// Coherency Data handshake channel signals + input CDREADYM; // slave ready to accept snoop data + output CDVALIDM; // Snoop Data valid + output [127:0] CDDATAM; // Snoop Data + output CDLASTM; // Snoop Data last transfer indicator + +// Read/Write Acknowledge signals + output RACKM; // Read Acknowledge + output WACKM; // Write Acknowledge + +// BEGIN NO-ACP pins +//----------------------------------------------------------------------------- +// ACP AXI Slave +//----------------------------------------------------------------------------- + input ACLKENS; // AXI slave clock enable + input AINACTS; // AXI slave interface no longer active or accepting requests + +// Write Address channel signals + output AWREADYS; // Write Address ready (slave ready to accept write address) + input AWVALIDS; // Write Address valid + input [4:0] AWIDS; // Write Address ID + input [43:0] AWADDRS; // Write Address + input [7:0] AWLENS; // Write Burst Length + input [3:0] AWCACHES; // Write Cache type + input [1:0] AWUSERS; // Write inner & outer shareability + input [2:0] AWPROTS; // Write Protection type + +// Write Data channel signals + output WREADYS; // Write Data ready (slave ready to accept data) + input WVALIDS; // Write Data valid + input [127:0] WDATAS; // Write Data + input [15:0] WSTRBS; // Write byte-lane strobes + input WLASTS; // Write Data last transfer indicator + +// Write Response channel signals + input BREADYS; // Write Response ready (master ready to accept response) + output BVALIDS; // Write Response Valid + output [4:0] BIDS; // Write Response ID tag + output [1:0] BRESPS; // Write Response + +// Read Address channel signals + output ARREADYS; // Read Address ready (slave ready to accept read address) + input ARVALIDS; // Read Address valid + input [4:0] ARIDS; // Read Address ID + input [43:0] ARADDRS; // Read Address + input [7:0] ARLENS; // Read Burst Length + input [3:0] ARCACHES; // Read Cache type + input [1:0] ARUSERS; // Read inner & outer shareability + input [2:0] ARPROTS; // Read Protection type + +// Read Data channel signals + input RREADYS; // Read Data ready (master ready to accept data) + output RVALIDS; // Read Data valid + output [4:0] RIDS; // Read Data ID + output [127:0] RDATAS; // Read Data + output [1:0] RRESPS; // Read Data response + output RLASTS; // Read Data last transfer indicator +// END NO-ACP pins + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (CLK) +//----------------------------------------------------------------------------- +// Debug CLK interface + input [43:12] DBGROMADDR; // Debug ROM base address + input DBGROMADDRV; // Debug ROM base address valid + + output [`MAIA_CN:0] DBGACK; // Debug acknowledge + output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt + output [`MAIA_CN:0] COMMRX; // Comms channel receive + output [`MAIA_CN:0] COMMTX; // Comms channel transmit + + output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request + output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request + + input DBGL1RSTDISABLE; // L1 DCache hardware reset disable + +// PMU CLK interface + output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request + output [24:0] PMUEVENT0; // PMU Event bus +// BEGIN INCLUDE FOR CPU1 + output [24:0] PMUEVENT1; // PMU Event bus +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + output [24:0] PMUEVENT2; // PMU Event bus +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + output [24:0] PMUEVENT3; // PMU Event bus +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (ATCLK) +//----------------------------------------------------------------------------- +// ETM ATB interface and Misc signals + input ATCLKEN; // ATB Clock Enable + input [63:0] TSVALUEB; // ATB Timestamp in binary + + input ATREADYM0; // ATDATA can be accepted + input AFVALIDM0; // ATB Fifo Flush Request + output [31:0] ATDATAM0; // ATB Data + output ATVALIDM0; // ATB Data Valid + output [1:0] ATBYTESM0; // ATB Data Size + output AFREADYM0; // ATB Fifo Flush Finished + output [6:0] ATIDM0; // ATB Trace Source ID + input SYNCREQM0; // ATB External synchronization request + +// BEGIN INCLUDE FOR CPU1 + input ATREADYM1; // ATDATA can be accepted + input AFVALIDM1; // ATB Fifo Flush Request + output [31:0] ATDATAM1; // ATB Data + output ATVALIDM1; // ATB Data Valid + output [1:0] ATBYTESM1; // ATB Data Size + output AFREADYM1; // ATB Fifo Flush Finished + output [6:0] ATIDM1; // ATB Trace Source ID + input SYNCREQM1; // ATB External synchronization request +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ATREADYM2; // ATDATA can be accepted + input AFVALIDM2; // ATB Fifo Flush Request + output [31:0] ATDATAM2; // ATB Data + output ATVALIDM2; // ATB Data Valid + output [1:0] ATBYTESM2; // ATB Data Size + output AFREADYM2; // ATB Fifo Flush Finished + output [6:0] ATIDM2; // ATB Trace Source ID + input SYNCREQM2; // ATB External synchronization request +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ATREADYM3; // ATDATA can be accepted + input AFVALIDM3; // ATB Fifo Flush Request + output [31:0] ATDATAM3; // ATB Data + output ATVALIDM3; // ATB Data Valid + output [1:0] ATBYTESM3; // ATB Data Size + output AFREADYM3; // ATB Fifo Flush Finished + output [6:0] ATIDM3; // ATB Trace Source ID + input SYNCREQM3; // ATB External synchronization request +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (PCLK) +//----------------------------------------------------------------------------- +// Debug-APBv3 port (APB) + input PCLKDBG; // APB Clock + input PCLKENDBG; // APB Clock Enable + input nPRESETDBG; // APB Reset + input PSELDBG; // Debug bus access + input [21:2] PADDRDBG; // APB address + input PADDRDBG31; // APB address bit[31] + input PENABLEDBG; // APB transfer complete flag + input PWRITEDBG; // APB read/write indicator + input [31:0] PWDATADBG; // APB write data + output [31:0] PRDATADBG; // APB read data + output PREADYDBG; // APB slave ready, used to extend a transfer + output PSLVERRDBG; // APB slave transfer error + +// Misc interface + input [`MAIA_CN:0] EDBGRQ; // External debug request + +// PMU Snapshot interface + input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request + output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge + +// Power-related interface + input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status + output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request + +// CTI interface + input [3:0] CTICHIN; // Channel In + input [3:0] CTICHOUTACK; // Channel Out acknowledge + output [3:0] CTICHOUT; // Channel Out + output [3:0] CTICHINACK; // Channel In acknowledge + input CISBYPASS; // Channel interface sync bypass + input [3:0] CIHSBYPASS; // Channel interface H/S bypass + output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt + input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge + +//----------------------------------------------------------------------------- +// Debug Authentication Interface (CLK & PCLK) +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] DBGEN; // Invasive debug enable + input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable + input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable + input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable + +//----------------------------------------------------------------------------- +// DFT Signals +//----------------------------------------------------------------------------- + input DFTSE; // Scan enable + input DFTRSTDISABLE; // Disable reset to cells during scan shift + input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr + input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 + input DFTRAMHOLD; // Holds data in RAMs + input DFTCLKBYPASS; // L2 RAM strobe clock bypass + input DFTMCPHOLD; // Disable multi-cycle RAM paths + +//----------------------------------------------------------------------------- +// MBIST Interface +//----------------------------------------------------------------------------- + input nMBISTRESET; // MBIST reset + input MBISTREQ; // MBIST mode request + + + // wires + wire aa64naa32_cpu0_o; + wire aa64naa32_cpu1_o; + wire aa64naa32_cpu2_o; + wire aa64naa32_cpu3_o; + wire afreadym_cpu0_i; + wire afreadym_cpu1_i; + wire afreadym_cpu2_i; + wire afreadym_cpu3_i; + wire afvalidm_cpu0_o; + wire afvalidm_cpu1_o; + wire afvalidm_cpu2_o; + wire afvalidm_cpu3_o; + wire [1:0] atbytesm_cpu0_i; + wire [1:0] atbytesm_cpu1_i; + wire [1:0] atbytesm_cpu2_i; + wire [1:0] atbytesm_cpu3_i; + wire atclken_cpu0_o; + wire atclken_cpu1_o; + wire atclken_cpu2_o; + wire atclken_cpu3_o; + wire [31:0] atdatam_cpu0_i; + wire [31:0] atdatam_cpu1_i; + wire [31:0] atdatam_cpu2_i; + wire [31:0] atdatam_cpu3_i; + wire [6:0] atidm_cpu0_i; + wire [6:0] atidm_cpu1_i; + wire [6:0] atidm_cpu2_i; + wire [6:0] atidm_cpu3_i; + wire atreadym_cpu0_o; + wire atreadym_cpu1_o; + wire atreadym_cpu2_o; + wire atreadym_cpu3_o; + wire atvalidm_cpu0_i; + wire atvalidm_cpu1_i; + wire atvalidm_cpu2_i; + wire atvalidm_cpu3_i; + wire cfgend_cpu0_o; + wire cfgend_cpu1_o; + wire cfgend_cpu2_o; + wire cfgend_cpu3_o; + wire cfgte_cpu0_o; + wire cfgte_cpu1_o; + wire cfgte_cpu2_o; + wire cfgte_cpu3_o; + wire ck_cpu0_crcx_clk_en_n; + wire ck_cpu0_event_reg; + wire ck_cpu0_wfe_ack; + wire ck_cpu0_wfi_ack; + wire ck_cpu1_crcx_clk_en_n; + wire ck_cpu1_event_reg; + wire ck_cpu1_wfe_ack; + wire ck_cpu1_wfi_ack; + wire ck_cpu2_crcx_clk_en_n; + wire ck_cpu2_event_reg; + wire ck_cpu2_wfe_ack; + wire ck_cpu2_wfi_ack; + wire ck_cpu3_crcx_clk_en_n; + wire ck_cpu3_event_reg; + wire ck_cpu3_wfe_ack; + wire ck_cpu3_wfi_ack; + wire [`MAIA_CN:0] ck_gclkt; + wire [7:0] clusteridaff1_cpu0_o; + wire [7:0] clusteridaff1_cpu1_o; + wire [7:0] clusteridaff1_cpu2_o; + wire [7:0] clusteridaff1_cpu3_o; + wire [7:0] clusteridaff2_cpu0_o; + wire [7:0] clusteridaff2_cpu1_o; + wire [7:0] clusteridaff2_cpu2_o; + wire [7:0] clusteridaff2_cpu3_o; + wire commrx_cpu0_i; + wire commrx_cpu1_i; + wire commrx_cpu2_i; + wire commrx_cpu3_i; + wire commtx_cpu0_i; + wire commtx_cpu1_i; + wire commtx_cpu2_i; + wire commtx_cpu3_i; + wire cp15sdisable_cpu0_o; + wire cp15sdisable_cpu1_o; + wire cp15sdisable_cpu2_o; + wire cp15sdisable_cpu3_o; + wire [1:0] cpuid_cpu0_o; + wire [1:0] cpuid_cpu1_o; + wire [1:0] cpuid_cpu2_o; + wire [1:0] cpuid_cpu3_o; + wire cryptodisable_cpu0_o; + wire cryptodisable_cpu1_o; + wire cryptodisable_cpu2_o; + wire cryptodisable_cpu3_o; + wire dbgack_cpu0_i; + wire dbgack_cpu1_i; + wire dbgack_cpu2_i; + wire dbgack_cpu3_i; + wire dbgen_cpu0_o; + wire dbgen_cpu1_o; + wire dbgen_cpu2_o; + wire dbgen_cpu3_o; + wire dbgl1rstdisable_cpu0_o; + wire dbgl1rstdisable_cpu1_o; + wire dbgl1rstdisable_cpu2_o; + wire dbgl1rstdisable_cpu3_o; + wire dbgnopwrdwn_cpu0_i; + wire dbgnopwrdwn_cpu1_i; + wire dbgnopwrdwn_cpu2_i; + wire dbgnopwrdwn_cpu3_i; + wire [43:12] dbgromaddr_cpu0_o; + wire [43:12] dbgromaddr_cpu1_o; + wire [43:12] dbgromaddr_cpu2_o; + wire [43:12] dbgromaddr_cpu3_o; + wire dbgromaddrv_cpu0_o; + wire dbgromaddrv_cpu1_o; + wire dbgromaddrv_cpu2_o; + wire dbgromaddrv_cpu3_o; + wire dbgrstreq_cpu0_i; + wire dbgrstreq_cpu1_i; + wire dbgrstreq_cpu2_i; + wire dbgrstreq_cpu3_i; + wire dftcrclkdisable_cpu0_o; + wire dftcrclkdisable_cpu1_o; + wire dftcrclkdisable_cpu2_o; + wire dftcrclkdisable_cpu3_o; + wire dftramhold_cpu0_o; + wire dftramhold_cpu1_o; + wire dftramhold_cpu2_o; + wire dftramhold_cpu3_o; + wire dftrstdisable_cpu0_o; + wire dftrstdisable_cpu1_o; + wire dftrstdisable_cpu2_o; + wire dftrstdisable_cpu3_o; + wire dftse_cpu0_o; + wire dftse_cpu1_o; + wire dftse_cpu2_o; + wire dftse_cpu3_o; + wire [2:0] ds_cpu0_cpuectlr_ret; + wire ds_cpu0_cpuectlr_smp; + wire ds_cpu0_fiq_wfe_qual; + wire ds_cpu0_fiq_wfi_qual; + wire ds_cpu0_flush; + wire [5:0] ds_cpu0_flush_type; + wire ds_cpu0_hcr_va; + wire ds_cpu0_hcr_vf; + wire ds_cpu0_hcr_vi; + wire ds_cpu0_ic_aa64naa32; + wire [4:0] ds_cpu0_ic_cpsr_mode; + wire ds_cpu0_ic_hcr_change; + wire ds_cpu0_ic_sample_spr; + wire ds_cpu0_ic_scr_change; + wire ds_cpu0_imp_abrt_wfe_qual; + wire ds_cpu0_imp_abrt_wfi_qual; + wire ds_cpu0_irq_wfe_qual; + wire ds_cpu0_irq_wfi_qual; + wire [8:0] ds_cpu0_l2_spr_addr; + wire ds_cpu0_l2_spr_dw; + wire ds_cpu0_l2_spr_en; + wire ds_cpu0_l2_spr_rd; + wire ds_cpu0_l2_spr_wr; + wire [63:0] ds_cpu0_l2_spr_wr_data; + wire ds_cpu0_reset_req; + wire ds_cpu0_sev_req; + wire ds_cpu0_sevl_req; + wire ds_cpu0_vfiq_wfe_qual; + wire ds_cpu0_vfiq_wfi_qual; + wire ds_cpu0_vimp_abrt_wfe_qual; + wire ds_cpu0_vimp_abrt_wfi_qual; + wire ds_cpu0_virq_wfe_qual; + wire ds_cpu0_virq_wfi_qual; + wire ds_cpu0_wfe_req; + wire ds_cpu0_wfi_req; + wire [2:0] ds_cpu1_cpuectlr_ret; + wire ds_cpu1_cpuectlr_smp; + wire ds_cpu1_fiq_wfe_qual; + wire ds_cpu1_fiq_wfi_qual; + wire ds_cpu1_flush; + wire [5:0] ds_cpu1_flush_type; + wire ds_cpu1_hcr_va; + wire ds_cpu1_hcr_vf; + wire ds_cpu1_hcr_vi; + wire ds_cpu1_ic_aa64naa32; + wire [4:0] ds_cpu1_ic_cpsr_mode; + wire ds_cpu1_ic_hcr_change; + wire ds_cpu1_ic_sample_spr; + wire ds_cpu1_ic_scr_change; + wire ds_cpu1_imp_abrt_wfe_qual; + wire ds_cpu1_imp_abrt_wfi_qual; + wire ds_cpu1_irq_wfe_qual; + wire ds_cpu1_irq_wfi_qual; + wire [8:0] ds_cpu1_l2_spr_addr; + wire ds_cpu1_l2_spr_dw; + wire ds_cpu1_l2_spr_en; + wire ds_cpu1_l2_spr_rd; + wire ds_cpu1_l2_spr_wr; + wire [63:0] ds_cpu1_l2_spr_wr_data; + wire ds_cpu1_reset_req; + wire ds_cpu1_sev_req; + wire ds_cpu1_sevl_req; + wire ds_cpu1_vfiq_wfe_qual; + wire ds_cpu1_vfiq_wfi_qual; + wire ds_cpu1_vimp_abrt_wfe_qual; + wire ds_cpu1_vimp_abrt_wfi_qual; + wire ds_cpu1_virq_wfe_qual; + wire ds_cpu1_virq_wfi_qual; + wire ds_cpu1_wfe_req; + wire ds_cpu1_wfi_req; + wire [2:0] ds_cpu2_cpuectlr_ret; + wire ds_cpu2_cpuectlr_smp; + wire ds_cpu2_fiq_wfe_qual; + wire ds_cpu2_fiq_wfi_qual; + wire ds_cpu2_flush; + wire [5:0] ds_cpu2_flush_type; + wire ds_cpu2_hcr_va; + wire ds_cpu2_hcr_vf; + wire ds_cpu2_hcr_vi; + wire ds_cpu2_ic_aa64naa32; + wire [4:0] ds_cpu2_ic_cpsr_mode; + wire ds_cpu2_ic_hcr_change; + wire ds_cpu2_ic_sample_spr; + wire ds_cpu2_ic_scr_change; + wire ds_cpu2_imp_abrt_wfe_qual; + wire ds_cpu2_imp_abrt_wfi_qual; + wire ds_cpu2_irq_wfe_qual; + wire ds_cpu2_irq_wfi_qual; + wire [8:0] ds_cpu2_l2_spr_addr; + wire ds_cpu2_l2_spr_dw; + wire ds_cpu2_l2_spr_en; + wire ds_cpu2_l2_spr_rd; + wire ds_cpu2_l2_spr_wr; + wire [63:0] ds_cpu2_l2_spr_wr_data; + wire ds_cpu2_reset_req; + wire ds_cpu2_sev_req; + wire ds_cpu2_sevl_req; + wire ds_cpu2_vfiq_wfe_qual; + wire ds_cpu2_vfiq_wfi_qual; + wire ds_cpu2_vimp_abrt_wfe_qual; + wire ds_cpu2_vimp_abrt_wfi_qual; + wire ds_cpu2_virq_wfe_qual; + wire ds_cpu2_virq_wfi_qual; + wire ds_cpu2_wfe_req; + wire ds_cpu2_wfi_req; + wire [2:0] ds_cpu3_cpuectlr_ret; + wire ds_cpu3_cpuectlr_smp; + wire ds_cpu3_fiq_wfe_qual; + wire ds_cpu3_fiq_wfi_qual; + wire ds_cpu3_flush; + wire [5:0] ds_cpu3_flush_type; + wire ds_cpu3_hcr_va; + wire ds_cpu3_hcr_vf; + wire ds_cpu3_hcr_vi; + wire ds_cpu3_ic_aa64naa32; + wire [4:0] ds_cpu3_ic_cpsr_mode; + wire ds_cpu3_ic_hcr_change; + wire ds_cpu3_ic_sample_spr; + wire ds_cpu3_ic_scr_change; + wire ds_cpu3_imp_abrt_wfe_qual; + wire ds_cpu3_imp_abrt_wfi_qual; + wire ds_cpu3_irq_wfe_qual; + wire ds_cpu3_irq_wfi_qual; + wire [8:0] ds_cpu3_l2_spr_addr; + wire ds_cpu3_l2_spr_dw; + wire ds_cpu3_l2_spr_en; + wire ds_cpu3_l2_spr_rd; + wire ds_cpu3_l2_spr_wr; + wire [63:0] ds_cpu3_l2_spr_wr_data; + wire ds_cpu3_reset_req; + wire ds_cpu3_sev_req; + wire ds_cpu3_sevl_req; + wire ds_cpu3_vfiq_wfe_qual; + wire ds_cpu3_vfiq_wfi_qual; + wire ds_cpu3_vimp_abrt_wfe_qual; + wire ds_cpu3_vimp_abrt_wfi_qual; + wire ds_cpu3_virq_wfe_qual; + wire ds_cpu3_virq_wfi_qual; + wire ds_cpu3_wfe_req; + wire ds_cpu3_wfi_req; + wire dt_cpu0_coredbg_in_reset_gclk; + wire [1:0] dt_cpu0_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu0_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu0_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu0_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu0_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu0_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; + wire dt_cpu0_cti_trigoutack_bit1_gclk; + wire dt_cpu0_dbif_ack_gclk; + wire [14:2] dt_cpu0_dbif_addr_pclk; + wire dt_cpu0_dbif_err_gclk; + wire dt_cpu0_dbif_locked_pclk; + wire [31:0] dt_cpu0_dbif_rddata_gclk; + wire dt_cpu0_dbif_req_pclk; + wire [31:0] dt_cpu0_dbif_wrdata_pclk; + wire dt_cpu0_dbif_write_pclk; + wire dt_cpu0_edacr_frc_idleack_pclk; + wire dt_cpu0_edbgrq_pclk; + wire dt_cpu0_edecr_osuce_pclk; + wire dt_cpu0_edecr_rce_pclk; + wire dt_cpu0_edecr_ss_pclk; + wire dt_cpu0_edprcr_corepurq_pclk; + wire dt_cpu0_et_oslock_gclk; + wire dt_cpu0_halt_ack_gclk; + wire dt_cpu0_hlt_dbgevt_ok_gclk; + wire dt_cpu0_noclkstop_pclk; + wire dt_cpu0_os_double_lock_gclk; + wire dt_cpu0_pmusnapshot_ack_gclk; + wire dt_cpu0_pmusnapshot_req_pclk; + wire dt_cpu0_wfx_dbg_req_gclk; + wire dt_cpu0_wfx_wakeup_pclk; + wire dt_cpu1_coredbg_in_reset_gclk; + wire [1:0] dt_cpu1_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu1_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu1_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu1_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu1_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu1_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; + wire dt_cpu1_cti_trigoutack_bit1_gclk; + wire dt_cpu1_dbif_ack_gclk; + wire [14:2] dt_cpu1_dbif_addr_pclk; + wire dt_cpu1_dbif_err_gclk; + wire dt_cpu1_dbif_locked_pclk; + wire [31:0] dt_cpu1_dbif_rddata_gclk; + wire dt_cpu1_dbif_req_pclk; + wire [31:0] dt_cpu1_dbif_wrdata_pclk; + wire dt_cpu1_dbif_write_pclk; + wire dt_cpu1_edacr_frc_idleack_pclk; + wire dt_cpu1_edbgrq_pclk; + wire dt_cpu1_edecr_osuce_pclk; + wire dt_cpu1_edecr_rce_pclk; + wire dt_cpu1_edecr_ss_pclk; + wire dt_cpu1_edprcr_corepurq_pclk; + wire dt_cpu1_et_oslock_gclk; + wire dt_cpu1_halt_ack_gclk; + wire dt_cpu1_hlt_dbgevt_ok_gclk; + wire dt_cpu1_noclkstop_pclk; + wire dt_cpu1_os_double_lock_gclk; + wire dt_cpu1_pmusnapshot_ack_gclk; + wire dt_cpu1_pmusnapshot_req_pclk; + wire dt_cpu1_wfx_dbg_req_gclk; + wire dt_cpu1_wfx_wakeup_pclk; + wire dt_cpu2_coredbg_in_reset_gclk; + wire [1:0] dt_cpu2_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu2_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu2_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu2_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu2_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu2_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; + wire dt_cpu2_cti_trigoutack_bit1_gclk; + wire dt_cpu2_dbif_ack_gclk; + wire [14:2] dt_cpu2_dbif_addr_pclk; + wire dt_cpu2_dbif_err_gclk; + wire dt_cpu2_dbif_locked_pclk; + wire [31:0] dt_cpu2_dbif_rddata_gclk; + wire dt_cpu2_dbif_req_pclk; + wire [31:0] dt_cpu2_dbif_wrdata_pclk; + wire dt_cpu2_dbif_write_pclk; + wire dt_cpu2_edacr_frc_idleack_pclk; + wire dt_cpu2_edbgrq_pclk; + wire dt_cpu2_edecr_osuce_pclk; + wire dt_cpu2_edecr_rce_pclk; + wire dt_cpu2_edecr_ss_pclk; + wire dt_cpu2_edprcr_corepurq_pclk; + wire dt_cpu2_et_oslock_gclk; + wire dt_cpu2_halt_ack_gclk; + wire dt_cpu2_hlt_dbgevt_ok_gclk; + wire dt_cpu2_noclkstop_pclk; + wire dt_cpu2_os_double_lock_gclk; + wire dt_cpu2_pmusnapshot_ack_gclk; + wire dt_cpu2_pmusnapshot_req_pclk; + wire dt_cpu2_wfx_dbg_req_gclk; + wire dt_cpu2_wfx_wakeup_pclk; + wire dt_cpu3_coredbg_in_reset_gclk; + wire [1:0] dt_cpu3_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu3_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu3_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu3_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu3_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu3_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; + wire dt_cpu3_cti_trigoutack_bit1_gclk; + wire dt_cpu3_dbif_ack_gclk; + wire [14:2] dt_cpu3_dbif_addr_pclk; + wire dt_cpu3_dbif_err_gclk; + wire dt_cpu3_dbif_locked_pclk; + wire [31:0] dt_cpu3_dbif_rddata_gclk; + wire dt_cpu3_dbif_req_pclk; + wire [31:0] dt_cpu3_dbif_wrdata_pclk; + wire dt_cpu3_dbif_write_pclk; + wire dt_cpu3_edacr_frc_idleack_pclk; + wire dt_cpu3_edbgrq_pclk; + wire dt_cpu3_edecr_osuce_pclk; + wire dt_cpu3_edecr_rce_pclk; + wire dt_cpu3_edecr_ss_pclk; + wire dt_cpu3_edprcr_corepurq_pclk; + wire dt_cpu3_et_oslock_gclk; + wire dt_cpu3_halt_ack_gclk; + wire dt_cpu3_hlt_dbgevt_ok_gclk; + wire dt_cpu3_noclkstop_pclk; + wire dt_cpu3_os_double_lock_gclk; + wire dt_cpu3_pmusnapshot_ack_gclk; + wire dt_cpu3_pmusnapshot_req_pclk; + wire dt_cpu3_wfx_dbg_req_gclk; + wire dt_cpu3_wfx_wakeup_pclk; + wire etclken_cpu0_i; + wire etclken_cpu1_i; + wire etclken_cpu2_i; + wire etclken_cpu3_i; + wire giccdisable_cpu0_o; + wire giccdisable_cpu1_o; + wire giccdisable_cpu2_o; + wire giccdisable_cpu3_o; + wire [`MAIA_CN:0] ic_block_eoi_sgi_wr; + wire [`MAIA_CN:0] ic_el_change_complete; + wire [`MAIA_CN:0] ic_hcr_change_complete; + wire [`MAIA_CN:0] ic_ich_el2_tall0; + wire [`MAIA_CN:0] ic_ich_el2_tall1; + wire [`MAIA_CN:0] ic_ich_el2_tc; + wire [`MAIA_CN:0] ic_nfiq; + wire [`MAIA_CN:0] ic_nirq; + wire [`MAIA_CN:0] ic_nsei; + wire [`MAIA_CN:0] ic_nvfiq; + wire [`MAIA_CN:0] ic_nvirq; + wire [`MAIA_CN:0] ic_nvsei; + wire [`MAIA_CN:0] ic_p_valid; + wire [`MAIA_CN:0] ic_sample_spr; + wire [`MAIA_CN:0] ic_scr_change_complete; + wire [`MAIA_CN:0] ic_sra_el1ns_en; + wire [`MAIA_CN:0] ic_sra_el1s_en; + wire [`MAIA_CN:0] ic_sra_el2_en; + wire [`MAIA_CN:0] ic_sra_el3_en; + wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; + wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap; + wire [`MAIA_CN:0] ic_sre_el1s_mon_trap; + wire [`MAIA_CN:0] ic_sre_el2_mon_trap; + wire l2_cpu0_arb_thrshld_timeout_en; + wire l2_cpu0_barrier_done; + wire l2_cpu0_blk_non_evict_wr; + wire l2_cpu0_ccb_dbg_req_c3; + wire [48:0] l2_cpu0_ccb_req_addr_c3; + wire [4:0] l2_cpu0_ccb_req_id_c3; + wire [23:0] l2_cpu0_ccb_req_info_c3; + wire [8:0] l2_cpu0_ccb_req_type_c3; + wire l2_cpu0_cfg_ecc_en; + wire [2:0] l2_cpu0_dbufid_r1; + wire [129:0] l2_cpu0_ddata_r2; + wire l2_cpu0_ddlb_ecc_err_r3; + wire l2_cpu0_dext_err_r2; + wire l2_cpu0_dext_err_type_r2; + wire l2_cpu0_disable_clean_evict_opt; + wire l2_cpu0_dlast_r1; + wire l2_cpu0_dsngl_ecc_err_r3; + wire [3:0] l2_cpu0_dsq_clr_id_q; + wire l2_cpu0_dsq_clr_vld_q; + wire [3:0] l2_cpu0_dsq_rd_buf_id; + wire [15:0] l2_cpu0_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu0_dsq_rd_data_q; + wire l2_cpu0_dsq_rd_en; + wire l2_cpu0_dsq_rd_en_x2; + wire l2_cpu0_dt_pmu_evt_en; + wire l2_cpu0_dvalid_r1; + wire l2_cpu0_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; + wire l2_cpu0_flsh_if_rd_l4_dly; + wire l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; + wire l2_cpu0_flsh_ls_rd_l2_dly; + wire l2_cpu0_flsh_ls_rd_l4_dly; + wire l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; + wire l2_cpu0_flsh_ls_wr_l2_dly; + wire l2_cpu0_flsh_ls_wr_l4_dly; + wire l2_cpu0_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu0_ibufid_r1; + wire [15:0] l2_cpu0_ic_addr_arb_set; + wire l2_cpu0_ic_arb_fast; + wire l2_cpu0_ic_barrier_stall_q; + wire [43:18] l2_cpu0_ic_base; + wire [31:0] l2_cpu0_ic_data_arb_set; + wire [2:0] l2_cpu0_ic_elem_size_arb_set; + wire l2_cpu0_ic_excl_arb_set; + wire [2:0] l2_cpu0_ic_id_arb_set; + wire l2_cpu0_ic_ns_arb_set; + wire l2_cpu0_ic_vld_skid; + wire l2_cpu0_ic_write_arb_set; + wire [127:0] l2_cpu0_idata_r2; + wire l2_cpu0_idlb_ecc_err_r3; + wire l2_cpu0_idle_block_reqs_q; + wire l2_cpu0_idle_wakeup_q; + wire l2_cpu0_iext_err_r2; + wire l2_cpu0_iext_err_type_r2; + wire l2_cpu0_if_ccb_clken_c3; + wire l2_cpu0_if_ccb_req_c3; + wire l2_cpu0_if_ccb_resp; + wire [4:0] l2_cpu0_if_ccb_resp_id; + wire l2_cpu0_if_sync_done_q; + wire l2_cpu0_if_sync_req; + wire l2_cpu0_ifq_haz_pending; + wire l2_cpu0_isngl_ecc_err_r3; + wire l2_cpu0_ivalid_r1; + wire [1:0] l2_cpu0_l2_cache_size; + wire [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; + wire l2_cpu0_lrq_haz_pending; + wire l2_cpu0_ls_ccb_clken_c3; + wire l2_cpu0_ls_ccb_data_wr; + wire l2_cpu0_ls_ccb_req_c3; + wire l2_cpu0_ls_ccb_resp; + wire [4:0] l2_cpu0_ls_ccb_resp_id; + wire l2_cpu0_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu0_ls_rd_haz_id_arb_q; + wire l2_cpu0_ls_rd_haz_vld_arb_q; + wire l2_cpu0_ls_sync_req; + wire [4:0] l2_cpu0_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu0_ls_wr_data_w2a; + wire l2_cpu0_ls_wr_dirty_w2a; + wire l2_cpu0_ls_wr_err_w2a; + wire [2:0] l2_cpu0_ls_wr_haz_id_arb_q; + wire l2_cpu0_ls_wr_haz_vld_arb_q; + wire l2_cpu0_ls_wr_last_w2a; + wire l2_cpu0_ls_wr_req_w2a; + wire [2:0] l2_cpu0_ls_wr_type_w2a; + wire [12:0] l2_cpu0_mbist1_addr_b1; + wire l2_cpu0_mbist1_all_b1; + wire [3:0] l2_cpu0_mbist1_array_b1; + wire [7:0] l2_cpu0_mbist1_be_b1; + wire l2_cpu0_mbist1_en_b1; + wire l2_cpu0_mbist1_rd_en_b1; + wire l2_cpu0_mbist1_wr_en_b1; + wire l2_cpu0_no_intctrl; + wire l2_cpu0_pf_rd_vld_skid_popped; + wire l2_cpu0_pf_throttle_q; + wire [33:0] l2_cpu0_pmu_events; + wire [2:0] l2_cpu0_rbufid; + wire l2_cpu0_rd_aarch64_arb_set; + wire [44:0] l2_cpu0_rd_addr_arb_set; + wire l2_cpu0_rd_arb; + wire l2_cpu0_rd_arb_fast; + wire [15:8] l2_cpu0_rd_asid_arb_set; + wire l2_cpu0_rd_bypass_arb_set; + wire [2:0] l2_cpu0_rd_bypass_bufid_e5; + wire [2:0] l2_cpu0_rd_bypass_lrq_id_e5; + wire l2_cpu0_rd_bypass_req_can_e5; + wire l2_cpu0_rd_bypass_way_e5; + wire [2:0] l2_cpu0_rd_cache_attr_arb_set; + wire [2:0] l2_cpu0_rd_elem_size_arb_set; + wire l2_cpu0_rd_excl_arb_set; + wire [4:0] l2_cpu0_rd_id_arb_set; + wire [2:0] l2_cpu0_rd_lrq_id_arb_set; + wire [7:0] l2_cpu0_rd_page_attr_arb_set; + wire l2_cpu0_rd_prfm_arb_set; + wire l2_cpu0_rd_priv_arb_set; + wire l2_cpu0_rd_replayed_arb_set; + wire [1:0] l2_cpu0_rd_shared_arb_set; + wire [6:0] l2_cpu0_rd_type_arb_set; + wire l2_cpu0_rd_va48_arb_set; + wire l2_cpu0_rd_vld_skid; + wire l2_cpu0_rd_way_arb_set; + wire l2_cpu0_rexfail; + wire [1:0] l2_cpu0_rstate; + wire l2_cpu0_rvalid; + wire [2:0] l2_cpu0_spec_bufid; + wire l2_cpu0_spec_valid; + wire [63:0] l2_cpu0_spr_rd_data; + wire l2_cpu0_tbw_dbl_ecc_err; + wire [63:0] l2_cpu0_tbw_desc_data; + wire l2_cpu0_tbw_desc_vld; + wire l2_cpu0_tbw_ext_err; + wire l2_cpu0_tbw_ext_err_type; + wire l2_cpu0_tlb_ccb_clken_c3; + wire l2_cpu0_tlb_ccb_req_c3; + wire l2_cpu0_tlb_sync_complete; + wire l2_cpu0_tlb_sync_done_q; + wire l2_cpu0_tlb_sync_req; + wire l2_cpu0_trq_haz_pending; + wire l2_cpu0_tw_ccb_resp; + wire [4:0] l2_cpu0_tw_ccb_resp_id; + wire l2_cpu0_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu0_wr_addr_arb_set; + wire l2_cpu0_wr_arb; + wire l2_cpu0_wr_arb_fast; + wire [2:0] l2_cpu0_wr_cache_attr_arb_set; + wire [11:0] l2_cpu0_wr_cl_id_arb_set; + wire l2_cpu0_wr_clean_evict_arb_set; + wire [143:0] l2_cpu0_wr_data; + wire l2_cpu0_wr_data_stall; + wire l2_cpu0_wr_data_vld_x1_q; + wire l2_cpu0_wr_dirty_arb_set; + wire [2:0] l2_cpu0_wr_elem_size_arb_set; + wire l2_cpu0_wr_err_arb_set; + wire l2_cpu0_wr_evict_x1_q; + wire l2_cpu0_wr_ex_fail; + wire l2_cpu0_wr_ex_resp; + wire [3:0] l2_cpu0_wr_id_arb_set; + wire l2_cpu0_wr_last_arb_set; + wire [7:0] l2_cpu0_wr_page_attr_arb_set; + wire [3:0] l2_cpu0_wr_partial_dw_arb_set; + wire l2_cpu0_wr_priv_arb_set; + wire [1:0] l2_cpu0_wr_shared_arb_set; + wire [2:0] l2_cpu0_wr_type_arb_set; + wire l2_cpu0_wr_vld_skid; + wire l2_cpu0_wr_way_arb_set; + wire l2_cpu0_wrq_almost_full; + wire [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; + wire l2_cpu0_wrq_haz_pending; + wire l2_cpu1_arb_thrshld_timeout_en; + wire l2_cpu1_barrier_done; + wire l2_cpu1_blk_non_evict_wr; + wire l2_cpu1_ccb_dbg_req_c3; + wire [48:0] l2_cpu1_ccb_req_addr_c3; + wire [4:0] l2_cpu1_ccb_req_id_c3; + wire [23:0] l2_cpu1_ccb_req_info_c3; + wire [8:0] l2_cpu1_ccb_req_type_c3; + wire l2_cpu1_cfg_ecc_en; + wire [2:0] l2_cpu1_dbufid_r1; + wire [129:0] l2_cpu1_ddata_r2; + wire l2_cpu1_ddlb_ecc_err_r3; + wire l2_cpu1_dext_err_r2; + wire l2_cpu1_dext_err_type_r2; + wire l2_cpu1_disable_clean_evict_opt; + wire l2_cpu1_dlast_r1; + wire l2_cpu1_dsngl_ecc_err_r3; + wire [3:0] l2_cpu1_dsq_clr_id_q; + wire l2_cpu1_dsq_clr_vld_q; + wire [3:0] l2_cpu1_dsq_rd_buf_id; + wire [15:0] l2_cpu1_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu1_dsq_rd_data_q; + wire l2_cpu1_dsq_rd_en; + wire l2_cpu1_dsq_rd_en_x2; + wire l2_cpu1_dt_pmu_evt_en; + wire l2_cpu1_dvalid_r1; + wire l2_cpu1_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; + wire l2_cpu1_flsh_if_rd_l4_dly; + wire l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; + wire l2_cpu1_flsh_ls_rd_l2_dly; + wire l2_cpu1_flsh_ls_rd_l4_dly; + wire l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; + wire l2_cpu1_flsh_ls_wr_l2_dly; + wire l2_cpu1_flsh_ls_wr_l4_dly; + wire l2_cpu1_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu1_ibufid_r1; + wire [15:0] l2_cpu1_ic_addr_arb_set; + wire l2_cpu1_ic_arb_fast; + wire l2_cpu1_ic_barrier_stall_q; + wire [43:18] l2_cpu1_ic_base; + wire [31:0] l2_cpu1_ic_data_arb_set; + wire [2:0] l2_cpu1_ic_elem_size_arb_set; + wire l2_cpu1_ic_excl_arb_set; + wire [2:0] l2_cpu1_ic_id_arb_set; + wire l2_cpu1_ic_ns_arb_set; + wire l2_cpu1_ic_vld_skid; + wire l2_cpu1_ic_write_arb_set; + wire [127:0] l2_cpu1_idata_r2; + wire l2_cpu1_idlb_ecc_err_r3; + wire l2_cpu1_idle_block_reqs_q; + wire l2_cpu1_idle_wakeup_q; + wire l2_cpu1_iext_err_r2; + wire l2_cpu1_iext_err_type_r2; + wire l2_cpu1_if_ccb_clken_c3; + wire l2_cpu1_if_ccb_req_c3; + wire l2_cpu1_if_ccb_resp; + wire [4:0] l2_cpu1_if_ccb_resp_id; + wire l2_cpu1_if_sync_done_q; + wire l2_cpu1_if_sync_req; + wire l2_cpu1_ifq_haz_pending; + wire l2_cpu1_isngl_ecc_err_r3; + wire l2_cpu1_ivalid_r1; + wire [1:0] l2_cpu1_l2_cache_size; + wire [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; + wire l2_cpu1_lrq_haz_pending; + wire l2_cpu1_ls_ccb_clken_c3; + wire l2_cpu1_ls_ccb_data_wr; + wire l2_cpu1_ls_ccb_req_c3; + wire l2_cpu1_ls_ccb_resp; + wire [4:0] l2_cpu1_ls_ccb_resp_id; + wire l2_cpu1_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu1_ls_rd_haz_id_arb_q; + wire l2_cpu1_ls_rd_haz_vld_arb_q; + wire l2_cpu1_ls_sync_req; + wire [4:0] l2_cpu1_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu1_ls_wr_data_w2a; + wire l2_cpu1_ls_wr_dirty_w2a; + wire l2_cpu1_ls_wr_err_w2a; + wire [2:0] l2_cpu1_ls_wr_haz_id_arb_q; + wire l2_cpu1_ls_wr_haz_vld_arb_q; + wire l2_cpu1_ls_wr_last_w2a; + wire l2_cpu1_ls_wr_req_w2a; + wire [2:0] l2_cpu1_ls_wr_type_w2a; + wire [12:0] l2_cpu1_mbist1_addr_b1; + wire l2_cpu1_mbist1_all_b1; + wire [3:0] l2_cpu1_mbist1_array_b1; + wire [7:0] l2_cpu1_mbist1_be_b1; + wire l2_cpu1_mbist1_en_b1; + wire l2_cpu1_mbist1_rd_en_b1; + wire l2_cpu1_mbist1_wr_en_b1; + wire l2_cpu1_no_intctrl; + wire l2_cpu1_pf_rd_vld_skid_popped; + wire l2_cpu1_pf_throttle_q; + wire [33:0] l2_cpu1_pmu_events; + wire [2:0] l2_cpu1_rbufid; + wire l2_cpu1_rd_aarch64_arb_set; + wire [44:0] l2_cpu1_rd_addr_arb_set; + wire l2_cpu1_rd_arb; + wire l2_cpu1_rd_arb_fast; + wire [15:8] l2_cpu1_rd_asid_arb_set; + wire l2_cpu1_rd_bypass_arb_set; + wire [2:0] l2_cpu1_rd_bypass_bufid_e5; + wire [2:0] l2_cpu1_rd_bypass_lrq_id_e5; + wire l2_cpu1_rd_bypass_req_can_e5; + wire l2_cpu1_rd_bypass_way_e5; + wire [2:0] l2_cpu1_rd_cache_attr_arb_set; + wire [2:0] l2_cpu1_rd_elem_size_arb_set; + wire l2_cpu1_rd_excl_arb_set; + wire [4:0] l2_cpu1_rd_id_arb_set; + wire [2:0] l2_cpu1_rd_lrq_id_arb_set; + wire [7:0] l2_cpu1_rd_page_attr_arb_set; + wire l2_cpu1_rd_prfm_arb_set; + wire l2_cpu1_rd_priv_arb_set; + wire l2_cpu1_rd_replayed_arb_set; + wire [1:0] l2_cpu1_rd_shared_arb_set; + wire [6:0] l2_cpu1_rd_type_arb_set; + wire l2_cpu1_rd_va48_arb_set; + wire l2_cpu1_rd_vld_skid; + wire l2_cpu1_rd_way_arb_set; + wire l2_cpu1_rexfail; + wire [1:0] l2_cpu1_rstate; + wire l2_cpu1_rvalid; + wire [2:0] l2_cpu1_spec_bufid; + wire l2_cpu1_spec_valid; + wire [63:0] l2_cpu1_spr_rd_data; + wire l2_cpu1_tbw_dbl_ecc_err; + wire [63:0] l2_cpu1_tbw_desc_data; + wire l2_cpu1_tbw_desc_vld; + wire l2_cpu1_tbw_ext_err; + wire l2_cpu1_tbw_ext_err_type; + wire l2_cpu1_tlb_ccb_clken_c3; + wire l2_cpu1_tlb_ccb_req_c3; + wire l2_cpu1_tlb_sync_complete; + wire l2_cpu1_tlb_sync_done_q; + wire l2_cpu1_tlb_sync_req; + wire l2_cpu1_trq_haz_pending; + wire l2_cpu1_tw_ccb_resp; + wire [4:0] l2_cpu1_tw_ccb_resp_id; + wire l2_cpu1_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu1_wr_addr_arb_set; + wire l2_cpu1_wr_arb; + wire l2_cpu1_wr_arb_fast; + wire [2:0] l2_cpu1_wr_cache_attr_arb_set; + wire [11:0] l2_cpu1_wr_cl_id_arb_set; + wire l2_cpu1_wr_clean_evict_arb_set; + wire [143:0] l2_cpu1_wr_data; + wire l2_cpu1_wr_data_stall; + wire l2_cpu1_wr_data_vld_x1_q; + wire l2_cpu1_wr_dirty_arb_set; + wire [2:0] l2_cpu1_wr_elem_size_arb_set; + wire l2_cpu1_wr_err_arb_set; + wire l2_cpu1_wr_evict_x1_q; + wire l2_cpu1_wr_ex_fail; + wire l2_cpu1_wr_ex_resp; + wire [3:0] l2_cpu1_wr_id_arb_set; + wire l2_cpu1_wr_last_arb_set; + wire [7:0] l2_cpu1_wr_page_attr_arb_set; + wire [3:0] l2_cpu1_wr_partial_dw_arb_set; + wire l2_cpu1_wr_priv_arb_set; + wire [1:0] l2_cpu1_wr_shared_arb_set; + wire [2:0] l2_cpu1_wr_type_arb_set; + wire l2_cpu1_wr_vld_skid; + wire l2_cpu1_wr_way_arb_set; + wire l2_cpu1_wrq_almost_full; + wire [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; + wire l2_cpu1_wrq_haz_pending; + wire l2_cpu2_arb_thrshld_timeout_en; + wire l2_cpu2_barrier_done; + wire l2_cpu2_blk_non_evict_wr; + wire l2_cpu2_ccb_dbg_req_c3; + wire [48:0] l2_cpu2_ccb_req_addr_c3; + wire [4:0] l2_cpu2_ccb_req_id_c3; + wire [23:0] l2_cpu2_ccb_req_info_c3; + wire [8:0] l2_cpu2_ccb_req_type_c3; + wire l2_cpu2_cfg_ecc_en; + wire [2:0] l2_cpu2_dbufid_r1; + wire [129:0] l2_cpu2_ddata_r2; + wire l2_cpu2_ddlb_ecc_err_r3; + wire l2_cpu2_dext_err_r2; + wire l2_cpu2_dext_err_type_r2; + wire l2_cpu2_disable_clean_evict_opt; + wire l2_cpu2_dlast_r1; + wire l2_cpu2_dsngl_ecc_err_r3; + wire [3:0] l2_cpu2_dsq_clr_id_q; + wire l2_cpu2_dsq_clr_vld_q; + wire [3:0] l2_cpu2_dsq_rd_buf_id; + wire [15:0] l2_cpu2_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu2_dsq_rd_data_q; + wire l2_cpu2_dsq_rd_en; + wire l2_cpu2_dsq_rd_en_x2; + wire l2_cpu2_dt_pmu_evt_en; + wire l2_cpu2_dvalid_r1; + wire l2_cpu2_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; + wire l2_cpu2_flsh_if_rd_l4_dly; + wire l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; + wire l2_cpu2_flsh_ls_rd_l2_dly; + wire l2_cpu2_flsh_ls_rd_l4_dly; + wire l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; + wire l2_cpu2_flsh_ls_wr_l2_dly; + wire l2_cpu2_flsh_ls_wr_l4_dly; + wire l2_cpu2_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu2_ibufid_r1; + wire [15:0] l2_cpu2_ic_addr_arb_set; + wire l2_cpu2_ic_arb_fast; + wire l2_cpu2_ic_barrier_stall_q; + wire [43:18] l2_cpu2_ic_base; + wire [31:0] l2_cpu2_ic_data_arb_set; + wire [2:0] l2_cpu2_ic_elem_size_arb_set; + wire l2_cpu2_ic_excl_arb_set; + wire [2:0] l2_cpu2_ic_id_arb_set; + wire l2_cpu2_ic_ns_arb_set; + wire l2_cpu2_ic_vld_skid; + wire l2_cpu2_ic_write_arb_set; + wire [127:0] l2_cpu2_idata_r2; + wire l2_cpu2_idlb_ecc_err_r3; + wire l2_cpu2_idle_block_reqs_q; + wire l2_cpu2_idle_wakeup_q; + wire l2_cpu2_iext_err_r2; + wire l2_cpu2_iext_err_type_r2; + wire l2_cpu2_if_ccb_clken_c3; + wire l2_cpu2_if_ccb_req_c3; + wire l2_cpu2_if_ccb_resp; + wire [4:0] l2_cpu2_if_ccb_resp_id; + wire l2_cpu2_if_sync_done_q; + wire l2_cpu2_if_sync_req; + wire l2_cpu2_ifq_haz_pending; + wire l2_cpu2_isngl_ecc_err_r3; + wire l2_cpu2_ivalid_r1; + wire [1:0] l2_cpu2_l2_cache_size; + wire [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; + wire l2_cpu2_lrq_haz_pending; + wire l2_cpu2_ls_ccb_clken_c3; + wire l2_cpu2_ls_ccb_data_wr; + wire l2_cpu2_ls_ccb_req_c3; + wire l2_cpu2_ls_ccb_resp; + wire [4:0] l2_cpu2_ls_ccb_resp_id; + wire l2_cpu2_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu2_ls_rd_haz_id_arb_q; + wire l2_cpu2_ls_rd_haz_vld_arb_q; + wire l2_cpu2_ls_sync_req; + wire [4:0] l2_cpu2_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu2_ls_wr_data_w2a; + wire l2_cpu2_ls_wr_dirty_w2a; + wire l2_cpu2_ls_wr_err_w2a; + wire [2:0] l2_cpu2_ls_wr_haz_id_arb_q; + wire l2_cpu2_ls_wr_haz_vld_arb_q; + wire l2_cpu2_ls_wr_last_w2a; + wire l2_cpu2_ls_wr_req_w2a; + wire [2:0] l2_cpu2_ls_wr_type_w2a; + wire [12:0] l2_cpu2_mbist1_addr_b1; + wire l2_cpu2_mbist1_all_b1; + wire [3:0] l2_cpu2_mbist1_array_b1; + wire [7:0] l2_cpu2_mbist1_be_b1; + wire l2_cpu2_mbist1_en_b1; + wire l2_cpu2_mbist1_rd_en_b1; + wire l2_cpu2_mbist1_wr_en_b1; + wire l2_cpu2_no_intctrl; + wire l2_cpu2_pf_rd_vld_skid_popped; + wire l2_cpu2_pf_throttle_q; + wire [33:0] l2_cpu2_pmu_events; + wire [2:0] l2_cpu2_rbufid; + wire l2_cpu2_rd_aarch64_arb_set; + wire [44:0] l2_cpu2_rd_addr_arb_set; + wire l2_cpu2_rd_arb; + wire l2_cpu2_rd_arb_fast; + wire [15:8] l2_cpu2_rd_asid_arb_set; + wire l2_cpu2_rd_bypass_arb_set; + wire [2:0] l2_cpu2_rd_bypass_bufid_e5; + wire [2:0] l2_cpu2_rd_bypass_lrq_id_e5; + wire l2_cpu2_rd_bypass_req_can_e5; + wire l2_cpu2_rd_bypass_way_e5; + wire [2:0] l2_cpu2_rd_cache_attr_arb_set; + wire [2:0] l2_cpu2_rd_elem_size_arb_set; + wire l2_cpu2_rd_excl_arb_set; + wire [4:0] l2_cpu2_rd_id_arb_set; + wire [2:0] l2_cpu2_rd_lrq_id_arb_set; + wire [7:0] l2_cpu2_rd_page_attr_arb_set; + wire l2_cpu2_rd_prfm_arb_set; + wire l2_cpu2_rd_priv_arb_set; + wire l2_cpu2_rd_replayed_arb_set; + wire [1:0] l2_cpu2_rd_shared_arb_set; + wire [6:0] l2_cpu2_rd_type_arb_set; + wire l2_cpu2_rd_va48_arb_set; + wire l2_cpu2_rd_vld_skid; + wire l2_cpu2_rd_way_arb_set; + wire l2_cpu2_rexfail; + wire [1:0] l2_cpu2_rstate; + wire l2_cpu2_rvalid; + wire [2:0] l2_cpu2_spec_bufid; + wire l2_cpu2_spec_valid; + wire [63:0] l2_cpu2_spr_rd_data; + wire l2_cpu2_tbw_dbl_ecc_err; + wire [63:0] l2_cpu2_tbw_desc_data; + wire l2_cpu2_tbw_desc_vld; + wire l2_cpu2_tbw_ext_err; + wire l2_cpu2_tbw_ext_err_type; + wire l2_cpu2_tlb_ccb_clken_c3; + wire l2_cpu2_tlb_ccb_req_c3; + wire l2_cpu2_tlb_sync_complete; + wire l2_cpu2_tlb_sync_done_q; + wire l2_cpu2_tlb_sync_req; + wire l2_cpu2_trq_haz_pending; + wire l2_cpu2_tw_ccb_resp; + wire [4:0] l2_cpu2_tw_ccb_resp_id; + wire l2_cpu2_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu2_wr_addr_arb_set; + wire l2_cpu2_wr_arb; + wire l2_cpu2_wr_arb_fast; + wire [2:0] l2_cpu2_wr_cache_attr_arb_set; + wire [11:0] l2_cpu2_wr_cl_id_arb_set; + wire l2_cpu2_wr_clean_evict_arb_set; + wire [143:0] l2_cpu2_wr_data; + wire l2_cpu2_wr_data_stall; + wire l2_cpu2_wr_data_vld_x1_q; + wire l2_cpu2_wr_dirty_arb_set; + wire [2:0] l2_cpu2_wr_elem_size_arb_set; + wire l2_cpu2_wr_err_arb_set; + wire l2_cpu2_wr_evict_x1_q; + wire l2_cpu2_wr_ex_fail; + wire l2_cpu2_wr_ex_resp; + wire [3:0] l2_cpu2_wr_id_arb_set; + wire l2_cpu2_wr_last_arb_set; + wire [7:0] l2_cpu2_wr_page_attr_arb_set; + wire [3:0] l2_cpu2_wr_partial_dw_arb_set; + wire l2_cpu2_wr_priv_arb_set; + wire [1:0] l2_cpu2_wr_shared_arb_set; + wire [2:0] l2_cpu2_wr_type_arb_set; + wire l2_cpu2_wr_vld_skid; + wire l2_cpu2_wr_way_arb_set; + wire l2_cpu2_wrq_almost_full; + wire [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; + wire l2_cpu2_wrq_haz_pending; + wire l2_cpu3_arb_thrshld_timeout_en; + wire l2_cpu3_barrier_done; + wire l2_cpu3_blk_non_evict_wr; + wire l2_cpu3_ccb_dbg_req_c3; + wire [48:0] l2_cpu3_ccb_req_addr_c3; + wire [4:0] l2_cpu3_ccb_req_id_c3; + wire [23:0] l2_cpu3_ccb_req_info_c3; + wire [8:0] l2_cpu3_ccb_req_type_c3; + wire l2_cpu3_cfg_ecc_en; + wire [2:0] l2_cpu3_dbufid_r1; + wire [129:0] l2_cpu3_ddata_r2; + wire l2_cpu3_ddlb_ecc_err_r3; + wire l2_cpu3_dext_err_r2; + wire l2_cpu3_dext_err_type_r2; + wire l2_cpu3_disable_clean_evict_opt; + wire l2_cpu3_dlast_r1; + wire l2_cpu3_dsngl_ecc_err_r3; + wire [3:0] l2_cpu3_dsq_clr_id_q; + wire l2_cpu3_dsq_clr_vld_q; + wire [3:0] l2_cpu3_dsq_rd_buf_id; + wire [15:0] l2_cpu3_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu3_dsq_rd_data_q; + wire l2_cpu3_dsq_rd_en; + wire l2_cpu3_dsq_rd_en_x2; + wire l2_cpu3_dt_pmu_evt_en; + wire l2_cpu3_dvalid_r1; + wire l2_cpu3_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; + wire l2_cpu3_flsh_if_rd_l4_dly; + wire l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; + wire l2_cpu3_flsh_ls_rd_l2_dly; + wire l2_cpu3_flsh_ls_rd_l4_dly; + wire l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; + wire l2_cpu3_flsh_ls_wr_l2_dly; + wire l2_cpu3_flsh_ls_wr_l4_dly; + wire l2_cpu3_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu3_ibufid_r1; + wire [15:0] l2_cpu3_ic_addr_arb_set; + wire l2_cpu3_ic_arb_fast; + wire l2_cpu3_ic_barrier_stall_q; + wire [43:18] l2_cpu3_ic_base; + wire [31:0] l2_cpu3_ic_data_arb_set; + wire [2:0] l2_cpu3_ic_elem_size_arb_set; + wire l2_cpu3_ic_excl_arb_set; + wire [2:0] l2_cpu3_ic_id_arb_set; + wire l2_cpu3_ic_ns_arb_set; + wire l2_cpu3_ic_vld_skid; + wire l2_cpu3_ic_write_arb_set; + wire [127:0] l2_cpu3_idata_r2; + wire l2_cpu3_idlb_ecc_err_r3; + wire l2_cpu3_idle_block_reqs_q; + wire l2_cpu3_idle_wakeup_q; + wire l2_cpu3_iext_err_r2; + wire l2_cpu3_iext_err_type_r2; + wire l2_cpu3_if_ccb_clken_c3; + wire l2_cpu3_if_ccb_req_c3; + wire l2_cpu3_if_ccb_resp; + wire [4:0] l2_cpu3_if_ccb_resp_id; + wire l2_cpu3_if_sync_done_q; + wire l2_cpu3_if_sync_req; + wire l2_cpu3_ifq_haz_pending; + wire l2_cpu3_isngl_ecc_err_r3; + wire l2_cpu3_ivalid_r1; + wire [1:0] l2_cpu3_l2_cache_size; + wire [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; + wire l2_cpu3_lrq_haz_pending; + wire l2_cpu3_ls_ccb_clken_c3; + wire l2_cpu3_ls_ccb_data_wr; + wire l2_cpu3_ls_ccb_req_c3; + wire l2_cpu3_ls_ccb_resp; + wire [4:0] l2_cpu3_ls_ccb_resp_id; + wire l2_cpu3_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu3_ls_rd_haz_id_arb_q; + wire l2_cpu3_ls_rd_haz_vld_arb_q; + wire l2_cpu3_ls_sync_req; + wire [4:0] l2_cpu3_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu3_ls_wr_data_w2a; + wire l2_cpu3_ls_wr_dirty_w2a; + wire l2_cpu3_ls_wr_err_w2a; + wire [2:0] l2_cpu3_ls_wr_haz_id_arb_q; + wire l2_cpu3_ls_wr_haz_vld_arb_q; + wire l2_cpu3_ls_wr_last_w2a; + wire l2_cpu3_ls_wr_req_w2a; + wire [2:0] l2_cpu3_ls_wr_type_w2a; + wire [12:0] l2_cpu3_mbist1_addr_b1; + wire l2_cpu3_mbist1_all_b1; + wire [3:0] l2_cpu3_mbist1_array_b1; + wire [7:0] l2_cpu3_mbist1_be_b1; + wire l2_cpu3_mbist1_en_b1; + wire l2_cpu3_mbist1_rd_en_b1; + wire l2_cpu3_mbist1_wr_en_b1; + wire l2_cpu3_no_intctrl; + wire l2_cpu3_pf_rd_vld_skid_popped; + wire l2_cpu3_pf_throttle_q; + wire [33:0] l2_cpu3_pmu_events; + wire [2:0] l2_cpu3_rbufid; + wire l2_cpu3_rd_aarch64_arb_set; + wire [44:0] l2_cpu3_rd_addr_arb_set; + wire l2_cpu3_rd_arb; + wire l2_cpu3_rd_arb_fast; + wire [15:8] l2_cpu3_rd_asid_arb_set; + wire l2_cpu3_rd_bypass_arb_set; + wire [2:0] l2_cpu3_rd_bypass_bufid_e5; + wire [2:0] l2_cpu3_rd_bypass_lrq_id_e5; + wire l2_cpu3_rd_bypass_req_can_e5; + wire l2_cpu3_rd_bypass_way_e5; + wire [2:0] l2_cpu3_rd_cache_attr_arb_set; + wire [2:0] l2_cpu3_rd_elem_size_arb_set; + wire l2_cpu3_rd_excl_arb_set; + wire [4:0] l2_cpu3_rd_id_arb_set; + wire [2:0] l2_cpu3_rd_lrq_id_arb_set; + wire [7:0] l2_cpu3_rd_page_attr_arb_set; + wire l2_cpu3_rd_prfm_arb_set; + wire l2_cpu3_rd_priv_arb_set; + wire l2_cpu3_rd_replayed_arb_set; + wire [1:0] l2_cpu3_rd_shared_arb_set; + wire [6:0] l2_cpu3_rd_type_arb_set; + wire l2_cpu3_rd_va48_arb_set; + wire l2_cpu3_rd_vld_skid; + wire l2_cpu3_rd_way_arb_set; + wire l2_cpu3_rexfail; + wire [1:0] l2_cpu3_rstate; + wire l2_cpu3_rvalid; + wire [2:0] l2_cpu3_spec_bufid; + wire l2_cpu3_spec_valid; + wire [63:0] l2_cpu3_spr_rd_data; + wire l2_cpu3_tbw_dbl_ecc_err; + wire [63:0] l2_cpu3_tbw_desc_data; + wire l2_cpu3_tbw_desc_vld; + wire l2_cpu3_tbw_ext_err; + wire l2_cpu3_tbw_ext_err_type; + wire l2_cpu3_tlb_ccb_clken_c3; + wire l2_cpu3_tlb_ccb_req_c3; + wire l2_cpu3_tlb_sync_complete; + wire l2_cpu3_tlb_sync_done_q; + wire l2_cpu3_tlb_sync_req; + wire l2_cpu3_trq_haz_pending; + wire l2_cpu3_tw_ccb_resp; + wire [4:0] l2_cpu3_tw_ccb_resp_id; + wire l2_cpu3_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu3_wr_addr_arb_set; + wire l2_cpu3_wr_arb; + wire l2_cpu3_wr_arb_fast; + wire [2:0] l2_cpu3_wr_cache_attr_arb_set; + wire [11:0] l2_cpu3_wr_cl_id_arb_set; + wire l2_cpu3_wr_clean_evict_arb_set; + wire [143:0] l2_cpu3_wr_data; + wire l2_cpu3_wr_data_stall; + wire l2_cpu3_wr_data_vld_x1_q; + wire l2_cpu3_wr_dirty_arb_set; + wire [2:0] l2_cpu3_wr_elem_size_arb_set; + wire l2_cpu3_wr_err_arb_set; + wire l2_cpu3_wr_evict_x1_q; + wire l2_cpu3_wr_ex_fail; + wire l2_cpu3_wr_ex_resp; + wire [3:0] l2_cpu3_wr_id_arb_set; + wire l2_cpu3_wr_last_arb_set; + wire [7:0] l2_cpu3_wr_page_attr_arb_set; + wire [3:0] l2_cpu3_wr_partial_dw_arb_set; + wire l2_cpu3_wr_priv_arb_set; + wire [1:0] l2_cpu3_wr_shared_arb_set; + wire [2:0] l2_cpu3_wr_type_arb_set; + wire l2_cpu3_wr_vld_skid; + wire l2_cpu3_wr_way_arb_set; + wire l2_cpu3_wrq_almost_full; + wire [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; + wire l2_cpu3_wrq_haz_pending; + wire [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu0_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu1_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu2_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu3_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu0_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu1_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu2_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu3_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; + wire ls_cpu0_clrexmon; + wire ls_cpu0_imp_abort_containable; + wire ls_cpu0_imp_abort_dec; + wire ls_cpu0_imp_abort_ecc; + wire ls_cpu0_imp_abort_slv; + wire ls_cpu0_raw_eae_nonsec; + wire ls_cpu0_raw_eae_secure; + wire ls_cpu1_clrexmon; + wire ls_cpu1_imp_abort_containable; + wire ls_cpu1_imp_abort_dec; + wire ls_cpu1_imp_abort_ecc; + wire ls_cpu1_imp_abort_slv; + wire ls_cpu1_raw_eae_nonsec; + wire ls_cpu1_raw_eae_secure; + wire ls_cpu2_clrexmon; + wire ls_cpu2_imp_abort_containable; + wire ls_cpu2_imp_abort_dec; + wire ls_cpu2_imp_abort_ecc; + wire ls_cpu2_imp_abort_slv; + wire ls_cpu2_raw_eae_nonsec; + wire ls_cpu2_raw_eae_secure; + wire ls_cpu3_clrexmon; + wire ls_cpu3_imp_abort_containable; + wire ls_cpu3_imp_abort_dec; + wire ls_cpu3_imp_abort_ecc; + wire ls_cpu3_imp_abort_slv; + wire ls_cpu3_raw_eae_nonsec; + wire ls_cpu3_raw_eae_secure; + wire ncommirq_cpu0_i; + wire ncommirq_cpu1_i; + wire ncommirq_cpu2_i; + wire ncommirq_cpu3_i; + wire ncorereset_cpu0_o; + wire ncorereset_cpu1_o; + wire ncorereset_cpu2_o; + wire ncorereset_cpu3_o; + wire ncpuporeset_cpu0_o; + wire ncpuporeset_cpu1_o; + wire ncpuporeset_cpu2_o; + wire ncpuporeset_cpu3_o; + wire niden_cpu0_o; + wire niden_cpu1_o; + wire niden_cpu2_o; + wire niden_cpu3_o; + wire nmbistreset_cpu0_o; + wire nmbistreset_cpu1_o; + wire nmbistreset_cpu2_o; + wire nmbistreset_cpu3_o; + wire npmuirq_cpu0_i; + wire npmuirq_cpu1_i; + wire npmuirq_cpu2_i; + wire npmuirq_cpu3_i; + wire pm_export_cpu0_i; + wire pm_export_cpu1_i; + wire pm_export_cpu2_i; + wire pm_export_cpu3_i; + wire [24:0] pmuevent_cpu0_i; + wire [24:0] pmuevent_cpu1_i; + wire [24:0] pmuevent_cpu2_i; + wire [24:0] pmuevent_cpu3_i; + wire [43:2] rvbaraddr_cpu0_o; + wire [43:2] rvbaraddr_cpu1_o; + wire [43:2] rvbaraddr_cpu2_o; + wire [43:2] rvbaraddr_cpu3_o; + wire spiden_cpu0_o; + wire spiden_cpu1_o; + wire spiden_cpu2_o; + wire spiden_cpu3_o; + wire spniden_cpu0_o; + wire spniden_cpu1_o; + wire spniden_cpu2_o; + wire spniden_cpu3_o; + wire syncreqm_cpu0_o; + wire syncreqm_cpu1_o; + wire syncreqm_cpu2_o; + wire syncreqm_cpu3_o; + wire [1:0] tm_cpu0_cnthctl_kernel; + wire [3:0] tm_cpu0_cntkctl_usr; + wire [1:0] tm_cpu1_cnthctl_kernel; + wire [3:0] tm_cpu1_cntkctl_usr; + wire [1:0] tm_cpu2_cnthctl_kernel; + wire [3:0] tm_cpu2_cntkctl_usr; + wire [1:0] tm_cpu3_cnthctl_kernel; + wire [3:0] tm_cpu3_cntkctl_usr; + wire [63:0] tsvalueb_cpu0_o; + wire [63:0] tsvalueb_cpu1_o; + wire [63:0] tsvalueb_cpu2_o; + wire [63:0] tsvalueb_cpu3_o; + wire vinithi_cpu0_o; + wire vinithi_cpu1_o; + wire vinithi_cpu2_o; + wire vinithi_cpu3_o; + + maia_cpu ucpu0( // outputs + .afreadym_cpu (afreadym_cpu0_i), + .atbytesm_cpu (atbytesm_cpu0_i[1:0]), + .atdatam_cpu (atdatam_cpu0_i[31:0]), + .atidm_cpu (atidm_cpu0_i[6:0]), + .atvalidm_cpu (atvalidm_cpu0_i), + .commrx_cpu (commrx_cpu0_i), + .commtx_cpu (commtx_cpu0_i), + .dbgack_cpu (dbgack_cpu0_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu0_i), + .dbgrstreq_cpu (dbgrstreq_cpu0_i), + .ds_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_flush (ds_cpu0_flush), + .ds_flush_type (ds_cpu0_flush_type[5:0]), + .ds_hcr_va (ds_cpu0_hcr_va), + .ds_hcr_vf (ds_cpu0_hcr_vf), + .ds_hcr_vi (ds_cpu0_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu0_reset_req), + .ds_sev_req (ds_cpu0_sev_req), + .ds_sevl_req (ds_cpu0_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_wfe_req (ds_cpu0_wfe_req), + .ds_wfi_req (ds_cpu0_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu0_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu0_clrexmon), + .ls_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu0_i), + .npmuirq_cpu (npmuirq_cpu0_i), + .pm_export_cpu (pm_export_cpu0_i), + .pmuevent_cpu (pmuevent_cpu0_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu0_o), + .afvalidm_cpu (afvalidm_cpu0_o), + .atclken_cpu (atclken_cpu0_o), + .atreadym_cpu (atreadym_cpu0_o), + .cfgend_cpu (cfgend_cpu0_o), + .cfgte_cpu (cfgte_cpu0_o), + .ck_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_event_reg (ck_cpu0_event_reg), + .ck_gclkt (ck_gclkt[0]), + .ck_wfe_ack (ck_cpu0_wfe_ack), + .ck_wfi_ack (ck_cpu0_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu0_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu0_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu0_o), + .cpuid (cpuid_cpu0_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu0_o), + .dbgen_cpu (dbgen_cpu0_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu0_o), + .dbgromaddr_cpu (dbgromaddr_cpu0_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu0_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu0_o), + .dftramhold_cpu (dftramhold_cpu0_o), + .dftrstdisable_cpu (dftrstdisable_cpu0_o), + .dftse_cpu (dftse_cpu0_o), + .dt_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu0_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[0]), + .ic_el_change_complete (ic_el_change_complete[0]), + .ic_hcr_change_complete (ic_hcr_change_complete[0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[0]), + .ic_ich_el2_tc (ic_ich_el2_tc[0]), + .ic_nfiq (ic_nfiq[0]), + .ic_nirq (ic_nirq[0]), + .ic_nsei (ic_nsei[0]), + .ic_nvfiq (ic_nvfiq[0]), + .ic_nvirq (ic_nvirq[0]), + .ic_nvsei (ic_nvsei[0]), + .ic_p_valid (ic_p_valid[0]), + .ic_sample_spr (ic_sample_spr[0]), + .ic_scr_change_complete (ic_scr_change_complete[0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[0]), + .ic_sra_el1s_en (ic_sra_el1s_en[0]), + .ic_sra_el2_en (ic_sra_el2_en[0]), + .ic_sra_el3_en (ic_sra_el3_en[0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[0]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu0_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu0_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu0_rexfail), + .l2_cpu_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu0_rvalid), + .l2_cpu_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu0_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu0_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu0_o), + .ncpuporeset_cpu (ncpuporeset_cpu0_o), + .niden_cpu (niden_cpu0_o), + .nmbistreset_cpu (nmbistreset_cpu0_o), + .rvbaraddr_cpu (rvbaraddr_cpu0_o[43:2]), + .spiden_cpu (spiden_cpu0_o), + .spniden_cpu (spniden_cpu0_o), + .syncreqm_cpu (syncreqm_cpu0_o), + .tm_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu0_o[63:0]), + .vinithi_cpu (vinithi_cpu0_o) + ); // ucpu0 + + maia_cpu ucpu1( // outputs + .afreadym_cpu (afreadym_cpu1_i), + .atbytesm_cpu (atbytesm_cpu1_i[1:0]), + .atdatam_cpu (atdatam_cpu1_i[31:0]), + .atidm_cpu (atidm_cpu1_i[6:0]), + .atvalidm_cpu (atvalidm_cpu1_i), + .commrx_cpu (commrx_cpu1_i), + .commtx_cpu (commtx_cpu1_i), + .dbgack_cpu (dbgack_cpu1_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu1_i), + .dbgrstreq_cpu (dbgrstreq_cpu1_i), + .ds_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_flush (ds_cpu1_flush), + .ds_flush_type (ds_cpu1_flush_type[5:0]), + .ds_hcr_va (ds_cpu1_hcr_va), + .ds_hcr_vf (ds_cpu1_hcr_vf), + .ds_hcr_vi (ds_cpu1_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu1_reset_req), + .ds_sev_req (ds_cpu1_sev_req), + .ds_sevl_req (ds_cpu1_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_wfe_req (ds_cpu1_wfe_req), + .ds_wfi_req (ds_cpu1_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu1_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu1_clrexmon), + .ls_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu1_i), + .npmuirq_cpu (npmuirq_cpu1_i), + .pm_export_cpu (pm_export_cpu1_i), + .pmuevent_cpu (pmuevent_cpu1_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu1_o), + .afvalidm_cpu (afvalidm_cpu1_o), + .atclken_cpu (atclken_cpu1_o), + .atreadym_cpu (atreadym_cpu1_o), + .cfgend_cpu (cfgend_cpu1_o), + .cfgte_cpu (cfgte_cpu1_o), + .ck_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_event_reg (ck_cpu1_event_reg), + .ck_gclkt (ck_gclkt[1]), + .ck_wfe_ack (ck_cpu1_wfe_ack), + .ck_wfi_ack (ck_cpu1_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu1_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu1_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu1_o), + .cpuid (cpuid_cpu1_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu1_o), + .dbgen_cpu (dbgen_cpu1_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu1_o), + .dbgromaddr_cpu (dbgromaddr_cpu1_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu1_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu1_o), + .dftramhold_cpu (dftramhold_cpu1_o), + .dftrstdisable_cpu (dftrstdisable_cpu1_o), + .dftse_cpu (dftse_cpu1_o), + .dt_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu1_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[1]), + .ic_el_change_complete (ic_el_change_complete[1]), + .ic_hcr_change_complete (ic_hcr_change_complete[1]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[1]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[1]), + .ic_ich_el2_tc (ic_ich_el2_tc[1]), + .ic_nfiq (ic_nfiq[1]), + .ic_nirq (ic_nirq[1]), + .ic_nsei (ic_nsei[1]), + .ic_nvfiq (ic_nvfiq[1]), + .ic_nvirq (ic_nvirq[1]), + .ic_nvsei (ic_nvsei[1]), + .ic_p_valid (ic_p_valid[1]), + .ic_sample_spr (ic_sample_spr[1]), + .ic_scr_change_complete (ic_scr_change_complete[1]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[1]), + .ic_sra_el1s_en (ic_sra_el1s_en[1]), + .ic_sra_el2_en (ic_sra_el2_en[1]), + .ic_sra_el3_en (ic_sra_el3_en[1]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[1]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[1]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[1]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[1]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu1_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu1_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu1_rexfail), + .l2_cpu_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu1_rvalid), + .l2_cpu_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu1_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu1_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu1_o), + .ncpuporeset_cpu (ncpuporeset_cpu1_o), + .niden_cpu (niden_cpu1_o), + .nmbistreset_cpu (nmbistreset_cpu1_o), + .rvbaraddr_cpu (rvbaraddr_cpu1_o[43:2]), + .spiden_cpu (spiden_cpu1_o), + .spniden_cpu (spniden_cpu1_o), + .syncreqm_cpu (syncreqm_cpu1_o), + .tm_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu1_o[63:0]), + .vinithi_cpu (vinithi_cpu1_o) + ); // ucpu1 + + maia_cpu ucpu2( // outputs + .afreadym_cpu (afreadym_cpu2_i), + .atbytesm_cpu (atbytesm_cpu2_i[1:0]), + .atdatam_cpu (atdatam_cpu2_i[31:0]), + .atidm_cpu (atidm_cpu2_i[6:0]), + .atvalidm_cpu (atvalidm_cpu2_i), + .commrx_cpu (commrx_cpu2_i), + .commtx_cpu (commtx_cpu2_i), + .dbgack_cpu (dbgack_cpu2_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu2_i), + .dbgrstreq_cpu (dbgrstreq_cpu2_i), + .ds_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_flush (ds_cpu2_flush), + .ds_flush_type (ds_cpu2_flush_type[5:0]), + .ds_hcr_va (ds_cpu2_hcr_va), + .ds_hcr_vf (ds_cpu2_hcr_vf), + .ds_hcr_vi (ds_cpu2_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu2_reset_req), + .ds_sev_req (ds_cpu2_sev_req), + .ds_sevl_req (ds_cpu2_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_wfe_req (ds_cpu2_wfe_req), + .ds_wfi_req (ds_cpu2_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu2_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu2_clrexmon), + .ls_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu2_i), + .npmuirq_cpu (npmuirq_cpu2_i), + .pm_export_cpu (pm_export_cpu2_i), + .pmuevent_cpu (pmuevent_cpu2_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu2_o), + .afvalidm_cpu (afvalidm_cpu2_o), + .atclken_cpu (atclken_cpu2_o), + .atreadym_cpu (atreadym_cpu2_o), + .cfgend_cpu (cfgend_cpu2_o), + .cfgte_cpu (cfgte_cpu2_o), + .ck_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_event_reg (ck_cpu2_event_reg), + .ck_gclkt (ck_gclkt[2]), + .ck_wfe_ack (ck_cpu2_wfe_ack), + .ck_wfi_ack (ck_cpu2_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu2_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu2_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu2_o), + .cpuid (cpuid_cpu2_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu2_o), + .dbgen_cpu (dbgen_cpu2_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu2_o), + .dbgromaddr_cpu (dbgromaddr_cpu2_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu2_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu2_o), + .dftramhold_cpu (dftramhold_cpu2_o), + .dftrstdisable_cpu (dftrstdisable_cpu2_o), + .dftse_cpu (dftse_cpu2_o), + .dt_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu2_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[2]), + .ic_el_change_complete (ic_el_change_complete[2]), + .ic_hcr_change_complete (ic_hcr_change_complete[2]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[2]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[2]), + .ic_ich_el2_tc (ic_ich_el2_tc[2]), + .ic_nfiq (ic_nfiq[2]), + .ic_nirq (ic_nirq[2]), + .ic_nsei (ic_nsei[2]), + .ic_nvfiq (ic_nvfiq[2]), + .ic_nvirq (ic_nvirq[2]), + .ic_nvsei (ic_nvsei[2]), + .ic_p_valid (ic_p_valid[2]), + .ic_sample_spr (ic_sample_spr[2]), + .ic_scr_change_complete (ic_scr_change_complete[2]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[2]), + .ic_sra_el1s_en (ic_sra_el1s_en[2]), + .ic_sra_el2_en (ic_sra_el2_en[2]), + .ic_sra_el3_en (ic_sra_el3_en[2]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[2]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[2]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[2]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[2]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu2_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu2_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu2_rexfail), + .l2_cpu_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu2_rvalid), + .l2_cpu_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu2_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu2_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu2_o), + .ncpuporeset_cpu (ncpuporeset_cpu2_o), + .niden_cpu (niden_cpu2_o), + .nmbistreset_cpu (nmbistreset_cpu2_o), + .rvbaraddr_cpu (rvbaraddr_cpu2_o[43:2]), + .spiden_cpu (spiden_cpu2_o), + .spniden_cpu (spniden_cpu2_o), + .syncreqm_cpu (syncreqm_cpu2_o), + .tm_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu2_o[63:0]), + .vinithi_cpu (vinithi_cpu2_o) + ); // ucpu2 + + maia_cpu ucpu3( // outputs + .afreadym_cpu (afreadym_cpu3_i), + .atbytesm_cpu (atbytesm_cpu3_i[1:0]), + .atdatam_cpu (atdatam_cpu3_i[31:0]), + .atidm_cpu (atidm_cpu3_i[6:0]), + .atvalidm_cpu (atvalidm_cpu3_i), + .commrx_cpu (commrx_cpu3_i), + .commtx_cpu (commtx_cpu3_i), + .dbgack_cpu (dbgack_cpu3_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu (dbgrstreq_cpu3_i), + .ds_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_flush (ds_cpu3_flush), + .ds_flush_type (ds_cpu3_flush_type[5:0]), + .ds_hcr_va (ds_cpu3_hcr_va), + .ds_hcr_vf (ds_cpu3_hcr_vf), + .ds_hcr_vi (ds_cpu3_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_ic_scr_change (ds_cpu3_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu3_reset_req), + .ds_sev_req (ds_cpu3_sev_req), + .ds_sevl_req (ds_cpu3_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_wfe_req (ds_cpu3_wfe_req), + .ds_wfi_req (ds_cpu3_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu3_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu3_clrexmon), + .ls_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu3_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu3_i), + .npmuirq_cpu (npmuirq_cpu3_i), + .pm_export_cpu (pm_export_cpu3_i), + .pmuevent_cpu (pmuevent_cpu3_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu3_o), + .afvalidm_cpu (afvalidm_cpu3_o), + .atclken_cpu (atclken_cpu3_o), + .atreadym_cpu (atreadym_cpu3_o), + .cfgend_cpu (cfgend_cpu3_o), + .cfgte_cpu (cfgte_cpu3_o), + .ck_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_event_reg (ck_cpu3_event_reg), + .ck_gclkt (ck_gclkt[3]), + .ck_wfe_ack (ck_cpu3_wfe_ack), + .ck_wfi_ack (ck_cpu3_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu3_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu3_o), + .cpuid (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu3_o), + .dbgen_cpu (dbgen_cpu3_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu3_o), + .dbgromaddr_cpu (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu3_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu3_o), + .dftramhold_cpu (dftramhold_cpu3_o), + .dftrstdisable_cpu (dftrstdisable_cpu3_o), + .dftse_cpu (dftse_cpu3_o), + .dt_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu3_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[3]), + .ic_el_change_complete (ic_el_change_complete[3]), + .ic_hcr_change_complete (ic_hcr_change_complete[3]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[3]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[3]), + .ic_ich_el2_tc (ic_ich_el2_tc[3]), + .ic_nfiq (ic_nfiq[3]), + .ic_nirq (ic_nirq[3]), + .ic_nsei (ic_nsei[3]), + .ic_nvfiq (ic_nvfiq[3]), + .ic_nvirq (ic_nvirq[3]), + .ic_nvsei (ic_nvsei[3]), + .ic_p_valid (ic_p_valid[3]), + .ic_sample_spr (ic_sample_spr[3]), + .ic_scr_change_complete (ic_scr_change_complete[3]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[3]), + .ic_sra_el1s_en (ic_sra_el1s_en[3]), + .ic_sra_el2_en (ic_sra_el2_en[3]), + .ic_sra_el3_en (ic_sra_el3_en[3]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[3]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[3]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[3]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[3]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu3_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu3_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu3_rexfail), + .l2_cpu_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu3_rvalid), + .l2_cpu_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu3_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu3_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu3_o), + .ncpuporeset_cpu (ncpuporeset_cpu3_o), + .niden_cpu (niden_cpu3_o), + .nmbistreset_cpu (nmbistreset_cpu3_o), + .rvbaraddr_cpu (rvbaraddr_cpu3_o[43:2]), + .spiden_cpu (spiden_cpu3_o), + .spniden_cpu (spniden_cpu3_o), + .syncreqm_cpu (syncreqm_cpu3_o), + .tm_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu3_o[63:0]), + .vinithi_cpu (vinithi_cpu3_o) + ); // ucpu3 + + maia_noncpu_feq28 unoncpu( // outputs + .ACREADYM (ACREADYM), + .AFREADYM0 (AFREADYM0), + .AFREADYM1 (AFREADYM1), + .AFREADYM2 (AFREADYM2), + .AFREADYM3 (AFREADYM3), + .ARADDRM (ARADDRM[43:0]), + .ARBARM (ARBARM[1:0]), + .ARBURSTM (ARBURSTM[1:0]), + .ARCACHEM (ARCACHEM[3:0]), + .ARDOMAINM (ARDOMAINM[1:0]), + .ARIDM (ARIDM[6:0]), + .ARLENM (ARLENM[7:0]), + .ARLOCKM (ARLOCKM), + .ARPROTM (ARPROTM[2:0]), + .ARREADYS (ARREADYS), + .ARSIZEM (ARSIZEM[2:0]), + .ARSNOOPM (ARSNOOPM[3:0]), + .ARVALIDM (ARVALIDM), + .ATBYTESM0 (ATBYTESM0[1:0]), + .ATBYTESM1 (ATBYTESM1[1:0]), + .ATBYTESM2 (ATBYTESM2[1:0]), + .ATBYTESM3 (ATBYTESM3[1:0]), + .ATDATAM0 (ATDATAM0[31:0]), + .ATDATAM1 (ATDATAM1[31:0]), + .ATDATAM2 (ATDATAM2[31:0]), + .ATDATAM3 (ATDATAM3[31:0]), + .ATIDM0 (ATIDM0[6:0]), + .ATIDM1 (ATIDM1[6:0]), + .ATIDM2 (ATIDM2[6:0]), + .ATIDM3 (ATIDM3[6:0]), + .ATVALIDM0 (ATVALIDM0), + .ATVALIDM1 (ATVALIDM1), + .ATVALIDM2 (ATVALIDM2), + .ATVALIDM3 (ATVALIDM3), + .AWADDRM (AWADDRM[43:0]), + .AWBARM (AWBARM[1:0]), + .AWBURSTM (AWBURSTM[1:0]), + .AWCACHEM (AWCACHEM[3:0]), + .AWDOMAINM (AWDOMAINM[1:0]), + .AWIDM (AWIDM[6:0]), + .AWLENM (AWLENM[7:0]), + .AWLOCKM (AWLOCKM), + .AWPROTM (AWPROTM[2:0]), + .AWREADYS (AWREADYS), + .AWSIZEM (AWSIZEM[2:0]), + .AWSNOOPM (AWSNOOPM[2:0]), + .AWUNIQUEM (AWUNIQUEM), + .AWVALIDM (AWVALIDM), + .BIDS (BIDS[4:0]), + .BREADYM (BREADYM), + .BRESPS (BRESPS[1:0]), + .BVALIDS (BVALIDS), + .CDDATAM (CDDATAM[127:0]), + .CDLASTM (CDLASTM), + .CDVALIDM (CDVALIDM), + .CLREXMONACK (CLREXMONACK), + .COMMRX (COMMRX[`MAIA_CN:0]), + .COMMTX (COMMTX[`MAIA_CN:0]), + .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), + .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), + .CPUQDENY (CPUQDENY[`MAIA_CN:0]), + .CRRESPM (CRRESPM[4:0]), + .CRVALIDM (CRVALIDM), + .CTICHINACK (CTICHINACK[3:0]), + .CTICHOUT (CTICHOUT[3:0]), + .CTIIRQ (CTIIRQ[`MAIA_CN:0]), + .DBGACK (DBGACK[`MAIA_CN:0]), + .DBGNOPWRDWN (DBGNOPWRDWN[`MAIA_CN:0]), + .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), + .DBGRSTREQ (DBGRSTREQ[`MAIA_CN:0]), + .EVENTO (EVENTO), + .ICCTDATA (ICCTDATA[15:0]), + .ICCTID (ICCTID[1:0]), + .ICCTLAST (ICCTLAST), + .ICCTVALID (ICCTVALID), + .ICDTREADY (ICDTREADY), + .L2FLUSHDONE (L2FLUSHDONE), + .L2QACCEPTn (L2QACCEPTn), + .L2QACTIVE (L2QACTIVE), + .L2QDENY (L2QDENY), + .PMUEVENT0 (PMUEVENT0[24:0]), + .PMUEVENT1 (PMUEVENT1[24:0]), + .PMUEVENT2 (PMUEVENT2[24:0]), + .PMUEVENT3 (PMUEVENT3[24:0]), + .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), + .PRDATADBG (PRDATADBG[31:0]), + .PREADYDBG (PREADYDBG), + .PSLVERRDBG (PSLVERRDBG), + .RACKM (RACKM), + .RDATAS (RDATAS[127:0]), + .RDMEMATTR (RDMEMATTR[7:0]), + .RIDS (RIDS[4:0]), + .RLASTS (RLASTS), + .RREADYM (RREADYM), + .RRESPS (RRESPS[1:0]), + .RVALIDS (RVALIDS), + .SMPEN (SMPEN[`MAIA_CN:0]), + .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), + .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), + .STANDBYWFIL2 (STANDBYWFIL2), + .WACKM (WACKM), + .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), + .WDATAM (WDATAM[127:0]), + .WIDM (WIDM[6:0]), + .WLASTM (WLASTM), + .WREADYS (WREADYS), + .WRMEMATTR (WRMEMATTR[7:0]), + .WSTRBM (WSTRBM[15:0]), + .WVALIDM (WVALIDM), + .aa64naa32_cpu0_o (aa64naa32_cpu0_o), + .aa64naa32_cpu1_o (aa64naa32_cpu1_o), + .aa64naa32_cpu2_o (aa64naa32_cpu2_o), + .aa64naa32_cpu3_o (aa64naa32_cpu3_o), + .afvalidm_cpu0_o (afvalidm_cpu0_o), + .afvalidm_cpu1_o (afvalidm_cpu1_o), + .afvalidm_cpu2_o (afvalidm_cpu2_o), + .afvalidm_cpu3_o (afvalidm_cpu3_o), + .atclken_cpu0_o (atclken_cpu0_o), + .atclken_cpu1_o (atclken_cpu1_o), + .atclken_cpu2_o (atclken_cpu2_o), + .atclken_cpu3_o (atclken_cpu3_o), + .atreadym_cpu0_o (atreadym_cpu0_o), + .atreadym_cpu1_o (atreadym_cpu1_o), + .atreadym_cpu2_o (atreadym_cpu2_o), + .atreadym_cpu3_o (atreadym_cpu3_o), + .cfgend_cpu0_o (cfgend_cpu0_o), + .cfgend_cpu1_o (cfgend_cpu1_o), + .cfgend_cpu2_o (cfgend_cpu2_o), + .cfgend_cpu3_o (cfgend_cpu3_o), + .cfgte_cpu0_o (cfgte_cpu0_o), + .cfgte_cpu1_o (cfgte_cpu1_o), + .cfgte_cpu2_o (cfgte_cpu2_o), + .cfgte_cpu3_o (cfgte_cpu3_o), + .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_cpu0_event_reg (ck_cpu0_event_reg), + .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), + .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), + .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_cpu1_event_reg (ck_cpu1_event_reg), + .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), + .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), + .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_cpu2_event_reg (ck_cpu2_event_reg), + .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), + .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), + .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_cpu3_event_reg (ck_cpu3_event_reg), + .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), + .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), + .ck_gclkt (ck_gclkt[`MAIA_CN:0]), + .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), + .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), + .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), + .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), + .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), + .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), + .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), + .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), + .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), + .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), + .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), + .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), + .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), + .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), + .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu0_o (cryptodisable_cpu0_o), + .cryptodisable_cpu1_o (cryptodisable_cpu1_o), + .cryptodisable_cpu2_o (cryptodisable_cpu2_o), + .cryptodisable_cpu3_o (cryptodisable_cpu3_o), + .dbgen_cpu0_o (dbgen_cpu0_o), + .dbgen_cpu1_o (dbgen_cpu1_o), + .dbgen_cpu2_o (dbgen_cpu2_o), + .dbgen_cpu3_o (dbgen_cpu3_o), + .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), + .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), + .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), + .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), + .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), + .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), + .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), + .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), + .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), + .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), + .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), + .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), + .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), + .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), + .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), + .dftramhold_cpu0_o (dftramhold_cpu0_o), + .dftramhold_cpu1_o (dftramhold_cpu1_o), + .dftramhold_cpu2_o (dftramhold_cpu2_o), + .dftramhold_cpu3_o (dftramhold_cpu3_o), + .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), + .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), + .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), + .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), + .dftse_cpu0_o (dftse_cpu0_o), + .dftse_cpu1_o (dftse_cpu1_o), + .dftse_cpu2_o (dftse_cpu2_o), + .dftse_cpu3_o (dftse_cpu3_o), + .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .giccdisable_cpu0_o (giccdisable_cpu0_o), + .giccdisable_cpu1_o (giccdisable_cpu1_o), + .giccdisable_cpu2_o (giccdisable_cpu2_o), + .giccdisable_cpu3_o (giccdisable_cpu3_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[`MAIA_CN:0]), + .ic_el_change_complete (ic_el_change_complete[`MAIA_CN:0]), + .ic_hcr_change_complete (ic_hcr_change_complete[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq[`MAIA_CN:0]), + .ic_nirq (ic_nirq[`MAIA_CN:0]), + .ic_nsei (ic_nsei[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei[`MAIA_CN:0]), + .ic_p_valid (ic_p_valid[`MAIA_CN:0]), + .ic_sample_spr (ic_sample_spr[`MAIA_CN:0]), + .ic_scr_change_complete (ic_scr_change_complete[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[`MAIA_CN:0]), + .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu0_barrier_done (l2_cpu0_barrier_done), + .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), + .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), + .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu0_rd_arb (l2_cpu0_rd_arb), + .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu0_rexfail (l2_cpu0_rexfail), + .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu0_rvalid (l2_cpu0_rvalid), + .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu0_spec_valid (l2_cpu0_spec_valid), + .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu0_wr_arb (l2_cpu0_wr_arb), + .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu1_barrier_done (l2_cpu1_barrier_done), + .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), + .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), + .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu1_rd_arb (l2_cpu1_rd_arb), + .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu1_rexfail (l2_cpu1_rexfail), + .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu1_rvalid (l2_cpu1_rvalid), + .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu1_spec_valid (l2_cpu1_spec_valid), + .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu1_wr_arb (l2_cpu1_wr_arb), + .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu2_barrier_done (l2_cpu2_barrier_done), + .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), + .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), + .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu2_rd_arb (l2_cpu2_rd_arb), + .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu2_rexfail (l2_cpu2_rexfail), + .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu2_rvalid (l2_cpu2_rvalid), + .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu2_spec_valid (l2_cpu2_spec_valid), + .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu2_wr_arb (l2_cpu2_wr_arb), + .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu3_barrier_done (l2_cpu3_barrier_done), + .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), + .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), + .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu3_rd_arb (l2_cpu3_rd_arb), + .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu3_rexfail (l2_cpu3_rexfail), + .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu3_rvalid (l2_cpu3_rvalid), + .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu3_spec_valid (l2_cpu3_spec_valid), + .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu3_wr_arb (l2_cpu3_wr_arb), + .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), + .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), + .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), + .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), + .nCOMMIRQ (nCOMMIRQ[`MAIA_CN:0]), + .nEXTERRIRQ (nEXTERRIRQ), + .nINTERRIRQ (nINTERRIRQ), + .nPMUIRQ (nPMUIRQ[`MAIA_CN:0]), + .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), + .ncorereset_cpu0_o (ncorereset_cpu0_o), + .ncorereset_cpu1_o (ncorereset_cpu1_o), + .ncorereset_cpu2_o (ncorereset_cpu2_o), + .ncorereset_cpu3_o (ncorereset_cpu3_o), + .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), + .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), + .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), + .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), + .niden_cpu0_o (niden_cpu0_o), + .niden_cpu1_o (niden_cpu1_o), + .niden_cpu2_o (niden_cpu2_o), + .niden_cpu3_o (niden_cpu3_o), + .nmbistreset_cpu0_o (nmbistreset_cpu0_o), + .nmbistreset_cpu1_o (nmbistreset_cpu1_o), + .nmbistreset_cpu2_o (nmbistreset_cpu2_o), + .nmbistreset_cpu3_o (nmbistreset_cpu3_o), + .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), + .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), + .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), + .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), + .spiden_cpu0_o (spiden_cpu0_o), + .spiden_cpu1_o (spiden_cpu1_o), + .spiden_cpu2_o (spiden_cpu2_o), + .spiden_cpu3_o (spiden_cpu3_o), + .spniden_cpu0_o (spniden_cpu0_o), + .spniden_cpu1_o (spniden_cpu1_o), + .spniden_cpu2_o (spniden_cpu2_o), + .spniden_cpu3_o (spniden_cpu3_o), + .syncreqm_cpu0_o (syncreqm_cpu0_o), + .syncreqm_cpu1_o (syncreqm_cpu1_o), + .syncreqm_cpu2_o (syncreqm_cpu2_o), + .syncreqm_cpu3_o (syncreqm_cpu3_o), + .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), + .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), + .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), + .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), + .vinithi_cpu0_o (vinithi_cpu0_o), + .vinithi_cpu1_o (vinithi_cpu1_o), + .vinithi_cpu2_o (vinithi_cpu2_o), + .vinithi_cpu3_o (vinithi_cpu3_o), + + // inputs + .AA64nAA32 (AA64nAA32[`MAIA_CN:0]), + .ACADDRM (ACADDRM[43:0]), + .ACINACTM (ACINACTM), + .ACLKENM (ACLKENM), + .ACLKENS (ACLKENS), + .ACPROTM (ACPROTM[2:0]), + .ACSNOOPM (ACSNOOPM[3:0]), + .ACVALIDM (ACVALIDM), + .AFVALIDM0 (AFVALIDM0), + .AFVALIDM1 (AFVALIDM1), + .AFVALIDM2 (AFVALIDM2), + .AFVALIDM3 (AFVALIDM3), + .AINACTS (AINACTS), + .ARADDRS (ARADDRS[43:0]), + .ARCACHES (ARCACHES[3:0]), + .ARIDS (ARIDS[4:0]), + .ARLENS (ARLENS[7:0]), + .ARPROTS (ARPROTS[2:0]), + .ARREADYM (ARREADYM), + .ARUSERS (ARUSERS[1:0]), + .ARVALIDS (ARVALIDS), + .ATCLKEN (ATCLKEN), + .ATREADYM0 (ATREADYM0), + .ATREADYM1 (ATREADYM1), + .ATREADYM2 (ATREADYM2), + .ATREADYM3 (ATREADYM3), + .AWADDRS (AWADDRS[43:0]), + .AWCACHES (AWCACHES[3:0]), + .AWIDS (AWIDS[4:0]), + .AWLENS (AWLENS[7:0]), + .AWPROTS (AWPROTS[2:0]), + .AWREADYM (AWREADYM), + .AWUSERS (AWUSERS[1:0]), + .AWVALIDS (AWVALIDS), + .BIDM (BIDM[6:0]), + .BREADYS (BREADYS), + .BRESPM (BRESPM[1:0]), + .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), + .BROADCASTINNER (BROADCASTINNER), + .BROADCASTOUTER (BROADCASTOUTER), + .BVALIDM (BVALIDM), + .CDREADYM (CDREADYM), + .CFGEND (CFGEND[`MAIA_CN:0]), + .CFGTE (CFGTE[`MAIA_CN:0]), + .CIHSBYPASS (CIHSBYPASS[3:0]), + .CISBYPASS (CISBYPASS), + .CLK (CLK), + .CLKEN (CLKEN), + .CLREXMONREQ (CLREXMONREQ), + .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), + .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), + .CNTCLKEN (CNTCLKEN), + .CNTVALUEB (CNTVALUEB[63:0]), + .CP15SDISABLE (CP15SDISABLE[`MAIA_CN:0]), + .CPUQREQn (CPUQREQn[`MAIA_CN:0]), + .CRREADYM (CRREADYM), + .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), + .CTICHIN (CTICHIN[3:0]), + .CTICHOUTACK (CTICHOUTACK[3:0]), + .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), + .DBGEN (DBGEN[`MAIA_CN:0]), + .DBGL1RSTDISABLE (DBGL1RSTDISABLE), + .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), + .DBGROMADDR (DBGROMADDR[43:12]), + .DBGROMADDRV (DBGROMADDRV), + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTCRCLKDISABLE (DFTCRCLKDISABLE[`MAIA_CN:0]), + .DFTL2CLKDISABLE (DFTL2CLKDISABLE), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .EDBGRQ (EDBGRQ[`MAIA_CN:0]), + .EVENTI (EVENTI), + .GICCDISABLE (GICCDISABLE), + .ICCTREADY (ICCTREADY), + .ICDTDATA (ICDTDATA[15:0]), + .ICDTDEST (ICDTDEST[1:0]), + .ICDTLAST (ICDTLAST), + .ICDTVALID (ICDTVALID), + .L2FLUSHREQ (L2FLUSHREQ), + .L2QREQn (L2QREQn), + .L2RSTDISABLE (L2RSTDISABLE), + .MBISTREQ (MBISTREQ), + .NIDEN (NIDEN[`MAIA_CN:0]), + .PADDRDBG (PADDRDBG[21:2]), + .PADDRDBG31 (PADDRDBG31), + .PCLKDBG (PCLKDBG), + .PCLKENDBG (PCLKENDBG), + .PENABLEDBG (PENABLEDBG), + .PERIPHBASE (PERIPHBASE[43:18]), + .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), + .PSELDBG (PSELDBG), + .PWDATADBG (PWDATADBG[31:0]), + .PWRITEDBG (PWRITEDBG), + .RDATAM (RDATAM[127:0]), + .RIDM (RIDM[6:0]), + .RLASTM (RLASTM), + .RREADYS (RREADYS), + .RRESPM (RRESPM[3:0]), + .RVALIDM (RVALIDM), + .RVBARADDR0 (RVBARADDR0[43:2]), + .RVBARADDR1 (RVBARADDR1[43:2]), + .RVBARADDR2 (RVBARADDR2[43:2]), + .RVBARADDR3 (RVBARADDR3[43:2]), + .SPIDEN (SPIDEN[`MAIA_CN:0]), + .SPNIDEN (SPNIDEN[`MAIA_CN:0]), + .SYNCREQM0 (SYNCREQM0), + .SYNCREQM1 (SYNCREQM1), + .SYNCREQM2 (SYNCREQM2), + .SYNCREQM3 (SYNCREQM3), + .SYSBARDISABLE (SYSBARDISABLE), + .TSVALUEB (TSVALUEB[63:0]), + .VINITHI (VINITHI[`MAIA_CN:0]), + .WDATAS (WDATAS[127:0]), + .WLASTS (WLASTS), + .WREADYM (WREADYM), + .WSTRBS (WSTRBS[15:0]), + .WVALIDS (WVALIDS), + .afreadym_cpu0_i (afreadym_cpu0_i), + .afreadym_cpu1_i (afreadym_cpu1_i), + .afreadym_cpu2_i (afreadym_cpu2_i), + .afreadym_cpu3_i (afreadym_cpu3_i), + .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), + .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), + .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), + .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), + .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), + .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), + .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), + .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), + .atidm_cpu0_i (atidm_cpu0_i[6:0]), + .atidm_cpu1_i (atidm_cpu1_i[6:0]), + .atidm_cpu2_i (atidm_cpu2_i[6:0]), + .atidm_cpu3_i (atidm_cpu3_i[6:0]), + .atvalidm_cpu0_i (atvalidm_cpu0_i), + .atvalidm_cpu1_i (atvalidm_cpu1_i), + .atvalidm_cpu2_i (atvalidm_cpu2_i), + .atvalidm_cpu3_i (atvalidm_cpu3_i), + .commrx_cpu0_i (commrx_cpu0_i), + .commrx_cpu1_i (commrx_cpu1_i), + .commrx_cpu2_i (commrx_cpu2_i), + .commrx_cpu3_i (commrx_cpu3_i), + .commtx_cpu0_i (commtx_cpu0_i), + .commtx_cpu1_i (commtx_cpu1_i), + .commtx_cpu2_i (commtx_cpu2_i), + .commtx_cpu3_i (commtx_cpu3_i), + .dbgack_cpu0_i (dbgack_cpu0_i), + .dbgack_cpu1_i (dbgack_cpu1_i), + .dbgack_cpu2_i (dbgack_cpu2_i), + .dbgack_cpu3_i (dbgack_cpu3_i), + .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), + .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), + .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), + .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), + .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), + .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), + .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), + .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_cpu0_flush (ds_cpu0_flush), + .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), + .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), + .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu0_reset_req (ds_cpu0_reset_req), + .ds_cpu0_sev_req (ds_cpu0_sev_req), + .ds_cpu0_sevl_req (ds_cpu0_sevl_req), + .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_cpu0_wfe_req (ds_cpu0_wfe_req), + .ds_cpu0_wfi_req (ds_cpu0_wfi_req), + .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_cpu1_flush (ds_cpu1_flush), + .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), + .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), + .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu1_reset_req (ds_cpu1_reset_req), + .ds_cpu1_sev_req (ds_cpu1_sev_req), + .ds_cpu1_sevl_req (ds_cpu1_sevl_req), + .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_cpu1_wfe_req (ds_cpu1_wfe_req), + .ds_cpu1_wfi_req (ds_cpu1_wfi_req), + .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_cpu2_flush (ds_cpu2_flush), + .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), + .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), + .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu2_reset_req (ds_cpu2_reset_req), + .ds_cpu2_sev_req (ds_cpu2_sev_req), + .ds_cpu2_sevl_req (ds_cpu2_sevl_req), + .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_cpu2_wfe_req (ds_cpu2_wfe_req), + .ds_cpu2_wfi_req (ds_cpu2_wfi_req), + .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_cpu3_flush (ds_cpu3_flush), + .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), + .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), + .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), + .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_cpu3_reset_req (ds_cpu3_reset_req), + .ds_cpu3_sev_req (ds_cpu3_sev_req), + .ds_cpu3_sevl_req (ds_cpu3_sevl_req), + .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_cpu3_wfe_req (ds_cpu3_wfe_req), + .ds_cpu3_wfi_req (ds_cpu3_wfi_req), + .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .etclken_cpu0_i (etclken_cpu0_i), + .etclken_cpu1_i (etclken_cpu1_i), + .etclken_cpu2_i (etclken_cpu2_i), + .etclken_cpu3_i (etclken_cpu3_i), + .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .ls_cpu0_clrexmon (ls_cpu0_clrexmon), + .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ls_cpu1_clrexmon (ls_cpu1_clrexmon), + .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ls_cpu2_clrexmon (ls_cpu2_clrexmon), + .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ls_cpu3_clrexmon (ls_cpu3_clrexmon), + .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), + .nCORERESET (nCORERESET[`MAIA_CN:0]), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nFIQ (nFIQ[`MAIA_CN:0]), + .nIRQ (nIRQ[`MAIA_CN:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .nPRESETDBG (nPRESETDBG), + .nREI (nREI[`MAIA_CN:0]), + .nSEI (nSEI[`MAIA_CN:0]), + .nVFIQ (nVFIQ[`MAIA_CN:0]), + .nVIRQ (nVIRQ[`MAIA_CN:0]), + .nVSEI (nVSEI[`MAIA_CN:0]), + .ncommirq_cpu0_i (ncommirq_cpu0_i), + .ncommirq_cpu1_i (ncommirq_cpu1_i), + .ncommirq_cpu2_i (ncommirq_cpu2_i), + .ncommirq_cpu3_i (ncommirq_cpu3_i), + .npmuirq_cpu0_i (npmuirq_cpu0_i), + .npmuirq_cpu1_i (npmuirq_cpu1_i), + .npmuirq_cpu2_i (npmuirq_cpu2_i), + .npmuirq_cpu3_i (npmuirq_cpu3_i), + .pm_export_cpu0_i (pm_export_cpu0_i), + .pm_export_cpu1_i (pm_export_cpu1_i), + .pm_export_cpu2_i (pm_export_cpu2_i), + .pm_export_cpu3_i (pm_export_cpu3_i), + .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), + .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), + .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), + .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]) + ); // unoncpu +endmodule // MAIA_feq28 + + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/MAIA_feq28_s.v b/Security Algo Accelerator/logical/maia/verilog/MAIA_feq28_s.v new file mode 100644 index 0000000000..e3c19e8f3f --- /dev/null +++ b/Security Algo Accelerator/logical/maia/verilog/MAIA_feq28_s.v @@ -0,0 +1,4821 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: MAIA_feq28.v $ +// Checked In : $Date: 2014-10-14 15:20:06 -0500 (Tue, 14 Oct 2014) $ +// Revision : $Revision: 71806 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// +// This is top-level interconnect layer for the MAIA_feq28 top-level. +// + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +`define MAIA_CN 3 + +module MAIA_feq28_s ( + CLK, + CLKEN, + nCPUPORESET, + nCORERESET, + nL2RESET, + L2RSTDISABLE, + WARMRSTREQ, + CFGEND, + VINITHI, + CFGTE, + CP15SDISABLE, + CLUSTERIDAFF1, + CLUSTERIDAFF2, + AA64nAA32, + RVBARADDR0, +// BEGIN INCLUDE FOR CPU1 + RVBARADDR1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + RVBARADDR2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + RVBARADDR3, +// END INCLUDE FOR CPU3 + CRYPTODISABLE, + nFIQ, + nIRQ, + nSEI, + nREI, + nVFIQ, + nVIRQ, + nVSEI, +// BEGIN NO-GIC pins + nVCPUMNTIRQ, +// END NO-GIC pins + PERIPHBASE, +// BEGIN NO-GIC pins + GICCDISABLE, + ICDTVALID, + ICDTREADY, + ICDTDATA, + ICDTLAST, + ICDTDEST, + ICCTVALID, + ICCTREADY, + ICCTDATA, + ICCTLAST, + ICCTID, +// END NO-GIC pins + CNTVALUEB, + CNTCLKEN, + nCNTPNSIRQ, + nCNTPSIRQ, + nCNTVIRQ, + nCNTHPIRQ, + CLREXMONREQ, + CLREXMONACK, + EVENTI, + EVENTO, + STANDBYWFI, + STANDBYWFE, + STANDBYWFIL2, + SMPEN, + CPUQACTIVE, + CPUQREQn, + CPUQACCEPTn, + CPUQDENY, + L2QACTIVE, + L2QREQn, + L2QACCEPTn, + L2QDENY, + L2FLUSHREQ, + L2FLUSHDONE, + nINTERRIRQ, + nEXTERRIRQ, + SYSBARDISABLE, + BROADCASTINNER, + BROADCASTOUTER, + BROADCASTCACHEMAINT, + SCLKEN, + SINACT, + NODEID, + TXSACTIVE, + RXSACTIVE, + TXLINKACTIVEREQ, + TXLINKACTIVEACK, + RXLINKACTIVEREQ, + RXLINKACTIVEACK, + TXREQFLITPEND, + TXREQFLITV, + TXREQFLIT, + REQMEMATTR, + TXREQLCRDV, + TXRSPFLITPEND, + TXRSPFLITV, + TXRSPFLIT, + TXRSPLCRDV, + TXDATFLITPEND, + TXDATFLITV, + TXDATFLIT, + TXDATLCRDV, + RXSNPFLITPEND, + RXSNPFLITV, + RXSNPFLIT, + RXSNPLCRDV, + RXRSPFLITPEND, + RXRSPFLITV, + RXRSPFLIT, + RXRSPLCRDV, + RXDATFLITPEND, + RXDATFLITV, + RXDATFLIT, + RXDATLCRDV, + SAMMNBASE, + SAMADDRMAP0, + SAMADDRMAP1, + SAMADDRMAP2, + SAMADDRMAP3, + SAMADDRMAP4, + SAMADDRMAP5, + SAMADDRMAP6, + SAMADDRMAP7, + SAMADDRMAP8, + SAMADDRMAP9, + SAMADDRMAP10, + SAMADDRMAP11, + SAMADDRMAP12, + SAMADDRMAP13, + SAMADDRMAP14, + SAMADDRMAP15, + SAMADDRMAP16, + SAMADDRMAP17, + SAMADDRMAP18, + SAMADDRMAP19, + SAMMNNODEID, + SAMHNI0NODEID, + SAMHNI1NODEID, + SAMHNF0NODEID, + SAMHNF1NODEID, + SAMHNF2NODEID, + SAMHNF3NODEID, + SAMHNF4NODEID, + SAMHNF5NODEID, + SAMHNF6NODEID, + SAMHNF7NODEID, + SAMHNFMODE, +// BEGIN NO-ACP pins + ACLKENS, + AINACTS, + AWREADYS, + AWVALIDS, + AWIDS, + AWADDRS, + AWLENS, + AWCACHES, + AWUSERS, + AWPROTS, + WREADYS, + WVALIDS, + WDATAS, + WSTRBS, + WLASTS, + BREADYS, + BVALIDS, + BIDS, + BRESPS, + ARREADYS, + ARVALIDS, + ARIDS, + ARADDRS, + ARLENS, + ARCACHES, + ARUSERS, + ARPROTS, + RREADYS, + RVALIDS, + RIDS, + RDATAS, + RRESPS, + RLASTS, +// END NO-ACP pins + DBGROMADDR, + DBGROMADDRV, + DBGACK, + nCOMMIRQ, + COMMRX, + COMMTX, + DBGRSTREQ, + DBGNOPWRDWN, + DBGL1RSTDISABLE, + nPMUIRQ, + PMUEVENT0, +// BEGIN INCLUDE FOR CPU1 + PMUEVENT1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + PMUEVENT2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + PMUEVENT3, +// END INCLUDE FOR CPU3 + ATCLKEN, + TSVALUEB, + ATREADYM0, + AFVALIDM0, + ATDATAM0, + ATVALIDM0, + ATBYTESM0, + AFREADYM0, + ATIDM0, + SYNCREQM0, +// BEGIN INCLUDE FOR CPU1 + ATREADYM1, + AFVALIDM1, + ATDATAM1, + ATVALIDM1, + ATBYTESM1, + AFREADYM1, + ATIDM1, + SYNCREQM1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ATREADYM2, + AFVALIDM2, + ATDATAM2, + ATVALIDM2, + ATBYTESM2, + AFREADYM2, + ATIDM2, + SYNCREQM2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ATREADYM3, + AFVALIDM3, + ATDATAM3, + ATVALIDM3, + ATBYTESM3, + AFREADYM3, + ATIDM3, + SYNCREQM3, +// END INCLUDE FOR CPU3 + PCLKDBG, + PCLKENDBG, + nPRESETDBG, + PSELDBG, + PADDRDBG, + PADDRDBG31, + PENABLEDBG, + PWRITEDBG, + PWDATADBG, + PRDATADBG, + PREADYDBG, + PSLVERRDBG, + EDBGRQ, + PMUSNAPSHOTREQ, + PMUSNAPSHOTACK, + DBGPWRDUP, + DBGPWRUPREQ, + CTICHIN, + CTICHOUTACK, + CTICHOUT, + CTICHINACK, + CISBYPASS, + CIHSBYPASS, + CTIIRQ, + CTIIRQACK, + DBGEN, + NIDEN, + SPIDEN, + SPNIDEN, + DFTSE, + DFTRSTDISABLE, + DFTCRCLKDISABLE, + DFTL2CLKDISABLE, + DFTRAMHOLD, + DFTCLKBYPASS, + DFTMCPHOLD, + nMBISTRESET, + MBISTREQ +); + +//# +//# Interface Signals +//# ================= +//# + +//----------------------------------------------------------------------------- +// Clock and Reset Signals +//----------------------------------------------------------------------------- + input CLK; // Fast Clock + input CLKEN; // Fast Clock Enable + + input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset + input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) + input nL2RESET; // L2 reset + input L2RSTDISABLE; // L2 RAMs hardware reset disable + output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request +//See also nPRESETDBG; // Debug APB reset (PCLK) + +//----------------------------------------------------------------------------- +// Static Configuration Signals +//----------------------------------------------------------------------------- +// Static configuration signals that should be tied off and not change dynamically. +// Many of the initial values specified by these inputs +// may be overridden in software using CP15 registers. + + input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) + input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors + input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) + input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers + + input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] + input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] + + input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) + input [43:2] RVBARADDR0; // RVBAR address +// BEGIN INCLUDE FOR CPU1 + input [43:2] RVBARADDR1; // RVBAR address +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input [43:2] RVBARADDR2; // RVBAR address +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input [43:2] RVBARADDR3; // RVBAR address +// END INCLUDE FOR CPU3 + input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension + +//----------------------------------------------------------------------------- +// Interrupt Controller Signals +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] nFIQ; // Fast Interrupt request + input [`MAIA_CN:0] nIRQ; // Interrupt request + input [`MAIA_CN:0] nSEI; // System Error Interrupt + input [`MAIA_CN:0] nREI; // RAM Error Interrupt + input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request + input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request + input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt + +// BEGIN NO-GIC pins + output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output +// END NO-GIC pins + + input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers +// BEGIN NO-GIC pins + input GICCDISABLE; // Put GIC into bypass mode + + input ICDTVALID; // Distrubuter AXI4 SP Message Valid + output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message + input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data + input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet + input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID + + output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid + input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message + output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data + output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet + output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID +// END NO-GIC pins + +//----------------------------------------------------------------------------- +// Timer Signals +//----------------------------------------------------------------------------- + input [63:0] CNTVALUEB; // Counter value in binary + input CNTCLKEN; // Counter clock enable + output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event + output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event + output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event + output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event + +//----------------------------------------------------------------------------- +// Power Management Signals +//----------------------------------------------------------------------------- + input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) + output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) + input EVENTI; // Event input for processor wake-up from WFE state + output EVENTO; // Event output, signal is active when SEV instruction is executed + output [`MAIA_CN:0] STANDBYWFI; // WFI mode + output [`MAIA_CN:0] STANDBYWFE; // WFE mode + output STANDBYWFIL2; // WFI mode for L2 + output [`MAIA_CN:0] SMPEN; // CPU SMP bit + + output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE + input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn + output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn + output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY + + output L2QACTIVE; // L2 Q-channel QACTIVE + input L2QREQn; // L2 Q-channel QREQn + output L2QACCEPTn; // L2 Q-channel QACCEPTn + output L2QDENY; // L2 Q-channel QDENY + + input L2FLUSHREQ; // L2 hardware flush request + output L2FLUSHDONE; // L2 hardware flush done + +//----------------------------------------------------------------------------- +// Asynchronous Error Signals +//----------------------------------------------------------------------------- + output nINTERRIRQ; // L2 RAM dbl-bit ECC error + output nEXTERRIRQ; // Write transaction error + +//----------------------------------------------------------------------------- +// Bus Configuration Signals +//----------------------------------------------------------------------------- + input SYSBARDISABLE; // Disable broadcast of barriers + input BROADCASTINNER; // Extend Inner Shared Domain + input BROADCASTOUTER; // Extend Outer Shared Domain + input BROADCASTCACHEMAINT; // Broadcast cache maint ops + +//----------------------------------------------------------------------------- +// Skyros RN-F Interface +//----------------------------------------------------------------------------- + input SCLKEN; // Skyros clock enable + input SINACT; // Skyros snoop inactive + + input [6:0] NODEID; // Skyros requestor NodeID + + output TXSACTIVE; // Skyros active - indicates pending activity on pins + input RXSACTIVE; // Skyros active - indicates pending activity on pins + + output TXLINKACTIVEREQ; // Skyros transmit link active request + input TXLINKACTIVEACK; // SKyros transmit link active acknowledge + + input RXLINKACTIVEREQ; // SKyros receive link active request + output RXLINKACTIVEACK; // Skyros receive link active acknowledge + +// TXREQ - outbound requests + output TXREQFLITPEND; // Skyros TXREQ FLIT pending + output TXREQFLITV; // Skyros TXREQ FLIT valid + output [99:0] TXREQFLIT; // Skyros TXREQ FLIT payload + output [7:0] REQMEMATTR; // Skyros TXREQ raw memory attributes + input TXREQLCRDV; // Skyros TXREQ link-layer credit valid + +// TXRSP - outbound response + output TXRSPFLITPEND; // Skyros TXRSP FLIT pending + output TXRSPFLITV; // Skyros TXRSP FLIT valid + output [44:0] TXRSPFLIT; // Skyros TXRSP FLIT payload + input TXRSPLCRDV; // Skyros TXRSP link-layer credit valid + +// TXDAT - outbound data + output TXDATFLITPEND; // Skyros TXDAT FLIT pending + output TXDATFLITV; // Skyros TXDAT FLIT valid + output [193:0] TXDATFLIT; // Skyros TXDAT FLIT payload + input TXDATLCRDV; // Skyros TXDAT link-layer credit valid + +// RXSNP - inbound snoops + input RXSNPFLITPEND; // Skyros RXSNP FLIT pending + input RXSNPFLITV; // Skyros RXSNP FLIT valid + input [64:0] RXSNPFLIT; // Skyros RXSNP FLIT payload + output RXSNPLCRDV; // Skyros RXSNP link-layer credit valid + +// RXRSP - inbound response + input RXRSPFLITPEND; // Skyros RXRSP FLIT pending + input RXRSPFLITV; // Skyros RXRSP FLIT valid + input [44:0] RXRSPFLIT; // Skyros RXRSP FLIT payload + output RXRSPLCRDV; // Skyros RXRSP link-layer credit valid + +// RXDAT - inbound data + input RXDATFLITPEND; // Skyros RXDAT FLIT pending + input RXDATFLITV; // Skyros RXDAT FLIT valid + input [193:0] RXDATFLIT; // Skyros RXDAT FLIT payload + output RXDATLCRDV; // Skyros RXDAT link-layer credit valid + + input [43:24] SAMMNBASE; // Skyros SAM MN base address + input [1:0] SAMADDRMAP0; // Skyros SAM address region 0 mapping + input [1:0] SAMADDRMAP1; // Skyros SAM address region 1 mapping + input [1:0] SAMADDRMAP2; // Skyros SAM address region 2 mapping + input [1:0] SAMADDRMAP3; // Skyros SAM address region 3 mapping + input [1:0] SAMADDRMAP4; // Skyros SAM address region 4 mapping + input [1:0] SAMADDRMAP5; // Skyros SAM address region 5 mapping + input [1:0] SAMADDRMAP6; // Skyros SAM address region 6 mapping + input [1:0] SAMADDRMAP7; // Skyros SAM address region 7 mapping + input [1:0] SAMADDRMAP8; // Skyros SAM address region 8 mapping + input [1:0] SAMADDRMAP9; // Skyros SAM address region 9 mapping + input [1:0] SAMADDRMAP10; // Skyros SAM address region 10 mapping + input [1:0] SAMADDRMAP11; // Skyros SAM address region 11 mapping + input [1:0] SAMADDRMAP12; // Skyros SAM address region 12 mapping + input [1:0] SAMADDRMAP13; // Skyros SAM address region 13 mapping + input [1:0] SAMADDRMAP14; // Skyros SAM address region 14 mapping + input [1:0] SAMADDRMAP15; // Skyros SAM address region 15 mapping + input [1:0] SAMADDRMAP16; // Skyros SAM address region 16 mapping + input [1:0] SAMADDRMAP17; // Skyros SAM address region 17 mapping + input [1:0] SAMADDRMAP18; // Skyros SAM address region 18 mapping + input [1:0] SAMADDRMAP19; // Skyros SAM address region 19 mapping + input [6:0] SAMMNNODEID; // Skyros SAM MN target ID + input [6:0] SAMHNI0NODEID; // Skyros SAM HNI0 target ID + input [6:0] SAMHNI1NODEID; // Skyros SAM HNI1 target ID + input [6:0] SAMHNF0NODEID; // Skyros SAM HNF0 target ID + input [6:0] SAMHNF1NODEID; // Skyros SAM HNF1 target ID + input [6:0] SAMHNF2NODEID; // Skyros SAM HNF2 target ID + input [6:0] SAMHNF3NODEID; // Skyros SAM HNF3 target ID + input [6:0] SAMHNF4NODEID; // Skyros SAM HNF4 target ID + input [6:0] SAMHNF5NODEID; // Skyros SAM HNF5 target ID + input [6:0] SAMHNF6NODEID; // Skyros SAM HNF6 target ID + input [6:0] SAMHNF7NODEID; // Skyros SAM HNF7 target ID + input [2:0] SAMHNFMODE; // Skyros SAM HNF interleaving mode + +// BEGIN NO-ACP pins +//----------------------------------------------------------------------------- +// ACP AXI Slave +//----------------------------------------------------------------------------- + input ACLKENS; // AXI slave clock enable + input AINACTS; // AXI slave interface no longer active or accepting requests + +// Write Address channel signals + output AWREADYS; // Write Address ready (slave ready to accept write address) + input AWVALIDS; // Write Address valid + input [4:0] AWIDS; // Write Address ID + input [43:0] AWADDRS; // Write Address + input [7:0] AWLENS; // Write Burst Length + input [3:0] AWCACHES; // Write Cache type + input [1:0] AWUSERS; // Write inner & outer shareability + input [2:0] AWPROTS; // Write Protection type + +// Write Data channel signals + output WREADYS; // Write Data ready (slave ready to accept data) + input WVALIDS; // Write Data valid + input [127:0] WDATAS; // Write Data + input [15:0] WSTRBS; // Write byte-lane strobes + input WLASTS; // Write Data last transfer indicator + +// Write Response channel signals + input BREADYS; // Write Response ready (master ready to accept response) + output BVALIDS; // Write Response Valid + output [4:0] BIDS; // Write Response ID tag + output [1:0] BRESPS; // Write Response + +// Read Address channel signals + output ARREADYS; // Read Address ready (slave ready to accept read address) + input ARVALIDS; // Read Address valid + input [4:0] ARIDS; // Read Address ID + input [43:0] ARADDRS; // Read Address + input [7:0] ARLENS; // Read Burst Length + input [3:0] ARCACHES; // Read Cache type + input [1:0] ARUSERS; // Read inner & outer shareability + input [2:0] ARPROTS; // Read Protection type + +// Read Data channel signals + input RREADYS; // Read Data ready (master ready to accept data) + output RVALIDS; // Read Data valid + output [4:0] RIDS; // Read Data ID + output [127:0] RDATAS; // Read Data + output [1:0] RRESPS; // Read Data response + output RLASTS; // Read Data last transfer indicator +// END NO-ACP pins +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (CLK) +//----------------------------------------------------------------------------- +// Debug CLK interface + input [43:12] DBGROMADDR; // Debug ROM base address + input DBGROMADDRV; // Debug ROM base address valid + + output [`MAIA_CN:0] DBGACK; // Debug acknowledge + output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt + output [`MAIA_CN:0] COMMRX; // Comms channel receive + output [`MAIA_CN:0] COMMTX; // Comms channel transmit + + output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request + output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request + + input DBGL1RSTDISABLE; // L1 DCache hardware reset disable + +// PMU CLK interface + output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request + output [24:0] PMUEVENT0; // PMU Event bus +// BEGIN INCLUDE FOR CPU1 + output [24:0] PMUEVENT1; // PMU Event bus +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + output [24:0] PMUEVENT2; // PMU Event bus +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + output [24:0] PMUEVENT3; // PMU Event bus +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (ATCLK) +//----------------------------------------------------------------------------- +// ETM ATB interface and Misc signals + input ATCLKEN; // ATB Clock Enable + input [63:0] TSVALUEB; // ATB Timestamp in binary + + input ATREADYM0; // ATDATA can be accepted + input AFVALIDM0; // ATB Fifo Flush Request + output [31:0] ATDATAM0; // ATB Data + output ATVALIDM0; // ATB Data Valid + output [1:0] ATBYTESM0; // ATB Data Size + output AFREADYM0; // ATB Fifo Flush Finished + output [6:0] ATIDM0; // ATB Trace Source ID + input SYNCREQM0; // ATB External synchronization request + +// BEGIN INCLUDE FOR CPU1 + input ATREADYM1; // ATDATA can be accepted + input AFVALIDM1; // ATB Fifo Flush Request + output [31:0] ATDATAM1; // ATB Data + output ATVALIDM1; // ATB Data Valid + output [1:0] ATBYTESM1; // ATB Data Size + output AFREADYM1; // ATB Fifo Flush Finished + output [6:0] ATIDM1; // ATB Trace Source ID + input SYNCREQM1; // ATB External synchronization request +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ATREADYM2; // ATDATA can be accepted + input AFVALIDM2; // ATB Fifo Flush Request + output [31:0] ATDATAM2; // ATB Data + output ATVALIDM2; // ATB Data Valid + output [1:0] ATBYTESM2; // ATB Data Size + output AFREADYM2; // ATB Fifo Flush Finished + output [6:0] ATIDM2; // ATB Trace Source ID + input SYNCREQM2; // ATB External synchronization request +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ATREADYM3; // ATDATA can be accepted + input AFVALIDM3; // ATB Fifo Flush Request + output [31:0] ATDATAM3; // ATB Data + output ATVALIDM3; // ATB Data Valid + output [1:0] ATBYTESM3; // ATB Data Size + output AFREADYM3; // ATB Fifo Flush Finished + output [6:0] ATIDM3; // ATB Trace Source ID + input SYNCREQM3; // ATB External synchronization request +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (PCLK) +//----------------------------------------------------------------------------- +// Debug-APBv3 port (APB) + input PCLKDBG; // APB Clock + input PCLKENDBG; // APB Clock Enable + input nPRESETDBG; // APB Reset + input PSELDBG; // Debug bus access + input [21:2] PADDRDBG; // APB address + input PADDRDBG31; // APB address bit[31] + input PENABLEDBG; // APB transfer complete flag + input PWRITEDBG; // APB read/write indicator + input [31:0] PWDATADBG; // APB write data + output [31:0] PRDATADBG; // APB read data + output PREADYDBG; // APB slave ready, used to extend a transfer + output PSLVERRDBG; // APB slave transfer error + +// Misc interface + input [`MAIA_CN:0] EDBGRQ; // External debug request + +// PMU Snapshot interface + input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request + output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge + +// Power-related interface + input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status + output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request + +// CTI interface + input [3:0] CTICHIN; // Channel In + input [3:0] CTICHOUTACK; // Channel Out acknowledge + output [3:0] CTICHOUT; // Channel Out + output [3:0] CTICHINACK; // Channel In acknowledge + input CISBYPASS; // Channel interface sync bypass + input [3:0] CIHSBYPASS; // Channel interface H/S bypass + output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt + input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge + +//----------------------------------------------------------------------------- +// Debug Authentication Interface (CLK & PCLK) +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] DBGEN; // Invasive debug enable + input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable + input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable + input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable + +//----------------------------------------------------------------------------- +// DFT Signals +//----------------------------------------------------------------------------- + input DFTSE; // Scan enable + input DFTRSTDISABLE; // Disable reset to cells during scan shift + input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr + input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 + input DFTRAMHOLD; // Holds data in RAMs + input DFTCLKBYPASS; // L2 RAM strobe clock bypass + input DFTMCPHOLD; // Disable multi-cycle RAM paths + +//----------------------------------------------------------------------------- +// MBIST Interface +//----------------------------------------------------------------------------- + input nMBISTRESET; // MBIST reset + input MBISTREQ; // MBIST mode request + + + // wires + wire aa64naa32_cpu0_o; + wire aa64naa32_cpu1_o; + wire aa64naa32_cpu2_o; + wire aa64naa32_cpu3_o; + wire afreadym_cpu0_i; + wire afreadym_cpu1_i; + wire afreadym_cpu2_i; + wire afreadym_cpu3_i; + wire afvalidm_cpu0_o; + wire afvalidm_cpu1_o; + wire afvalidm_cpu2_o; + wire afvalidm_cpu3_o; + wire [1:0] atbytesm_cpu0_i; + wire [1:0] atbytesm_cpu1_i; + wire [1:0] atbytesm_cpu2_i; + wire [1:0] atbytesm_cpu3_i; + wire atclken_cpu0_o; + wire atclken_cpu1_o; + wire atclken_cpu2_o; + wire atclken_cpu3_o; + wire [31:0] atdatam_cpu0_i; + wire [31:0] atdatam_cpu1_i; + wire [31:0] atdatam_cpu2_i; + wire [31:0] atdatam_cpu3_i; + wire [6:0] atidm_cpu0_i; + wire [6:0] atidm_cpu1_i; + wire [6:0] atidm_cpu2_i; + wire [6:0] atidm_cpu3_i; + wire atreadym_cpu0_o; + wire atreadym_cpu1_o; + wire atreadym_cpu2_o; + wire atreadym_cpu3_o; + wire atvalidm_cpu0_i; + wire atvalidm_cpu1_i; + wire atvalidm_cpu2_i; + wire atvalidm_cpu3_i; + wire cfgend_cpu0_o; + wire cfgend_cpu1_o; + wire cfgend_cpu2_o; + wire cfgend_cpu3_o; + wire cfgte_cpu0_o; + wire cfgte_cpu1_o; + wire cfgte_cpu2_o; + wire cfgte_cpu3_o; + wire ck_cpu0_crcx_clk_en_n; + wire ck_cpu0_event_reg; + wire ck_cpu0_wfe_ack; + wire ck_cpu0_wfi_ack; + wire ck_cpu1_crcx_clk_en_n; + wire ck_cpu1_event_reg; + wire ck_cpu1_wfe_ack; + wire ck_cpu1_wfi_ack; + wire ck_cpu2_crcx_clk_en_n; + wire ck_cpu2_event_reg; + wire ck_cpu2_wfe_ack; + wire ck_cpu2_wfi_ack; + wire ck_cpu3_crcx_clk_en_n; + wire ck_cpu3_event_reg; + wire ck_cpu3_wfe_ack; + wire ck_cpu3_wfi_ack; + wire [`MAIA_CN:0] ck_gclkt; + wire [7:0] clusteridaff1_cpu0_o; + wire [7:0] clusteridaff1_cpu1_o; + wire [7:0] clusteridaff1_cpu2_o; + wire [7:0] clusteridaff1_cpu3_o; + wire [7:0] clusteridaff2_cpu0_o; + wire [7:0] clusteridaff2_cpu1_o; + wire [7:0] clusteridaff2_cpu2_o; + wire [7:0] clusteridaff2_cpu3_o; + wire commrx_cpu0_i; + wire commrx_cpu1_i; + wire commrx_cpu2_i; + wire commrx_cpu3_i; + wire commtx_cpu0_i; + wire commtx_cpu1_i; + wire commtx_cpu2_i; + wire commtx_cpu3_i; + wire cp15sdisable_cpu0_o; + wire cp15sdisable_cpu1_o; + wire cp15sdisable_cpu2_o; + wire cp15sdisable_cpu3_o; + wire [1:0] cpuid_cpu0_o; + wire [1:0] cpuid_cpu1_o; + wire [1:0] cpuid_cpu2_o; + wire [1:0] cpuid_cpu3_o; + wire cryptodisable_cpu0_o; + wire cryptodisable_cpu1_o; + wire cryptodisable_cpu2_o; + wire cryptodisable_cpu3_o; + wire dbgack_cpu0_i; + wire dbgack_cpu1_i; + wire dbgack_cpu2_i; + wire dbgack_cpu3_i; + wire dbgen_cpu0_o; + wire dbgen_cpu1_o; + wire dbgen_cpu2_o; + wire dbgen_cpu3_o; + wire dbgl1rstdisable_cpu0_o; + wire dbgl1rstdisable_cpu1_o; + wire dbgl1rstdisable_cpu2_o; + wire dbgl1rstdisable_cpu3_o; + wire dbgnopwrdwn_cpu0_i; + wire dbgnopwrdwn_cpu1_i; + wire dbgnopwrdwn_cpu2_i; + wire dbgnopwrdwn_cpu3_i; + wire [43:12] dbgromaddr_cpu0_o; + wire [43:12] dbgromaddr_cpu1_o; + wire [43:12] dbgromaddr_cpu2_o; + wire [43:12] dbgromaddr_cpu3_o; + wire dbgromaddrv_cpu0_o; + wire dbgromaddrv_cpu1_o; + wire dbgromaddrv_cpu2_o; + wire dbgromaddrv_cpu3_o; + wire dbgrstreq_cpu0_i; + wire dbgrstreq_cpu1_i; + wire dbgrstreq_cpu2_i; + wire dbgrstreq_cpu3_i; + wire dftcrclkdisable_cpu0_o; + wire dftcrclkdisable_cpu1_o; + wire dftcrclkdisable_cpu2_o; + wire dftcrclkdisable_cpu3_o; + wire dftramhold_cpu0_o; + wire dftramhold_cpu1_o; + wire dftramhold_cpu2_o; + wire dftramhold_cpu3_o; + wire dftrstdisable_cpu0_o; + wire dftrstdisable_cpu1_o; + wire dftrstdisable_cpu2_o; + wire dftrstdisable_cpu3_o; + wire dftse_cpu0_o; + wire dftse_cpu1_o; + wire dftse_cpu2_o; + wire dftse_cpu3_o; + wire [2:0] ds_cpu0_cpuectlr_ret; + wire ds_cpu0_cpuectlr_smp; + wire ds_cpu0_fiq_wfe_qual; + wire ds_cpu0_fiq_wfi_qual; + wire ds_cpu0_flush; + wire [5:0] ds_cpu0_flush_type; + wire ds_cpu0_hcr_va; + wire ds_cpu0_hcr_vf; + wire ds_cpu0_hcr_vi; + wire ds_cpu0_ic_aa64naa32; + wire [4:0] ds_cpu0_ic_cpsr_mode; + wire ds_cpu0_ic_hcr_change; + wire ds_cpu0_ic_sample_spr; + wire ds_cpu0_ic_scr_change; + wire ds_cpu0_imp_abrt_wfe_qual; + wire ds_cpu0_imp_abrt_wfi_qual; + wire ds_cpu0_irq_wfe_qual; + wire ds_cpu0_irq_wfi_qual; + wire [8:0] ds_cpu0_l2_spr_addr; + wire ds_cpu0_l2_spr_dw; + wire ds_cpu0_l2_spr_en; + wire ds_cpu0_l2_spr_rd; + wire ds_cpu0_l2_spr_wr; + wire [63:0] ds_cpu0_l2_spr_wr_data; + wire ds_cpu0_reset_req; + wire ds_cpu0_sev_req; + wire ds_cpu0_sevl_req; + wire ds_cpu0_vfiq_wfe_qual; + wire ds_cpu0_vfiq_wfi_qual; + wire ds_cpu0_vimp_abrt_wfe_qual; + wire ds_cpu0_vimp_abrt_wfi_qual; + wire ds_cpu0_virq_wfe_qual; + wire ds_cpu0_virq_wfi_qual; + wire ds_cpu0_wfe_req; + wire ds_cpu0_wfi_req; + wire [2:0] ds_cpu1_cpuectlr_ret; + wire ds_cpu1_cpuectlr_smp; + wire ds_cpu1_fiq_wfe_qual; + wire ds_cpu1_fiq_wfi_qual; + wire ds_cpu1_flush; + wire [5:0] ds_cpu1_flush_type; + wire ds_cpu1_hcr_va; + wire ds_cpu1_hcr_vf; + wire ds_cpu1_hcr_vi; + wire ds_cpu1_ic_aa64naa32; + wire [4:0] ds_cpu1_ic_cpsr_mode; + wire ds_cpu1_ic_hcr_change; + wire ds_cpu1_ic_sample_spr; + wire ds_cpu1_ic_scr_change; + wire ds_cpu1_imp_abrt_wfe_qual; + wire ds_cpu1_imp_abrt_wfi_qual; + wire ds_cpu1_irq_wfe_qual; + wire ds_cpu1_irq_wfi_qual; + wire [8:0] ds_cpu1_l2_spr_addr; + wire ds_cpu1_l2_spr_dw; + wire ds_cpu1_l2_spr_en; + wire ds_cpu1_l2_spr_rd; + wire ds_cpu1_l2_spr_wr; + wire [63:0] ds_cpu1_l2_spr_wr_data; + wire ds_cpu1_reset_req; + wire ds_cpu1_sev_req; + wire ds_cpu1_sevl_req; + wire ds_cpu1_vfiq_wfe_qual; + wire ds_cpu1_vfiq_wfi_qual; + wire ds_cpu1_vimp_abrt_wfe_qual; + wire ds_cpu1_vimp_abrt_wfi_qual; + wire ds_cpu1_virq_wfe_qual; + wire ds_cpu1_virq_wfi_qual; + wire ds_cpu1_wfe_req; + wire ds_cpu1_wfi_req; + wire [2:0] ds_cpu2_cpuectlr_ret; + wire ds_cpu2_cpuectlr_smp; + wire ds_cpu2_fiq_wfe_qual; + wire ds_cpu2_fiq_wfi_qual; + wire ds_cpu2_flush; + wire [5:0] ds_cpu2_flush_type; + wire ds_cpu2_hcr_va; + wire ds_cpu2_hcr_vf; + wire ds_cpu2_hcr_vi; + wire ds_cpu2_ic_aa64naa32; + wire [4:0] ds_cpu2_ic_cpsr_mode; + wire ds_cpu2_ic_hcr_change; + wire ds_cpu2_ic_sample_spr; + wire ds_cpu2_ic_scr_change; + wire ds_cpu2_imp_abrt_wfe_qual; + wire ds_cpu2_imp_abrt_wfi_qual; + wire ds_cpu2_irq_wfe_qual; + wire ds_cpu2_irq_wfi_qual; + wire [8:0] ds_cpu2_l2_spr_addr; + wire ds_cpu2_l2_spr_dw; + wire ds_cpu2_l2_spr_en; + wire ds_cpu2_l2_spr_rd; + wire ds_cpu2_l2_spr_wr; + wire [63:0] ds_cpu2_l2_spr_wr_data; + wire ds_cpu2_reset_req; + wire ds_cpu2_sev_req; + wire ds_cpu2_sevl_req; + wire ds_cpu2_vfiq_wfe_qual; + wire ds_cpu2_vfiq_wfi_qual; + wire ds_cpu2_vimp_abrt_wfe_qual; + wire ds_cpu2_vimp_abrt_wfi_qual; + wire ds_cpu2_virq_wfe_qual; + wire ds_cpu2_virq_wfi_qual; + wire ds_cpu2_wfe_req; + wire ds_cpu2_wfi_req; + wire [2:0] ds_cpu3_cpuectlr_ret; + wire ds_cpu3_cpuectlr_smp; + wire ds_cpu3_fiq_wfe_qual; + wire ds_cpu3_fiq_wfi_qual; + wire ds_cpu3_flush; + wire [5:0] ds_cpu3_flush_type; + wire ds_cpu3_hcr_va; + wire ds_cpu3_hcr_vf; + wire ds_cpu3_hcr_vi; + wire ds_cpu3_ic_aa64naa32; + wire [4:0] ds_cpu3_ic_cpsr_mode; + wire ds_cpu3_ic_hcr_change; + wire ds_cpu3_ic_sample_spr; + wire ds_cpu3_ic_scr_change; + wire ds_cpu3_imp_abrt_wfe_qual; + wire ds_cpu3_imp_abrt_wfi_qual; + wire ds_cpu3_irq_wfe_qual; + wire ds_cpu3_irq_wfi_qual; + wire [8:0] ds_cpu3_l2_spr_addr; + wire ds_cpu3_l2_spr_dw; + wire ds_cpu3_l2_spr_en; + wire ds_cpu3_l2_spr_rd; + wire ds_cpu3_l2_spr_wr; + wire [63:0] ds_cpu3_l2_spr_wr_data; + wire ds_cpu3_reset_req; + wire ds_cpu3_sev_req; + wire ds_cpu3_sevl_req; + wire ds_cpu3_vfiq_wfe_qual; + wire ds_cpu3_vfiq_wfi_qual; + wire ds_cpu3_vimp_abrt_wfe_qual; + wire ds_cpu3_vimp_abrt_wfi_qual; + wire ds_cpu3_virq_wfe_qual; + wire ds_cpu3_virq_wfi_qual; + wire ds_cpu3_wfe_req; + wire ds_cpu3_wfi_req; + wire dt_cpu0_coredbg_in_reset_gclk; + wire [1:0] dt_cpu0_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu0_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu0_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu0_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu0_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu0_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; + wire dt_cpu0_cti_trigoutack_bit1_gclk; + wire dt_cpu0_dbif_ack_gclk; + wire [14:2] dt_cpu0_dbif_addr_pclk; + wire dt_cpu0_dbif_err_gclk; + wire dt_cpu0_dbif_locked_pclk; + wire [31:0] dt_cpu0_dbif_rddata_gclk; + wire dt_cpu0_dbif_req_pclk; + wire [31:0] dt_cpu0_dbif_wrdata_pclk; + wire dt_cpu0_dbif_write_pclk; + wire dt_cpu0_edacr_frc_idleack_pclk; + wire dt_cpu0_edbgrq_pclk; + wire dt_cpu0_edecr_osuce_pclk; + wire dt_cpu0_edecr_rce_pclk; + wire dt_cpu0_edecr_ss_pclk; + wire dt_cpu0_edprcr_corepurq_pclk; + wire dt_cpu0_et_oslock_gclk; + wire dt_cpu0_halt_ack_gclk; + wire dt_cpu0_hlt_dbgevt_ok_gclk; + wire dt_cpu0_noclkstop_pclk; + wire dt_cpu0_os_double_lock_gclk; + wire dt_cpu0_pmusnapshot_ack_gclk; + wire dt_cpu0_pmusnapshot_req_pclk; + wire dt_cpu0_wfx_dbg_req_gclk; + wire dt_cpu0_wfx_wakeup_pclk; + wire dt_cpu1_coredbg_in_reset_gclk; + wire [1:0] dt_cpu1_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu1_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu1_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu1_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu1_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu1_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; + wire dt_cpu1_cti_trigoutack_bit1_gclk; + wire dt_cpu1_dbif_ack_gclk; + wire [14:2] dt_cpu1_dbif_addr_pclk; + wire dt_cpu1_dbif_err_gclk; + wire dt_cpu1_dbif_locked_pclk; + wire [31:0] dt_cpu1_dbif_rddata_gclk; + wire dt_cpu1_dbif_req_pclk; + wire [31:0] dt_cpu1_dbif_wrdata_pclk; + wire dt_cpu1_dbif_write_pclk; + wire dt_cpu1_edacr_frc_idleack_pclk; + wire dt_cpu1_edbgrq_pclk; + wire dt_cpu1_edecr_osuce_pclk; + wire dt_cpu1_edecr_rce_pclk; + wire dt_cpu1_edecr_ss_pclk; + wire dt_cpu1_edprcr_corepurq_pclk; + wire dt_cpu1_et_oslock_gclk; + wire dt_cpu1_halt_ack_gclk; + wire dt_cpu1_hlt_dbgevt_ok_gclk; + wire dt_cpu1_noclkstop_pclk; + wire dt_cpu1_os_double_lock_gclk; + wire dt_cpu1_pmusnapshot_ack_gclk; + wire dt_cpu1_pmusnapshot_req_pclk; + wire dt_cpu1_wfx_dbg_req_gclk; + wire dt_cpu1_wfx_wakeup_pclk; + wire dt_cpu2_coredbg_in_reset_gclk; + wire [1:0] dt_cpu2_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu2_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu2_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu2_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu2_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu2_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; + wire dt_cpu2_cti_trigoutack_bit1_gclk; + wire dt_cpu2_dbif_ack_gclk; + wire [14:2] dt_cpu2_dbif_addr_pclk; + wire dt_cpu2_dbif_err_gclk; + wire dt_cpu2_dbif_locked_pclk; + wire [31:0] dt_cpu2_dbif_rddata_gclk; + wire dt_cpu2_dbif_req_pclk; + wire [31:0] dt_cpu2_dbif_wrdata_pclk; + wire dt_cpu2_dbif_write_pclk; + wire dt_cpu2_edacr_frc_idleack_pclk; + wire dt_cpu2_edbgrq_pclk; + wire dt_cpu2_edecr_osuce_pclk; + wire dt_cpu2_edecr_rce_pclk; + wire dt_cpu2_edecr_ss_pclk; + wire dt_cpu2_edprcr_corepurq_pclk; + wire dt_cpu2_et_oslock_gclk; + wire dt_cpu2_halt_ack_gclk; + wire dt_cpu2_hlt_dbgevt_ok_gclk; + wire dt_cpu2_noclkstop_pclk; + wire dt_cpu2_os_double_lock_gclk; + wire dt_cpu2_pmusnapshot_ack_gclk; + wire dt_cpu2_pmusnapshot_req_pclk; + wire dt_cpu2_wfx_dbg_req_gclk; + wire dt_cpu2_wfx_wakeup_pclk; + wire dt_cpu3_coredbg_in_reset_gclk; + wire [1:0] dt_cpu3_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu3_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu3_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu3_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu3_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu3_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; + wire dt_cpu3_cti_trigoutack_bit1_gclk; + wire dt_cpu3_dbif_ack_gclk; + wire [14:2] dt_cpu3_dbif_addr_pclk; + wire dt_cpu3_dbif_err_gclk; + wire dt_cpu3_dbif_locked_pclk; + wire [31:0] dt_cpu3_dbif_rddata_gclk; + wire dt_cpu3_dbif_req_pclk; + wire [31:0] dt_cpu3_dbif_wrdata_pclk; + wire dt_cpu3_dbif_write_pclk; + wire dt_cpu3_edacr_frc_idleack_pclk; + wire dt_cpu3_edbgrq_pclk; + wire dt_cpu3_edecr_osuce_pclk; + wire dt_cpu3_edecr_rce_pclk; + wire dt_cpu3_edecr_ss_pclk; + wire dt_cpu3_edprcr_corepurq_pclk; + wire dt_cpu3_et_oslock_gclk; + wire dt_cpu3_halt_ack_gclk; + wire dt_cpu3_hlt_dbgevt_ok_gclk; + wire dt_cpu3_noclkstop_pclk; + wire dt_cpu3_os_double_lock_gclk; + wire dt_cpu3_pmusnapshot_ack_gclk; + wire dt_cpu3_pmusnapshot_req_pclk; + wire dt_cpu3_wfx_dbg_req_gclk; + wire dt_cpu3_wfx_wakeup_pclk; + wire etclken_cpu0_i; + wire etclken_cpu1_i; + wire etclken_cpu2_i; + wire etclken_cpu3_i; + wire giccdisable_cpu0_o; + wire giccdisable_cpu1_o; + wire giccdisable_cpu2_o; + wire giccdisable_cpu3_o; + wire [`MAIA_CN:0] ic_block_eoi_sgi_wr; + wire [`MAIA_CN:0] ic_el_change_complete; + wire [`MAIA_CN:0] ic_hcr_change_complete; + wire [`MAIA_CN:0] ic_ich_el2_tall0; + wire [`MAIA_CN:0] ic_ich_el2_tall1; + wire [`MAIA_CN:0] ic_ich_el2_tc; + wire [`MAIA_CN:0] ic_nfiq; + wire [`MAIA_CN:0] ic_nirq; + wire [`MAIA_CN:0] ic_nsei; + wire [`MAIA_CN:0] ic_nvfiq; + wire [`MAIA_CN:0] ic_nvirq; + wire [`MAIA_CN:0] ic_nvsei; + wire [`MAIA_CN:0] ic_p_valid; + wire [`MAIA_CN:0] ic_sample_spr; + wire [`MAIA_CN:0] ic_scr_change_complete; + wire [`MAIA_CN:0] ic_sra_el1ns_en; + wire [`MAIA_CN:0] ic_sra_el1s_en; + wire [`MAIA_CN:0] ic_sra_el2_en; + wire [`MAIA_CN:0] ic_sra_el3_en; + wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; + wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap; + wire [`MAIA_CN:0] ic_sre_el1s_mon_trap; + wire [`MAIA_CN:0] ic_sre_el2_mon_trap; + wire l2_cpu0_arb_thrshld_timeout_en; + wire l2_cpu0_barrier_done; + wire l2_cpu0_blk_non_evict_wr; + wire l2_cpu0_ccb_dbg_req_c3; + wire [48:0] l2_cpu0_ccb_req_addr_c3; + wire [4:0] l2_cpu0_ccb_req_id_c3; + wire [23:0] l2_cpu0_ccb_req_info_c3; + wire [8:0] l2_cpu0_ccb_req_type_c3; + wire l2_cpu0_cfg_ecc_en; + wire [2:0] l2_cpu0_dbufid_r1; + wire [129:0] l2_cpu0_ddata_r2; + wire l2_cpu0_ddlb_ecc_err_r3; + wire l2_cpu0_dext_err_r2; + wire l2_cpu0_dext_err_type_r2; + wire l2_cpu0_disable_clean_evict_opt; + wire l2_cpu0_dlast_r1; + wire l2_cpu0_dsngl_ecc_err_r3; + wire [3:0] l2_cpu0_dsq_clr_id_q; + wire l2_cpu0_dsq_clr_vld_q; + wire [3:0] l2_cpu0_dsq_rd_buf_id; + wire [15:0] l2_cpu0_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu0_dsq_rd_data_q; + wire l2_cpu0_dsq_rd_en; + wire l2_cpu0_dsq_rd_en_x2; + wire l2_cpu0_dt_pmu_evt_en; + wire l2_cpu0_dvalid_r1; + wire l2_cpu0_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; + wire l2_cpu0_flsh_if_rd_l4_dly; + wire l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; + wire l2_cpu0_flsh_ls_rd_l2_dly; + wire l2_cpu0_flsh_ls_rd_l4_dly; + wire l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; + wire l2_cpu0_flsh_ls_wr_l2_dly; + wire l2_cpu0_flsh_ls_wr_l4_dly; + wire l2_cpu0_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu0_ibufid_r1; + wire [15:0] l2_cpu0_ic_addr_arb_set; + wire l2_cpu0_ic_arb_fast; + wire l2_cpu0_ic_barrier_stall_q; + wire [43:18] l2_cpu0_ic_base; + wire [31:0] l2_cpu0_ic_data_arb_set; + wire [2:0] l2_cpu0_ic_elem_size_arb_set; + wire l2_cpu0_ic_excl_arb_set; + wire [2:0] l2_cpu0_ic_id_arb_set; + wire l2_cpu0_ic_ns_arb_set; + wire l2_cpu0_ic_vld_skid; + wire l2_cpu0_ic_write_arb_set; + wire [127:0] l2_cpu0_idata_r2; + wire l2_cpu0_idlb_ecc_err_r3; + wire l2_cpu0_idle_block_reqs_q; + wire l2_cpu0_idle_wakeup_q; + wire l2_cpu0_iext_err_r2; + wire l2_cpu0_iext_err_type_r2; + wire l2_cpu0_if_ccb_clken_c3; + wire l2_cpu0_if_ccb_req_c3; + wire l2_cpu0_if_ccb_resp; + wire [4:0] l2_cpu0_if_ccb_resp_id; + wire l2_cpu0_if_sync_done_q; + wire l2_cpu0_if_sync_req; + wire l2_cpu0_ifq_haz_pending; + wire l2_cpu0_isngl_ecc_err_r3; + wire l2_cpu0_ivalid_r1; + wire [1:0] l2_cpu0_l2_cache_size; + wire [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; + wire l2_cpu0_lrq_haz_pending; + wire l2_cpu0_ls_ccb_clken_c3; + wire l2_cpu0_ls_ccb_data_wr; + wire l2_cpu0_ls_ccb_req_c3; + wire l2_cpu0_ls_ccb_resp; + wire [4:0] l2_cpu0_ls_ccb_resp_id; + wire l2_cpu0_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu0_ls_rd_haz_id_arb_q; + wire l2_cpu0_ls_rd_haz_vld_arb_q; + wire l2_cpu0_ls_sync_req; + wire [4:0] l2_cpu0_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu0_ls_wr_data_w2a; + wire l2_cpu0_ls_wr_dirty_w2a; + wire l2_cpu0_ls_wr_err_w2a; + wire [2:0] l2_cpu0_ls_wr_haz_id_arb_q; + wire l2_cpu0_ls_wr_haz_vld_arb_q; + wire l2_cpu0_ls_wr_last_w2a; + wire l2_cpu0_ls_wr_req_w2a; + wire [2:0] l2_cpu0_ls_wr_type_w2a; + wire [12:0] l2_cpu0_mbist1_addr_b1; + wire l2_cpu0_mbist1_all_b1; + wire [3:0] l2_cpu0_mbist1_array_b1; + wire [7:0] l2_cpu0_mbist1_be_b1; + wire l2_cpu0_mbist1_en_b1; + wire l2_cpu0_mbist1_rd_en_b1; + wire l2_cpu0_mbist1_wr_en_b1; + wire l2_cpu0_no_intctrl; + wire l2_cpu0_pf_rd_vld_skid_popped; + wire l2_cpu0_pf_throttle_q; + wire [33:0] l2_cpu0_pmu_events; + wire [2:0] l2_cpu0_rbufid; + wire l2_cpu0_rd_aarch64_arb_set; + wire [44:0] l2_cpu0_rd_addr_arb_set; + wire l2_cpu0_rd_arb; + wire l2_cpu0_rd_arb_fast; + wire [15:8] l2_cpu0_rd_asid_arb_set; + wire l2_cpu0_rd_bypass_arb_set; + wire [2:0] l2_cpu0_rd_bypass_bufid_e5; + wire [2:0] l2_cpu0_rd_bypass_lrq_id_e5; + wire l2_cpu0_rd_bypass_req_can_e5; + wire l2_cpu0_rd_bypass_way_e5; + wire [2:0] l2_cpu0_rd_cache_attr_arb_set; + wire [2:0] l2_cpu0_rd_elem_size_arb_set; + wire l2_cpu0_rd_excl_arb_set; + wire [4:0] l2_cpu0_rd_id_arb_set; + wire [2:0] l2_cpu0_rd_lrq_id_arb_set; + wire [7:0] l2_cpu0_rd_page_attr_arb_set; + wire l2_cpu0_rd_prfm_arb_set; + wire l2_cpu0_rd_priv_arb_set; + wire l2_cpu0_rd_replayed_arb_set; + wire [1:0] l2_cpu0_rd_shared_arb_set; + wire [6:0] l2_cpu0_rd_type_arb_set; + wire l2_cpu0_rd_va48_arb_set; + wire l2_cpu0_rd_vld_skid; + wire l2_cpu0_rd_way_arb_set; + wire l2_cpu0_rexfail; + wire [1:0] l2_cpu0_rstate; + wire l2_cpu0_rvalid; + wire [2:0] l2_cpu0_spec_bufid; + wire l2_cpu0_spec_valid; + wire [63:0] l2_cpu0_spr_rd_data; + wire l2_cpu0_tbw_dbl_ecc_err; + wire [63:0] l2_cpu0_tbw_desc_data; + wire l2_cpu0_tbw_desc_vld; + wire l2_cpu0_tbw_ext_err; + wire l2_cpu0_tbw_ext_err_type; + wire l2_cpu0_tlb_ccb_clken_c3; + wire l2_cpu0_tlb_ccb_req_c3; + wire l2_cpu0_tlb_sync_complete; + wire l2_cpu0_tlb_sync_done_q; + wire l2_cpu0_tlb_sync_req; + wire l2_cpu0_trq_haz_pending; + wire l2_cpu0_tw_ccb_resp; + wire [4:0] l2_cpu0_tw_ccb_resp_id; + wire l2_cpu0_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu0_wr_addr_arb_set; + wire l2_cpu0_wr_arb; + wire l2_cpu0_wr_arb_fast; + wire [2:0] l2_cpu0_wr_cache_attr_arb_set; + wire [11:0] l2_cpu0_wr_cl_id_arb_set; + wire l2_cpu0_wr_clean_evict_arb_set; + wire [143:0] l2_cpu0_wr_data; + wire l2_cpu0_wr_data_stall; + wire l2_cpu0_wr_data_vld_x1_q; + wire l2_cpu0_wr_dirty_arb_set; + wire [2:0] l2_cpu0_wr_elem_size_arb_set; + wire l2_cpu0_wr_err_arb_set; + wire l2_cpu0_wr_evict_x1_q; + wire l2_cpu0_wr_ex_fail; + wire l2_cpu0_wr_ex_resp; + wire [3:0] l2_cpu0_wr_id_arb_set; + wire l2_cpu0_wr_last_arb_set; + wire [7:0] l2_cpu0_wr_page_attr_arb_set; + wire [3:0] l2_cpu0_wr_partial_dw_arb_set; + wire l2_cpu0_wr_priv_arb_set; + wire [1:0] l2_cpu0_wr_shared_arb_set; + wire [2:0] l2_cpu0_wr_type_arb_set; + wire l2_cpu0_wr_vld_skid; + wire l2_cpu0_wr_way_arb_set; + wire l2_cpu0_wrq_almost_full; + wire [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; + wire l2_cpu0_wrq_haz_pending; + wire l2_cpu1_arb_thrshld_timeout_en; + wire l2_cpu1_barrier_done; + wire l2_cpu1_blk_non_evict_wr; + wire l2_cpu1_ccb_dbg_req_c3; + wire [48:0] l2_cpu1_ccb_req_addr_c3; + wire [4:0] l2_cpu1_ccb_req_id_c3; + wire [23:0] l2_cpu1_ccb_req_info_c3; + wire [8:0] l2_cpu1_ccb_req_type_c3; + wire l2_cpu1_cfg_ecc_en; + wire [2:0] l2_cpu1_dbufid_r1; + wire [129:0] l2_cpu1_ddata_r2; + wire l2_cpu1_ddlb_ecc_err_r3; + wire l2_cpu1_dext_err_r2; + wire l2_cpu1_dext_err_type_r2; + wire l2_cpu1_disable_clean_evict_opt; + wire l2_cpu1_dlast_r1; + wire l2_cpu1_dsngl_ecc_err_r3; + wire [3:0] l2_cpu1_dsq_clr_id_q; + wire l2_cpu1_dsq_clr_vld_q; + wire [3:0] l2_cpu1_dsq_rd_buf_id; + wire [15:0] l2_cpu1_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu1_dsq_rd_data_q; + wire l2_cpu1_dsq_rd_en; + wire l2_cpu1_dsq_rd_en_x2; + wire l2_cpu1_dt_pmu_evt_en; + wire l2_cpu1_dvalid_r1; + wire l2_cpu1_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; + wire l2_cpu1_flsh_if_rd_l4_dly; + wire l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; + wire l2_cpu1_flsh_ls_rd_l2_dly; + wire l2_cpu1_flsh_ls_rd_l4_dly; + wire l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; + wire l2_cpu1_flsh_ls_wr_l2_dly; + wire l2_cpu1_flsh_ls_wr_l4_dly; + wire l2_cpu1_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu1_ibufid_r1; + wire [15:0] l2_cpu1_ic_addr_arb_set; + wire l2_cpu1_ic_arb_fast; + wire l2_cpu1_ic_barrier_stall_q; + wire [43:18] l2_cpu1_ic_base; + wire [31:0] l2_cpu1_ic_data_arb_set; + wire [2:0] l2_cpu1_ic_elem_size_arb_set; + wire l2_cpu1_ic_excl_arb_set; + wire [2:0] l2_cpu1_ic_id_arb_set; + wire l2_cpu1_ic_ns_arb_set; + wire l2_cpu1_ic_vld_skid; + wire l2_cpu1_ic_write_arb_set; + wire [127:0] l2_cpu1_idata_r2; + wire l2_cpu1_idlb_ecc_err_r3; + wire l2_cpu1_idle_block_reqs_q; + wire l2_cpu1_idle_wakeup_q; + wire l2_cpu1_iext_err_r2; + wire l2_cpu1_iext_err_type_r2; + wire l2_cpu1_if_ccb_clken_c3; + wire l2_cpu1_if_ccb_req_c3; + wire l2_cpu1_if_ccb_resp; + wire [4:0] l2_cpu1_if_ccb_resp_id; + wire l2_cpu1_if_sync_done_q; + wire l2_cpu1_if_sync_req; + wire l2_cpu1_ifq_haz_pending; + wire l2_cpu1_isngl_ecc_err_r3; + wire l2_cpu1_ivalid_r1; + wire [1:0] l2_cpu1_l2_cache_size; + wire [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; + wire l2_cpu1_lrq_haz_pending; + wire l2_cpu1_ls_ccb_clken_c3; + wire l2_cpu1_ls_ccb_data_wr; + wire l2_cpu1_ls_ccb_req_c3; + wire l2_cpu1_ls_ccb_resp; + wire [4:0] l2_cpu1_ls_ccb_resp_id; + wire l2_cpu1_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu1_ls_rd_haz_id_arb_q; + wire l2_cpu1_ls_rd_haz_vld_arb_q; + wire l2_cpu1_ls_sync_req; + wire [4:0] l2_cpu1_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu1_ls_wr_data_w2a; + wire l2_cpu1_ls_wr_dirty_w2a; + wire l2_cpu1_ls_wr_err_w2a; + wire [2:0] l2_cpu1_ls_wr_haz_id_arb_q; + wire l2_cpu1_ls_wr_haz_vld_arb_q; + wire l2_cpu1_ls_wr_last_w2a; + wire l2_cpu1_ls_wr_req_w2a; + wire [2:0] l2_cpu1_ls_wr_type_w2a; + wire [12:0] l2_cpu1_mbist1_addr_b1; + wire l2_cpu1_mbist1_all_b1; + wire [3:0] l2_cpu1_mbist1_array_b1; + wire [7:0] l2_cpu1_mbist1_be_b1; + wire l2_cpu1_mbist1_en_b1; + wire l2_cpu1_mbist1_rd_en_b1; + wire l2_cpu1_mbist1_wr_en_b1; + wire l2_cpu1_no_intctrl; + wire l2_cpu1_pf_rd_vld_skid_popped; + wire l2_cpu1_pf_throttle_q; + wire [33:0] l2_cpu1_pmu_events; + wire [2:0] l2_cpu1_rbufid; + wire l2_cpu1_rd_aarch64_arb_set; + wire [44:0] l2_cpu1_rd_addr_arb_set; + wire l2_cpu1_rd_arb; + wire l2_cpu1_rd_arb_fast; + wire [15:8] l2_cpu1_rd_asid_arb_set; + wire l2_cpu1_rd_bypass_arb_set; + wire [2:0] l2_cpu1_rd_bypass_bufid_e5; + wire [2:0] l2_cpu1_rd_bypass_lrq_id_e5; + wire l2_cpu1_rd_bypass_req_can_e5; + wire l2_cpu1_rd_bypass_way_e5; + wire [2:0] l2_cpu1_rd_cache_attr_arb_set; + wire [2:0] l2_cpu1_rd_elem_size_arb_set; + wire l2_cpu1_rd_excl_arb_set; + wire [4:0] l2_cpu1_rd_id_arb_set; + wire [2:0] l2_cpu1_rd_lrq_id_arb_set; + wire [7:0] l2_cpu1_rd_page_attr_arb_set; + wire l2_cpu1_rd_prfm_arb_set; + wire l2_cpu1_rd_priv_arb_set; + wire l2_cpu1_rd_replayed_arb_set; + wire [1:0] l2_cpu1_rd_shared_arb_set; + wire [6:0] l2_cpu1_rd_type_arb_set; + wire l2_cpu1_rd_va48_arb_set; + wire l2_cpu1_rd_vld_skid; + wire l2_cpu1_rd_way_arb_set; + wire l2_cpu1_rexfail; + wire [1:0] l2_cpu1_rstate; + wire l2_cpu1_rvalid; + wire [2:0] l2_cpu1_spec_bufid; + wire l2_cpu1_spec_valid; + wire [63:0] l2_cpu1_spr_rd_data; + wire l2_cpu1_tbw_dbl_ecc_err; + wire [63:0] l2_cpu1_tbw_desc_data; + wire l2_cpu1_tbw_desc_vld; + wire l2_cpu1_tbw_ext_err; + wire l2_cpu1_tbw_ext_err_type; + wire l2_cpu1_tlb_ccb_clken_c3; + wire l2_cpu1_tlb_ccb_req_c3; + wire l2_cpu1_tlb_sync_complete; + wire l2_cpu1_tlb_sync_done_q; + wire l2_cpu1_tlb_sync_req; + wire l2_cpu1_trq_haz_pending; + wire l2_cpu1_tw_ccb_resp; + wire [4:0] l2_cpu1_tw_ccb_resp_id; + wire l2_cpu1_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu1_wr_addr_arb_set; + wire l2_cpu1_wr_arb; + wire l2_cpu1_wr_arb_fast; + wire [2:0] l2_cpu1_wr_cache_attr_arb_set; + wire [11:0] l2_cpu1_wr_cl_id_arb_set; + wire l2_cpu1_wr_clean_evict_arb_set; + wire [143:0] l2_cpu1_wr_data; + wire l2_cpu1_wr_data_stall; + wire l2_cpu1_wr_data_vld_x1_q; + wire l2_cpu1_wr_dirty_arb_set; + wire [2:0] l2_cpu1_wr_elem_size_arb_set; + wire l2_cpu1_wr_err_arb_set; + wire l2_cpu1_wr_evict_x1_q; + wire l2_cpu1_wr_ex_fail; + wire l2_cpu1_wr_ex_resp; + wire [3:0] l2_cpu1_wr_id_arb_set; + wire l2_cpu1_wr_last_arb_set; + wire [7:0] l2_cpu1_wr_page_attr_arb_set; + wire [3:0] l2_cpu1_wr_partial_dw_arb_set; + wire l2_cpu1_wr_priv_arb_set; + wire [1:0] l2_cpu1_wr_shared_arb_set; + wire [2:0] l2_cpu1_wr_type_arb_set; + wire l2_cpu1_wr_vld_skid; + wire l2_cpu1_wr_way_arb_set; + wire l2_cpu1_wrq_almost_full; + wire [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; + wire l2_cpu1_wrq_haz_pending; + wire l2_cpu2_arb_thrshld_timeout_en; + wire l2_cpu2_barrier_done; + wire l2_cpu2_blk_non_evict_wr; + wire l2_cpu2_ccb_dbg_req_c3; + wire [48:0] l2_cpu2_ccb_req_addr_c3; + wire [4:0] l2_cpu2_ccb_req_id_c3; + wire [23:0] l2_cpu2_ccb_req_info_c3; + wire [8:0] l2_cpu2_ccb_req_type_c3; + wire l2_cpu2_cfg_ecc_en; + wire [2:0] l2_cpu2_dbufid_r1; + wire [129:0] l2_cpu2_ddata_r2; + wire l2_cpu2_ddlb_ecc_err_r3; + wire l2_cpu2_dext_err_r2; + wire l2_cpu2_dext_err_type_r2; + wire l2_cpu2_disable_clean_evict_opt; + wire l2_cpu2_dlast_r1; + wire l2_cpu2_dsngl_ecc_err_r3; + wire [3:0] l2_cpu2_dsq_clr_id_q; + wire l2_cpu2_dsq_clr_vld_q; + wire [3:0] l2_cpu2_dsq_rd_buf_id; + wire [15:0] l2_cpu2_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu2_dsq_rd_data_q; + wire l2_cpu2_dsq_rd_en; + wire l2_cpu2_dsq_rd_en_x2; + wire l2_cpu2_dt_pmu_evt_en; + wire l2_cpu2_dvalid_r1; + wire l2_cpu2_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; + wire l2_cpu2_flsh_if_rd_l4_dly; + wire l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; + wire l2_cpu2_flsh_ls_rd_l2_dly; + wire l2_cpu2_flsh_ls_rd_l4_dly; + wire l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; + wire l2_cpu2_flsh_ls_wr_l2_dly; + wire l2_cpu2_flsh_ls_wr_l4_dly; + wire l2_cpu2_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu2_ibufid_r1; + wire [15:0] l2_cpu2_ic_addr_arb_set; + wire l2_cpu2_ic_arb_fast; + wire l2_cpu2_ic_barrier_stall_q; + wire [43:18] l2_cpu2_ic_base; + wire [31:0] l2_cpu2_ic_data_arb_set; + wire [2:0] l2_cpu2_ic_elem_size_arb_set; + wire l2_cpu2_ic_excl_arb_set; + wire [2:0] l2_cpu2_ic_id_arb_set; + wire l2_cpu2_ic_ns_arb_set; + wire l2_cpu2_ic_vld_skid; + wire l2_cpu2_ic_write_arb_set; + wire [127:0] l2_cpu2_idata_r2; + wire l2_cpu2_idlb_ecc_err_r3; + wire l2_cpu2_idle_block_reqs_q; + wire l2_cpu2_idle_wakeup_q; + wire l2_cpu2_iext_err_r2; + wire l2_cpu2_iext_err_type_r2; + wire l2_cpu2_if_ccb_clken_c3; + wire l2_cpu2_if_ccb_req_c3; + wire l2_cpu2_if_ccb_resp; + wire [4:0] l2_cpu2_if_ccb_resp_id; + wire l2_cpu2_if_sync_done_q; + wire l2_cpu2_if_sync_req; + wire l2_cpu2_ifq_haz_pending; + wire l2_cpu2_isngl_ecc_err_r3; + wire l2_cpu2_ivalid_r1; + wire [1:0] l2_cpu2_l2_cache_size; + wire [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; + wire l2_cpu2_lrq_haz_pending; + wire l2_cpu2_ls_ccb_clken_c3; + wire l2_cpu2_ls_ccb_data_wr; + wire l2_cpu2_ls_ccb_req_c3; + wire l2_cpu2_ls_ccb_resp; + wire [4:0] l2_cpu2_ls_ccb_resp_id; + wire l2_cpu2_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu2_ls_rd_haz_id_arb_q; + wire l2_cpu2_ls_rd_haz_vld_arb_q; + wire l2_cpu2_ls_sync_req; + wire [4:0] l2_cpu2_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu2_ls_wr_data_w2a; + wire l2_cpu2_ls_wr_dirty_w2a; + wire l2_cpu2_ls_wr_err_w2a; + wire [2:0] l2_cpu2_ls_wr_haz_id_arb_q; + wire l2_cpu2_ls_wr_haz_vld_arb_q; + wire l2_cpu2_ls_wr_last_w2a; + wire l2_cpu2_ls_wr_req_w2a; + wire [2:0] l2_cpu2_ls_wr_type_w2a; + wire [12:0] l2_cpu2_mbist1_addr_b1; + wire l2_cpu2_mbist1_all_b1; + wire [3:0] l2_cpu2_mbist1_array_b1; + wire [7:0] l2_cpu2_mbist1_be_b1; + wire l2_cpu2_mbist1_en_b1; + wire l2_cpu2_mbist1_rd_en_b1; + wire l2_cpu2_mbist1_wr_en_b1; + wire l2_cpu2_no_intctrl; + wire l2_cpu2_pf_rd_vld_skid_popped; + wire l2_cpu2_pf_throttle_q; + wire [33:0] l2_cpu2_pmu_events; + wire [2:0] l2_cpu2_rbufid; + wire l2_cpu2_rd_aarch64_arb_set; + wire [44:0] l2_cpu2_rd_addr_arb_set; + wire l2_cpu2_rd_arb; + wire l2_cpu2_rd_arb_fast; + wire [15:8] l2_cpu2_rd_asid_arb_set; + wire l2_cpu2_rd_bypass_arb_set; + wire [2:0] l2_cpu2_rd_bypass_bufid_e5; + wire [2:0] l2_cpu2_rd_bypass_lrq_id_e5; + wire l2_cpu2_rd_bypass_req_can_e5; + wire l2_cpu2_rd_bypass_way_e5; + wire [2:0] l2_cpu2_rd_cache_attr_arb_set; + wire [2:0] l2_cpu2_rd_elem_size_arb_set; + wire l2_cpu2_rd_excl_arb_set; + wire [4:0] l2_cpu2_rd_id_arb_set; + wire [2:0] l2_cpu2_rd_lrq_id_arb_set; + wire [7:0] l2_cpu2_rd_page_attr_arb_set; + wire l2_cpu2_rd_prfm_arb_set; + wire l2_cpu2_rd_priv_arb_set; + wire l2_cpu2_rd_replayed_arb_set; + wire [1:0] l2_cpu2_rd_shared_arb_set; + wire [6:0] l2_cpu2_rd_type_arb_set; + wire l2_cpu2_rd_va48_arb_set; + wire l2_cpu2_rd_vld_skid; + wire l2_cpu2_rd_way_arb_set; + wire l2_cpu2_rexfail; + wire [1:0] l2_cpu2_rstate; + wire l2_cpu2_rvalid; + wire [2:0] l2_cpu2_spec_bufid; + wire l2_cpu2_spec_valid; + wire [63:0] l2_cpu2_spr_rd_data; + wire l2_cpu2_tbw_dbl_ecc_err; + wire [63:0] l2_cpu2_tbw_desc_data; + wire l2_cpu2_tbw_desc_vld; + wire l2_cpu2_tbw_ext_err; + wire l2_cpu2_tbw_ext_err_type; + wire l2_cpu2_tlb_ccb_clken_c3; + wire l2_cpu2_tlb_ccb_req_c3; + wire l2_cpu2_tlb_sync_complete; + wire l2_cpu2_tlb_sync_done_q; + wire l2_cpu2_tlb_sync_req; + wire l2_cpu2_trq_haz_pending; + wire l2_cpu2_tw_ccb_resp; + wire [4:0] l2_cpu2_tw_ccb_resp_id; + wire l2_cpu2_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu2_wr_addr_arb_set; + wire l2_cpu2_wr_arb; + wire l2_cpu2_wr_arb_fast; + wire [2:0] l2_cpu2_wr_cache_attr_arb_set; + wire [11:0] l2_cpu2_wr_cl_id_arb_set; + wire l2_cpu2_wr_clean_evict_arb_set; + wire [143:0] l2_cpu2_wr_data; + wire l2_cpu2_wr_data_stall; + wire l2_cpu2_wr_data_vld_x1_q; + wire l2_cpu2_wr_dirty_arb_set; + wire [2:0] l2_cpu2_wr_elem_size_arb_set; + wire l2_cpu2_wr_err_arb_set; + wire l2_cpu2_wr_evict_x1_q; + wire l2_cpu2_wr_ex_fail; + wire l2_cpu2_wr_ex_resp; + wire [3:0] l2_cpu2_wr_id_arb_set; + wire l2_cpu2_wr_last_arb_set; + wire [7:0] l2_cpu2_wr_page_attr_arb_set; + wire [3:0] l2_cpu2_wr_partial_dw_arb_set; + wire l2_cpu2_wr_priv_arb_set; + wire [1:0] l2_cpu2_wr_shared_arb_set; + wire [2:0] l2_cpu2_wr_type_arb_set; + wire l2_cpu2_wr_vld_skid; + wire l2_cpu2_wr_way_arb_set; + wire l2_cpu2_wrq_almost_full; + wire [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; + wire l2_cpu2_wrq_haz_pending; + wire l2_cpu3_arb_thrshld_timeout_en; + wire l2_cpu3_barrier_done; + wire l2_cpu3_blk_non_evict_wr; + wire l2_cpu3_ccb_dbg_req_c3; + wire [48:0] l2_cpu3_ccb_req_addr_c3; + wire [4:0] l2_cpu3_ccb_req_id_c3; + wire [23:0] l2_cpu3_ccb_req_info_c3; + wire [8:0] l2_cpu3_ccb_req_type_c3; + wire l2_cpu3_cfg_ecc_en; + wire [2:0] l2_cpu3_dbufid_r1; + wire [129:0] l2_cpu3_ddata_r2; + wire l2_cpu3_ddlb_ecc_err_r3; + wire l2_cpu3_dext_err_r2; + wire l2_cpu3_dext_err_type_r2; + wire l2_cpu3_disable_clean_evict_opt; + wire l2_cpu3_dlast_r1; + wire l2_cpu3_dsngl_ecc_err_r3; + wire [3:0] l2_cpu3_dsq_clr_id_q; + wire l2_cpu3_dsq_clr_vld_q; + wire [3:0] l2_cpu3_dsq_rd_buf_id; + wire [15:0] l2_cpu3_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu3_dsq_rd_data_q; + wire l2_cpu3_dsq_rd_en; + wire l2_cpu3_dsq_rd_en_x2; + wire l2_cpu3_dt_pmu_evt_en; + wire l2_cpu3_dvalid_r1; + wire l2_cpu3_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; + wire l2_cpu3_flsh_if_rd_l4_dly; + wire l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; + wire l2_cpu3_flsh_ls_rd_l2_dly; + wire l2_cpu3_flsh_ls_rd_l4_dly; + wire l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; + wire l2_cpu3_flsh_ls_wr_l2_dly; + wire l2_cpu3_flsh_ls_wr_l4_dly; + wire l2_cpu3_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu3_ibufid_r1; + wire [15:0] l2_cpu3_ic_addr_arb_set; + wire l2_cpu3_ic_arb_fast; + wire l2_cpu3_ic_barrier_stall_q; + wire [43:18] l2_cpu3_ic_base; + wire [31:0] l2_cpu3_ic_data_arb_set; + wire [2:0] l2_cpu3_ic_elem_size_arb_set; + wire l2_cpu3_ic_excl_arb_set; + wire [2:0] l2_cpu3_ic_id_arb_set; + wire l2_cpu3_ic_ns_arb_set; + wire l2_cpu3_ic_vld_skid; + wire l2_cpu3_ic_write_arb_set; + wire [127:0] l2_cpu3_idata_r2; + wire l2_cpu3_idlb_ecc_err_r3; + wire l2_cpu3_idle_block_reqs_q; + wire l2_cpu3_idle_wakeup_q; + wire l2_cpu3_iext_err_r2; + wire l2_cpu3_iext_err_type_r2; + wire l2_cpu3_if_ccb_clken_c3; + wire l2_cpu3_if_ccb_req_c3; + wire l2_cpu3_if_ccb_resp; + wire [4:0] l2_cpu3_if_ccb_resp_id; + wire l2_cpu3_if_sync_done_q; + wire l2_cpu3_if_sync_req; + wire l2_cpu3_ifq_haz_pending; + wire l2_cpu3_isngl_ecc_err_r3; + wire l2_cpu3_ivalid_r1; + wire [1:0] l2_cpu3_l2_cache_size; + wire [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; + wire l2_cpu3_lrq_haz_pending; + wire l2_cpu3_ls_ccb_clken_c3; + wire l2_cpu3_ls_ccb_data_wr; + wire l2_cpu3_ls_ccb_req_c3; + wire l2_cpu3_ls_ccb_resp; + wire [4:0] l2_cpu3_ls_ccb_resp_id; + wire l2_cpu3_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu3_ls_rd_haz_id_arb_q; + wire l2_cpu3_ls_rd_haz_vld_arb_q; + wire l2_cpu3_ls_sync_req; + wire [4:0] l2_cpu3_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu3_ls_wr_data_w2a; + wire l2_cpu3_ls_wr_dirty_w2a; + wire l2_cpu3_ls_wr_err_w2a; + wire [2:0] l2_cpu3_ls_wr_haz_id_arb_q; + wire l2_cpu3_ls_wr_haz_vld_arb_q; + wire l2_cpu3_ls_wr_last_w2a; + wire l2_cpu3_ls_wr_req_w2a; + wire [2:0] l2_cpu3_ls_wr_type_w2a; + wire [12:0] l2_cpu3_mbist1_addr_b1; + wire l2_cpu3_mbist1_all_b1; + wire [3:0] l2_cpu3_mbist1_array_b1; + wire [7:0] l2_cpu3_mbist1_be_b1; + wire l2_cpu3_mbist1_en_b1; + wire l2_cpu3_mbist1_rd_en_b1; + wire l2_cpu3_mbist1_wr_en_b1; + wire l2_cpu3_no_intctrl; + wire l2_cpu3_pf_rd_vld_skid_popped; + wire l2_cpu3_pf_throttle_q; + wire [33:0] l2_cpu3_pmu_events; + wire [2:0] l2_cpu3_rbufid; + wire l2_cpu3_rd_aarch64_arb_set; + wire [44:0] l2_cpu3_rd_addr_arb_set; + wire l2_cpu3_rd_arb; + wire l2_cpu3_rd_arb_fast; + wire [15:8] l2_cpu3_rd_asid_arb_set; + wire l2_cpu3_rd_bypass_arb_set; + wire [2:0] l2_cpu3_rd_bypass_bufid_e5; + wire [2:0] l2_cpu3_rd_bypass_lrq_id_e5; + wire l2_cpu3_rd_bypass_req_can_e5; + wire l2_cpu3_rd_bypass_way_e5; + wire [2:0] l2_cpu3_rd_cache_attr_arb_set; + wire [2:0] l2_cpu3_rd_elem_size_arb_set; + wire l2_cpu3_rd_excl_arb_set; + wire [4:0] l2_cpu3_rd_id_arb_set; + wire [2:0] l2_cpu3_rd_lrq_id_arb_set; + wire [7:0] l2_cpu3_rd_page_attr_arb_set; + wire l2_cpu3_rd_prfm_arb_set; + wire l2_cpu3_rd_priv_arb_set; + wire l2_cpu3_rd_replayed_arb_set; + wire [1:0] l2_cpu3_rd_shared_arb_set; + wire [6:0] l2_cpu3_rd_type_arb_set; + wire l2_cpu3_rd_va48_arb_set; + wire l2_cpu3_rd_vld_skid; + wire l2_cpu3_rd_way_arb_set; + wire l2_cpu3_rexfail; + wire [1:0] l2_cpu3_rstate; + wire l2_cpu3_rvalid; + wire [2:0] l2_cpu3_spec_bufid; + wire l2_cpu3_spec_valid; + wire [63:0] l2_cpu3_spr_rd_data; + wire l2_cpu3_tbw_dbl_ecc_err; + wire [63:0] l2_cpu3_tbw_desc_data; + wire l2_cpu3_tbw_desc_vld; + wire l2_cpu3_tbw_ext_err; + wire l2_cpu3_tbw_ext_err_type; + wire l2_cpu3_tlb_ccb_clken_c3; + wire l2_cpu3_tlb_ccb_req_c3; + wire l2_cpu3_tlb_sync_complete; + wire l2_cpu3_tlb_sync_done_q; + wire l2_cpu3_tlb_sync_req; + wire l2_cpu3_trq_haz_pending; + wire l2_cpu3_tw_ccb_resp; + wire [4:0] l2_cpu3_tw_ccb_resp_id; + wire l2_cpu3_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu3_wr_addr_arb_set; + wire l2_cpu3_wr_arb; + wire l2_cpu3_wr_arb_fast; + wire [2:0] l2_cpu3_wr_cache_attr_arb_set; + wire [11:0] l2_cpu3_wr_cl_id_arb_set; + wire l2_cpu3_wr_clean_evict_arb_set; + wire [143:0] l2_cpu3_wr_data; + wire l2_cpu3_wr_data_stall; + wire l2_cpu3_wr_data_vld_x1_q; + wire l2_cpu3_wr_dirty_arb_set; + wire [2:0] l2_cpu3_wr_elem_size_arb_set; + wire l2_cpu3_wr_err_arb_set; + wire l2_cpu3_wr_evict_x1_q; + wire l2_cpu3_wr_ex_fail; + wire l2_cpu3_wr_ex_resp; + wire [3:0] l2_cpu3_wr_id_arb_set; + wire l2_cpu3_wr_last_arb_set; + wire [7:0] l2_cpu3_wr_page_attr_arb_set; + wire [3:0] l2_cpu3_wr_partial_dw_arb_set; + wire l2_cpu3_wr_priv_arb_set; + wire [1:0] l2_cpu3_wr_shared_arb_set; + wire [2:0] l2_cpu3_wr_type_arb_set; + wire l2_cpu3_wr_vld_skid; + wire l2_cpu3_wr_way_arb_set; + wire l2_cpu3_wrq_almost_full; + wire [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; + wire l2_cpu3_wrq_haz_pending; + wire [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu0_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu1_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu2_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu3_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu0_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu1_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu2_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu3_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; + wire ls_cpu0_clrexmon; + wire ls_cpu0_imp_abort_containable; + wire ls_cpu0_imp_abort_dec; + wire ls_cpu0_imp_abort_ecc; + wire ls_cpu0_imp_abort_slv; + wire ls_cpu0_raw_eae_nonsec; + wire ls_cpu0_raw_eae_secure; + wire ls_cpu1_clrexmon; + wire ls_cpu1_imp_abort_containable; + wire ls_cpu1_imp_abort_dec; + wire ls_cpu1_imp_abort_ecc; + wire ls_cpu1_imp_abort_slv; + wire ls_cpu1_raw_eae_nonsec; + wire ls_cpu1_raw_eae_secure; + wire ls_cpu2_clrexmon; + wire ls_cpu2_imp_abort_containable; + wire ls_cpu2_imp_abort_dec; + wire ls_cpu2_imp_abort_ecc; + wire ls_cpu2_imp_abort_slv; + wire ls_cpu2_raw_eae_nonsec; + wire ls_cpu2_raw_eae_secure; + wire ls_cpu3_clrexmon; + wire ls_cpu3_imp_abort_containable; + wire ls_cpu3_imp_abort_dec; + wire ls_cpu3_imp_abort_ecc; + wire ls_cpu3_imp_abort_slv; + wire ls_cpu3_raw_eae_nonsec; + wire ls_cpu3_raw_eae_secure; + wire ncommirq_cpu0_i; + wire ncommirq_cpu1_i; + wire ncommirq_cpu2_i; + wire ncommirq_cpu3_i; + wire ncorereset_cpu0_o; + wire ncorereset_cpu1_o; + wire ncorereset_cpu2_o; + wire ncorereset_cpu3_o; + wire ncpuporeset_cpu0_o; + wire ncpuporeset_cpu1_o; + wire ncpuporeset_cpu2_o; + wire ncpuporeset_cpu3_o; + wire niden_cpu0_o; + wire niden_cpu1_o; + wire niden_cpu2_o; + wire niden_cpu3_o; + wire nmbistreset_cpu0_o; + wire nmbistreset_cpu1_o; + wire nmbistreset_cpu2_o; + wire nmbistreset_cpu3_o; + wire npmuirq_cpu0_i; + wire npmuirq_cpu1_i; + wire npmuirq_cpu2_i; + wire npmuirq_cpu3_i; + wire pm_export_cpu0_i; + wire pm_export_cpu1_i; + wire pm_export_cpu2_i; + wire pm_export_cpu3_i; + wire [24:0] pmuevent_cpu0_i; + wire [24:0] pmuevent_cpu1_i; + wire [24:0] pmuevent_cpu2_i; + wire [24:0] pmuevent_cpu3_i; + wire [43:2] rvbaraddr_cpu0_o; + wire [43:2] rvbaraddr_cpu1_o; + wire [43:2] rvbaraddr_cpu2_o; + wire [43:2] rvbaraddr_cpu3_o; + wire spiden_cpu0_o; + wire spiden_cpu1_o; + wire spiden_cpu2_o; + wire spiden_cpu3_o; + wire spniden_cpu0_o; + wire spniden_cpu1_o; + wire spniden_cpu2_o; + wire spniden_cpu3_o; + wire syncreqm_cpu0_o; + wire syncreqm_cpu1_o; + wire syncreqm_cpu2_o; + wire syncreqm_cpu3_o; + wire [1:0] tm_cpu0_cnthctl_kernel; + wire [3:0] tm_cpu0_cntkctl_usr; + wire [1:0] tm_cpu1_cnthctl_kernel; + wire [3:0] tm_cpu1_cntkctl_usr; + wire [1:0] tm_cpu2_cnthctl_kernel; + wire [3:0] tm_cpu2_cntkctl_usr; + wire [1:0] tm_cpu3_cnthctl_kernel; + wire [3:0] tm_cpu3_cntkctl_usr; + wire [63:0] tsvalueb_cpu0_o; + wire [63:0] tsvalueb_cpu1_o; + wire [63:0] tsvalueb_cpu2_o; + wire [63:0] tsvalueb_cpu3_o; + wire vinithi_cpu0_o; + wire vinithi_cpu1_o; + wire vinithi_cpu2_o; + wire vinithi_cpu3_o; + + maia_cpu ucpu0( // outputs + .afreadym_cpu (afreadym_cpu0_i), + .atbytesm_cpu (atbytesm_cpu0_i[1:0]), + .atdatam_cpu (atdatam_cpu0_i[31:0]), + .atidm_cpu (atidm_cpu0_i[6:0]), + .atvalidm_cpu (atvalidm_cpu0_i), + .commrx_cpu (commrx_cpu0_i), + .commtx_cpu (commtx_cpu0_i), + .dbgack_cpu (dbgack_cpu0_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu0_i), + .dbgrstreq_cpu (dbgrstreq_cpu0_i), + .ds_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_flush (ds_cpu0_flush), + .ds_flush_type (ds_cpu0_flush_type[5:0]), + .ds_hcr_va (ds_cpu0_hcr_va), + .ds_hcr_vf (ds_cpu0_hcr_vf), + .ds_hcr_vi (ds_cpu0_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu0_reset_req), + .ds_sev_req (ds_cpu0_sev_req), + .ds_sevl_req (ds_cpu0_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_wfe_req (ds_cpu0_wfe_req), + .ds_wfi_req (ds_cpu0_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu0_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu0_clrexmon), + .ls_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu0_i), + .npmuirq_cpu (npmuirq_cpu0_i), + .pm_export_cpu (pm_export_cpu0_i), + .pmuevent_cpu (pmuevent_cpu0_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu0_o), + .afvalidm_cpu (afvalidm_cpu0_o), + .atclken_cpu (atclken_cpu0_o), + .atreadym_cpu (atreadym_cpu0_o), + .cfgend_cpu (cfgend_cpu0_o), + .cfgte_cpu (cfgte_cpu0_o), + .ck_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_event_reg (ck_cpu0_event_reg), + .ck_gclkt (ck_gclkt[0]), + .ck_wfe_ack (ck_cpu0_wfe_ack), + .ck_wfi_ack (ck_cpu0_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu0_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu0_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu0_o), + .cpuid (cpuid_cpu0_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu0_o), + .dbgen_cpu (dbgen_cpu0_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu0_o), + .dbgromaddr_cpu (dbgromaddr_cpu0_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu0_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu0_o), + .dftramhold_cpu (dftramhold_cpu0_o), + .dftrstdisable_cpu (dftrstdisable_cpu0_o), + .dftse_cpu (dftse_cpu0_o), + .dt_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu0_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[0]), + .ic_el_change_complete (ic_el_change_complete[0]), + .ic_hcr_change_complete (ic_hcr_change_complete[0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[0]), + .ic_ich_el2_tc (ic_ich_el2_tc[0]), + .ic_nfiq (ic_nfiq[0]), + .ic_nirq (ic_nirq[0]), + .ic_nsei (ic_nsei[0]), + .ic_nvfiq (ic_nvfiq[0]), + .ic_nvirq (ic_nvirq[0]), + .ic_nvsei (ic_nvsei[0]), + .ic_p_valid (ic_p_valid[0]), + .ic_sample_spr (ic_sample_spr[0]), + .ic_scr_change_complete (ic_scr_change_complete[0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[0]), + .ic_sra_el1s_en (ic_sra_el1s_en[0]), + .ic_sra_el2_en (ic_sra_el2_en[0]), + .ic_sra_el3_en (ic_sra_el3_en[0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[0]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu0_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu0_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu0_rexfail), + .l2_cpu_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu0_rvalid), + .l2_cpu_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu0_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu0_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu0_o), + .ncpuporeset_cpu (ncpuporeset_cpu0_o), + .niden_cpu (niden_cpu0_o), + .nmbistreset_cpu (nmbistreset_cpu0_o), + .rvbaraddr_cpu (rvbaraddr_cpu0_o[43:2]), + .spiden_cpu (spiden_cpu0_o), + .spniden_cpu (spniden_cpu0_o), + .syncreqm_cpu (syncreqm_cpu0_o), + .tm_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu0_o[63:0]), + .vinithi_cpu (vinithi_cpu0_o) + ); // ucpu0 + + maia_cpu ucpu1( // outputs + .afreadym_cpu (afreadym_cpu1_i), + .atbytesm_cpu (atbytesm_cpu1_i[1:0]), + .atdatam_cpu (atdatam_cpu1_i[31:0]), + .atidm_cpu (atidm_cpu1_i[6:0]), + .atvalidm_cpu (atvalidm_cpu1_i), + .commrx_cpu (commrx_cpu1_i), + .commtx_cpu (commtx_cpu1_i), + .dbgack_cpu (dbgack_cpu1_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu1_i), + .dbgrstreq_cpu (dbgrstreq_cpu1_i), + .ds_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_flush (ds_cpu1_flush), + .ds_flush_type (ds_cpu1_flush_type[5:0]), + .ds_hcr_va (ds_cpu1_hcr_va), + .ds_hcr_vf (ds_cpu1_hcr_vf), + .ds_hcr_vi (ds_cpu1_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu1_reset_req), + .ds_sev_req (ds_cpu1_sev_req), + .ds_sevl_req (ds_cpu1_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_wfe_req (ds_cpu1_wfe_req), + .ds_wfi_req (ds_cpu1_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu1_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu1_clrexmon), + .ls_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu1_i), + .npmuirq_cpu (npmuirq_cpu1_i), + .pm_export_cpu (pm_export_cpu1_i), + .pmuevent_cpu (pmuevent_cpu1_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu1_o), + .afvalidm_cpu (afvalidm_cpu1_o), + .atclken_cpu (atclken_cpu1_o), + .atreadym_cpu (atreadym_cpu1_o), + .cfgend_cpu (cfgend_cpu1_o), + .cfgte_cpu (cfgte_cpu1_o), + .ck_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_event_reg (ck_cpu1_event_reg), + .ck_gclkt (ck_gclkt[1]), + .ck_wfe_ack (ck_cpu1_wfe_ack), + .ck_wfi_ack (ck_cpu1_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu1_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu1_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu1_o), + .cpuid (cpuid_cpu1_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu1_o), + .dbgen_cpu (dbgen_cpu1_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu1_o), + .dbgromaddr_cpu (dbgromaddr_cpu1_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu1_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu1_o), + .dftramhold_cpu (dftramhold_cpu1_o), + .dftrstdisable_cpu (dftrstdisable_cpu1_o), + .dftse_cpu (dftse_cpu1_o), + .dt_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu1_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[1]), + .ic_el_change_complete (ic_el_change_complete[1]), + .ic_hcr_change_complete (ic_hcr_change_complete[1]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[1]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[1]), + .ic_ich_el2_tc (ic_ich_el2_tc[1]), + .ic_nfiq (ic_nfiq[1]), + .ic_nirq (ic_nirq[1]), + .ic_nsei (ic_nsei[1]), + .ic_nvfiq (ic_nvfiq[1]), + .ic_nvirq (ic_nvirq[1]), + .ic_nvsei (ic_nvsei[1]), + .ic_p_valid (ic_p_valid[1]), + .ic_sample_spr (ic_sample_spr[1]), + .ic_scr_change_complete (ic_scr_change_complete[1]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[1]), + .ic_sra_el1s_en (ic_sra_el1s_en[1]), + .ic_sra_el2_en (ic_sra_el2_en[1]), + .ic_sra_el3_en (ic_sra_el3_en[1]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[1]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[1]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[1]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[1]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu1_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu1_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu1_rexfail), + .l2_cpu_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu1_rvalid), + .l2_cpu_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu1_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu1_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu1_o), + .ncpuporeset_cpu (ncpuporeset_cpu1_o), + .niden_cpu (niden_cpu1_o), + .nmbistreset_cpu (nmbistreset_cpu1_o), + .rvbaraddr_cpu (rvbaraddr_cpu1_o[43:2]), + .spiden_cpu (spiden_cpu1_o), + .spniden_cpu (spniden_cpu1_o), + .syncreqm_cpu (syncreqm_cpu1_o), + .tm_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu1_o[63:0]), + .vinithi_cpu (vinithi_cpu1_o) + ); // ucpu1 + + maia_cpu ucpu2( // outputs + .afreadym_cpu (afreadym_cpu2_i), + .atbytesm_cpu (atbytesm_cpu2_i[1:0]), + .atdatam_cpu (atdatam_cpu2_i[31:0]), + .atidm_cpu (atidm_cpu2_i[6:0]), + .atvalidm_cpu (atvalidm_cpu2_i), + .commrx_cpu (commrx_cpu2_i), + .commtx_cpu (commtx_cpu2_i), + .dbgack_cpu (dbgack_cpu2_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu2_i), + .dbgrstreq_cpu (dbgrstreq_cpu2_i), + .ds_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_flush (ds_cpu2_flush), + .ds_flush_type (ds_cpu2_flush_type[5:0]), + .ds_hcr_va (ds_cpu2_hcr_va), + .ds_hcr_vf (ds_cpu2_hcr_vf), + .ds_hcr_vi (ds_cpu2_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu2_reset_req), + .ds_sev_req (ds_cpu2_sev_req), + .ds_sevl_req (ds_cpu2_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_wfe_req (ds_cpu2_wfe_req), + .ds_wfi_req (ds_cpu2_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu2_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu2_clrexmon), + .ls_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu2_i), + .npmuirq_cpu (npmuirq_cpu2_i), + .pm_export_cpu (pm_export_cpu2_i), + .pmuevent_cpu (pmuevent_cpu2_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu2_o), + .afvalidm_cpu (afvalidm_cpu2_o), + .atclken_cpu (atclken_cpu2_o), + .atreadym_cpu (atreadym_cpu2_o), + .cfgend_cpu (cfgend_cpu2_o), + .cfgte_cpu (cfgte_cpu2_o), + .ck_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_event_reg (ck_cpu2_event_reg), + .ck_gclkt (ck_gclkt[2]), + .ck_wfe_ack (ck_cpu2_wfe_ack), + .ck_wfi_ack (ck_cpu2_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu2_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu2_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu2_o), + .cpuid (cpuid_cpu2_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu2_o), + .dbgen_cpu (dbgen_cpu2_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu2_o), + .dbgromaddr_cpu (dbgromaddr_cpu2_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu2_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu2_o), + .dftramhold_cpu (dftramhold_cpu2_o), + .dftrstdisable_cpu (dftrstdisable_cpu2_o), + .dftse_cpu (dftse_cpu2_o), + .dt_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu2_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[2]), + .ic_el_change_complete (ic_el_change_complete[2]), + .ic_hcr_change_complete (ic_hcr_change_complete[2]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[2]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[2]), + .ic_ich_el2_tc (ic_ich_el2_tc[2]), + .ic_nfiq (ic_nfiq[2]), + .ic_nirq (ic_nirq[2]), + .ic_nsei (ic_nsei[2]), + .ic_nvfiq (ic_nvfiq[2]), + .ic_nvirq (ic_nvirq[2]), + .ic_nvsei (ic_nvsei[2]), + .ic_p_valid (ic_p_valid[2]), + .ic_sample_spr (ic_sample_spr[2]), + .ic_scr_change_complete (ic_scr_change_complete[2]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[2]), + .ic_sra_el1s_en (ic_sra_el1s_en[2]), + .ic_sra_el2_en (ic_sra_el2_en[2]), + .ic_sra_el3_en (ic_sra_el3_en[2]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[2]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[2]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[2]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[2]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu2_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu2_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu2_rexfail), + .l2_cpu_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu2_rvalid), + .l2_cpu_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu2_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu2_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu2_o), + .ncpuporeset_cpu (ncpuporeset_cpu2_o), + .niden_cpu (niden_cpu2_o), + .nmbistreset_cpu (nmbistreset_cpu2_o), + .rvbaraddr_cpu (rvbaraddr_cpu2_o[43:2]), + .spiden_cpu (spiden_cpu2_o), + .spniden_cpu (spniden_cpu2_o), + .syncreqm_cpu (syncreqm_cpu2_o), + .tm_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu2_o[63:0]), + .vinithi_cpu (vinithi_cpu2_o) + ); // ucpu2 + + maia_cpu ucpu3( // outputs + .afreadym_cpu (afreadym_cpu3_i), + .atbytesm_cpu (atbytesm_cpu3_i[1:0]), + .atdatam_cpu (atdatam_cpu3_i[31:0]), + .atidm_cpu (atidm_cpu3_i[6:0]), + .atvalidm_cpu (atvalidm_cpu3_i), + .commrx_cpu (commrx_cpu3_i), + .commtx_cpu (commtx_cpu3_i), + .dbgack_cpu (dbgack_cpu3_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu (dbgrstreq_cpu3_i), + .ds_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_flush (ds_cpu3_flush), + .ds_flush_type (ds_cpu3_flush_type[5:0]), + .ds_hcr_va (ds_cpu3_hcr_va), + .ds_hcr_vf (ds_cpu3_hcr_vf), + .ds_hcr_vi (ds_cpu3_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_ic_scr_change (ds_cpu3_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu3_reset_req), + .ds_sev_req (ds_cpu3_sev_req), + .ds_sevl_req (ds_cpu3_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_wfe_req (ds_cpu3_wfe_req), + .ds_wfi_req (ds_cpu3_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu3_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu3_clrexmon), + .ls_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu3_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu3_i), + .npmuirq_cpu (npmuirq_cpu3_i), + .pm_export_cpu (pm_export_cpu3_i), + .pmuevent_cpu (pmuevent_cpu3_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu3_o), + .afvalidm_cpu (afvalidm_cpu3_o), + .atclken_cpu (atclken_cpu3_o), + .atreadym_cpu (atreadym_cpu3_o), + .cfgend_cpu (cfgend_cpu3_o), + .cfgte_cpu (cfgte_cpu3_o), + .ck_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_event_reg (ck_cpu3_event_reg), + .ck_gclkt (ck_gclkt[3]), + .ck_wfe_ack (ck_cpu3_wfe_ack), + .ck_wfi_ack (ck_cpu3_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu3_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu3_o), + .cpuid (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu3_o), + .dbgen_cpu (dbgen_cpu3_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu3_o), + .dbgromaddr_cpu (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu3_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu3_o), + .dftramhold_cpu (dftramhold_cpu3_o), + .dftrstdisable_cpu (dftrstdisable_cpu3_o), + .dftse_cpu (dftse_cpu3_o), + .dt_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu3_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[3]), + .ic_el_change_complete (ic_el_change_complete[3]), + .ic_hcr_change_complete (ic_hcr_change_complete[3]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[3]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[3]), + .ic_ich_el2_tc (ic_ich_el2_tc[3]), + .ic_nfiq (ic_nfiq[3]), + .ic_nirq (ic_nirq[3]), + .ic_nsei (ic_nsei[3]), + .ic_nvfiq (ic_nvfiq[3]), + .ic_nvirq (ic_nvirq[3]), + .ic_nvsei (ic_nvsei[3]), + .ic_p_valid (ic_p_valid[3]), + .ic_sample_spr (ic_sample_spr[3]), + .ic_scr_change_complete (ic_scr_change_complete[3]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[3]), + .ic_sra_el1s_en (ic_sra_el1s_en[3]), + .ic_sra_el2_en (ic_sra_el2_en[3]), + .ic_sra_el3_en (ic_sra_el3_en[3]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[3]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[3]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[3]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[3]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu3_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu3_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu3_rexfail), + .l2_cpu_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu3_rvalid), + .l2_cpu_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu3_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu3_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu3_o), + .ncpuporeset_cpu (ncpuporeset_cpu3_o), + .niden_cpu (niden_cpu3_o), + .nmbistreset_cpu (nmbistreset_cpu3_o), + .rvbaraddr_cpu (rvbaraddr_cpu3_o[43:2]), + .spiden_cpu (spiden_cpu3_o), + .spniden_cpu (spniden_cpu3_o), + .syncreqm_cpu (syncreqm_cpu3_o), + .tm_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu3_o[63:0]), + .vinithi_cpu (vinithi_cpu3_o) + ); // ucpu3 + + maia_noncpu_feq28_s unoncpu( // outputs + .AFREADYM0 (AFREADYM0), + .AFREADYM1 (AFREADYM1), + .AFREADYM2 (AFREADYM2), + .AFREADYM3 (AFREADYM3), + .ARREADYS (ARREADYS), + .ATBYTESM0 (ATBYTESM0[1:0]), + .ATBYTESM1 (ATBYTESM1[1:0]), + .ATBYTESM2 (ATBYTESM2[1:0]), + .ATBYTESM3 (ATBYTESM3[1:0]), + .ATDATAM0 (ATDATAM0[31:0]), + .ATDATAM1 (ATDATAM1[31:0]), + .ATDATAM2 (ATDATAM2[31:0]), + .ATDATAM3 (ATDATAM3[31:0]), + .ATIDM0 (ATIDM0[6:0]), + .ATIDM1 (ATIDM1[6:0]), + .ATIDM2 (ATIDM2[6:0]), + .ATIDM3 (ATIDM3[6:0]), + .ATVALIDM0 (ATVALIDM0), + .ATVALIDM1 (ATVALIDM1), + .ATVALIDM2 (ATVALIDM2), + .ATVALIDM3 (ATVALIDM3), + .AWREADYS (AWREADYS), + .BIDS (BIDS[4:0]), + .BRESPS (BRESPS[1:0]), + .BVALIDS (BVALIDS), + .CLREXMONACK (CLREXMONACK), + .COMMRX (COMMRX[`MAIA_CN:0]), + .COMMTX (COMMTX[`MAIA_CN:0]), + .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), + .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), + .CPUQDENY (CPUQDENY[`MAIA_CN:0]), + .CTICHINACK (CTICHINACK[3:0]), + .CTICHOUT (CTICHOUT[3:0]), + .CTIIRQ (CTIIRQ[`MAIA_CN:0]), + .DBGACK (DBGACK[`MAIA_CN:0]), + .DBGNOPWRDWN (DBGNOPWRDWN[`MAIA_CN:0]), + .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), + .DBGRSTREQ (DBGRSTREQ[`MAIA_CN:0]), + .EVENTO (EVENTO), + .ICCTDATA (ICCTDATA[15:0]), + .ICCTID (ICCTID[1:0]), + .ICCTLAST (ICCTLAST), + .ICCTVALID (ICCTVALID), + .ICDTREADY (ICDTREADY), + .L2FLUSHDONE (L2FLUSHDONE), + .L2QACCEPTn (L2QACCEPTn), + .L2QACTIVE (L2QACTIVE), + .L2QDENY (L2QDENY), + .PMUEVENT0 (PMUEVENT0[24:0]), + .PMUEVENT1 (PMUEVENT1[24:0]), + .PMUEVENT2 (PMUEVENT2[24:0]), + .PMUEVENT3 (PMUEVENT3[24:0]), + .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), + .PRDATADBG (PRDATADBG[31:0]), + .PREADYDBG (PREADYDBG), + .PSLVERRDBG (PSLVERRDBG), + .RDATAS (RDATAS[127:0]), + .REQMEMATTR (REQMEMATTR[7:0]), + .RIDS (RIDS[4:0]), + .RLASTS (RLASTS), + .RRESPS (RRESPS[1:0]), + .RVALIDS (RVALIDS), + .RXDATLCRDV (RXDATLCRDV), + .RXLINKACTIVEACK (RXLINKACTIVEACK), + .RXRSPLCRDV (RXRSPLCRDV), + .RXSNPLCRDV (RXSNPLCRDV), + .SMPEN (SMPEN[`MAIA_CN:0]), + .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), + .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), + .STANDBYWFIL2 (STANDBYWFIL2), + .TXDATFLIT (TXDATFLIT[193:0]), + .TXDATFLITPEND (TXDATFLITPEND), + .TXDATFLITV (TXDATFLITV), + .TXLINKACTIVEREQ (TXLINKACTIVEREQ), + .TXREQFLIT (TXREQFLIT[99:0]), + .TXREQFLITPEND (TXREQFLITPEND), + .TXREQFLITV (TXREQFLITV), + .TXRSPFLIT (TXRSPFLIT[44:0]), + .TXRSPFLITPEND (TXRSPFLITPEND), + .TXRSPFLITV (TXRSPFLITV), + .TXSACTIVE (TXSACTIVE), + .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), + .WREADYS (WREADYS), + .aa64naa32_cpu0_o (aa64naa32_cpu0_o), + .aa64naa32_cpu1_o (aa64naa32_cpu1_o), + .aa64naa32_cpu2_o (aa64naa32_cpu2_o), + .aa64naa32_cpu3_o (aa64naa32_cpu3_o), + .afvalidm_cpu0_o (afvalidm_cpu0_o), + .afvalidm_cpu1_o (afvalidm_cpu1_o), + .afvalidm_cpu2_o (afvalidm_cpu2_o), + .afvalidm_cpu3_o (afvalidm_cpu3_o), + .atclken_cpu0_o (atclken_cpu0_o), + .atclken_cpu1_o (atclken_cpu1_o), + .atclken_cpu2_o (atclken_cpu2_o), + .atclken_cpu3_o (atclken_cpu3_o), + .atreadym_cpu0_o (atreadym_cpu0_o), + .atreadym_cpu1_o (atreadym_cpu1_o), + .atreadym_cpu2_o (atreadym_cpu2_o), + .atreadym_cpu3_o (atreadym_cpu3_o), + .cfgend_cpu0_o (cfgend_cpu0_o), + .cfgend_cpu1_o (cfgend_cpu1_o), + .cfgend_cpu2_o (cfgend_cpu2_o), + .cfgend_cpu3_o (cfgend_cpu3_o), + .cfgte_cpu0_o (cfgte_cpu0_o), + .cfgte_cpu1_o (cfgte_cpu1_o), + .cfgte_cpu2_o (cfgte_cpu2_o), + .cfgte_cpu3_o (cfgte_cpu3_o), + .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_cpu0_event_reg (ck_cpu0_event_reg), + .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), + .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), + .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_cpu1_event_reg (ck_cpu1_event_reg), + .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), + .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), + .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_cpu2_event_reg (ck_cpu2_event_reg), + .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), + .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), + .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_cpu3_event_reg (ck_cpu3_event_reg), + .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), + .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), + .ck_gclkt (ck_gclkt[`MAIA_CN:0]), + .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), + .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), + .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), + .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), + .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), + .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), + .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), + .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), + .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), + .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), + .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), + .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), + .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), + .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), + .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu0_o (cryptodisable_cpu0_o), + .cryptodisable_cpu1_o (cryptodisable_cpu1_o), + .cryptodisable_cpu2_o (cryptodisable_cpu2_o), + .cryptodisable_cpu3_o (cryptodisable_cpu3_o), + .dbgen_cpu0_o (dbgen_cpu0_o), + .dbgen_cpu1_o (dbgen_cpu1_o), + .dbgen_cpu2_o (dbgen_cpu2_o), + .dbgen_cpu3_o (dbgen_cpu3_o), + .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), + .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), + .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), + .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), + .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), + .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), + .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), + .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), + .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), + .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), + .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), + .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), + .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), + .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), + .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), + .dftramhold_cpu0_o (dftramhold_cpu0_o), + .dftramhold_cpu1_o (dftramhold_cpu1_o), + .dftramhold_cpu2_o (dftramhold_cpu2_o), + .dftramhold_cpu3_o (dftramhold_cpu3_o), + .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), + .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), + .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), + .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), + .dftse_cpu0_o (dftse_cpu0_o), + .dftse_cpu1_o (dftse_cpu1_o), + .dftse_cpu2_o (dftse_cpu2_o), + .dftse_cpu3_o (dftse_cpu3_o), + .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .giccdisable_cpu0_o (giccdisable_cpu0_o), + .giccdisable_cpu1_o (giccdisable_cpu1_o), + .giccdisable_cpu2_o (giccdisable_cpu2_o), + .giccdisable_cpu3_o (giccdisable_cpu3_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[`MAIA_CN:0]), + .ic_el_change_complete (ic_el_change_complete[`MAIA_CN:0]), + .ic_hcr_change_complete (ic_hcr_change_complete[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq[`MAIA_CN:0]), + .ic_nirq (ic_nirq[`MAIA_CN:0]), + .ic_nsei (ic_nsei[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei[`MAIA_CN:0]), + .ic_p_valid (ic_p_valid[`MAIA_CN:0]), + .ic_sample_spr (ic_sample_spr[`MAIA_CN:0]), + .ic_scr_change_complete (ic_scr_change_complete[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[`MAIA_CN:0]), + .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu0_barrier_done (l2_cpu0_barrier_done), + .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), + .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), + .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu0_rd_arb (l2_cpu0_rd_arb), + .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu0_rexfail (l2_cpu0_rexfail), + .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu0_rvalid (l2_cpu0_rvalid), + .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu0_spec_valid (l2_cpu0_spec_valid), + .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu0_wr_arb (l2_cpu0_wr_arb), + .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu1_barrier_done (l2_cpu1_barrier_done), + .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), + .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), + .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu1_rd_arb (l2_cpu1_rd_arb), + .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu1_rexfail (l2_cpu1_rexfail), + .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu1_rvalid (l2_cpu1_rvalid), + .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu1_spec_valid (l2_cpu1_spec_valid), + .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu1_wr_arb (l2_cpu1_wr_arb), + .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu2_barrier_done (l2_cpu2_barrier_done), + .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), + .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), + .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu2_rd_arb (l2_cpu2_rd_arb), + .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu2_rexfail (l2_cpu2_rexfail), + .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu2_rvalid (l2_cpu2_rvalid), + .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu2_spec_valid (l2_cpu2_spec_valid), + .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu2_wr_arb (l2_cpu2_wr_arb), + .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu3_barrier_done (l2_cpu3_barrier_done), + .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), + .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), + .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu3_rd_arb (l2_cpu3_rd_arb), + .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu3_rexfail (l2_cpu3_rexfail), + .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu3_rvalid (l2_cpu3_rvalid), + .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu3_spec_valid (l2_cpu3_spec_valid), + .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu3_wr_arb (l2_cpu3_wr_arb), + .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), + .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), + .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), + .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), + .nCOMMIRQ (nCOMMIRQ[`MAIA_CN:0]), + .nEXTERRIRQ (nEXTERRIRQ), + .nINTERRIRQ (nINTERRIRQ), + .nPMUIRQ (nPMUIRQ[`MAIA_CN:0]), + .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), + .ncorereset_cpu0_o (ncorereset_cpu0_o), + .ncorereset_cpu1_o (ncorereset_cpu1_o), + .ncorereset_cpu2_o (ncorereset_cpu2_o), + .ncorereset_cpu3_o (ncorereset_cpu3_o), + .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), + .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), + .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), + .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), + .niden_cpu0_o (niden_cpu0_o), + .niden_cpu1_o (niden_cpu1_o), + .niden_cpu2_o (niden_cpu2_o), + .niden_cpu3_o (niden_cpu3_o), + .nmbistreset_cpu0_o (nmbistreset_cpu0_o), + .nmbistreset_cpu1_o (nmbistreset_cpu1_o), + .nmbistreset_cpu2_o (nmbistreset_cpu2_o), + .nmbistreset_cpu3_o (nmbistreset_cpu3_o), + .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), + .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), + .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), + .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), + .spiden_cpu0_o (spiden_cpu0_o), + .spiden_cpu1_o (spiden_cpu1_o), + .spiden_cpu2_o (spiden_cpu2_o), + .spiden_cpu3_o (spiden_cpu3_o), + .spniden_cpu0_o (spniden_cpu0_o), + .spniden_cpu1_o (spniden_cpu1_o), + .spniden_cpu2_o (spniden_cpu2_o), + .spniden_cpu3_o (spniden_cpu3_o), + .syncreqm_cpu0_o (syncreqm_cpu0_o), + .syncreqm_cpu1_o (syncreqm_cpu1_o), + .syncreqm_cpu2_o (syncreqm_cpu2_o), + .syncreqm_cpu3_o (syncreqm_cpu3_o), + .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), + .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), + .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), + .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), + .vinithi_cpu0_o (vinithi_cpu0_o), + .vinithi_cpu1_o (vinithi_cpu1_o), + .vinithi_cpu2_o (vinithi_cpu2_o), + .vinithi_cpu3_o (vinithi_cpu3_o), + + // inputs + .AA64nAA32 (AA64nAA32[`MAIA_CN:0]), + .ACLKENS (ACLKENS), + .AFVALIDM0 (AFVALIDM0), + .AFVALIDM1 (AFVALIDM1), + .AFVALIDM2 (AFVALIDM2), + .AFVALIDM3 (AFVALIDM3), + .AINACTS (AINACTS), + .ARADDRS (ARADDRS[43:0]), + .ARCACHES (ARCACHES[3:0]), + .ARIDS (ARIDS[4:0]), + .ARLENS (ARLENS[7:0]), + .ARPROTS (ARPROTS[2:0]), + .ARUSERS (ARUSERS[1:0]), + .ARVALIDS (ARVALIDS), + .ATCLKEN (ATCLKEN), + .ATREADYM0 (ATREADYM0), + .ATREADYM1 (ATREADYM1), + .ATREADYM2 (ATREADYM2), + .ATREADYM3 (ATREADYM3), + .AWADDRS (AWADDRS[43:0]), + .AWCACHES (AWCACHES[3:0]), + .AWIDS (AWIDS[4:0]), + .AWLENS (AWLENS[7:0]), + .AWPROTS (AWPROTS[2:0]), + .AWUSERS (AWUSERS[1:0]), + .AWVALIDS (AWVALIDS), + .BREADYS (BREADYS), + .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), + .BROADCASTINNER (BROADCASTINNER), + .BROADCASTOUTER (BROADCASTOUTER), + .CFGEND (CFGEND[`MAIA_CN:0]), + .CFGTE (CFGTE[`MAIA_CN:0]), + .CIHSBYPASS (CIHSBYPASS[3:0]), + .CISBYPASS (CISBYPASS), + .CLK (CLK), + .CLKEN (CLKEN), + .CLREXMONREQ (CLREXMONREQ), + .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), + .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), + .CNTCLKEN (CNTCLKEN), + .CNTVALUEB (CNTVALUEB[63:0]), + .CP15SDISABLE (CP15SDISABLE[`MAIA_CN:0]), + .CPUQREQn (CPUQREQn[`MAIA_CN:0]), + .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), + .CTICHIN (CTICHIN[3:0]), + .CTICHOUTACK (CTICHOUTACK[3:0]), + .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), + .DBGEN (DBGEN[`MAIA_CN:0]), + .DBGL1RSTDISABLE (DBGL1RSTDISABLE), + .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), + .DBGROMADDR (DBGROMADDR[43:12]), + .DBGROMADDRV (DBGROMADDRV), + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTCRCLKDISABLE (DFTCRCLKDISABLE[`MAIA_CN:0]), + .DFTL2CLKDISABLE (DFTL2CLKDISABLE), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .EDBGRQ (EDBGRQ[`MAIA_CN:0]), + .EVENTI (EVENTI), + .GICCDISABLE (GICCDISABLE), + .ICCTREADY (ICCTREADY), + .ICDTDATA (ICDTDATA[15:0]), + .ICDTDEST (ICDTDEST[1:0]), + .ICDTLAST (ICDTLAST), + .ICDTVALID (ICDTVALID), + .L2FLUSHREQ (L2FLUSHREQ), + .L2QREQn (L2QREQn), + .L2RSTDISABLE (L2RSTDISABLE), + .MBISTREQ (MBISTREQ), + .NIDEN (NIDEN[`MAIA_CN:0]), + .NODEID (NODEID[6:0]), + .PADDRDBG (PADDRDBG[21:2]), + .PADDRDBG31 (PADDRDBG31), + .PCLKDBG (PCLKDBG), + .PCLKENDBG (PCLKENDBG), + .PENABLEDBG (PENABLEDBG), + .PERIPHBASE (PERIPHBASE[43:18]), + .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), + .PSELDBG (PSELDBG), + .PWDATADBG (PWDATADBG[31:0]), + .PWRITEDBG (PWRITEDBG), + .RREADYS (RREADYS), + .RVBARADDR0 (RVBARADDR0[43:2]), + .RVBARADDR1 (RVBARADDR1[43:2]), + .RVBARADDR2 (RVBARADDR2[43:2]), + .RVBARADDR3 (RVBARADDR3[43:2]), + .RXDATFLIT (RXDATFLIT[193:0]), + .RXDATFLITPEND (RXDATFLITPEND), + .RXDATFLITV (RXDATFLITV), + .RXLINKACTIVEREQ (RXLINKACTIVEREQ), + .RXRSPFLIT (RXRSPFLIT[44:0]), + .RXRSPFLITPEND (RXRSPFLITPEND), + .RXRSPFLITV (RXRSPFLITV), + .RXSACTIVE (RXSACTIVE), + .RXSNPFLIT (RXSNPFLIT[64:0]), + .RXSNPFLITPEND (RXSNPFLITPEND), + .RXSNPFLITV (RXSNPFLITV), + .SAMADDRMAP0 (SAMADDRMAP0[1:0]), + .SAMADDRMAP1 (SAMADDRMAP1[1:0]), + .SAMADDRMAP10 (SAMADDRMAP10[1:0]), + .SAMADDRMAP11 (SAMADDRMAP11[1:0]), + .SAMADDRMAP12 (SAMADDRMAP12[1:0]), + .SAMADDRMAP13 (SAMADDRMAP13[1:0]), + .SAMADDRMAP14 (SAMADDRMAP14[1:0]), + .SAMADDRMAP15 (SAMADDRMAP15[1:0]), + .SAMADDRMAP16 (SAMADDRMAP16[1:0]), + .SAMADDRMAP17 (SAMADDRMAP17[1:0]), + .SAMADDRMAP18 (SAMADDRMAP18[1:0]), + .SAMADDRMAP19 (SAMADDRMAP19[1:0]), + .SAMADDRMAP2 (SAMADDRMAP2[1:0]), + .SAMADDRMAP3 (SAMADDRMAP3[1:0]), + .SAMADDRMAP4 (SAMADDRMAP4[1:0]), + .SAMADDRMAP5 (SAMADDRMAP5[1:0]), + .SAMADDRMAP6 (SAMADDRMAP6[1:0]), + .SAMADDRMAP7 (SAMADDRMAP7[1:0]), + .SAMADDRMAP8 (SAMADDRMAP8[1:0]), + .SAMADDRMAP9 (SAMADDRMAP9[1:0]), + .SAMHNF0NODEID (SAMHNF0NODEID[6:0]), + .SAMHNF1NODEID (SAMHNF1NODEID[6:0]), + .SAMHNF2NODEID (SAMHNF2NODEID[6:0]), + .SAMHNF3NODEID (SAMHNF3NODEID[6:0]), + .SAMHNF4NODEID (SAMHNF4NODEID[6:0]), + .SAMHNF5NODEID (SAMHNF5NODEID[6:0]), + .SAMHNF6NODEID (SAMHNF6NODEID[6:0]), + .SAMHNF7NODEID (SAMHNF7NODEID[6:0]), + .SAMHNFMODE (SAMHNFMODE[2:0]), + .SAMHNI0NODEID (SAMHNI0NODEID[6:0]), + .SAMHNI1NODEID (SAMHNI1NODEID[6:0]), + .SAMMNBASE (SAMMNBASE[43:24]), + .SAMMNNODEID (SAMMNNODEID[6:0]), + .SCLKEN (SCLKEN), + .SINACT (SINACT), + .SPIDEN (SPIDEN[`MAIA_CN:0]), + .SPNIDEN (SPNIDEN[`MAIA_CN:0]), + .SYNCREQM0 (SYNCREQM0), + .SYNCREQM1 (SYNCREQM1), + .SYNCREQM2 (SYNCREQM2), + .SYNCREQM3 (SYNCREQM3), + .SYSBARDISABLE (SYSBARDISABLE), + .TSVALUEB (TSVALUEB[63:0]), + .TXDATLCRDV (TXDATLCRDV), + .TXLINKACTIVEACK (TXLINKACTIVEACK), + .TXREQLCRDV (TXREQLCRDV), + .TXRSPLCRDV (TXRSPLCRDV), + .VINITHI (VINITHI[`MAIA_CN:0]), + .WDATAS (WDATAS[127:0]), + .WLASTS (WLASTS), + .WSTRBS (WSTRBS[15:0]), + .WVALIDS (WVALIDS), + .afreadym_cpu0_i (afreadym_cpu0_i), + .afreadym_cpu1_i (afreadym_cpu1_i), + .afreadym_cpu2_i (afreadym_cpu2_i), + .afreadym_cpu3_i (afreadym_cpu3_i), + .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), + .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), + .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), + .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), + .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), + .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), + .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), + .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), + .atidm_cpu0_i (atidm_cpu0_i[6:0]), + .atidm_cpu1_i (atidm_cpu1_i[6:0]), + .atidm_cpu2_i (atidm_cpu2_i[6:0]), + .atidm_cpu3_i (atidm_cpu3_i[6:0]), + .atvalidm_cpu0_i (atvalidm_cpu0_i), + .atvalidm_cpu1_i (atvalidm_cpu1_i), + .atvalidm_cpu2_i (atvalidm_cpu2_i), + .atvalidm_cpu3_i (atvalidm_cpu3_i), + .commrx_cpu0_i (commrx_cpu0_i), + .commrx_cpu1_i (commrx_cpu1_i), + .commrx_cpu2_i (commrx_cpu2_i), + .commrx_cpu3_i (commrx_cpu3_i), + .commtx_cpu0_i (commtx_cpu0_i), + .commtx_cpu1_i (commtx_cpu1_i), + .commtx_cpu2_i (commtx_cpu2_i), + .commtx_cpu3_i (commtx_cpu3_i), + .dbgack_cpu0_i (dbgack_cpu0_i), + .dbgack_cpu1_i (dbgack_cpu1_i), + .dbgack_cpu2_i (dbgack_cpu2_i), + .dbgack_cpu3_i (dbgack_cpu3_i), + .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), + .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), + .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), + .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), + .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), + .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), + .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), + .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_cpu0_flush (ds_cpu0_flush), + .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), + .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), + .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu0_reset_req (ds_cpu0_reset_req), + .ds_cpu0_sev_req (ds_cpu0_sev_req), + .ds_cpu0_sevl_req (ds_cpu0_sevl_req), + .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_cpu0_wfe_req (ds_cpu0_wfe_req), + .ds_cpu0_wfi_req (ds_cpu0_wfi_req), + .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_cpu1_flush (ds_cpu1_flush), + .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), + .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), + .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu1_reset_req (ds_cpu1_reset_req), + .ds_cpu1_sev_req (ds_cpu1_sev_req), + .ds_cpu1_sevl_req (ds_cpu1_sevl_req), + .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_cpu1_wfe_req (ds_cpu1_wfe_req), + .ds_cpu1_wfi_req (ds_cpu1_wfi_req), + .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_cpu2_flush (ds_cpu2_flush), + .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), + .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), + .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu2_reset_req (ds_cpu2_reset_req), + .ds_cpu2_sev_req (ds_cpu2_sev_req), + .ds_cpu2_sevl_req (ds_cpu2_sevl_req), + .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_cpu2_wfe_req (ds_cpu2_wfe_req), + .ds_cpu2_wfi_req (ds_cpu2_wfi_req), + .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_cpu3_flush (ds_cpu3_flush), + .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), + .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), + .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), + .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_cpu3_reset_req (ds_cpu3_reset_req), + .ds_cpu3_sev_req (ds_cpu3_sev_req), + .ds_cpu3_sevl_req (ds_cpu3_sevl_req), + .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_cpu3_wfe_req (ds_cpu3_wfe_req), + .ds_cpu3_wfi_req (ds_cpu3_wfi_req), + .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .etclken_cpu0_i (etclken_cpu0_i), + .etclken_cpu1_i (etclken_cpu1_i), + .etclken_cpu2_i (etclken_cpu2_i), + .etclken_cpu3_i (etclken_cpu3_i), + .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .ls_cpu0_clrexmon (ls_cpu0_clrexmon), + .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ls_cpu1_clrexmon (ls_cpu1_clrexmon), + .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ls_cpu2_clrexmon (ls_cpu2_clrexmon), + .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ls_cpu3_clrexmon (ls_cpu3_clrexmon), + .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), + .nCORERESET (nCORERESET[`MAIA_CN:0]), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nFIQ (nFIQ[`MAIA_CN:0]), + .nIRQ (nIRQ[`MAIA_CN:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .nPRESETDBG (nPRESETDBG), + .nREI (nREI[`MAIA_CN:0]), + .nSEI (nSEI[`MAIA_CN:0]), + .nVFIQ (nVFIQ[`MAIA_CN:0]), + .nVIRQ (nVIRQ[`MAIA_CN:0]), + .nVSEI (nVSEI[`MAIA_CN:0]), + .ncommirq_cpu0_i (ncommirq_cpu0_i), + .ncommirq_cpu1_i (ncommirq_cpu1_i), + .ncommirq_cpu2_i (ncommirq_cpu2_i), + .ncommirq_cpu3_i (ncommirq_cpu3_i), + .npmuirq_cpu0_i (npmuirq_cpu0_i), + .npmuirq_cpu1_i (npmuirq_cpu1_i), + .npmuirq_cpu2_i (npmuirq_cpu2_i), + .npmuirq_cpu3_i (npmuirq_cpu3_i), + .pm_export_cpu0_i (pm_export_cpu0_i), + .pm_export_cpu1_i (pm_export_cpu1_i), + .pm_export_cpu2_i (pm_export_cpu2_i), + .pm_export_cpu3_i (pm_export_cpu3_i), + .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), + .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), + .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), + .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]) + ); // unoncpu +endmodule // MAIA_feq28_s + + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/MAIA_s.v b/Security Algo Accelerator/logical/maia/verilog/MAIA_s.v new file mode 100644 index 0000000000..1b2ee6a6eb --- /dev/null +++ b/Security Algo Accelerator/logical/maia/verilog/MAIA_s.v @@ -0,0 +1,4821 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: MAIA.v $ +// Checked In : $Date: 2014-10-14 15:20:06 -0500 (Tue, 14 Oct 2014) $ +// Revision : $Revision: 71806 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// +// This is top-level interconnect layer for the MAIA top-level. +// + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +`define MAIA_CN 3 + +module MAIA_s ( + CLK, + CLKEN, + nCPUPORESET, + nCORERESET, + nL2RESET, + L2RSTDISABLE, + WARMRSTREQ, + CFGEND, + VINITHI, + CFGTE, + CP15SDISABLE, + CLUSTERIDAFF1, + CLUSTERIDAFF2, + AA64nAA32, + RVBARADDR0, +// BEGIN INCLUDE FOR CPU1 + RVBARADDR1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + RVBARADDR2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + RVBARADDR3, +// END INCLUDE FOR CPU3 + CRYPTODISABLE, + nFIQ, + nIRQ, + nSEI, + nREI, + nVFIQ, + nVIRQ, + nVSEI, +// BEGIN NO-GIC pins + nVCPUMNTIRQ, +// END NO-GIC pins + PERIPHBASE, +// BEGIN NO-GIC pins + GICCDISABLE, + ICDTVALID, + ICDTREADY, + ICDTDATA, + ICDTLAST, + ICDTDEST, + ICCTVALID, + ICCTREADY, + ICCTDATA, + ICCTLAST, + ICCTID, +// END NO-GIC pins + CNTVALUEB, + CNTCLKEN, + nCNTPNSIRQ, + nCNTPSIRQ, + nCNTVIRQ, + nCNTHPIRQ, + CLREXMONREQ, + CLREXMONACK, + EVENTI, + EVENTO, + STANDBYWFI, + STANDBYWFE, + STANDBYWFIL2, + SMPEN, + CPUQACTIVE, + CPUQREQn, + CPUQACCEPTn, + CPUQDENY, + L2QACTIVE, + L2QREQn, + L2QACCEPTn, + L2QDENY, + L2FLUSHREQ, + L2FLUSHDONE, + nINTERRIRQ, + nEXTERRIRQ, + SYSBARDISABLE, + BROADCASTINNER, + BROADCASTOUTER, + BROADCASTCACHEMAINT, + SCLKEN, + SINACT, + NODEID, + TXSACTIVE, + RXSACTIVE, + TXLINKACTIVEREQ, + TXLINKACTIVEACK, + RXLINKACTIVEREQ, + RXLINKACTIVEACK, + TXREQFLITPEND, + TXREQFLITV, + TXREQFLIT, + REQMEMATTR, + TXREQLCRDV, + TXRSPFLITPEND, + TXRSPFLITV, + TXRSPFLIT, + TXRSPLCRDV, + TXDATFLITPEND, + TXDATFLITV, + TXDATFLIT, + TXDATLCRDV, + RXSNPFLITPEND, + RXSNPFLITV, + RXSNPFLIT, + RXSNPLCRDV, + RXRSPFLITPEND, + RXRSPFLITV, + RXRSPFLIT, + RXRSPLCRDV, + RXDATFLITPEND, + RXDATFLITV, + RXDATFLIT, + RXDATLCRDV, + SAMMNBASE, + SAMADDRMAP0, + SAMADDRMAP1, + SAMADDRMAP2, + SAMADDRMAP3, + SAMADDRMAP4, + SAMADDRMAP5, + SAMADDRMAP6, + SAMADDRMAP7, + SAMADDRMAP8, + SAMADDRMAP9, + SAMADDRMAP10, + SAMADDRMAP11, + SAMADDRMAP12, + SAMADDRMAP13, + SAMADDRMAP14, + SAMADDRMAP15, + SAMADDRMAP16, + SAMADDRMAP17, + SAMADDRMAP18, + SAMADDRMAP19, + SAMMNNODEID, + SAMHNI0NODEID, + SAMHNI1NODEID, + SAMHNF0NODEID, + SAMHNF1NODEID, + SAMHNF2NODEID, + SAMHNF3NODEID, + SAMHNF4NODEID, + SAMHNF5NODEID, + SAMHNF6NODEID, + SAMHNF7NODEID, + SAMHNFMODE, +// BEGIN NO-ACP pins + ACLKENS, + AINACTS, + AWREADYS, + AWVALIDS, + AWIDS, + AWADDRS, + AWLENS, + AWCACHES, + AWUSERS, + AWPROTS, + WREADYS, + WVALIDS, + WDATAS, + WSTRBS, + WLASTS, + BREADYS, + BVALIDS, + BIDS, + BRESPS, + ARREADYS, + ARVALIDS, + ARIDS, + ARADDRS, + ARLENS, + ARCACHES, + ARUSERS, + ARPROTS, + RREADYS, + RVALIDS, + RIDS, + RDATAS, + RRESPS, + RLASTS, +// END NO-ACP pins + DBGROMADDR, + DBGROMADDRV, + DBGACK, + nCOMMIRQ, + COMMRX, + COMMTX, + DBGRSTREQ, + DBGNOPWRDWN, + DBGL1RSTDISABLE, + nPMUIRQ, + PMUEVENT0, +// BEGIN INCLUDE FOR CPU1 + PMUEVENT1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + PMUEVENT2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + PMUEVENT3, +// END INCLUDE FOR CPU3 + ATCLKEN, + TSVALUEB, + ATREADYM0, + AFVALIDM0, + ATDATAM0, + ATVALIDM0, + ATBYTESM0, + AFREADYM0, + ATIDM0, + SYNCREQM0, +// BEGIN INCLUDE FOR CPU1 + ATREADYM1, + AFVALIDM1, + ATDATAM1, + ATVALIDM1, + ATBYTESM1, + AFREADYM1, + ATIDM1, + SYNCREQM1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ATREADYM2, + AFVALIDM2, + ATDATAM2, + ATVALIDM2, + ATBYTESM2, + AFREADYM2, + ATIDM2, + SYNCREQM2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ATREADYM3, + AFVALIDM3, + ATDATAM3, + ATVALIDM3, + ATBYTESM3, + AFREADYM3, + ATIDM3, + SYNCREQM3, +// END INCLUDE FOR CPU3 + PCLKDBG, + PCLKENDBG, + nPRESETDBG, + PSELDBG, + PADDRDBG, + PADDRDBG31, + PENABLEDBG, + PWRITEDBG, + PWDATADBG, + PRDATADBG, + PREADYDBG, + PSLVERRDBG, + EDBGRQ, + PMUSNAPSHOTREQ, + PMUSNAPSHOTACK, + DBGPWRDUP, + DBGPWRUPREQ, + CTICHIN, + CTICHOUTACK, + CTICHOUT, + CTICHINACK, + CISBYPASS, + CIHSBYPASS, + CTIIRQ, + CTIIRQACK, + DBGEN, + NIDEN, + SPIDEN, + SPNIDEN, + DFTSE, + DFTRSTDISABLE, + DFTCRCLKDISABLE, + DFTL2CLKDISABLE, + DFTRAMHOLD, + DFTCLKBYPASS, + DFTMCPHOLD, + nMBISTRESET, + MBISTREQ +); + +//# +//# Interface Signals +//# ================= +//# + +//----------------------------------------------------------------------------- +// Clock and Reset Signals +//----------------------------------------------------------------------------- + input CLK; // Fast Clock + input CLKEN; // Fast Clock Enable + + input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset + input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) + input nL2RESET; // L2 reset + input L2RSTDISABLE; // L2 RAMs hardware reset disable + output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request +//See also nPRESETDBG; // Debug APB reset (PCLK) + +//----------------------------------------------------------------------------- +// Static Configuration Signals +//----------------------------------------------------------------------------- +// Static configuration signals that should be tied off and not change dynamically. +// Many of the initial values specified by these inputs +// may be overridden in software using CP15 registers. + + input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) + input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors + input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) + input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers + + input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] + input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] + + input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) + input [43:2] RVBARADDR0; // RVBAR address +// BEGIN INCLUDE FOR CPU1 + input [43:2] RVBARADDR1; // RVBAR address +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input [43:2] RVBARADDR2; // RVBAR address +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input [43:2] RVBARADDR3; // RVBAR address +// END INCLUDE FOR CPU3 + input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension + +//----------------------------------------------------------------------------- +// Interrupt Controller Signals +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] nFIQ; // Fast Interrupt request + input [`MAIA_CN:0] nIRQ; // Interrupt request + input [`MAIA_CN:0] nSEI; // System Error Interrupt + input [`MAIA_CN:0] nREI; // RAM Error Interrupt + input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request + input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request + input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt + +// BEGIN NO-GIC pins + output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output +// END NO-GIC pins + + input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers +// BEGIN NO-GIC pins + input GICCDISABLE; // Put GIC into bypass mode + + input ICDTVALID; // Distrubuter AXI4 SP Message Valid + output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message + input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data + input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet + input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID + + output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid + input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message + output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data + output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet + output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID +// END NO-GIC pins + +//----------------------------------------------------------------------------- +// Timer Signals +//----------------------------------------------------------------------------- + input [63:0] CNTVALUEB; // Counter value in binary + input CNTCLKEN; // Counter clock enable + output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event + output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event + output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event + output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event + +//----------------------------------------------------------------------------- +// Power Management Signals +//----------------------------------------------------------------------------- + input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) + output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) + input EVENTI; // Event input for processor wake-up from WFE state + output EVENTO; // Event output, signal is active when SEV instruction is executed + output [`MAIA_CN:0] STANDBYWFI; // WFI mode + output [`MAIA_CN:0] STANDBYWFE; // WFE mode + output STANDBYWFIL2; // WFI mode for L2 + output [`MAIA_CN:0] SMPEN; // CPU SMP bit + + output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE + input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn + output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn + output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY + + output L2QACTIVE; // L2 Q-channel QACTIVE + input L2QREQn; // L2 Q-channel QREQn + output L2QACCEPTn; // L2 Q-channel QACCEPTn + output L2QDENY; // L2 Q-channel QDENY + + input L2FLUSHREQ; // L2 hardware flush request + output L2FLUSHDONE; // L2 hardware flush done + +//----------------------------------------------------------------------------- +// Asynchronous Error Signals +//----------------------------------------------------------------------------- + output nINTERRIRQ; // L2 RAM dbl-bit ECC error + output nEXTERRIRQ; // Write transaction error + +//----------------------------------------------------------------------------- +// Bus Configuration Signals +//----------------------------------------------------------------------------- + input SYSBARDISABLE; // Disable broadcast of barriers + input BROADCASTINNER; // Extend Inner Shared Domain + input BROADCASTOUTER; // Extend Outer Shared Domain + input BROADCASTCACHEMAINT; // Broadcast cache maint ops + +//----------------------------------------------------------------------------- +// Skyros RN-F Interface +//----------------------------------------------------------------------------- + input SCLKEN; // Skyros clock enable + input SINACT; // Skyros snoop inactive + + input [6:0] NODEID; // Skyros requestor NodeID + + output TXSACTIVE; // Skyros active - indicates pending activity on pins + input RXSACTIVE; // Skyros active - indicates pending activity on pins + + output TXLINKACTIVEREQ; // Skyros transmit link active request + input TXLINKACTIVEACK; // SKyros transmit link active acknowledge + + input RXLINKACTIVEREQ; // SKyros receive link active request + output RXLINKACTIVEACK; // Skyros receive link active acknowledge + +// TXREQ - outbound requests + output TXREQFLITPEND; // Skyros TXREQ FLIT pending + output TXREQFLITV; // Skyros TXREQ FLIT valid + output [99:0] TXREQFLIT; // Skyros TXREQ FLIT payload + output [7:0] REQMEMATTR; // Skyros TXREQ raw memory attributes + input TXREQLCRDV; // Skyros TXREQ link-layer credit valid + +// TXRSP - outbound response + output TXRSPFLITPEND; // Skyros TXRSP FLIT pending + output TXRSPFLITV; // Skyros TXRSP FLIT valid + output [44:0] TXRSPFLIT; // Skyros TXRSP FLIT payload + input TXRSPLCRDV; // Skyros TXRSP link-layer credit valid + +// TXDAT - outbound data + output TXDATFLITPEND; // Skyros TXDAT FLIT pending + output TXDATFLITV; // Skyros TXDAT FLIT valid + output [193:0] TXDATFLIT; // Skyros TXDAT FLIT payload + input TXDATLCRDV; // Skyros TXDAT link-layer credit valid + +// RXSNP - inbound snoops + input RXSNPFLITPEND; // Skyros RXSNP FLIT pending + input RXSNPFLITV; // Skyros RXSNP FLIT valid + input [64:0] RXSNPFLIT; // Skyros RXSNP FLIT payload + output RXSNPLCRDV; // Skyros RXSNP link-layer credit valid + +// RXRSP - inbound response + input RXRSPFLITPEND; // Skyros RXRSP FLIT pending + input RXRSPFLITV; // Skyros RXRSP FLIT valid + input [44:0] RXRSPFLIT; // Skyros RXRSP FLIT payload + output RXRSPLCRDV; // Skyros RXRSP link-layer credit valid + +// RXDAT - inbound data + input RXDATFLITPEND; // Skyros RXDAT FLIT pending + input RXDATFLITV; // Skyros RXDAT FLIT valid + input [193:0] RXDATFLIT; // Skyros RXDAT FLIT payload + output RXDATLCRDV; // Skyros RXDAT link-layer credit valid + + input [43:24] SAMMNBASE; // Skyros SAM MN base address + input [1:0] SAMADDRMAP0; // Skyros SAM address region 0 mapping + input [1:0] SAMADDRMAP1; // Skyros SAM address region 1 mapping + input [1:0] SAMADDRMAP2; // Skyros SAM address region 2 mapping + input [1:0] SAMADDRMAP3; // Skyros SAM address region 3 mapping + input [1:0] SAMADDRMAP4; // Skyros SAM address region 4 mapping + input [1:0] SAMADDRMAP5; // Skyros SAM address region 5 mapping + input [1:0] SAMADDRMAP6; // Skyros SAM address region 6 mapping + input [1:0] SAMADDRMAP7; // Skyros SAM address region 7 mapping + input [1:0] SAMADDRMAP8; // Skyros SAM address region 8 mapping + input [1:0] SAMADDRMAP9; // Skyros SAM address region 9 mapping + input [1:0] SAMADDRMAP10; // Skyros SAM address region 10 mapping + input [1:0] SAMADDRMAP11; // Skyros SAM address region 11 mapping + input [1:0] SAMADDRMAP12; // Skyros SAM address region 12 mapping + input [1:0] SAMADDRMAP13; // Skyros SAM address region 13 mapping + input [1:0] SAMADDRMAP14; // Skyros SAM address region 14 mapping + input [1:0] SAMADDRMAP15; // Skyros SAM address region 15 mapping + input [1:0] SAMADDRMAP16; // Skyros SAM address region 16 mapping + input [1:0] SAMADDRMAP17; // Skyros SAM address region 17 mapping + input [1:0] SAMADDRMAP18; // Skyros SAM address region 18 mapping + input [1:0] SAMADDRMAP19; // Skyros SAM address region 19 mapping + input [6:0] SAMMNNODEID; // Skyros SAM MN target ID + input [6:0] SAMHNI0NODEID; // Skyros SAM HNI0 target ID + input [6:0] SAMHNI1NODEID; // Skyros SAM HNI1 target ID + input [6:0] SAMHNF0NODEID; // Skyros SAM HNF0 target ID + input [6:0] SAMHNF1NODEID; // Skyros SAM HNF1 target ID + input [6:0] SAMHNF2NODEID; // Skyros SAM HNF2 target ID + input [6:0] SAMHNF3NODEID; // Skyros SAM HNF3 target ID + input [6:0] SAMHNF4NODEID; // Skyros SAM HNF4 target ID + input [6:0] SAMHNF5NODEID; // Skyros SAM HNF5 target ID + input [6:0] SAMHNF6NODEID; // Skyros SAM HNF6 target ID + input [6:0] SAMHNF7NODEID; // Skyros SAM HNF7 target ID + input [2:0] SAMHNFMODE; // Skyros SAM HNF interleaving mode + +// BEGIN NO-ACP pins +//----------------------------------------------------------------------------- +// ACP AXI Slave +//----------------------------------------------------------------------------- + input ACLKENS; // AXI slave clock enable + input AINACTS; // AXI slave interface no longer active or accepting requests +// Write Address channel signals + output AWREADYS; // Write Address ready (slave ready to accept write address) + input AWVALIDS; // Write Address valid + input [4:0] AWIDS; // Write Address ID + input [43:0] AWADDRS; // Write Address + input [7:0] AWLENS; // Write Burst Length + input [3:0] AWCACHES; // Write Cache type + input [1:0] AWUSERS; // Write inner & outer shareability + input [2:0] AWPROTS; // Write Protection type + +// Write Data channel signals + output WREADYS; // Write Data ready (slave ready to accept data) + input WVALIDS; // Write Data valid + input [127:0] WDATAS; // Write Data + input [15:0] WSTRBS; // Write byte-lane strobes + input WLASTS; // Write Data last transfer indicator + +// Write Response channel signals + input BREADYS; // Write Response ready (master ready to accept response) + output BVALIDS; // Write Response Valid + output [4:0] BIDS; // Write Response ID tag + output [1:0] BRESPS; // Write Response + +// Read Address channel signals + output ARREADYS; // Read Address ready (slave ready to accept read address) + input ARVALIDS; // Read Address valid + input [4:0] ARIDS; // Read Address ID + input [43:0] ARADDRS; // Read Address + input [7:0] ARLENS; // Read Burst Length + input [3:0] ARCACHES; // Read Cache type + input [1:0] ARUSERS; // Read inner & outer shareability + input [2:0] ARPROTS; // Read Protection type + +// Read Data channel signals + input RREADYS; // Read Data ready (master ready to accept data) + output RVALIDS; // Read Data valid + output [4:0] RIDS; // Read Data ID + output [127:0] RDATAS; // Read Data + output [1:0] RRESPS; // Read Data response + output RLASTS; // Read Data last transfer indicator +// END NO-ACP pins + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (CLK) +//----------------------------------------------------------------------------- +// Debug CLK interface + input [43:12] DBGROMADDR; // Debug ROM base address + input DBGROMADDRV; // Debug ROM base address valid + + output [`MAIA_CN:0] DBGACK; // Debug acknowledge + output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt + output [`MAIA_CN:0] COMMRX; // Comms channel receive + output [`MAIA_CN:0] COMMTX; // Comms channel transmit + + output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request + output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request + + input DBGL1RSTDISABLE; // L1 DCache hardware reset disable + +// PMU CLK interface + output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request + output [24:0] PMUEVENT0; // PMU Event bus +// BEGIN INCLUDE FOR CPU1 + output [24:0] PMUEVENT1; // PMU Event bus +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + output [24:0] PMUEVENT2; // PMU Event bus +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + output [24:0] PMUEVENT3; // PMU Event bus +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (ATCLK) +//----------------------------------------------------------------------------- +// ETM ATB interface and Misc signals + input ATCLKEN; // ATB Clock Enable + input [63:0] TSVALUEB; // ATB Timestamp in binary + + input ATREADYM0; // ATDATA can be accepted + input AFVALIDM0; // ATB Fifo Flush Request + output [31:0] ATDATAM0; // ATB Data + output ATVALIDM0; // ATB Data Valid + output [1:0] ATBYTESM0; // ATB Data Size + output AFREADYM0; // ATB Fifo Flush Finished + output [6:0] ATIDM0; // ATB Trace Source ID + input SYNCREQM0; // ATB External synchronization request + +// BEGIN INCLUDE FOR CPU1 + input ATREADYM1; // ATDATA can be accepted + input AFVALIDM1; // ATB Fifo Flush Request + output [31:0] ATDATAM1; // ATB Data + output ATVALIDM1; // ATB Data Valid + output [1:0] ATBYTESM1; // ATB Data Size + output AFREADYM1; // ATB Fifo Flush Finished + output [6:0] ATIDM1; // ATB Trace Source ID + input SYNCREQM1; // ATB External synchronization request +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ATREADYM2; // ATDATA can be accepted + input AFVALIDM2; // ATB Fifo Flush Request + output [31:0] ATDATAM2; // ATB Data + output ATVALIDM2; // ATB Data Valid + output [1:0] ATBYTESM2; // ATB Data Size + output AFREADYM2; // ATB Fifo Flush Finished + output [6:0] ATIDM2; // ATB Trace Source ID + input SYNCREQM2; // ATB External synchronization request +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ATREADYM3; // ATDATA can be accepted + input AFVALIDM3; // ATB Fifo Flush Request + output [31:0] ATDATAM3; // ATB Data + output ATVALIDM3; // ATB Data Valid + output [1:0] ATBYTESM3; // ATB Data Size + output AFREADYM3; // ATB Fifo Flush Finished + output [6:0] ATIDM3; // ATB Trace Source ID + input SYNCREQM3; // ATB External synchronization request +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (PCLK) +//----------------------------------------------------------------------------- +// Debug-APBv3 port (APB) + input PCLKDBG; // APB Clock + input PCLKENDBG; // APB Clock Enable + input nPRESETDBG; // APB Reset + input PSELDBG; // Debug bus access + input [21:2] PADDRDBG; // APB address + input PADDRDBG31; // APB address bit[31] + input PENABLEDBG; // APB transfer complete flag + input PWRITEDBG; // APB read/write indicator + input [31:0] PWDATADBG; // APB write data + output [31:0] PRDATADBG; // APB read data + output PREADYDBG; // APB slave ready, used to extend a transfer + output PSLVERRDBG; // APB slave transfer error + +// Misc interface + input [`MAIA_CN:0] EDBGRQ; // External debug request + +// PMU Snapshot interface + input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request + output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge + +// Power-related interface + input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status + output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request + +// CTI interface + input [3:0] CTICHIN; // Channel In + input [3:0] CTICHOUTACK; // Channel Out acknowledge + output [3:0] CTICHOUT; // Channel Out + output [3:0] CTICHINACK; // Channel In acknowledge + input CISBYPASS; // Channel interface sync bypass + input [3:0] CIHSBYPASS; // Channel interface H/S bypass + output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt + input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge + +//----------------------------------------------------------------------------- +// Debug Authentication Interface (CLK & PCLK) +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] DBGEN; // Invasive debug enable + input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable + input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable + input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable + +//----------------------------------------------------------------------------- +// DFT Signals +//----------------------------------------------------------------------------- + input DFTSE; // Scan enable + input DFTRSTDISABLE; // Disable reset to cells during scan shift + input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr + input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 + input DFTRAMHOLD; // Holds data in RAMs + input DFTCLKBYPASS; // L2 RAM strobe clock bypass + input DFTMCPHOLD; // Disable multi-cycle RAM paths + +//----------------------------------------------------------------------------- +// MBIST Interface +//----------------------------------------------------------------------------- + input nMBISTRESET; // MBIST reset + input MBISTREQ; // MBIST mode request + + + // wires + wire aa64naa32_cpu0_o; + wire aa64naa32_cpu1_o; + wire aa64naa32_cpu2_o; + wire aa64naa32_cpu3_o; + wire afreadym_cpu0_i; + wire afreadym_cpu1_i; + wire afreadym_cpu2_i; + wire afreadym_cpu3_i; + wire afvalidm_cpu0_o; + wire afvalidm_cpu1_o; + wire afvalidm_cpu2_o; + wire afvalidm_cpu3_o; + wire [1:0] atbytesm_cpu0_i; + wire [1:0] atbytesm_cpu1_i; + wire [1:0] atbytesm_cpu2_i; + wire [1:0] atbytesm_cpu3_i; + wire atclken_cpu0_o; + wire atclken_cpu1_o; + wire atclken_cpu2_o; + wire atclken_cpu3_o; + wire [31:0] atdatam_cpu0_i; + wire [31:0] atdatam_cpu1_i; + wire [31:0] atdatam_cpu2_i; + wire [31:0] atdatam_cpu3_i; + wire [6:0] atidm_cpu0_i; + wire [6:0] atidm_cpu1_i; + wire [6:0] atidm_cpu2_i; + wire [6:0] atidm_cpu3_i; + wire atreadym_cpu0_o; + wire atreadym_cpu1_o; + wire atreadym_cpu2_o; + wire atreadym_cpu3_o; + wire atvalidm_cpu0_i; + wire atvalidm_cpu1_i; + wire atvalidm_cpu2_i; + wire atvalidm_cpu3_i; + wire cfgend_cpu0_o; + wire cfgend_cpu1_o; + wire cfgend_cpu2_o; + wire cfgend_cpu3_o; + wire cfgte_cpu0_o; + wire cfgte_cpu1_o; + wire cfgte_cpu2_o; + wire cfgte_cpu3_o; + wire ck_cpu0_crcx_clk_en_n; + wire ck_cpu0_event_reg; + wire ck_cpu0_wfe_ack; + wire ck_cpu0_wfi_ack; + wire ck_cpu1_crcx_clk_en_n; + wire ck_cpu1_event_reg; + wire ck_cpu1_wfe_ack; + wire ck_cpu1_wfi_ack; + wire ck_cpu2_crcx_clk_en_n; + wire ck_cpu2_event_reg; + wire ck_cpu2_wfe_ack; + wire ck_cpu2_wfi_ack; + wire ck_cpu3_crcx_clk_en_n; + wire ck_cpu3_event_reg; + wire ck_cpu3_wfe_ack; + wire ck_cpu3_wfi_ack; + wire [`MAIA_CN:0] ck_gclkt; + wire [7:0] clusteridaff1_cpu0_o; + wire [7:0] clusteridaff1_cpu1_o; + wire [7:0] clusteridaff1_cpu2_o; + wire [7:0] clusteridaff1_cpu3_o; + wire [7:0] clusteridaff2_cpu0_o; + wire [7:0] clusteridaff2_cpu1_o; + wire [7:0] clusteridaff2_cpu2_o; + wire [7:0] clusteridaff2_cpu3_o; + wire commrx_cpu0_i; + wire commrx_cpu1_i; + wire commrx_cpu2_i; + wire commrx_cpu3_i; + wire commtx_cpu0_i; + wire commtx_cpu1_i; + wire commtx_cpu2_i; + wire commtx_cpu3_i; + wire cp15sdisable_cpu0_o; + wire cp15sdisable_cpu1_o; + wire cp15sdisable_cpu2_o; + wire cp15sdisable_cpu3_o; + wire [1:0] cpuid_cpu0_o; + wire [1:0] cpuid_cpu1_o; + wire [1:0] cpuid_cpu2_o; + wire [1:0] cpuid_cpu3_o; + wire cryptodisable_cpu0_o; + wire cryptodisable_cpu1_o; + wire cryptodisable_cpu2_o; + wire cryptodisable_cpu3_o; + wire dbgack_cpu0_i; + wire dbgack_cpu1_i; + wire dbgack_cpu2_i; + wire dbgack_cpu3_i; + wire dbgen_cpu0_o; + wire dbgen_cpu1_o; + wire dbgen_cpu2_o; + wire dbgen_cpu3_o; + wire dbgl1rstdisable_cpu0_o; + wire dbgl1rstdisable_cpu1_o; + wire dbgl1rstdisable_cpu2_o; + wire dbgl1rstdisable_cpu3_o; + wire dbgnopwrdwn_cpu0_i; + wire dbgnopwrdwn_cpu1_i; + wire dbgnopwrdwn_cpu2_i; + wire dbgnopwrdwn_cpu3_i; + wire [43:12] dbgromaddr_cpu0_o; + wire [43:12] dbgromaddr_cpu1_o; + wire [43:12] dbgromaddr_cpu2_o; + wire [43:12] dbgromaddr_cpu3_o; + wire dbgromaddrv_cpu0_o; + wire dbgromaddrv_cpu1_o; + wire dbgromaddrv_cpu2_o; + wire dbgromaddrv_cpu3_o; + wire dbgrstreq_cpu0_i; + wire dbgrstreq_cpu1_i; + wire dbgrstreq_cpu2_i; + wire dbgrstreq_cpu3_i; + wire dftcrclkdisable_cpu0_o; + wire dftcrclkdisable_cpu1_o; + wire dftcrclkdisable_cpu2_o; + wire dftcrclkdisable_cpu3_o; + wire dftramhold_cpu0_o; + wire dftramhold_cpu1_o; + wire dftramhold_cpu2_o; + wire dftramhold_cpu3_o; + wire dftrstdisable_cpu0_o; + wire dftrstdisable_cpu1_o; + wire dftrstdisable_cpu2_o; + wire dftrstdisable_cpu3_o; + wire dftse_cpu0_o; + wire dftse_cpu1_o; + wire dftse_cpu2_o; + wire dftse_cpu3_o; + wire [2:0] ds_cpu0_cpuectlr_ret; + wire ds_cpu0_cpuectlr_smp; + wire ds_cpu0_fiq_wfe_qual; + wire ds_cpu0_fiq_wfi_qual; + wire ds_cpu0_flush; + wire [5:0] ds_cpu0_flush_type; + wire ds_cpu0_hcr_va; + wire ds_cpu0_hcr_vf; + wire ds_cpu0_hcr_vi; + wire ds_cpu0_ic_aa64naa32; + wire [4:0] ds_cpu0_ic_cpsr_mode; + wire ds_cpu0_ic_hcr_change; + wire ds_cpu0_ic_sample_spr; + wire ds_cpu0_ic_scr_change; + wire ds_cpu0_imp_abrt_wfe_qual; + wire ds_cpu0_imp_abrt_wfi_qual; + wire ds_cpu0_irq_wfe_qual; + wire ds_cpu0_irq_wfi_qual; + wire [8:0] ds_cpu0_l2_spr_addr; + wire ds_cpu0_l2_spr_dw; + wire ds_cpu0_l2_spr_en; + wire ds_cpu0_l2_spr_rd; + wire ds_cpu0_l2_spr_wr; + wire [63:0] ds_cpu0_l2_spr_wr_data; + wire ds_cpu0_reset_req; + wire ds_cpu0_sev_req; + wire ds_cpu0_sevl_req; + wire ds_cpu0_vfiq_wfe_qual; + wire ds_cpu0_vfiq_wfi_qual; + wire ds_cpu0_vimp_abrt_wfe_qual; + wire ds_cpu0_vimp_abrt_wfi_qual; + wire ds_cpu0_virq_wfe_qual; + wire ds_cpu0_virq_wfi_qual; + wire ds_cpu0_wfe_req; + wire ds_cpu0_wfi_req; + wire [2:0] ds_cpu1_cpuectlr_ret; + wire ds_cpu1_cpuectlr_smp; + wire ds_cpu1_fiq_wfe_qual; + wire ds_cpu1_fiq_wfi_qual; + wire ds_cpu1_flush; + wire [5:0] ds_cpu1_flush_type; + wire ds_cpu1_hcr_va; + wire ds_cpu1_hcr_vf; + wire ds_cpu1_hcr_vi; + wire ds_cpu1_ic_aa64naa32; + wire [4:0] ds_cpu1_ic_cpsr_mode; + wire ds_cpu1_ic_hcr_change; + wire ds_cpu1_ic_sample_spr; + wire ds_cpu1_ic_scr_change; + wire ds_cpu1_imp_abrt_wfe_qual; + wire ds_cpu1_imp_abrt_wfi_qual; + wire ds_cpu1_irq_wfe_qual; + wire ds_cpu1_irq_wfi_qual; + wire [8:0] ds_cpu1_l2_spr_addr; + wire ds_cpu1_l2_spr_dw; + wire ds_cpu1_l2_spr_en; + wire ds_cpu1_l2_spr_rd; + wire ds_cpu1_l2_spr_wr; + wire [63:0] ds_cpu1_l2_spr_wr_data; + wire ds_cpu1_reset_req; + wire ds_cpu1_sev_req; + wire ds_cpu1_sevl_req; + wire ds_cpu1_vfiq_wfe_qual; + wire ds_cpu1_vfiq_wfi_qual; + wire ds_cpu1_vimp_abrt_wfe_qual; + wire ds_cpu1_vimp_abrt_wfi_qual; + wire ds_cpu1_virq_wfe_qual; + wire ds_cpu1_virq_wfi_qual; + wire ds_cpu1_wfe_req; + wire ds_cpu1_wfi_req; + wire [2:0] ds_cpu2_cpuectlr_ret; + wire ds_cpu2_cpuectlr_smp; + wire ds_cpu2_fiq_wfe_qual; + wire ds_cpu2_fiq_wfi_qual; + wire ds_cpu2_flush; + wire [5:0] ds_cpu2_flush_type; + wire ds_cpu2_hcr_va; + wire ds_cpu2_hcr_vf; + wire ds_cpu2_hcr_vi; + wire ds_cpu2_ic_aa64naa32; + wire [4:0] ds_cpu2_ic_cpsr_mode; + wire ds_cpu2_ic_hcr_change; + wire ds_cpu2_ic_sample_spr; + wire ds_cpu2_ic_scr_change; + wire ds_cpu2_imp_abrt_wfe_qual; + wire ds_cpu2_imp_abrt_wfi_qual; + wire ds_cpu2_irq_wfe_qual; + wire ds_cpu2_irq_wfi_qual; + wire [8:0] ds_cpu2_l2_spr_addr; + wire ds_cpu2_l2_spr_dw; + wire ds_cpu2_l2_spr_en; + wire ds_cpu2_l2_spr_rd; + wire ds_cpu2_l2_spr_wr; + wire [63:0] ds_cpu2_l2_spr_wr_data; + wire ds_cpu2_reset_req; + wire ds_cpu2_sev_req; + wire ds_cpu2_sevl_req; + wire ds_cpu2_vfiq_wfe_qual; + wire ds_cpu2_vfiq_wfi_qual; + wire ds_cpu2_vimp_abrt_wfe_qual; + wire ds_cpu2_vimp_abrt_wfi_qual; + wire ds_cpu2_virq_wfe_qual; + wire ds_cpu2_virq_wfi_qual; + wire ds_cpu2_wfe_req; + wire ds_cpu2_wfi_req; + wire [2:0] ds_cpu3_cpuectlr_ret; + wire ds_cpu3_cpuectlr_smp; + wire ds_cpu3_fiq_wfe_qual; + wire ds_cpu3_fiq_wfi_qual; + wire ds_cpu3_flush; + wire [5:0] ds_cpu3_flush_type; + wire ds_cpu3_hcr_va; + wire ds_cpu3_hcr_vf; + wire ds_cpu3_hcr_vi; + wire ds_cpu3_ic_aa64naa32; + wire [4:0] ds_cpu3_ic_cpsr_mode; + wire ds_cpu3_ic_hcr_change; + wire ds_cpu3_ic_sample_spr; + wire ds_cpu3_ic_scr_change; + wire ds_cpu3_imp_abrt_wfe_qual; + wire ds_cpu3_imp_abrt_wfi_qual; + wire ds_cpu3_irq_wfe_qual; + wire ds_cpu3_irq_wfi_qual; + wire [8:0] ds_cpu3_l2_spr_addr; + wire ds_cpu3_l2_spr_dw; + wire ds_cpu3_l2_spr_en; + wire ds_cpu3_l2_spr_rd; + wire ds_cpu3_l2_spr_wr; + wire [63:0] ds_cpu3_l2_spr_wr_data; + wire ds_cpu3_reset_req; + wire ds_cpu3_sev_req; + wire ds_cpu3_sevl_req; + wire ds_cpu3_vfiq_wfe_qual; + wire ds_cpu3_vfiq_wfi_qual; + wire ds_cpu3_vimp_abrt_wfe_qual; + wire ds_cpu3_vimp_abrt_wfi_qual; + wire ds_cpu3_virq_wfe_qual; + wire ds_cpu3_virq_wfi_qual; + wire ds_cpu3_wfe_req; + wire ds_cpu3_wfi_req; + wire dt_cpu0_coredbg_in_reset_gclk; + wire [1:0] dt_cpu0_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu0_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu0_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu0_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu0_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu0_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; + wire dt_cpu0_cti_trigoutack_bit1_gclk; + wire dt_cpu0_dbif_ack_gclk; + wire [14:2] dt_cpu0_dbif_addr_pclk; + wire dt_cpu0_dbif_err_gclk; + wire dt_cpu0_dbif_locked_pclk; + wire [31:0] dt_cpu0_dbif_rddata_gclk; + wire dt_cpu0_dbif_req_pclk; + wire [31:0] dt_cpu0_dbif_wrdata_pclk; + wire dt_cpu0_dbif_write_pclk; + wire dt_cpu0_edacr_frc_idleack_pclk; + wire dt_cpu0_edbgrq_pclk; + wire dt_cpu0_edecr_osuce_pclk; + wire dt_cpu0_edecr_rce_pclk; + wire dt_cpu0_edecr_ss_pclk; + wire dt_cpu0_edprcr_corepurq_pclk; + wire dt_cpu0_et_oslock_gclk; + wire dt_cpu0_halt_ack_gclk; + wire dt_cpu0_hlt_dbgevt_ok_gclk; + wire dt_cpu0_noclkstop_pclk; + wire dt_cpu0_os_double_lock_gclk; + wire dt_cpu0_pmusnapshot_ack_gclk; + wire dt_cpu0_pmusnapshot_req_pclk; + wire dt_cpu0_wfx_dbg_req_gclk; + wire dt_cpu0_wfx_wakeup_pclk; + wire dt_cpu1_coredbg_in_reset_gclk; + wire [1:0] dt_cpu1_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu1_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu1_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu1_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu1_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu1_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; + wire dt_cpu1_cti_trigoutack_bit1_gclk; + wire dt_cpu1_dbif_ack_gclk; + wire [14:2] dt_cpu1_dbif_addr_pclk; + wire dt_cpu1_dbif_err_gclk; + wire dt_cpu1_dbif_locked_pclk; + wire [31:0] dt_cpu1_dbif_rddata_gclk; + wire dt_cpu1_dbif_req_pclk; + wire [31:0] dt_cpu1_dbif_wrdata_pclk; + wire dt_cpu1_dbif_write_pclk; + wire dt_cpu1_edacr_frc_idleack_pclk; + wire dt_cpu1_edbgrq_pclk; + wire dt_cpu1_edecr_osuce_pclk; + wire dt_cpu1_edecr_rce_pclk; + wire dt_cpu1_edecr_ss_pclk; + wire dt_cpu1_edprcr_corepurq_pclk; + wire dt_cpu1_et_oslock_gclk; + wire dt_cpu1_halt_ack_gclk; + wire dt_cpu1_hlt_dbgevt_ok_gclk; + wire dt_cpu1_noclkstop_pclk; + wire dt_cpu1_os_double_lock_gclk; + wire dt_cpu1_pmusnapshot_ack_gclk; + wire dt_cpu1_pmusnapshot_req_pclk; + wire dt_cpu1_wfx_dbg_req_gclk; + wire dt_cpu1_wfx_wakeup_pclk; + wire dt_cpu2_coredbg_in_reset_gclk; + wire [1:0] dt_cpu2_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu2_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu2_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu2_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu2_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu2_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; + wire dt_cpu2_cti_trigoutack_bit1_gclk; + wire dt_cpu2_dbif_ack_gclk; + wire [14:2] dt_cpu2_dbif_addr_pclk; + wire dt_cpu2_dbif_err_gclk; + wire dt_cpu2_dbif_locked_pclk; + wire [31:0] dt_cpu2_dbif_rddata_gclk; + wire dt_cpu2_dbif_req_pclk; + wire [31:0] dt_cpu2_dbif_wrdata_pclk; + wire dt_cpu2_dbif_write_pclk; + wire dt_cpu2_edacr_frc_idleack_pclk; + wire dt_cpu2_edbgrq_pclk; + wire dt_cpu2_edecr_osuce_pclk; + wire dt_cpu2_edecr_rce_pclk; + wire dt_cpu2_edecr_ss_pclk; + wire dt_cpu2_edprcr_corepurq_pclk; + wire dt_cpu2_et_oslock_gclk; + wire dt_cpu2_halt_ack_gclk; + wire dt_cpu2_hlt_dbgevt_ok_gclk; + wire dt_cpu2_noclkstop_pclk; + wire dt_cpu2_os_double_lock_gclk; + wire dt_cpu2_pmusnapshot_ack_gclk; + wire dt_cpu2_pmusnapshot_req_pclk; + wire dt_cpu2_wfx_dbg_req_gclk; + wire dt_cpu2_wfx_wakeup_pclk; + wire dt_cpu3_coredbg_in_reset_gclk; + wire [1:0] dt_cpu3_cti_trigin_1to0_gclk; + wire [3:0] dt_cpu3_cti_trigin_7to4_gclk; + wire [1:0] dt_cpu3_cti_triginack_1to0_pclk; + wire [3:0] dt_cpu3_cti_triginack_7to4_pclk; + wire [1:0] dt_cpu3_cti_trigout_1to0_pclk; + wire [3:0] dt_cpu3_cti_trigout_7to4_pclk; + wire [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; + wire dt_cpu3_cti_trigoutack_bit1_gclk; + wire dt_cpu3_dbif_ack_gclk; + wire [14:2] dt_cpu3_dbif_addr_pclk; + wire dt_cpu3_dbif_err_gclk; + wire dt_cpu3_dbif_locked_pclk; + wire [31:0] dt_cpu3_dbif_rddata_gclk; + wire dt_cpu3_dbif_req_pclk; + wire [31:0] dt_cpu3_dbif_wrdata_pclk; + wire dt_cpu3_dbif_write_pclk; + wire dt_cpu3_edacr_frc_idleack_pclk; + wire dt_cpu3_edbgrq_pclk; + wire dt_cpu3_edecr_osuce_pclk; + wire dt_cpu3_edecr_rce_pclk; + wire dt_cpu3_edecr_ss_pclk; + wire dt_cpu3_edprcr_corepurq_pclk; + wire dt_cpu3_et_oslock_gclk; + wire dt_cpu3_halt_ack_gclk; + wire dt_cpu3_hlt_dbgevt_ok_gclk; + wire dt_cpu3_noclkstop_pclk; + wire dt_cpu3_os_double_lock_gclk; + wire dt_cpu3_pmusnapshot_ack_gclk; + wire dt_cpu3_pmusnapshot_req_pclk; + wire dt_cpu3_wfx_dbg_req_gclk; + wire dt_cpu3_wfx_wakeup_pclk; + wire etclken_cpu0_i; + wire etclken_cpu1_i; + wire etclken_cpu2_i; + wire etclken_cpu3_i; + wire giccdisable_cpu0_o; + wire giccdisable_cpu1_o; + wire giccdisable_cpu2_o; + wire giccdisable_cpu3_o; + wire [`MAIA_CN:0] ic_block_eoi_sgi_wr; + wire [`MAIA_CN:0] ic_el_change_complete; + wire [`MAIA_CN:0] ic_hcr_change_complete; + wire [`MAIA_CN:0] ic_ich_el2_tall0; + wire [`MAIA_CN:0] ic_ich_el2_tall1; + wire [`MAIA_CN:0] ic_ich_el2_tc; + wire [`MAIA_CN:0] ic_nfiq; + wire [`MAIA_CN:0] ic_nirq; + wire [`MAIA_CN:0] ic_nsei; + wire [`MAIA_CN:0] ic_nvfiq; + wire [`MAIA_CN:0] ic_nvirq; + wire [`MAIA_CN:0] ic_nvsei; + wire [`MAIA_CN:0] ic_p_valid; + wire [`MAIA_CN:0] ic_sample_spr; + wire [`MAIA_CN:0] ic_scr_change_complete; + wire [`MAIA_CN:0] ic_sra_el1ns_en; + wire [`MAIA_CN:0] ic_sra_el1s_en; + wire [`MAIA_CN:0] ic_sra_el2_en; + wire [`MAIA_CN:0] ic_sra_el3_en; + wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; + wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap; + wire [`MAIA_CN:0] ic_sre_el1s_mon_trap; + wire [`MAIA_CN:0] ic_sre_el2_mon_trap; + wire l2_cpu0_arb_thrshld_timeout_en; + wire l2_cpu0_barrier_done; + wire l2_cpu0_blk_non_evict_wr; + wire l2_cpu0_ccb_dbg_req_c3; + wire [48:0] l2_cpu0_ccb_req_addr_c3; + wire [4:0] l2_cpu0_ccb_req_id_c3; + wire [23:0] l2_cpu0_ccb_req_info_c3; + wire [8:0] l2_cpu0_ccb_req_type_c3; + wire l2_cpu0_cfg_ecc_en; + wire [2:0] l2_cpu0_dbufid_r1; + wire [129:0] l2_cpu0_ddata_r2; + wire l2_cpu0_ddlb_ecc_err_r3; + wire l2_cpu0_dext_err_r2; + wire l2_cpu0_dext_err_type_r2; + wire l2_cpu0_disable_clean_evict_opt; + wire l2_cpu0_dlast_r1; + wire l2_cpu0_dsngl_ecc_err_r3; + wire [3:0] l2_cpu0_dsq_clr_id_q; + wire l2_cpu0_dsq_clr_vld_q; + wire [3:0] l2_cpu0_dsq_rd_buf_id; + wire [15:0] l2_cpu0_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu0_dsq_rd_data_q; + wire l2_cpu0_dsq_rd_en; + wire l2_cpu0_dsq_rd_en_x2; + wire l2_cpu0_dt_pmu_evt_en; + wire l2_cpu0_dvalid_r1; + wire l2_cpu0_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; + wire l2_cpu0_flsh_if_rd_l4_dly; + wire l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; + wire l2_cpu0_flsh_ls_rd_l2_dly; + wire l2_cpu0_flsh_ls_rd_l4_dly; + wire l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; + wire l2_cpu0_flsh_ls_wr_l2_dly; + wire l2_cpu0_flsh_ls_wr_l4_dly; + wire l2_cpu0_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu0_ibufid_r1; + wire [15:0] l2_cpu0_ic_addr_arb_set; + wire l2_cpu0_ic_arb_fast; + wire l2_cpu0_ic_barrier_stall_q; + wire [43:18] l2_cpu0_ic_base; + wire [31:0] l2_cpu0_ic_data_arb_set; + wire [2:0] l2_cpu0_ic_elem_size_arb_set; + wire l2_cpu0_ic_excl_arb_set; + wire [2:0] l2_cpu0_ic_id_arb_set; + wire l2_cpu0_ic_ns_arb_set; + wire l2_cpu0_ic_vld_skid; + wire l2_cpu0_ic_write_arb_set; + wire [127:0] l2_cpu0_idata_r2; + wire l2_cpu0_idlb_ecc_err_r3; + wire l2_cpu0_idle_block_reqs_q; + wire l2_cpu0_idle_wakeup_q; + wire l2_cpu0_iext_err_r2; + wire l2_cpu0_iext_err_type_r2; + wire l2_cpu0_if_ccb_clken_c3; + wire l2_cpu0_if_ccb_req_c3; + wire l2_cpu0_if_ccb_resp; + wire [4:0] l2_cpu0_if_ccb_resp_id; + wire l2_cpu0_if_sync_done_q; + wire l2_cpu0_if_sync_req; + wire l2_cpu0_ifq_haz_pending; + wire l2_cpu0_isngl_ecc_err_r3; + wire l2_cpu0_ivalid_r1; + wire [1:0] l2_cpu0_l2_cache_size; + wire [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; + wire l2_cpu0_lrq_haz_pending; + wire l2_cpu0_ls_ccb_clken_c3; + wire l2_cpu0_ls_ccb_data_wr; + wire l2_cpu0_ls_ccb_req_c3; + wire l2_cpu0_ls_ccb_resp; + wire [4:0] l2_cpu0_ls_ccb_resp_id; + wire l2_cpu0_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu0_ls_rd_haz_id_arb_q; + wire l2_cpu0_ls_rd_haz_vld_arb_q; + wire l2_cpu0_ls_sync_req; + wire [4:0] l2_cpu0_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu0_ls_wr_data_w2a; + wire l2_cpu0_ls_wr_dirty_w2a; + wire l2_cpu0_ls_wr_err_w2a; + wire [2:0] l2_cpu0_ls_wr_haz_id_arb_q; + wire l2_cpu0_ls_wr_haz_vld_arb_q; + wire l2_cpu0_ls_wr_last_w2a; + wire l2_cpu0_ls_wr_req_w2a; + wire [2:0] l2_cpu0_ls_wr_type_w2a; + wire [12:0] l2_cpu0_mbist1_addr_b1; + wire l2_cpu0_mbist1_all_b1; + wire [3:0] l2_cpu0_mbist1_array_b1; + wire [7:0] l2_cpu0_mbist1_be_b1; + wire l2_cpu0_mbist1_en_b1; + wire l2_cpu0_mbist1_rd_en_b1; + wire l2_cpu0_mbist1_wr_en_b1; + wire l2_cpu0_no_intctrl; + wire l2_cpu0_pf_rd_vld_skid_popped; + wire l2_cpu0_pf_throttle_q; + wire [33:0] l2_cpu0_pmu_events; + wire [2:0] l2_cpu0_rbufid; + wire l2_cpu0_rd_aarch64_arb_set; + wire [44:0] l2_cpu0_rd_addr_arb_set; + wire l2_cpu0_rd_arb; + wire l2_cpu0_rd_arb_fast; + wire [15:8] l2_cpu0_rd_asid_arb_set; + wire l2_cpu0_rd_bypass_arb_set; + wire [2:0] l2_cpu0_rd_bypass_bufid_e5; + wire [2:0] l2_cpu0_rd_bypass_lrq_id_e5; + wire l2_cpu0_rd_bypass_req_can_e5; + wire l2_cpu0_rd_bypass_way_e5; + wire [2:0] l2_cpu0_rd_cache_attr_arb_set; + wire [2:0] l2_cpu0_rd_elem_size_arb_set; + wire l2_cpu0_rd_excl_arb_set; + wire [4:0] l2_cpu0_rd_id_arb_set; + wire [2:0] l2_cpu0_rd_lrq_id_arb_set; + wire [7:0] l2_cpu0_rd_page_attr_arb_set; + wire l2_cpu0_rd_prfm_arb_set; + wire l2_cpu0_rd_priv_arb_set; + wire l2_cpu0_rd_replayed_arb_set; + wire [1:0] l2_cpu0_rd_shared_arb_set; + wire [6:0] l2_cpu0_rd_type_arb_set; + wire l2_cpu0_rd_va48_arb_set; + wire l2_cpu0_rd_vld_skid; + wire l2_cpu0_rd_way_arb_set; + wire l2_cpu0_rexfail; + wire [1:0] l2_cpu0_rstate; + wire l2_cpu0_rvalid; + wire [2:0] l2_cpu0_spec_bufid; + wire l2_cpu0_spec_valid; + wire [63:0] l2_cpu0_spr_rd_data; + wire l2_cpu0_tbw_dbl_ecc_err; + wire [63:0] l2_cpu0_tbw_desc_data; + wire l2_cpu0_tbw_desc_vld; + wire l2_cpu0_tbw_ext_err; + wire l2_cpu0_tbw_ext_err_type; + wire l2_cpu0_tlb_ccb_clken_c3; + wire l2_cpu0_tlb_ccb_req_c3; + wire l2_cpu0_tlb_sync_complete; + wire l2_cpu0_tlb_sync_done_q; + wire l2_cpu0_tlb_sync_req; + wire l2_cpu0_trq_haz_pending; + wire l2_cpu0_tw_ccb_resp; + wire [4:0] l2_cpu0_tw_ccb_resp_id; + wire l2_cpu0_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu0_wr_addr_arb_set; + wire l2_cpu0_wr_arb; + wire l2_cpu0_wr_arb_fast; + wire [2:0] l2_cpu0_wr_cache_attr_arb_set; + wire [11:0] l2_cpu0_wr_cl_id_arb_set; + wire l2_cpu0_wr_clean_evict_arb_set; + wire [143:0] l2_cpu0_wr_data; + wire l2_cpu0_wr_data_stall; + wire l2_cpu0_wr_data_vld_x1_q; + wire l2_cpu0_wr_dirty_arb_set; + wire [2:0] l2_cpu0_wr_elem_size_arb_set; + wire l2_cpu0_wr_err_arb_set; + wire l2_cpu0_wr_evict_x1_q; + wire l2_cpu0_wr_ex_fail; + wire l2_cpu0_wr_ex_resp; + wire [3:0] l2_cpu0_wr_id_arb_set; + wire l2_cpu0_wr_last_arb_set; + wire [7:0] l2_cpu0_wr_page_attr_arb_set; + wire [3:0] l2_cpu0_wr_partial_dw_arb_set; + wire l2_cpu0_wr_priv_arb_set; + wire [1:0] l2_cpu0_wr_shared_arb_set; + wire [2:0] l2_cpu0_wr_type_arb_set; + wire l2_cpu0_wr_vld_skid; + wire l2_cpu0_wr_way_arb_set; + wire l2_cpu0_wrq_almost_full; + wire [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; + wire l2_cpu0_wrq_haz_pending; + wire l2_cpu1_arb_thrshld_timeout_en; + wire l2_cpu1_barrier_done; + wire l2_cpu1_blk_non_evict_wr; + wire l2_cpu1_ccb_dbg_req_c3; + wire [48:0] l2_cpu1_ccb_req_addr_c3; + wire [4:0] l2_cpu1_ccb_req_id_c3; + wire [23:0] l2_cpu1_ccb_req_info_c3; + wire [8:0] l2_cpu1_ccb_req_type_c3; + wire l2_cpu1_cfg_ecc_en; + wire [2:0] l2_cpu1_dbufid_r1; + wire [129:0] l2_cpu1_ddata_r2; + wire l2_cpu1_ddlb_ecc_err_r3; + wire l2_cpu1_dext_err_r2; + wire l2_cpu1_dext_err_type_r2; + wire l2_cpu1_disable_clean_evict_opt; + wire l2_cpu1_dlast_r1; + wire l2_cpu1_dsngl_ecc_err_r3; + wire [3:0] l2_cpu1_dsq_clr_id_q; + wire l2_cpu1_dsq_clr_vld_q; + wire [3:0] l2_cpu1_dsq_rd_buf_id; + wire [15:0] l2_cpu1_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu1_dsq_rd_data_q; + wire l2_cpu1_dsq_rd_en; + wire l2_cpu1_dsq_rd_en_x2; + wire l2_cpu1_dt_pmu_evt_en; + wire l2_cpu1_dvalid_r1; + wire l2_cpu1_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; + wire l2_cpu1_flsh_if_rd_l4_dly; + wire l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; + wire l2_cpu1_flsh_ls_rd_l2_dly; + wire l2_cpu1_flsh_ls_rd_l4_dly; + wire l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; + wire l2_cpu1_flsh_ls_wr_l2_dly; + wire l2_cpu1_flsh_ls_wr_l4_dly; + wire l2_cpu1_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu1_ibufid_r1; + wire [15:0] l2_cpu1_ic_addr_arb_set; + wire l2_cpu1_ic_arb_fast; + wire l2_cpu1_ic_barrier_stall_q; + wire [43:18] l2_cpu1_ic_base; + wire [31:0] l2_cpu1_ic_data_arb_set; + wire [2:0] l2_cpu1_ic_elem_size_arb_set; + wire l2_cpu1_ic_excl_arb_set; + wire [2:0] l2_cpu1_ic_id_arb_set; + wire l2_cpu1_ic_ns_arb_set; + wire l2_cpu1_ic_vld_skid; + wire l2_cpu1_ic_write_arb_set; + wire [127:0] l2_cpu1_idata_r2; + wire l2_cpu1_idlb_ecc_err_r3; + wire l2_cpu1_idle_block_reqs_q; + wire l2_cpu1_idle_wakeup_q; + wire l2_cpu1_iext_err_r2; + wire l2_cpu1_iext_err_type_r2; + wire l2_cpu1_if_ccb_clken_c3; + wire l2_cpu1_if_ccb_req_c3; + wire l2_cpu1_if_ccb_resp; + wire [4:0] l2_cpu1_if_ccb_resp_id; + wire l2_cpu1_if_sync_done_q; + wire l2_cpu1_if_sync_req; + wire l2_cpu1_ifq_haz_pending; + wire l2_cpu1_isngl_ecc_err_r3; + wire l2_cpu1_ivalid_r1; + wire [1:0] l2_cpu1_l2_cache_size; + wire [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; + wire l2_cpu1_lrq_haz_pending; + wire l2_cpu1_ls_ccb_clken_c3; + wire l2_cpu1_ls_ccb_data_wr; + wire l2_cpu1_ls_ccb_req_c3; + wire l2_cpu1_ls_ccb_resp; + wire [4:0] l2_cpu1_ls_ccb_resp_id; + wire l2_cpu1_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu1_ls_rd_haz_id_arb_q; + wire l2_cpu1_ls_rd_haz_vld_arb_q; + wire l2_cpu1_ls_sync_req; + wire [4:0] l2_cpu1_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu1_ls_wr_data_w2a; + wire l2_cpu1_ls_wr_dirty_w2a; + wire l2_cpu1_ls_wr_err_w2a; + wire [2:0] l2_cpu1_ls_wr_haz_id_arb_q; + wire l2_cpu1_ls_wr_haz_vld_arb_q; + wire l2_cpu1_ls_wr_last_w2a; + wire l2_cpu1_ls_wr_req_w2a; + wire [2:0] l2_cpu1_ls_wr_type_w2a; + wire [12:0] l2_cpu1_mbist1_addr_b1; + wire l2_cpu1_mbist1_all_b1; + wire [3:0] l2_cpu1_mbist1_array_b1; + wire [7:0] l2_cpu1_mbist1_be_b1; + wire l2_cpu1_mbist1_en_b1; + wire l2_cpu1_mbist1_rd_en_b1; + wire l2_cpu1_mbist1_wr_en_b1; + wire l2_cpu1_no_intctrl; + wire l2_cpu1_pf_rd_vld_skid_popped; + wire l2_cpu1_pf_throttle_q; + wire [33:0] l2_cpu1_pmu_events; + wire [2:0] l2_cpu1_rbufid; + wire l2_cpu1_rd_aarch64_arb_set; + wire [44:0] l2_cpu1_rd_addr_arb_set; + wire l2_cpu1_rd_arb; + wire l2_cpu1_rd_arb_fast; + wire [15:8] l2_cpu1_rd_asid_arb_set; + wire l2_cpu1_rd_bypass_arb_set; + wire [2:0] l2_cpu1_rd_bypass_bufid_e5; + wire [2:0] l2_cpu1_rd_bypass_lrq_id_e5; + wire l2_cpu1_rd_bypass_req_can_e5; + wire l2_cpu1_rd_bypass_way_e5; + wire [2:0] l2_cpu1_rd_cache_attr_arb_set; + wire [2:0] l2_cpu1_rd_elem_size_arb_set; + wire l2_cpu1_rd_excl_arb_set; + wire [4:0] l2_cpu1_rd_id_arb_set; + wire [2:0] l2_cpu1_rd_lrq_id_arb_set; + wire [7:0] l2_cpu1_rd_page_attr_arb_set; + wire l2_cpu1_rd_prfm_arb_set; + wire l2_cpu1_rd_priv_arb_set; + wire l2_cpu1_rd_replayed_arb_set; + wire [1:0] l2_cpu1_rd_shared_arb_set; + wire [6:0] l2_cpu1_rd_type_arb_set; + wire l2_cpu1_rd_va48_arb_set; + wire l2_cpu1_rd_vld_skid; + wire l2_cpu1_rd_way_arb_set; + wire l2_cpu1_rexfail; + wire [1:0] l2_cpu1_rstate; + wire l2_cpu1_rvalid; + wire [2:0] l2_cpu1_spec_bufid; + wire l2_cpu1_spec_valid; + wire [63:0] l2_cpu1_spr_rd_data; + wire l2_cpu1_tbw_dbl_ecc_err; + wire [63:0] l2_cpu1_tbw_desc_data; + wire l2_cpu1_tbw_desc_vld; + wire l2_cpu1_tbw_ext_err; + wire l2_cpu1_tbw_ext_err_type; + wire l2_cpu1_tlb_ccb_clken_c3; + wire l2_cpu1_tlb_ccb_req_c3; + wire l2_cpu1_tlb_sync_complete; + wire l2_cpu1_tlb_sync_done_q; + wire l2_cpu1_tlb_sync_req; + wire l2_cpu1_trq_haz_pending; + wire l2_cpu1_tw_ccb_resp; + wire [4:0] l2_cpu1_tw_ccb_resp_id; + wire l2_cpu1_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu1_wr_addr_arb_set; + wire l2_cpu1_wr_arb; + wire l2_cpu1_wr_arb_fast; + wire [2:0] l2_cpu1_wr_cache_attr_arb_set; + wire [11:0] l2_cpu1_wr_cl_id_arb_set; + wire l2_cpu1_wr_clean_evict_arb_set; + wire [143:0] l2_cpu1_wr_data; + wire l2_cpu1_wr_data_stall; + wire l2_cpu1_wr_data_vld_x1_q; + wire l2_cpu1_wr_dirty_arb_set; + wire [2:0] l2_cpu1_wr_elem_size_arb_set; + wire l2_cpu1_wr_err_arb_set; + wire l2_cpu1_wr_evict_x1_q; + wire l2_cpu1_wr_ex_fail; + wire l2_cpu1_wr_ex_resp; + wire [3:0] l2_cpu1_wr_id_arb_set; + wire l2_cpu1_wr_last_arb_set; + wire [7:0] l2_cpu1_wr_page_attr_arb_set; + wire [3:0] l2_cpu1_wr_partial_dw_arb_set; + wire l2_cpu1_wr_priv_arb_set; + wire [1:0] l2_cpu1_wr_shared_arb_set; + wire [2:0] l2_cpu1_wr_type_arb_set; + wire l2_cpu1_wr_vld_skid; + wire l2_cpu1_wr_way_arb_set; + wire l2_cpu1_wrq_almost_full; + wire [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; + wire l2_cpu1_wrq_haz_pending; + wire l2_cpu2_arb_thrshld_timeout_en; + wire l2_cpu2_barrier_done; + wire l2_cpu2_blk_non_evict_wr; + wire l2_cpu2_ccb_dbg_req_c3; + wire [48:0] l2_cpu2_ccb_req_addr_c3; + wire [4:0] l2_cpu2_ccb_req_id_c3; + wire [23:0] l2_cpu2_ccb_req_info_c3; + wire [8:0] l2_cpu2_ccb_req_type_c3; + wire l2_cpu2_cfg_ecc_en; + wire [2:0] l2_cpu2_dbufid_r1; + wire [129:0] l2_cpu2_ddata_r2; + wire l2_cpu2_ddlb_ecc_err_r3; + wire l2_cpu2_dext_err_r2; + wire l2_cpu2_dext_err_type_r2; + wire l2_cpu2_disable_clean_evict_opt; + wire l2_cpu2_dlast_r1; + wire l2_cpu2_dsngl_ecc_err_r3; + wire [3:0] l2_cpu2_dsq_clr_id_q; + wire l2_cpu2_dsq_clr_vld_q; + wire [3:0] l2_cpu2_dsq_rd_buf_id; + wire [15:0] l2_cpu2_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu2_dsq_rd_data_q; + wire l2_cpu2_dsq_rd_en; + wire l2_cpu2_dsq_rd_en_x2; + wire l2_cpu2_dt_pmu_evt_en; + wire l2_cpu2_dvalid_r1; + wire l2_cpu2_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; + wire l2_cpu2_flsh_if_rd_l4_dly; + wire l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; + wire l2_cpu2_flsh_ls_rd_l2_dly; + wire l2_cpu2_flsh_ls_rd_l4_dly; + wire l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; + wire l2_cpu2_flsh_ls_wr_l2_dly; + wire l2_cpu2_flsh_ls_wr_l4_dly; + wire l2_cpu2_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu2_ibufid_r1; + wire [15:0] l2_cpu2_ic_addr_arb_set; + wire l2_cpu2_ic_arb_fast; + wire l2_cpu2_ic_barrier_stall_q; + wire [43:18] l2_cpu2_ic_base; + wire [31:0] l2_cpu2_ic_data_arb_set; + wire [2:0] l2_cpu2_ic_elem_size_arb_set; + wire l2_cpu2_ic_excl_arb_set; + wire [2:0] l2_cpu2_ic_id_arb_set; + wire l2_cpu2_ic_ns_arb_set; + wire l2_cpu2_ic_vld_skid; + wire l2_cpu2_ic_write_arb_set; + wire [127:0] l2_cpu2_idata_r2; + wire l2_cpu2_idlb_ecc_err_r3; + wire l2_cpu2_idle_block_reqs_q; + wire l2_cpu2_idle_wakeup_q; + wire l2_cpu2_iext_err_r2; + wire l2_cpu2_iext_err_type_r2; + wire l2_cpu2_if_ccb_clken_c3; + wire l2_cpu2_if_ccb_req_c3; + wire l2_cpu2_if_ccb_resp; + wire [4:0] l2_cpu2_if_ccb_resp_id; + wire l2_cpu2_if_sync_done_q; + wire l2_cpu2_if_sync_req; + wire l2_cpu2_ifq_haz_pending; + wire l2_cpu2_isngl_ecc_err_r3; + wire l2_cpu2_ivalid_r1; + wire [1:0] l2_cpu2_l2_cache_size; + wire [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; + wire l2_cpu2_lrq_haz_pending; + wire l2_cpu2_ls_ccb_clken_c3; + wire l2_cpu2_ls_ccb_data_wr; + wire l2_cpu2_ls_ccb_req_c3; + wire l2_cpu2_ls_ccb_resp; + wire [4:0] l2_cpu2_ls_ccb_resp_id; + wire l2_cpu2_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu2_ls_rd_haz_id_arb_q; + wire l2_cpu2_ls_rd_haz_vld_arb_q; + wire l2_cpu2_ls_sync_req; + wire [4:0] l2_cpu2_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu2_ls_wr_data_w2a; + wire l2_cpu2_ls_wr_dirty_w2a; + wire l2_cpu2_ls_wr_err_w2a; + wire [2:0] l2_cpu2_ls_wr_haz_id_arb_q; + wire l2_cpu2_ls_wr_haz_vld_arb_q; + wire l2_cpu2_ls_wr_last_w2a; + wire l2_cpu2_ls_wr_req_w2a; + wire [2:0] l2_cpu2_ls_wr_type_w2a; + wire [12:0] l2_cpu2_mbist1_addr_b1; + wire l2_cpu2_mbist1_all_b1; + wire [3:0] l2_cpu2_mbist1_array_b1; + wire [7:0] l2_cpu2_mbist1_be_b1; + wire l2_cpu2_mbist1_en_b1; + wire l2_cpu2_mbist1_rd_en_b1; + wire l2_cpu2_mbist1_wr_en_b1; + wire l2_cpu2_no_intctrl; + wire l2_cpu2_pf_rd_vld_skid_popped; + wire l2_cpu2_pf_throttle_q; + wire [33:0] l2_cpu2_pmu_events; + wire [2:0] l2_cpu2_rbufid; + wire l2_cpu2_rd_aarch64_arb_set; + wire [44:0] l2_cpu2_rd_addr_arb_set; + wire l2_cpu2_rd_arb; + wire l2_cpu2_rd_arb_fast; + wire [15:8] l2_cpu2_rd_asid_arb_set; + wire l2_cpu2_rd_bypass_arb_set; + wire [2:0] l2_cpu2_rd_bypass_bufid_e5; + wire [2:0] l2_cpu2_rd_bypass_lrq_id_e5; + wire l2_cpu2_rd_bypass_req_can_e5; + wire l2_cpu2_rd_bypass_way_e5; + wire [2:0] l2_cpu2_rd_cache_attr_arb_set; + wire [2:0] l2_cpu2_rd_elem_size_arb_set; + wire l2_cpu2_rd_excl_arb_set; + wire [4:0] l2_cpu2_rd_id_arb_set; + wire [2:0] l2_cpu2_rd_lrq_id_arb_set; + wire [7:0] l2_cpu2_rd_page_attr_arb_set; + wire l2_cpu2_rd_prfm_arb_set; + wire l2_cpu2_rd_priv_arb_set; + wire l2_cpu2_rd_replayed_arb_set; + wire [1:0] l2_cpu2_rd_shared_arb_set; + wire [6:0] l2_cpu2_rd_type_arb_set; + wire l2_cpu2_rd_va48_arb_set; + wire l2_cpu2_rd_vld_skid; + wire l2_cpu2_rd_way_arb_set; + wire l2_cpu2_rexfail; + wire [1:0] l2_cpu2_rstate; + wire l2_cpu2_rvalid; + wire [2:0] l2_cpu2_spec_bufid; + wire l2_cpu2_spec_valid; + wire [63:0] l2_cpu2_spr_rd_data; + wire l2_cpu2_tbw_dbl_ecc_err; + wire [63:0] l2_cpu2_tbw_desc_data; + wire l2_cpu2_tbw_desc_vld; + wire l2_cpu2_tbw_ext_err; + wire l2_cpu2_tbw_ext_err_type; + wire l2_cpu2_tlb_ccb_clken_c3; + wire l2_cpu2_tlb_ccb_req_c3; + wire l2_cpu2_tlb_sync_complete; + wire l2_cpu2_tlb_sync_done_q; + wire l2_cpu2_tlb_sync_req; + wire l2_cpu2_trq_haz_pending; + wire l2_cpu2_tw_ccb_resp; + wire [4:0] l2_cpu2_tw_ccb_resp_id; + wire l2_cpu2_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu2_wr_addr_arb_set; + wire l2_cpu2_wr_arb; + wire l2_cpu2_wr_arb_fast; + wire [2:0] l2_cpu2_wr_cache_attr_arb_set; + wire [11:0] l2_cpu2_wr_cl_id_arb_set; + wire l2_cpu2_wr_clean_evict_arb_set; + wire [143:0] l2_cpu2_wr_data; + wire l2_cpu2_wr_data_stall; + wire l2_cpu2_wr_data_vld_x1_q; + wire l2_cpu2_wr_dirty_arb_set; + wire [2:0] l2_cpu2_wr_elem_size_arb_set; + wire l2_cpu2_wr_err_arb_set; + wire l2_cpu2_wr_evict_x1_q; + wire l2_cpu2_wr_ex_fail; + wire l2_cpu2_wr_ex_resp; + wire [3:0] l2_cpu2_wr_id_arb_set; + wire l2_cpu2_wr_last_arb_set; + wire [7:0] l2_cpu2_wr_page_attr_arb_set; + wire [3:0] l2_cpu2_wr_partial_dw_arb_set; + wire l2_cpu2_wr_priv_arb_set; + wire [1:0] l2_cpu2_wr_shared_arb_set; + wire [2:0] l2_cpu2_wr_type_arb_set; + wire l2_cpu2_wr_vld_skid; + wire l2_cpu2_wr_way_arb_set; + wire l2_cpu2_wrq_almost_full; + wire [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; + wire l2_cpu2_wrq_haz_pending; + wire l2_cpu3_arb_thrshld_timeout_en; + wire l2_cpu3_barrier_done; + wire l2_cpu3_blk_non_evict_wr; + wire l2_cpu3_ccb_dbg_req_c3; + wire [48:0] l2_cpu3_ccb_req_addr_c3; + wire [4:0] l2_cpu3_ccb_req_id_c3; + wire [23:0] l2_cpu3_ccb_req_info_c3; + wire [8:0] l2_cpu3_ccb_req_type_c3; + wire l2_cpu3_cfg_ecc_en; + wire [2:0] l2_cpu3_dbufid_r1; + wire [129:0] l2_cpu3_ddata_r2; + wire l2_cpu3_ddlb_ecc_err_r3; + wire l2_cpu3_dext_err_r2; + wire l2_cpu3_dext_err_type_r2; + wire l2_cpu3_disable_clean_evict_opt; + wire l2_cpu3_dlast_r1; + wire l2_cpu3_dsngl_ecc_err_r3; + wire [3:0] l2_cpu3_dsq_clr_id_q; + wire l2_cpu3_dsq_clr_vld_q; + wire [3:0] l2_cpu3_dsq_rd_buf_id; + wire [15:0] l2_cpu3_dsq_rd_byte_strb_q; + wire [129:0] l2_cpu3_dsq_rd_data_q; + wire l2_cpu3_dsq_rd_en; + wire l2_cpu3_dsq_rd_en_x2; + wire l2_cpu3_dt_pmu_evt_en; + wire l2_cpu3_dvalid_r1; + wire l2_cpu3_early_rd_reqe4_e5_q; + wire [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; + wire l2_cpu3_flsh_if_rd_l4_dly; + wire l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; + wire [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; + wire [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; + wire l2_cpu3_flsh_ls_rd_l2_dly; + wire l2_cpu3_flsh_ls_rd_l4_dly; + wire l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_flsh_ls_wr_evict_l4_dly; + wire [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; + wire [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; + wire l2_cpu3_flsh_ls_wr_l2_dly; + wire l2_cpu3_flsh_ls_wr_l4_dly; + wire l2_cpu3_flsh_tw_rd_l4_dly; + wire [1:0] l2_cpu3_ibufid_r1; + wire [15:0] l2_cpu3_ic_addr_arb_set; + wire l2_cpu3_ic_arb_fast; + wire l2_cpu3_ic_barrier_stall_q; + wire [43:18] l2_cpu3_ic_base; + wire [31:0] l2_cpu3_ic_data_arb_set; + wire [2:0] l2_cpu3_ic_elem_size_arb_set; + wire l2_cpu3_ic_excl_arb_set; + wire [2:0] l2_cpu3_ic_id_arb_set; + wire l2_cpu3_ic_ns_arb_set; + wire l2_cpu3_ic_vld_skid; + wire l2_cpu3_ic_write_arb_set; + wire [127:0] l2_cpu3_idata_r2; + wire l2_cpu3_idlb_ecc_err_r3; + wire l2_cpu3_idle_block_reqs_q; + wire l2_cpu3_idle_wakeup_q; + wire l2_cpu3_iext_err_r2; + wire l2_cpu3_iext_err_type_r2; + wire l2_cpu3_if_ccb_clken_c3; + wire l2_cpu3_if_ccb_req_c3; + wire l2_cpu3_if_ccb_resp; + wire [4:0] l2_cpu3_if_ccb_resp_id; + wire l2_cpu3_if_sync_done_q; + wire l2_cpu3_if_sync_req; + wire l2_cpu3_ifq_haz_pending; + wire l2_cpu3_isngl_ecc_err_r3; + wire l2_cpu3_ivalid_r1; + wire [1:0] l2_cpu3_l2_cache_size; + wire [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; + wire l2_cpu3_lrq_haz_pending; + wire l2_cpu3_ls_ccb_clken_c3; + wire l2_cpu3_ls_ccb_data_wr; + wire l2_cpu3_ls_ccb_req_c3; + wire l2_cpu3_ls_ccb_resp; + wire [4:0] l2_cpu3_ls_ccb_resp_id; + wire l2_cpu3_ls_peq_coll_l4_dly; + wire [3:0] l2_cpu3_ls_rd_haz_id_arb_q; + wire l2_cpu3_ls_rd_haz_vld_arb_q; + wire l2_cpu3_ls_sync_req; + wire [4:0] l2_cpu3_ls_wr_ccb_id_w2a; + wire [127:0] l2_cpu3_ls_wr_data_w2a; + wire l2_cpu3_ls_wr_dirty_w2a; + wire l2_cpu3_ls_wr_err_w2a; + wire [2:0] l2_cpu3_ls_wr_haz_id_arb_q; + wire l2_cpu3_ls_wr_haz_vld_arb_q; + wire l2_cpu3_ls_wr_last_w2a; + wire l2_cpu3_ls_wr_req_w2a; + wire [2:0] l2_cpu3_ls_wr_type_w2a; + wire [12:0] l2_cpu3_mbist1_addr_b1; + wire l2_cpu3_mbist1_all_b1; + wire [3:0] l2_cpu3_mbist1_array_b1; + wire [7:0] l2_cpu3_mbist1_be_b1; + wire l2_cpu3_mbist1_en_b1; + wire l2_cpu3_mbist1_rd_en_b1; + wire l2_cpu3_mbist1_wr_en_b1; + wire l2_cpu3_no_intctrl; + wire l2_cpu3_pf_rd_vld_skid_popped; + wire l2_cpu3_pf_throttle_q; + wire [33:0] l2_cpu3_pmu_events; + wire [2:0] l2_cpu3_rbufid; + wire l2_cpu3_rd_aarch64_arb_set; + wire [44:0] l2_cpu3_rd_addr_arb_set; + wire l2_cpu3_rd_arb; + wire l2_cpu3_rd_arb_fast; + wire [15:8] l2_cpu3_rd_asid_arb_set; + wire l2_cpu3_rd_bypass_arb_set; + wire [2:0] l2_cpu3_rd_bypass_bufid_e5; + wire [2:0] l2_cpu3_rd_bypass_lrq_id_e5; + wire l2_cpu3_rd_bypass_req_can_e5; + wire l2_cpu3_rd_bypass_way_e5; + wire [2:0] l2_cpu3_rd_cache_attr_arb_set; + wire [2:0] l2_cpu3_rd_elem_size_arb_set; + wire l2_cpu3_rd_excl_arb_set; + wire [4:0] l2_cpu3_rd_id_arb_set; + wire [2:0] l2_cpu3_rd_lrq_id_arb_set; + wire [7:0] l2_cpu3_rd_page_attr_arb_set; + wire l2_cpu3_rd_prfm_arb_set; + wire l2_cpu3_rd_priv_arb_set; + wire l2_cpu3_rd_replayed_arb_set; + wire [1:0] l2_cpu3_rd_shared_arb_set; + wire [6:0] l2_cpu3_rd_type_arb_set; + wire l2_cpu3_rd_va48_arb_set; + wire l2_cpu3_rd_vld_skid; + wire l2_cpu3_rd_way_arb_set; + wire l2_cpu3_rexfail; + wire [1:0] l2_cpu3_rstate; + wire l2_cpu3_rvalid; + wire [2:0] l2_cpu3_spec_bufid; + wire l2_cpu3_spec_valid; + wire [63:0] l2_cpu3_spr_rd_data; + wire l2_cpu3_tbw_dbl_ecc_err; + wire [63:0] l2_cpu3_tbw_desc_data; + wire l2_cpu3_tbw_desc_vld; + wire l2_cpu3_tbw_ext_err; + wire l2_cpu3_tbw_ext_err_type; + wire l2_cpu3_tlb_ccb_clken_c3; + wire l2_cpu3_tlb_ccb_req_c3; + wire l2_cpu3_tlb_sync_complete; + wire l2_cpu3_tlb_sync_done_q; + wire l2_cpu3_tlb_sync_req; + wire l2_cpu3_trq_haz_pending; + wire l2_cpu3_tw_ccb_resp; + wire [4:0] l2_cpu3_tw_ccb_resp_id; + wire l2_cpu3_wr_1st_replayed_arb_set; + wire [44:0] l2_cpu3_wr_addr_arb_set; + wire l2_cpu3_wr_arb; + wire l2_cpu3_wr_arb_fast; + wire [2:0] l2_cpu3_wr_cache_attr_arb_set; + wire [11:0] l2_cpu3_wr_cl_id_arb_set; + wire l2_cpu3_wr_clean_evict_arb_set; + wire [143:0] l2_cpu3_wr_data; + wire l2_cpu3_wr_data_stall; + wire l2_cpu3_wr_data_vld_x1_q; + wire l2_cpu3_wr_dirty_arb_set; + wire [2:0] l2_cpu3_wr_elem_size_arb_set; + wire l2_cpu3_wr_err_arb_set; + wire l2_cpu3_wr_evict_x1_q; + wire l2_cpu3_wr_ex_fail; + wire l2_cpu3_wr_ex_resp; + wire [3:0] l2_cpu3_wr_id_arb_set; + wire l2_cpu3_wr_last_arb_set; + wire [7:0] l2_cpu3_wr_page_attr_arb_set; + wire [3:0] l2_cpu3_wr_partial_dw_arb_set; + wire l2_cpu3_wr_priv_arb_set; + wire [1:0] l2_cpu3_wr_shared_arb_set; + wire [2:0] l2_cpu3_wr_type_arb_set; + wire l2_cpu3_wr_vld_skid; + wire l2_cpu3_wr_way_arb_set; + wire l2_cpu3_wrq_almost_full; + wire [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; + wire l2_cpu3_wrq_haz_pending; + wire [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu0_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu1_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu2_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; + wire l2_tbnk0_cpu3_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu0_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu1_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu2_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; + wire [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; + wire [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; + wire l2_tbnk1_cpu3_trq_clr_l4_dly2_q; + wire [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; + wire ls_cpu0_clrexmon; + wire ls_cpu0_imp_abort_containable; + wire ls_cpu0_imp_abort_dec; + wire ls_cpu0_imp_abort_ecc; + wire ls_cpu0_imp_abort_slv; + wire ls_cpu0_raw_eae_nonsec; + wire ls_cpu0_raw_eae_secure; + wire ls_cpu1_clrexmon; + wire ls_cpu1_imp_abort_containable; + wire ls_cpu1_imp_abort_dec; + wire ls_cpu1_imp_abort_ecc; + wire ls_cpu1_imp_abort_slv; + wire ls_cpu1_raw_eae_nonsec; + wire ls_cpu1_raw_eae_secure; + wire ls_cpu2_clrexmon; + wire ls_cpu2_imp_abort_containable; + wire ls_cpu2_imp_abort_dec; + wire ls_cpu2_imp_abort_ecc; + wire ls_cpu2_imp_abort_slv; + wire ls_cpu2_raw_eae_nonsec; + wire ls_cpu2_raw_eae_secure; + wire ls_cpu3_clrexmon; + wire ls_cpu3_imp_abort_containable; + wire ls_cpu3_imp_abort_dec; + wire ls_cpu3_imp_abort_ecc; + wire ls_cpu3_imp_abort_slv; + wire ls_cpu3_raw_eae_nonsec; + wire ls_cpu3_raw_eae_secure; + wire ncommirq_cpu0_i; + wire ncommirq_cpu1_i; + wire ncommirq_cpu2_i; + wire ncommirq_cpu3_i; + wire ncorereset_cpu0_o; + wire ncorereset_cpu1_o; + wire ncorereset_cpu2_o; + wire ncorereset_cpu3_o; + wire ncpuporeset_cpu0_o; + wire ncpuporeset_cpu1_o; + wire ncpuporeset_cpu2_o; + wire ncpuporeset_cpu3_o; + wire niden_cpu0_o; + wire niden_cpu1_o; + wire niden_cpu2_o; + wire niden_cpu3_o; + wire nmbistreset_cpu0_o; + wire nmbistreset_cpu1_o; + wire nmbistreset_cpu2_o; + wire nmbistreset_cpu3_o; + wire npmuirq_cpu0_i; + wire npmuirq_cpu1_i; + wire npmuirq_cpu2_i; + wire npmuirq_cpu3_i; + wire pm_export_cpu0_i; + wire pm_export_cpu1_i; + wire pm_export_cpu2_i; + wire pm_export_cpu3_i; + wire [24:0] pmuevent_cpu0_i; + wire [24:0] pmuevent_cpu1_i; + wire [24:0] pmuevent_cpu2_i; + wire [24:0] pmuevent_cpu3_i; + wire [43:2] rvbaraddr_cpu0_o; + wire [43:2] rvbaraddr_cpu1_o; + wire [43:2] rvbaraddr_cpu2_o; + wire [43:2] rvbaraddr_cpu3_o; + wire spiden_cpu0_o; + wire spiden_cpu1_o; + wire spiden_cpu2_o; + wire spiden_cpu3_o; + wire spniden_cpu0_o; + wire spniden_cpu1_o; + wire spniden_cpu2_o; + wire spniden_cpu3_o; + wire syncreqm_cpu0_o; + wire syncreqm_cpu1_o; + wire syncreqm_cpu2_o; + wire syncreqm_cpu3_o; + wire [1:0] tm_cpu0_cnthctl_kernel; + wire [3:0] tm_cpu0_cntkctl_usr; + wire [1:0] tm_cpu1_cnthctl_kernel; + wire [3:0] tm_cpu1_cntkctl_usr; + wire [1:0] tm_cpu2_cnthctl_kernel; + wire [3:0] tm_cpu2_cntkctl_usr; + wire [1:0] tm_cpu3_cnthctl_kernel; + wire [3:0] tm_cpu3_cntkctl_usr; + wire [63:0] tsvalueb_cpu0_o; + wire [63:0] tsvalueb_cpu1_o; + wire [63:0] tsvalueb_cpu2_o; + wire [63:0] tsvalueb_cpu3_o; + wire vinithi_cpu0_o; + wire vinithi_cpu1_o; + wire vinithi_cpu2_o; + wire vinithi_cpu3_o; + + maia_cpu ucpu0( // outputs + .afreadym_cpu (afreadym_cpu0_i), + .atbytesm_cpu (atbytesm_cpu0_i[1:0]), + .atdatam_cpu (atdatam_cpu0_i[31:0]), + .atidm_cpu (atidm_cpu0_i[6:0]), + .atvalidm_cpu (atvalidm_cpu0_i), + .commrx_cpu (commrx_cpu0_i), + .commtx_cpu (commtx_cpu0_i), + .dbgack_cpu (dbgack_cpu0_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu0_i), + .dbgrstreq_cpu (dbgrstreq_cpu0_i), + .ds_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_flush (ds_cpu0_flush), + .ds_flush_type (ds_cpu0_flush_type[5:0]), + .ds_hcr_va (ds_cpu0_hcr_va), + .ds_hcr_vf (ds_cpu0_hcr_vf), + .ds_hcr_vi (ds_cpu0_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu0_reset_req), + .ds_sev_req (ds_cpu0_sev_req), + .ds_sevl_req (ds_cpu0_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_wfe_req (ds_cpu0_wfe_req), + .ds_wfi_req (ds_cpu0_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu0_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu0_clrexmon), + .ls_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu0_i), + .npmuirq_cpu (npmuirq_cpu0_i), + .pm_export_cpu (pm_export_cpu0_i), + .pmuevent_cpu (pmuevent_cpu0_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu0_o), + .afvalidm_cpu (afvalidm_cpu0_o), + .atclken_cpu (atclken_cpu0_o), + .atreadym_cpu (atreadym_cpu0_o), + .cfgend_cpu (cfgend_cpu0_o), + .cfgte_cpu (cfgte_cpu0_o), + .ck_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_event_reg (ck_cpu0_event_reg), + .ck_gclkt (ck_gclkt[0]), + .ck_wfe_ack (ck_cpu0_wfe_ack), + .ck_wfi_ack (ck_cpu0_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu0_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu0_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu0_o), + .cpuid (cpuid_cpu0_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu0_o), + .dbgen_cpu (dbgen_cpu0_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu0_o), + .dbgromaddr_cpu (dbgromaddr_cpu0_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu0_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu0_o), + .dftramhold_cpu (dftramhold_cpu0_o), + .dftrstdisable_cpu (dftrstdisable_cpu0_o), + .dftse_cpu (dftse_cpu0_o), + .dt_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu0_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[0]), + .ic_el_change_complete (ic_el_change_complete[0]), + .ic_hcr_change_complete (ic_hcr_change_complete[0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[0]), + .ic_ich_el2_tc (ic_ich_el2_tc[0]), + .ic_nfiq (ic_nfiq[0]), + .ic_nirq (ic_nirq[0]), + .ic_nsei (ic_nsei[0]), + .ic_nvfiq (ic_nvfiq[0]), + .ic_nvirq (ic_nvirq[0]), + .ic_nvsei (ic_nvsei[0]), + .ic_p_valid (ic_p_valid[0]), + .ic_sample_spr (ic_sample_spr[0]), + .ic_scr_change_complete (ic_scr_change_complete[0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[0]), + .ic_sra_el1s_en (ic_sra_el1s_en[0]), + .ic_sra_el2_en (ic_sra_el2_en[0]), + .ic_sra_el3_en (ic_sra_el3_en[0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[0]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu0_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu0_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu0_rexfail), + .l2_cpu_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu0_rvalid), + .l2_cpu_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu0_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu0_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu0_o), + .ncpuporeset_cpu (ncpuporeset_cpu0_o), + .niden_cpu (niden_cpu0_o), + .nmbistreset_cpu (nmbistreset_cpu0_o), + .rvbaraddr_cpu (rvbaraddr_cpu0_o[43:2]), + .spiden_cpu (spiden_cpu0_o), + .spniden_cpu (spniden_cpu0_o), + .syncreqm_cpu (syncreqm_cpu0_o), + .tm_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu0_o[63:0]), + .vinithi_cpu (vinithi_cpu0_o) + ); // ucpu0 + + maia_cpu ucpu1( // outputs + .afreadym_cpu (afreadym_cpu1_i), + .atbytesm_cpu (atbytesm_cpu1_i[1:0]), + .atdatam_cpu (atdatam_cpu1_i[31:0]), + .atidm_cpu (atidm_cpu1_i[6:0]), + .atvalidm_cpu (atvalidm_cpu1_i), + .commrx_cpu (commrx_cpu1_i), + .commtx_cpu (commtx_cpu1_i), + .dbgack_cpu (dbgack_cpu1_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu1_i), + .dbgrstreq_cpu (dbgrstreq_cpu1_i), + .ds_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_flush (ds_cpu1_flush), + .ds_flush_type (ds_cpu1_flush_type[5:0]), + .ds_hcr_va (ds_cpu1_hcr_va), + .ds_hcr_vf (ds_cpu1_hcr_vf), + .ds_hcr_vi (ds_cpu1_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu1_reset_req), + .ds_sev_req (ds_cpu1_sev_req), + .ds_sevl_req (ds_cpu1_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_wfe_req (ds_cpu1_wfe_req), + .ds_wfi_req (ds_cpu1_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu1_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu1_clrexmon), + .ls_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu1_i), + .npmuirq_cpu (npmuirq_cpu1_i), + .pm_export_cpu (pm_export_cpu1_i), + .pmuevent_cpu (pmuevent_cpu1_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu1_o), + .afvalidm_cpu (afvalidm_cpu1_o), + .atclken_cpu (atclken_cpu1_o), + .atreadym_cpu (atreadym_cpu1_o), + .cfgend_cpu (cfgend_cpu1_o), + .cfgte_cpu (cfgte_cpu1_o), + .ck_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_event_reg (ck_cpu1_event_reg), + .ck_gclkt (ck_gclkt[1]), + .ck_wfe_ack (ck_cpu1_wfe_ack), + .ck_wfi_ack (ck_cpu1_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu1_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu1_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu1_o), + .cpuid (cpuid_cpu1_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu1_o), + .dbgen_cpu (dbgen_cpu1_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu1_o), + .dbgromaddr_cpu (dbgromaddr_cpu1_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu1_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu1_o), + .dftramhold_cpu (dftramhold_cpu1_o), + .dftrstdisable_cpu (dftrstdisable_cpu1_o), + .dftse_cpu (dftse_cpu1_o), + .dt_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu1_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[1]), + .ic_el_change_complete (ic_el_change_complete[1]), + .ic_hcr_change_complete (ic_hcr_change_complete[1]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[1]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[1]), + .ic_ich_el2_tc (ic_ich_el2_tc[1]), + .ic_nfiq (ic_nfiq[1]), + .ic_nirq (ic_nirq[1]), + .ic_nsei (ic_nsei[1]), + .ic_nvfiq (ic_nvfiq[1]), + .ic_nvirq (ic_nvirq[1]), + .ic_nvsei (ic_nvsei[1]), + .ic_p_valid (ic_p_valid[1]), + .ic_sample_spr (ic_sample_spr[1]), + .ic_scr_change_complete (ic_scr_change_complete[1]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[1]), + .ic_sra_el1s_en (ic_sra_el1s_en[1]), + .ic_sra_el2_en (ic_sra_el2_en[1]), + .ic_sra_el3_en (ic_sra_el3_en[1]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[1]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[1]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[1]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[1]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu1_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu1_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu1_rexfail), + .l2_cpu_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu1_rvalid), + .l2_cpu_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu1_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu1_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu1_o), + .ncpuporeset_cpu (ncpuporeset_cpu1_o), + .niden_cpu (niden_cpu1_o), + .nmbistreset_cpu (nmbistreset_cpu1_o), + .rvbaraddr_cpu (rvbaraddr_cpu1_o[43:2]), + .spiden_cpu (spiden_cpu1_o), + .spniden_cpu (spniden_cpu1_o), + .syncreqm_cpu (syncreqm_cpu1_o), + .tm_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu1_o[63:0]), + .vinithi_cpu (vinithi_cpu1_o) + ); // ucpu1 + + maia_cpu ucpu2( // outputs + .afreadym_cpu (afreadym_cpu2_i), + .atbytesm_cpu (atbytesm_cpu2_i[1:0]), + .atdatam_cpu (atdatam_cpu2_i[31:0]), + .atidm_cpu (atidm_cpu2_i[6:0]), + .atvalidm_cpu (atvalidm_cpu2_i), + .commrx_cpu (commrx_cpu2_i), + .commtx_cpu (commtx_cpu2_i), + .dbgack_cpu (dbgack_cpu2_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu2_i), + .dbgrstreq_cpu (dbgrstreq_cpu2_i), + .ds_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_flush (ds_cpu2_flush), + .ds_flush_type (ds_cpu2_flush_type[5:0]), + .ds_hcr_va (ds_cpu2_hcr_va), + .ds_hcr_vf (ds_cpu2_hcr_vf), + .ds_hcr_vi (ds_cpu2_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu2_reset_req), + .ds_sev_req (ds_cpu2_sev_req), + .ds_sevl_req (ds_cpu2_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_wfe_req (ds_cpu2_wfe_req), + .ds_wfi_req (ds_cpu2_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu2_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu2_clrexmon), + .ls_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu2_i), + .npmuirq_cpu (npmuirq_cpu2_i), + .pm_export_cpu (pm_export_cpu2_i), + .pmuevent_cpu (pmuevent_cpu2_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu2_o), + .afvalidm_cpu (afvalidm_cpu2_o), + .atclken_cpu (atclken_cpu2_o), + .atreadym_cpu (atreadym_cpu2_o), + .cfgend_cpu (cfgend_cpu2_o), + .cfgte_cpu (cfgte_cpu2_o), + .ck_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_event_reg (ck_cpu2_event_reg), + .ck_gclkt (ck_gclkt[2]), + .ck_wfe_ack (ck_cpu2_wfe_ack), + .ck_wfi_ack (ck_cpu2_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu2_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu2_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu2_o), + .cpuid (cpuid_cpu2_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu2_o), + .dbgen_cpu (dbgen_cpu2_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu2_o), + .dbgromaddr_cpu (dbgromaddr_cpu2_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu2_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu2_o), + .dftramhold_cpu (dftramhold_cpu2_o), + .dftrstdisable_cpu (dftrstdisable_cpu2_o), + .dftse_cpu (dftse_cpu2_o), + .dt_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu2_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[2]), + .ic_el_change_complete (ic_el_change_complete[2]), + .ic_hcr_change_complete (ic_hcr_change_complete[2]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[2]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[2]), + .ic_ich_el2_tc (ic_ich_el2_tc[2]), + .ic_nfiq (ic_nfiq[2]), + .ic_nirq (ic_nirq[2]), + .ic_nsei (ic_nsei[2]), + .ic_nvfiq (ic_nvfiq[2]), + .ic_nvirq (ic_nvirq[2]), + .ic_nvsei (ic_nvsei[2]), + .ic_p_valid (ic_p_valid[2]), + .ic_sample_spr (ic_sample_spr[2]), + .ic_scr_change_complete (ic_scr_change_complete[2]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[2]), + .ic_sra_el1s_en (ic_sra_el1s_en[2]), + .ic_sra_el2_en (ic_sra_el2_en[2]), + .ic_sra_el3_en (ic_sra_el3_en[2]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[2]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[2]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[2]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[2]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu2_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu2_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu2_rexfail), + .l2_cpu_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu2_rvalid), + .l2_cpu_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu2_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu2_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu2_o), + .ncpuporeset_cpu (ncpuporeset_cpu2_o), + .niden_cpu (niden_cpu2_o), + .nmbistreset_cpu (nmbistreset_cpu2_o), + .rvbaraddr_cpu (rvbaraddr_cpu2_o[43:2]), + .spiden_cpu (spiden_cpu2_o), + .spniden_cpu (spniden_cpu2_o), + .syncreqm_cpu (syncreqm_cpu2_o), + .tm_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu2_o[63:0]), + .vinithi_cpu (vinithi_cpu2_o) + ); // ucpu2 + + maia_cpu ucpu3( // outputs + .afreadym_cpu (afreadym_cpu3_i), + .atbytesm_cpu (atbytesm_cpu3_i[1:0]), + .atdatam_cpu (atdatam_cpu3_i[31:0]), + .atidm_cpu (atidm_cpu3_i[6:0]), + .atvalidm_cpu (atvalidm_cpu3_i), + .commrx_cpu (commrx_cpu3_i), + .commtx_cpu (commtx_cpu3_i), + .dbgack_cpu (dbgack_cpu3_i), + .dbgnopwrdwn_cpu (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu (dbgrstreq_cpu3_i), + .ds_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_flush (ds_cpu3_flush), + .ds_flush_type (ds_cpu3_flush_type[5:0]), + .ds_hcr_va (ds_cpu3_hcr_va), + .ds_hcr_vf (ds_cpu3_hcr_vf), + .ds_hcr_vi (ds_cpu3_hcr_vi), + .ds_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_ic_scr_change (ds_cpu3_ic_scr_change), + .ds_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_reset_req (ds_cpu3_reset_req), + .ds_sev_req (ds_cpu3_sev_req), + .ds_sevl_req (ds_cpu3_sevl_req), + .ds_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_wfe_req (ds_cpu3_wfe_req), + .ds_wfi_req (ds_cpu3_wfi_req), + .dt_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .dt_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .etclken_cpu (etclken_cpu3_i), + .l2_cpu_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .ls_clrexmon (ls_cpu3_clrexmon), + .ls_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_raw_eae_secure (ls_cpu3_raw_eae_secure), + .ncommirq_cpu (ncommirq_cpu3_i), + .npmuirq_cpu (npmuirq_cpu3_i), + .pm_export_cpu (pm_export_cpu3_i), + .pmuevent_cpu (pmuevent_cpu3_i[24:0]), + + // inputs + .aa64naa32_cpu (aa64naa32_cpu3_o), + .afvalidm_cpu (afvalidm_cpu3_o), + .atclken_cpu (atclken_cpu3_o), + .atreadym_cpu (atreadym_cpu3_o), + .cfgend_cpu (cfgend_cpu3_o), + .cfgte_cpu (cfgte_cpu3_o), + .ck_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_event_reg (ck_cpu3_event_reg), + .ck_gclkt (ck_gclkt[3]), + .ck_wfe_ack (ck_cpu3_wfe_ack), + .ck_wfi_ack (ck_cpu3_wfi_ack), + .clusteridaff1_cpu (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu (clusteridaff2_cpu3_o[7:0]), + .cp15sdisable_cpu (cp15sdisable_cpu3_o), + .cpuid (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu (cryptodisable_cpu3_o), + .dbgen_cpu (dbgen_cpu3_o), + .dbgl1rstdisable_cpu (dbgl1rstdisable_cpu3_o), + .dbgromaddr_cpu (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu (dbgromaddrv_cpu3_o), + .dftcrclkdisable_cpu (dftcrclkdisable_cpu3_o), + .dftramhold_cpu (dftramhold_cpu3_o), + .dftrstdisable_cpu (dftrstdisable_cpu3_o), + .dftse_cpu (dftse_cpu3_o), + .dt_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .giccdisable_cpu (giccdisable_cpu3_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[3]), + .ic_el_change_complete (ic_el_change_complete[3]), + .ic_hcr_change_complete (ic_hcr_change_complete[3]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[3]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[3]), + .ic_ich_el2_tc (ic_ich_el2_tc[3]), + .ic_nfiq (ic_nfiq[3]), + .ic_nirq (ic_nirq[3]), + .ic_nsei (ic_nsei[3]), + .ic_nvfiq (ic_nvfiq[3]), + .ic_nvirq (ic_nvirq[3]), + .ic_nvsei (ic_nvsei[3]), + .ic_p_valid (ic_p_valid[3]), + .ic_sample_spr (ic_sample_spr[3]), + .ic_scr_change_complete (ic_scr_change_complete[3]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[3]), + .ic_sra_el1s_en (ic_sra_el1s_en[3]), + .ic_sra_el2_en (ic_sra_el2_en[3]), + .ic_sra_el3_en (ic_sra_el3_en[3]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[3]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[3]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[3]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[3]), + .l2_cpu_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu_barrier_done (l2_cpu3_barrier_done), + .l2_cpu_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), + .l2_cpu_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), + .l2_cpu_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu_rd_arb (l2_cpu3_rd_arb), + .l2_cpu_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu_rexfail (l2_cpu3_rexfail), + .l2_cpu_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu_rvalid (l2_cpu3_rvalid), + .l2_cpu_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu_spec_valid (l2_cpu3_spec_valid), + .l2_cpu_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu_wr_arb (l2_cpu3_wr_arb), + .l2_cpu_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_tbnk0_cpu_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .ncorereset_cpu (ncorereset_cpu3_o), + .ncpuporeset_cpu (ncpuporeset_cpu3_o), + .niden_cpu (niden_cpu3_o), + .nmbistreset_cpu (nmbistreset_cpu3_o), + .rvbaraddr_cpu (rvbaraddr_cpu3_o[43:2]), + .spiden_cpu (spiden_cpu3_o), + .spniden_cpu (spniden_cpu3_o), + .syncreqm_cpu (syncreqm_cpu3_o), + .tm_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tsvalueb_cpu (tsvalueb_cpu3_o[63:0]), + .vinithi_cpu (vinithi_cpu3_o) + ); // ucpu3 + + maia_noncpu_s unoncpu( // outputs + .AFREADYM0 (AFREADYM0), + .AFREADYM1 (AFREADYM1), + .AFREADYM2 (AFREADYM2), + .AFREADYM3 (AFREADYM3), + .ARREADYS (ARREADYS), + .ATBYTESM0 (ATBYTESM0[1:0]), + .ATBYTESM1 (ATBYTESM1[1:0]), + .ATBYTESM2 (ATBYTESM2[1:0]), + .ATBYTESM3 (ATBYTESM3[1:0]), + .ATDATAM0 (ATDATAM0[31:0]), + .ATDATAM1 (ATDATAM1[31:0]), + .ATDATAM2 (ATDATAM2[31:0]), + .ATDATAM3 (ATDATAM3[31:0]), + .ATIDM0 (ATIDM0[6:0]), + .ATIDM1 (ATIDM1[6:0]), + .ATIDM2 (ATIDM2[6:0]), + .ATIDM3 (ATIDM3[6:0]), + .ATVALIDM0 (ATVALIDM0), + .ATVALIDM1 (ATVALIDM1), + .ATVALIDM2 (ATVALIDM2), + .ATVALIDM3 (ATVALIDM3), + .AWREADYS (AWREADYS), + .BIDS (BIDS[4:0]), + .BRESPS (BRESPS[1:0]), + .BVALIDS (BVALIDS), + .CLREXMONACK (CLREXMONACK), + .COMMRX (COMMRX[`MAIA_CN:0]), + .COMMTX (COMMTX[`MAIA_CN:0]), + .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), + .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), + .CPUQDENY (CPUQDENY[`MAIA_CN:0]), + .CTICHINACK (CTICHINACK[3:0]), + .CTICHOUT (CTICHOUT[3:0]), + .CTIIRQ (CTIIRQ[`MAIA_CN:0]), + .DBGACK (DBGACK[`MAIA_CN:0]), + .DBGNOPWRDWN (DBGNOPWRDWN[`MAIA_CN:0]), + .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), + .DBGRSTREQ (DBGRSTREQ[`MAIA_CN:0]), + .EVENTO (EVENTO), + .ICCTDATA (ICCTDATA[15:0]), + .ICCTID (ICCTID[1:0]), + .ICCTLAST (ICCTLAST), + .ICCTVALID (ICCTVALID), + .ICDTREADY (ICDTREADY), + .L2FLUSHDONE (L2FLUSHDONE), + .L2QACCEPTn (L2QACCEPTn), + .L2QACTIVE (L2QACTIVE), + .L2QDENY (L2QDENY), + .PMUEVENT0 (PMUEVENT0[24:0]), + .PMUEVENT1 (PMUEVENT1[24:0]), + .PMUEVENT2 (PMUEVENT2[24:0]), + .PMUEVENT3 (PMUEVENT3[24:0]), + .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), + .PRDATADBG (PRDATADBG[31:0]), + .PREADYDBG (PREADYDBG), + .PSLVERRDBG (PSLVERRDBG), + .RDATAS (RDATAS[127:0]), + .REQMEMATTR (REQMEMATTR[7:0]), + .RIDS (RIDS[4:0]), + .RLASTS (RLASTS), + .RRESPS (RRESPS[1:0]), + .RVALIDS (RVALIDS), + .RXDATLCRDV (RXDATLCRDV), + .RXLINKACTIVEACK (RXLINKACTIVEACK), + .RXRSPLCRDV (RXRSPLCRDV), + .RXSNPLCRDV (RXSNPLCRDV), + .SMPEN (SMPEN[`MAIA_CN:0]), + .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), + .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), + .STANDBYWFIL2 (STANDBYWFIL2), + .TXDATFLIT (TXDATFLIT[193:0]), + .TXDATFLITPEND (TXDATFLITPEND), + .TXDATFLITV (TXDATFLITV), + .TXLINKACTIVEREQ (TXLINKACTIVEREQ), + .TXREQFLIT (TXREQFLIT[99:0]), + .TXREQFLITPEND (TXREQFLITPEND), + .TXREQFLITV (TXREQFLITV), + .TXRSPFLIT (TXRSPFLIT[44:0]), + .TXRSPFLITPEND (TXRSPFLITPEND), + .TXRSPFLITV (TXRSPFLITV), + .TXSACTIVE (TXSACTIVE), + .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), + .WREADYS (WREADYS), + .aa64naa32_cpu0_o (aa64naa32_cpu0_o), + .aa64naa32_cpu1_o (aa64naa32_cpu1_o), + .aa64naa32_cpu2_o (aa64naa32_cpu2_o), + .aa64naa32_cpu3_o (aa64naa32_cpu3_o), + .afvalidm_cpu0_o (afvalidm_cpu0_o), + .afvalidm_cpu1_o (afvalidm_cpu1_o), + .afvalidm_cpu2_o (afvalidm_cpu2_o), + .afvalidm_cpu3_o (afvalidm_cpu3_o), + .atclken_cpu0_o (atclken_cpu0_o), + .atclken_cpu1_o (atclken_cpu1_o), + .atclken_cpu2_o (atclken_cpu2_o), + .atclken_cpu3_o (atclken_cpu3_o), + .atreadym_cpu0_o (atreadym_cpu0_o), + .atreadym_cpu1_o (atreadym_cpu1_o), + .atreadym_cpu2_o (atreadym_cpu2_o), + .atreadym_cpu3_o (atreadym_cpu3_o), + .cfgend_cpu0_o (cfgend_cpu0_o), + .cfgend_cpu1_o (cfgend_cpu1_o), + .cfgend_cpu2_o (cfgend_cpu2_o), + .cfgend_cpu3_o (cfgend_cpu3_o), + .cfgte_cpu0_o (cfgte_cpu0_o), + .cfgte_cpu1_o (cfgte_cpu1_o), + .cfgte_cpu2_o (cfgte_cpu2_o), + .cfgte_cpu3_o (cfgte_cpu3_o), + .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_cpu0_event_reg (ck_cpu0_event_reg), + .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), + .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), + .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_cpu1_event_reg (ck_cpu1_event_reg), + .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), + .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), + .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_cpu2_event_reg (ck_cpu2_event_reg), + .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), + .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), + .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_cpu3_event_reg (ck_cpu3_event_reg), + .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), + .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), + .ck_gclkt (ck_gclkt[`MAIA_CN:0]), + .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), + .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), + .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), + .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), + .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), + .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), + .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), + .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), + .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), + .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), + .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), + .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), + .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), + .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), + .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu0_o (cryptodisable_cpu0_o), + .cryptodisable_cpu1_o (cryptodisable_cpu1_o), + .cryptodisable_cpu2_o (cryptodisable_cpu2_o), + .cryptodisable_cpu3_o (cryptodisable_cpu3_o), + .dbgen_cpu0_o (dbgen_cpu0_o), + .dbgen_cpu1_o (dbgen_cpu1_o), + .dbgen_cpu2_o (dbgen_cpu2_o), + .dbgen_cpu3_o (dbgen_cpu3_o), + .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), + .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), + .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), + .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), + .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), + .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), + .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), + .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), + .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), + .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), + .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), + .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), + .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), + .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), + .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), + .dftramhold_cpu0_o (dftramhold_cpu0_o), + .dftramhold_cpu1_o (dftramhold_cpu1_o), + .dftramhold_cpu2_o (dftramhold_cpu2_o), + .dftramhold_cpu3_o (dftramhold_cpu3_o), + .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), + .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), + .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), + .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), + .dftse_cpu0_o (dftse_cpu0_o), + .dftse_cpu1_o (dftse_cpu1_o), + .dftse_cpu2_o (dftse_cpu2_o), + .dftse_cpu3_o (dftse_cpu3_o), + .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .giccdisable_cpu0_o (giccdisable_cpu0_o), + .giccdisable_cpu1_o (giccdisable_cpu1_o), + .giccdisable_cpu2_o (giccdisable_cpu2_o), + .giccdisable_cpu3_o (giccdisable_cpu3_o), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr[`MAIA_CN:0]), + .ic_el_change_complete (ic_el_change_complete[`MAIA_CN:0]), + .ic_hcr_change_complete (ic_hcr_change_complete[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq[`MAIA_CN:0]), + .ic_nirq (ic_nirq[`MAIA_CN:0]), + .ic_nsei (ic_nsei[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei[`MAIA_CN:0]), + .ic_p_valid (ic_p_valid[`MAIA_CN:0]), + .ic_sample_spr (ic_sample_spr[`MAIA_CN:0]), + .ic_scr_change_complete (ic_scr_change_complete[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap[`MAIA_CN:0]), + .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu0_barrier_done (l2_cpu0_barrier_done), + .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddlb_ecc_err_r3), + .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idlb_ecc_err_r3), + .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu0_rd_arb (l2_cpu0_rd_arb), + .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu0_rexfail (l2_cpu0_rexfail), + .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu0_rvalid (l2_cpu0_rvalid), + .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu0_spec_valid (l2_cpu0_spec_valid), + .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu0_wr_arb (l2_cpu0_wr_arb), + .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu1_barrier_done (l2_cpu1_barrier_done), + .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddlb_ecc_err_r3), + .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idlb_ecc_err_r3), + .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu1_rd_arb (l2_cpu1_rd_arb), + .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu1_rexfail (l2_cpu1_rexfail), + .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu1_rvalid (l2_cpu1_rvalid), + .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu1_spec_valid (l2_cpu1_spec_valid), + .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu1_wr_arb (l2_cpu1_wr_arb), + .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu2_barrier_done (l2_cpu2_barrier_done), + .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddlb_ecc_err_r3), + .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idlb_ecc_err_r3), + .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu2_rd_arb (l2_cpu2_rd_arb), + .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu2_rexfail (l2_cpu2_rexfail), + .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu2_rvalid (l2_cpu2_rvalid), + .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu2_spec_valid (l2_cpu2_spec_valid), + .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu2_wr_arb (l2_cpu2_wr_arb), + .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu3_barrier_done (l2_cpu3_barrier_done), + .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddlb_ecc_err_r3), + .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idlb_ecc_err_r3), + .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu3_rd_arb (l2_cpu3_rd_arb), + .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu3_rexfail (l2_cpu3_rexfail), + .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu3_rvalid (l2_cpu3_rvalid), + .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu3_spec_valid (l2_cpu3_spec_valid), + .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu3_wr_arb (l2_cpu3_wr_arb), + .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), + .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), + .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), + .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), + .nCOMMIRQ (nCOMMIRQ[`MAIA_CN:0]), + .nEXTERRIRQ (nEXTERRIRQ), + .nINTERRIRQ (nINTERRIRQ), + .nPMUIRQ (nPMUIRQ[`MAIA_CN:0]), + .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), + .ncorereset_cpu0_o (ncorereset_cpu0_o), + .ncorereset_cpu1_o (ncorereset_cpu1_o), + .ncorereset_cpu2_o (ncorereset_cpu2_o), + .ncorereset_cpu3_o (ncorereset_cpu3_o), + .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), + .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), + .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), + .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), + .niden_cpu0_o (niden_cpu0_o), + .niden_cpu1_o (niden_cpu1_o), + .niden_cpu2_o (niden_cpu2_o), + .niden_cpu3_o (niden_cpu3_o), + .nmbistreset_cpu0_o (nmbistreset_cpu0_o), + .nmbistreset_cpu1_o (nmbistreset_cpu1_o), + .nmbistreset_cpu2_o (nmbistreset_cpu2_o), + .nmbistreset_cpu3_o (nmbistreset_cpu3_o), + .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), + .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), + .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), + .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), + .spiden_cpu0_o (spiden_cpu0_o), + .spiden_cpu1_o (spiden_cpu1_o), + .spiden_cpu2_o (spiden_cpu2_o), + .spiden_cpu3_o (spiden_cpu3_o), + .spniden_cpu0_o (spniden_cpu0_o), + .spniden_cpu1_o (spniden_cpu1_o), + .spniden_cpu2_o (spniden_cpu2_o), + .spniden_cpu3_o (spniden_cpu3_o), + .syncreqm_cpu0_o (syncreqm_cpu0_o), + .syncreqm_cpu1_o (syncreqm_cpu1_o), + .syncreqm_cpu2_o (syncreqm_cpu2_o), + .syncreqm_cpu3_o (syncreqm_cpu3_o), + .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), + .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), + .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), + .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), + .vinithi_cpu0_o (vinithi_cpu0_o), + .vinithi_cpu1_o (vinithi_cpu1_o), + .vinithi_cpu2_o (vinithi_cpu2_o), + .vinithi_cpu3_o (vinithi_cpu3_o), + + // inputs + .AA64nAA32 (AA64nAA32[`MAIA_CN:0]), + .ACLKENS (ACLKENS), + .AFVALIDM0 (AFVALIDM0), + .AFVALIDM1 (AFVALIDM1), + .AFVALIDM2 (AFVALIDM2), + .AFVALIDM3 (AFVALIDM3), + .AINACTS (AINACTS), + .ARADDRS (ARADDRS[43:0]), + .ARCACHES (ARCACHES[3:0]), + .ARIDS (ARIDS[4:0]), + .ARLENS (ARLENS[7:0]), + .ARPROTS (ARPROTS[2:0]), + .ARUSERS (ARUSERS[1:0]), + .ARVALIDS (ARVALIDS), + .ATCLKEN (ATCLKEN), + .ATREADYM0 (ATREADYM0), + .ATREADYM1 (ATREADYM1), + .ATREADYM2 (ATREADYM2), + .ATREADYM3 (ATREADYM3), + .AWADDRS (AWADDRS[43:0]), + .AWCACHES (AWCACHES[3:0]), + .AWIDS (AWIDS[4:0]), + .AWLENS (AWLENS[7:0]), + .AWPROTS (AWPROTS[2:0]), + .AWUSERS (AWUSERS[1:0]), + .AWVALIDS (AWVALIDS), + .BREADYS (BREADYS), + .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), + .BROADCASTINNER (BROADCASTINNER), + .BROADCASTOUTER (BROADCASTOUTER), + .CFGEND (CFGEND[`MAIA_CN:0]), + .CFGTE (CFGTE[`MAIA_CN:0]), + .CIHSBYPASS (CIHSBYPASS[3:0]), + .CISBYPASS (CISBYPASS), + .CLK (CLK), + .CLKEN (CLKEN), + .CLREXMONREQ (CLREXMONREQ), + .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), + .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), + .CNTCLKEN (CNTCLKEN), + .CNTVALUEB (CNTVALUEB[63:0]), + .CP15SDISABLE (CP15SDISABLE[`MAIA_CN:0]), + .CPUQREQn (CPUQREQn[`MAIA_CN:0]), + .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), + .CTICHIN (CTICHIN[3:0]), + .CTICHOUTACK (CTICHOUTACK[3:0]), + .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), + .DBGEN (DBGEN[`MAIA_CN:0]), + .DBGL1RSTDISABLE (DBGL1RSTDISABLE), + .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), + .DBGROMADDR (DBGROMADDR[43:12]), + .DBGROMADDRV (DBGROMADDRV), + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTCRCLKDISABLE (DFTCRCLKDISABLE[`MAIA_CN:0]), + .DFTL2CLKDISABLE (DFTL2CLKDISABLE), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .EDBGRQ (EDBGRQ[`MAIA_CN:0]), + .EVENTI (EVENTI), + .GICCDISABLE (GICCDISABLE), + .ICCTREADY (ICCTREADY), + .ICDTDATA (ICDTDATA[15:0]), + .ICDTDEST (ICDTDEST[1:0]), + .ICDTLAST (ICDTLAST), + .ICDTVALID (ICDTVALID), + .L2FLUSHREQ (L2FLUSHREQ), + .L2QREQn (L2QREQn), + .L2RSTDISABLE (L2RSTDISABLE), + .MBISTREQ (MBISTREQ), + .NIDEN (NIDEN[`MAIA_CN:0]), + .NODEID (NODEID[6:0]), + .PADDRDBG (PADDRDBG[21:2]), + .PADDRDBG31 (PADDRDBG31), + .PCLKDBG (PCLKDBG), + .PCLKENDBG (PCLKENDBG), + .PENABLEDBG (PENABLEDBG), + .PERIPHBASE (PERIPHBASE[43:18]), + .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), + .PSELDBG (PSELDBG), + .PWDATADBG (PWDATADBG[31:0]), + .PWRITEDBG (PWRITEDBG), + .RREADYS (RREADYS), + .RVBARADDR0 (RVBARADDR0[43:2]), + .RVBARADDR1 (RVBARADDR1[43:2]), + .RVBARADDR2 (RVBARADDR2[43:2]), + .RVBARADDR3 (RVBARADDR3[43:2]), + .RXDATFLIT (RXDATFLIT[193:0]), + .RXDATFLITPEND (RXDATFLITPEND), + .RXDATFLITV (RXDATFLITV), + .RXLINKACTIVEREQ (RXLINKACTIVEREQ), + .RXRSPFLIT (RXRSPFLIT[44:0]), + .RXRSPFLITPEND (RXRSPFLITPEND), + .RXRSPFLITV (RXRSPFLITV), + .RXSACTIVE (RXSACTIVE), + .RXSNPFLIT (RXSNPFLIT[64:0]), + .RXSNPFLITPEND (RXSNPFLITPEND), + .RXSNPFLITV (RXSNPFLITV), + .SAMADDRMAP0 (SAMADDRMAP0[1:0]), + .SAMADDRMAP1 (SAMADDRMAP1[1:0]), + .SAMADDRMAP10 (SAMADDRMAP10[1:0]), + .SAMADDRMAP11 (SAMADDRMAP11[1:0]), + .SAMADDRMAP12 (SAMADDRMAP12[1:0]), + .SAMADDRMAP13 (SAMADDRMAP13[1:0]), + .SAMADDRMAP14 (SAMADDRMAP14[1:0]), + .SAMADDRMAP15 (SAMADDRMAP15[1:0]), + .SAMADDRMAP16 (SAMADDRMAP16[1:0]), + .SAMADDRMAP17 (SAMADDRMAP17[1:0]), + .SAMADDRMAP18 (SAMADDRMAP18[1:0]), + .SAMADDRMAP19 (SAMADDRMAP19[1:0]), + .SAMADDRMAP2 (SAMADDRMAP2[1:0]), + .SAMADDRMAP3 (SAMADDRMAP3[1:0]), + .SAMADDRMAP4 (SAMADDRMAP4[1:0]), + .SAMADDRMAP5 (SAMADDRMAP5[1:0]), + .SAMADDRMAP6 (SAMADDRMAP6[1:0]), + .SAMADDRMAP7 (SAMADDRMAP7[1:0]), + .SAMADDRMAP8 (SAMADDRMAP8[1:0]), + .SAMADDRMAP9 (SAMADDRMAP9[1:0]), + .SAMHNF0NODEID (SAMHNF0NODEID[6:0]), + .SAMHNF1NODEID (SAMHNF1NODEID[6:0]), + .SAMHNF2NODEID (SAMHNF2NODEID[6:0]), + .SAMHNF3NODEID (SAMHNF3NODEID[6:0]), + .SAMHNF4NODEID (SAMHNF4NODEID[6:0]), + .SAMHNF5NODEID (SAMHNF5NODEID[6:0]), + .SAMHNF6NODEID (SAMHNF6NODEID[6:0]), + .SAMHNF7NODEID (SAMHNF7NODEID[6:0]), + .SAMHNFMODE (SAMHNFMODE[2:0]), + .SAMHNI0NODEID (SAMHNI0NODEID[6:0]), + .SAMHNI1NODEID (SAMHNI1NODEID[6:0]), + .SAMMNBASE (SAMMNBASE[43:24]), + .SAMMNNODEID (SAMMNNODEID[6:0]), + .SCLKEN (SCLKEN), + .SINACT (SINACT), + .SPIDEN (SPIDEN[`MAIA_CN:0]), + .SPNIDEN (SPNIDEN[`MAIA_CN:0]), + .SYNCREQM0 (SYNCREQM0), + .SYNCREQM1 (SYNCREQM1), + .SYNCREQM2 (SYNCREQM2), + .SYNCREQM3 (SYNCREQM3), + .SYSBARDISABLE (SYSBARDISABLE), + .TSVALUEB (TSVALUEB[63:0]), + .TXDATLCRDV (TXDATLCRDV), + .TXLINKACTIVEACK (TXLINKACTIVEACK), + .TXREQLCRDV (TXREQLCRDV), + .TXRSPLCRDV (TXRSPLCRDV), + .VINITHI (VINITHI[`MAIA_CN:0]), + .WDATAS (WDATAS[127:0]), + .WLASTS (WLASTS), + .WSTRBS (WSTRBS[15:0]), + .WVALIDS (WVALIDS), + .afreadym_cpu0_i (afreadym_cpu0_i), + .afreadym_cpu1_i (afreadym_cpu1_i), + .afreadym_cpu2_i (afreadym_cpu2_i), + .afreadym_cpu3_i (afreadym_cpu3_i), + .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), + .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), + .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), + .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), + .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), + .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), + .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), + .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), + .atidm_cpu0_i (atidm_cpu0_i[6:0]), + .atidm_cpu1_i (atidm_cpu1_i[6:0]), + .atidm_cpu2_i (atidm_cpu2_i[6:0]), + .atidm_cpu3_i (atidm_cpu3_i[6:0]), + .atvalidm_cpu0_i (atvalidm_cpu0_i), + .atvalidm_cpu1_i (atvalidm_cpu1_i), + .atvalidm_cpu2_i (atvalidm_cpu2_i), + .atvalidm_cpu3_i (atvalidm_cpu3_i), + .commrx_cpu0_i (commrx_cpu0_i), + .commrx_cpu1_i (commrx_cpu1_i), + .commrx_cpu2_i (commrx_cpu2_i), + .commrx_cpu3_i (commrx_cpu3_i), + .commtx_cpu0_i (commtx_cpu0_i), + .commtx_cpu1_i (commtx_cpu1_i), + .commtx_cpu2_i (commtx_cpu2_i), + .commtx_cpu3_i (commtx_cpu3_i), + .dbgack_cpu0_i (dbgack_cpu0_i), + .dbgack_cpu1_i (dbgack_cpu1_i), + .dbgack_cpu2_i (dbgack_cpu2_i), + .dbgack_cpu3_i (dbgack_cpu3_i), + .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), + .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), + .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), + .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), + .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), + .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), + .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), + .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_cpu0_flush (ds_cpu0_flush), + .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), + .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), + .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu0_reset_req (ds_cpu0_reset_req), + .ds_cpu0_sev_req (ds_cpu0_sev_req), + .ds_cpu0_sevl_req (ds_cpu0_sevl_req), + .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_cpu0_wfe_req (ds_cpu0_wfe_req), + .ds_cpu0_wfi_req (ds_cpu0_wfi_req), + .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_cpu1_flush (ds_cpu1_flush), + .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), + .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), + .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu1_reset_req (ds_cpu1_reset_req), + .ds_cpu1_sev_req (ds_cpu1_sev_req), + .ds_cpu1_sevl_req (ds_cpu1_sevl_req), + .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_cpu1_wfe_req (ds_cpu1_wfe_req), + .ds_cpu1_wfi_req (ds_cpu1_wfi_req), + .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_cpu2_flush (ds_cpu2_flush), + .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), + .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), + .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu2_reset_req (ds_cpu2_reset_req), + .ds_cpu2_sev_req (ds_cpu2_sev_req), + .ds_cpu2_sevl_req (ds_cpu2_sevl_req), + .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_cpu2_wfe_req (ds_cpu2_wfe_req), + .ds_cpu2_wfi_req (ds_cpu2_wfi_req), + .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_cpu3_flush (ds_cpu3_flush), + .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), + .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), + .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), + .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_cpu3_reset_req (ds_cpu3_reset_req), + .ds_cpu3_sev_req (ds_cpu3_sev_req), + .ds_cpu3_sevl_req (ds_cpu3_sevl_req), + .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_cpu3_wfe_req (ds_cpu3_wfe_req), + .ds_cpu3_wfi_req (ds_cpu3_wfi_req), + .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .etclken_cpu0_i (etclken_cpu0_i), + .etclken_cpu1_i (etclken_cpu1_i), + .etclken_cpu2_i (etclken_cpu2_i), + .etclken_cpu3_i (etclken_cpu3_i), + .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .ls_cpu0_clrexmon (ls_cpu0_clrexmon), + .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ls_cpu1_clrexmon (ls_cpu1_clrexmon), + .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ls_cpu2_clrexmon (ls_cpu2_clrexmon), + .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ls_cpu3_clrexmon (ls_cpu3_clrexmon), + .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), + .nCORERESET (nCORERESET[`MAIA_CN:0]), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nFIQ (nFIQ[`MAIA_CN:0]), + .nIRQ (nIRQ[`MAIA_CN:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .nPRESETDBG (nPRESETDBG), + .nREI (nREI[`MAIA_CN:0]), + .nSEI (nSEI[`MAIA_CN:0]), + .nVFIQ (nVFIQ[`MAIA_CN:0]), + .nVIRQ (nVIRQ[`MAIA_CN:0]), + .nVSEI (nVSEI[`MAIA_CN:0]), + .ncommirq_cpu0_i (ncommirq_cpu0_i), + .ncommirq_cpu1_i (ncommirq_cpu1_i), + .ncommirq_cpu2_i (ncommirq_cpu2_i), + .ncommirq_cpu3_i (ncommirq_cpu3_i), + .npmuirq_cpu0_i (npmuirq_cpu0_i), + .npmuirq_cpu1_i (npmuirq_cpu1_i), + .npmuirq_cpu2_i (npmuirq_cpu2_i), + .npmuirq_cpu3_i (npmuirq_cpu3_i), + .pm_export_cpu0_i (pm_export_cpu0_i), + .pm_export_cpu1_i (pm_export_cpu1_i), + .pm_export_cpu2_i (pm_export_cpu2_i), + .pm_export_cpu3_i (pm_export_cpu3_i), + .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), + .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), + .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), + .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]) + ); // unoncpu +endmodule // MAIA_s + + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu.v b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu.v new file mode 100644 index 0000000000..97ad653c68 --- /dev/null +++ b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu.v @@ -0,0 +1,7931 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: maia_noncpu.v $ +// Checked In : $Date: 2015-05-06 10:47:09 -0500 (Wed, 06 May 2015) $ +// Revision : $Revision: 73443 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// +// This is top-level interconnect layer for the non-CPU blocks at the Maia top-level. +// + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +`define MAIA_CN 3 + +module maia_noncpu ( + CLK, + CLKEN, + nCPUPORESET, + nCORERESET, + nL2RESET, + L2RSTDISABLE, + WARMRSTREQ, + CFGEND, + VINITHI, + CFGTE, + CP15SDISABLE, + CLUSTERIDAFF1, + CLUSTERIDAFF2, + AA64nAA32, + RVBARADDR0, +// BEGIN INCLUDE FOR CPU1 + RVBARADDR1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + RVBARADDR2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + RVBARADDR3, +// END INCLUDE FOR CPU3 + CRYPTODISABLE, + nFIQ, + nIRQ, + nSEI, + nREI, + nVFIQ, + nVIRQ, + nVSEI, +// BEGIN NO-GIC pins + nVCPUMNTIRQ, +// END NO-GIC pins + PERIPHBASE, +// BEGIN NO-GIC pins + GICCDISABLE, + ICDTVALID, + ICDTREADY, + ICDTDATA, + ICDTLAST, + ICDTDEST, + ICCTVALID, + ICCTREADY, + ICCTDATA, + ICCTLAST, + ICCTID, +// END NO-GIC pins + CNTVALUEB, + CNTCLKEN, + nCNTPNSIRQ, + nCNTPSIRQ, + nCNTVIRQ, + nCNTHPIRQ, + CLREXMONREQ, + CLREXMONACK, + EVENTI, + EVENTO, + STANDBYWFI, + STANDBYWFE, + STANDBYWFIL2, + SMPEN, + CPUQACTIVE, + CPUQREQn, + CPUQACCEPTn, + CPUQDENY, + L2QACTIVE, + L2QREQn, + L2QACCEPTn, + L2QDENY, + L2FLUSHREQ, + L2FLUSHDONE, + nINTERRIRQ, + nEXTERRIRQ, + SYSBARDISABLE, + BROADCASTINNER, + BROADCASTOUTER, + BROADCASTCACHEMAINT, + ACLKENM, + ACINACTM, + AWREADYM, + AWVALIDM, + AWIDM, + AWADDRM, + AWLENM, + AWSIZEM, + AWBURSTM, + AWBARM, + AWDOMAINM, + AWLOCKM, + AWCACHEM, + AWPROTM, + AWSNOOPM, + AWUNIQUEM, + WRMEMATTR, + WREADYM, + WVALIDM, + WDATAM, + WSTRBM, + WIDM, + WLASTM, + BREADYM, + BVALIDM, + BIDM, + BRESPM, + ARREADYM, + ARVALIDM, + ARIDM, + ARADDRM, + ARLENM, + ARSIZEM, + ARBURSTM, + ARBARM, + ARDOMAINM, + ARLOCKM, + ARCACHEM, + ARPROTM, + ARSNOOPM, + RDMEMATTR, + RREADYM, + RVALIDM, + RIDM, + RDATAM, + RRESPM, + RLASTM, + ACREADYM, + ACVALIDM, + ACADDRM, + ACPROTM, + ACSNOOPM, + CRREADYM, + CRVALIDM, + CRRESPM, + CDREADYM, + CDVALIDM, + CDDATAM, + CDLASTM, + RACKM, + WACKM, +// BEGIN NO-ACP pins + ACLKENS, + AINACTS, + AWREADYS, + AWVALIDS, + AWIDS, + AWADDRS, + AWLENS, + AWCACHES, + AWUSERS, + AWPROTS, + WREADYS, + WVALIDS, + WDATAS, + WSTRBS, + WLASTS, + BREADYS, + BVALIDS, + BIDS, + BRESPS, + ARREADYS, + ARVALIDS, + ARIDS, + ARADDRS, + ARLENS, + ARCACHES, + ARUSERS, + ARPROTS, + RREADYS, + RVALIDS, + RIDS, + RDATAS, + RRESPS, + RLASTS, +// END NO-ACP pins + DBGROMADDR, + DBGROMADDRV, + DBGACK, + nCOMMIRQ, + COMMRX, + COMMTX, + DBGRSTREQ, + DBGNOPWRDWN, + DBGL1RSTDISABLE, + nPMUIRQ, + PMUEVENT0, +// BEGIN INCLUDE FOR CPU1 + PMUEVENT1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + PMUEVENT2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + PMUEVENT3, +// END INCLUDE FOR CPU3 + ATCLKEN, + TSVALUEB, + ATREADYM0, + AFVALIDM0, + ATDATAM0, + ATVALIDM0, + ATBYTESM0, + AFREADYM0, + ATIDM0, + SYNCREQM0, +// BEGIN INCLUDE FOR CPU1 + ATREADYM1, + AFVALIDM1, + ATDATAM1, + ATVALIDM1, + ATBYTESM1, + AFREADYM1, + ATIDM1, + SYNCREQM1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ATREADYM2, + AFVALIDM2, + ATDATAM2, + ATVALIDM2, + ATBYTESM2, + AFREADYM2, + ATIDM2, + SYNCREQM2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ATREADYM3, + AFVALIDM3, + ATDATAM3, + ATVALIDM3, + ATBYTESM3, + AFREADYM3, + ATIDM3, + SYNCREQM3, +// END INCLUDE FOR CPU3 + PCLKDBG, + PCLKENDBG, + nPRESETDBG, + PSELDBG, + PADDRDBG, + PADDRDBG31, + PENABLEDBG, + PWRITEDBG, + PWDATADBG, + PRDATADBG, + PREADYDBG, + PSLVERRDBG, + EDBGRQ, + PMUSNAPSHOTREQ, + PMUSNAPSHOTACK, + DBGPWRDUP, + DBGPWRUPREQ, + CTICHIN, + CTICHOUTACK, + CTICHOUT, + CTICHINACK, + CISBYPASS, + CIHSBYPASS, + CTIIRQ, + CTIIRQACK, + DBGEN, + NIDEN, + SPIDEN, + SPNIDEN, + DFTSE, + DFTRSTDISABLE, + DFTCRCLKDISABLE, + DFTL2CLKDISABLE, + DFTRAMHOLD, + DFTCLKBYPASS, + DFTMCPHOLD, + nMBISTRESET, + MBISTREQ, + +//----------------------------------------------------------------------------- +// Signals from maia -> maia_cpu_io -> maia_cpu +//----------------------------------------------------------------------------- +// Outputs to maia_cpu + ncpuporeset_cpu0_o, + ncorereset_cpu0_o, + + cfgend_cpu0_o, + cfgte_cpu0_o, + cp15sdisable_cpu0_o, + vinithi_cpu0_o, + clusteridaff1_cpu0_o, + clusteridaff2_cpu0_o, + cpuid_cpu0_o, + aa64naa32_cpu0_o, + rvbaraddr_cpu0_o, + cryptodisable_cpu0_o, + giccdisable_cpu0_o, + + dbgromaddr_cpu0_o, + dbgromaddrv_cpu0_o, + dbgl1rstdisable_cpu0_o, + + dbgen_cpu0_o, + niden_cpu0_o, + spiden_cpu0_o, + spniden_cpu0_o, + + tsvalueb_cpu0_o, + + atclken_cpu0_o, + afvalidm_cpu0_o, + atreadym_cpu0_o, + syncreqm_cpu0_o, + + dftse_cpu0_o, + dftrstdisable_cpu0_o, + dftcrclkdisable_cpu0_o, + dftramhold_cpu0_o, + + nmbistreset_cpu0_o, + +// BEGIN INCLUDE FOR CPU1 + ncpuporeset_cpu1_o, + ncorereset_cpu1_o, + + cfgend_cpu1_o, + cfgte_cpu1_o, + cp15sdisable_cpu1_o, + vinithi_cpu1_o, + clusteridaff1_cpu1_o, + clusteridaff2_cpu1_o, + cpuid_cpu1_o, + aa64naa32_cpu1_o, + rvbaraddr_cpu1_o, + cryptodisable_cpu1_o, + giccdisable_cpu1_o, + + dbgromaddr_cpu1_o, + dbgromaddrv_cpu1_o, + dbgl1rstdisable_cpu1_o, + + dbgen_cpu1_o, + niden_cpu1_o, + spiden_cpu1_o, + spniden_cpu1_o, + + tsvalueb_cpu1_o, + + atclken_cpu1_o, + afvalidm_cpu1_o, + atreadym_cpu1_o, + syncreqm_cpu1_o, + + dftse_cpu1_o, + dftrstdisable_cpu1_o, + dftcrclkdisable_cpu1_o, + dftramhold_cpu1_o, + + nmbistreset_cpu1_o, +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + ncpuporeset_cpu2_o, + ncorereset_cpu2_o, + + cfgend_cpu2_o, + cfgte_cpu2_o, + cp15sdisable_cpu2_o, + vinithi_cpu2_o, + clusteridaff1_cpu2_o, + clusteridaff2_cpu2_o, + cpuid_cpu2_o, + aa64naa32_cpu2_o, + rvbaraddr_cpu2_o, + cryptodisable_cpu2_o, + giccdisable_cpu2_o, + + dbgromaddr_cpu2_o, + dbgromaddrv_cpu2_o, + dbgl1rstdisable_cpu2_o, + + dbgen_cpu2_o, + niden_cpu2_o, + spiden_cpu2_o, + spniden_cpu2_o, + + tsvalueb_cpu2_o, + + atclken_cpu2_o, + afvalidm_cpu2_o, + atreadym_cpu2_o, + syncreqm_cpu2_o, + + dftse_cpu2_o, + dftrstdisable_cpu2_o, + dftcrclkdisable_cpu2_o, + dftramhold_cpu2_o, + + nmbistreset_cpu2_o, +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + ncpuporeset_cpu3_o, + ncorereset_cpu3_o, + + cfgend_cpu3_o, + cfgte_cpu3_o, + cp15sdisable_cpu3_o, + vinithi_cpu3_o, + clusteridaff1_cpu3_o, + clusteridaff2_cpu3_o, + cpuid_cpu3_o, + aa64naa32_cpu3_o, + rvbaraddr_cpu3_o, + cryptodisable_cpu3_o, + giccdisable_cpu3_o, + + dbgromaddr_cpu3_o, + dbgromaddrv_cpu3_o, + dbgl1rstdisable_cpu3_o, + + dbgen_cpu3_o, + niden_cpu3_o, + spiden_cpu3_o, + spniden_cpu3_o, + + tsvalueb_cpu3_o, + + atclken_cpu3_o, + afvalidm_cpu3_o, + atreadym_cpu3_o, + syncreqm_cpu3_o, + + dftse_cpu3_o, + dftrstdisable_cpu3_o, + dftcrclkdisable_cpu3_o, + dftramhold_cpu3_o, + + nmbistreset_cpu3_o, +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Signals from maia_cpu -> maia_cpu_io -> maia +//----------------------------------------------------------------------------- +// Inputs from maia_cpu + ds_cpu0_sev_req, + ds_cpu0_sevl_req, + ds_cpu0_cpuectlr_smp, + + ncommirq_cpu0_i, + commrx_cpu0_i, + commtx_cpu0_i, + dbgack_cpu0_i, + dbgrstreq_cpu0_i, + dbgnopwrdwn_cpu0_i, + + npmuirq_cpu0_i, + pmuevent_cpu0_i, + pm_export_cpu0_i, + + etclken_cpu0_i, + afreadym_cpu0_i, + atbytesm_cpu0_i, + atdatam_cpu0_i, + atidm_cpu0_i, + atvalidm_cpu0_i, + +// BEGIN INCLUDE FOR CPU1 + ds_cpu1_sev_req, + ds_cpu1_sevl_req, + ds_cpu1_cpuectlr_smp, + + ncommirq_cpu1_i, + commrx_cpu1_i, + commtx_cpu1_i, + dbgack_cpu1_i, + dbgrstreq_cpu1_i, + dbgnopwrdwn_cpu1_i, + + npmuirq_cpu1_i, + pmuevent_cpu1_i, + pm_export_cpu1_i, + + etclken_cpu1_i, + afreadym_cpu1_i, + atbytesm_cpu1_i, + atdatam_cpu1_i, + atidm_cpu1_i, + atvalidm_cpu1_i, +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + ds_cpu2_sev_req, + ds_cpu2_sevl_req, + ds_cpu2_cpuectlr_smp, + + ncommirq_cpu2_i, + commrx_cpu2_i, + commtx_cpu2_i, + dbgack_cpu2_i, + dbgrstreq_cpu2_i, + dbgnopwrdwn_cpu2_i, + + npmuirq_cpu2_i, + pmuevent_cpu2_i, + pm_export_cpu2_i, + + etclken_cpu2_i, + afreadym_cpu2_i, + atbytesm_cpu2_i, + atdatam_cpu2_i, + atidm_cpu2_i, + atvalidm_cpu2_i, +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + ds_cpu3_sev_req, + ds_cpu3_sevl_req, + ds_cpu3_cpuectlr_smp, + + ncommirq_cpu3_i, + commrx_cpu3_i, + commtx_cpu3_i, + dbgack_cpu3_i, + dbgrstreq_cpu3_i, + dbgnopwrdwn_cpu3_i, + + npmuirq_cpu3_i, + pmuevent_cpu3_i, + pm_export_cpu3_i, + + etclken_cpu3_i, + afreadym_cpu3_i, + atbytesm_cpu3_i, + atdatam_cpu3_i, + atidm_cpu3_i, + atvalidm_cpu3_i, +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// L2 interface +//----------------------------------------------------------------------------- + l2_cpu0_mbist1_addr_b1, + l2_cpu0_mbist1_array_b1, + l2_cpu0_mbist1_be_b1, + l2_cpu0_mbist1_en_b1, + l2_cpu0_mbist1_rd_en_b1, + l2_cpu0_mbist1_wr_en_b1, + l2_cpu0_mbist1_all_b1, +// BEGIN INCLUDE FOR CPU1 + l2_cpu1_mbist1_addr_b1, + l2_cpu1_mbist1_array_b1, + l2_cpu1_mbist1_be_b1, + l2_cpu1_mbist1_en_b1, + l2_cpu1_mbist1_rd_en_b1, + l2_cpu1_mbist1_wr_en_b1, + l2_cpu1_mbist1_all_b1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + l2_cpu2_mbist1_addr_b1, + l2_cpu2_mbist1_array_b1, + l2_cpu2_mbist1_be_b1, + l2_cpu2_mbist1_en_b1, + l2_cpu2_mbist1_rd_en_b1, + l2_cpu2_mbist1_wr_en_b1, + l2_cpu2_mbist1_all_b1, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + l2_cpu3_mbist1_addr_b1, + l2_cpu3_mbist1_array_b1, + l2_cpu3_mbist1_be_b1, + l2_cpu3_mbist1_en_b1, + l2_cpu3_mbist1_rd_en_b1, + l2_cpu3_mbist1_wr_en_b1, + l2_cpu3_mbist1_all_b1, +// END INCLUDE FOR CPU3 + +// BEGIN L2-CPU interface + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + l2_cpu0_cfg_ecc_en, + l2_cpu0_arb_thrshld_timeout_en, + l2_cpu0_disable_clean_evict_opt, + l2_cpu0_dext_err_r2, + l2_cpu0_dext_err_type_r2, + l2_cpu0_dsngl_ecc_err_r3, + l2_cpu0_ddbl_ecc_err_r3, + l2_cpu0_ddata_r2, + l2_cpu0_barrier_done, + l2_cpu0_spec_valid, + l2_cpu0_spec_bufid, + l2_cpu0_rvalid, + l2_cpu0_rstate, + l2_cpu0_rexfail, + l2_cpu0_rbufid, + l2_cpu0_dvalid_r1, + l2_cpu0_dlast_r1, + l2_cpu0_dbufid_r1, + l2_cpu0_iext_err_r2, + l2_cpu0_iext_err_type_r2, + l2_cpu0_isngl_ecc_err_r3, + l2_cpu0_idbl_ecc_err_r3, + l2_cpu0_idata_r2, + l2_cpu0_ivalid_r1, + l2_cpu0_ibufid_r1, + l2_cpu0_ls_sync_req, + l2_cpu0_ccb_req_addr_c3, + l2_cpu0_ccb_dbg_req_c3, + l2_cpu0_ls_ccb_clken_c3, + l2_cpu0_ls_ccb_req_c3, + l2_cpu0_ccb_req_id_c3, + l2_cpu0_ccb_req_type_c3, + l2_cpu0_ccb_req_info_c3, + l2_cpu0_if_ccb_clken_c3, + l2_cpu0_if_ccb_req_c3, + l2_cpu0_if_sync_req, + l2_cpu0_tlb_ccb_clken_c3, + l2_cpu0_tlb_ccb_req_c3, + l2_cpu0_tlb_sync_req, + l2_cpu0_tlb_sync_complete, + l2_cpu0_tbw_desc_vld, + l2_cpu0_tbw_ext_err, + l2_cpu0_tbw_ext_err_type, + l2_cpu0_tbw_dbl_ecc_err, + l2_cpu0_tbw_desc_data, + l2_cpu0_spr_rd_data, + l2_cpu0_l2_cache_size, + l2_cpu0_pf_throttle_q, + + l2_cpu0_wr_ex_resp, + l2_cpu0_wr_ex_fail, + + l2_cpu0_ic_base, + l2_cpu0_no_intctrl, + + + l2_cpu0_pmu_events, + + ds_cpu0_l2_spr_en, + ds_cpu0_l2_spr_rd, + ds_cpu0_l2_spr_wr, + ds_cpu0_l2_spr_addr, + ds_cpu0_l2_spr_dw, + ds_cpu0_l2_spr_wr_data, + + l2_cpu0_wr_data_vld_x1_q, + l2_cpu0_wr_evict_x1_q, + l2_cpu0_wr_data, + l2_cpu0_ls_rd_haz_vld_arb_q, + l2_cpu0_ls_wr_haz_vld_arb_q, + l2_cpu0_dt_pmu_evt_en, + + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + l2_cpu1_cfg_ecc_en, + l2_cpu1_arb_thrshld_timeout_en, + l2_cpu1_disable_clean_evict_opt, + l2_cpu1_dext_err_r2, + l2_cpu1_dext_err_type_r2, + l2_cpu1_dsngl_ecc_err_r3, + l2_cpu1_ddbl_ecc_err_r3, + l2_cpu1_ddata_r2, + l2_cpu1_barrier_done, + l2_cpu1_spec_valid, + l2_cpu1_spec_bufid, + l2_cpu1_rvalid, + l2_cpu1_rstate, + l2_cpu1_rexfail, + l2_cpu1_rbufid, + l2_cpu1_dvalid_r1, + l2_cpu1_dlast_r1, + l2_cpu1_dbufid_r1, + l2_cpu1_iext_err_r2, + l2_cpu1_iext_err_type_r2, + l2_cpu1_isngl_ecc_err_r3, + l2_cpu1_idbl_ecc_err_r3, + l2_cpu1_idata_r2, + l2_cpu1_ivalid_r1, + l2_cpu1_ibufid_r1, + l2_cpu1_ls_sync_req, + l2_cpu1_ccb_req_addr_c3, + l2_cpu1_ccb_dbg_req_c3, + l2_cpu1_ls_ccb_clken_c3, + l2_cpu1_ls_ccb_req_c3, + l2_cpu1_ccb_req_id_c3, + l2_cpu1_ccb_req_type_c3, + l2_cpu1_ccb_req_info_c3, + l2_cpu1_if_ccb_clken_c3, + l2_cpu1_if_ccb_req_c3, + l2_cpu1_if_sync_req, + l2_cpu1_tlb_ccb_clken_c3, + l2_cpu1_tlb_ccb_req_c3, + l2_cpu1_tlb_sync_req, + l2_cpu1_tlb_sync_complete, + l2_cpu1_tbw_desc_vld, + l2_cpu1_tbw_ext_err, + l2_cpu1_tbw_ext_err_type, + l2_cpu1_tbw_dbl_ecc_err, + l2_cpu1_tbw_desc_data, + l2_cpu1_spr_rd_data, + l2_cpu1_l2_cache_size, + l2_cpu1_pf_throttle_q, + + l2_cpu1_wr_ex_resp, + l2_cpu1_wr_ex_fail, + + l2_cpu1_ic_base, + l2_cpu1_no_intctrl, + + l2_cpu1_pmu_events, + + ds_cpu1_l2_spr_en, + ds_cpu1_l2_spr_rd, + ds_cpu1_l2_spr_wr, + ds_cpu1_l2_spr_addr, + ds_cpu1_l2_spr_dw, + ds_cpu1_l2_spr_wr_data, + + l2_cpu1_wr_data_vld_x1_q, + l2_cpu1_wr_evict_x1_q, + l2_cpu1_wr_data, + l2_cpu1_ls_rd_haz_vld_arb_q, + l2_cpu1_ls_wr_haz_vld_arb_q, + l2_cpu1_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + l2_cpu2_cfg_ecc_en, + l2_cpu2_arb_thrshld_timeout_en, + l2_cpu2_disable_clean_evict_opt, + l2_cpu2_dext_err_r2, + l2_cpu2_dext_err_type_r2, + l2_cpu2_dsngl_ecc_err_r3, + l2_cpu2_ddbl_ecc_err_r3, + l2_cpu2_ddata_r2, + l2_cpu2_barrier_done, + l2_cpu2_spec_valid, + l2_cpu2_spec_bufid, + l2_cpu2_rvalid, + l2_cpu2_rstate, + l2_cpu2_rexfail, + l2_cpu2_rbufid, + l2_cpu2_dvalid_r1, + l2_cpu2_dlast_r1, + l2_cpu2_dbufid_r1, + l2_cpu2_iext_err_r2, + l2_cpu2_iext_err_type_r2, + l2_cpu2_isngl_ecc_err_r3, + l2_cpu2_idbl_ecc_err_r3, + l2_cpu2_idata_r2, + l2_cpu2_ivalid_r1, + l2_cpu2_ibufid_r1, + l2_cpu2_ls_sync_req, + l2_cpu2_ccb_req_addr_c3, + l2_cpu2_ccb_dbg_req_c3, + l2_cpu2_ls_ccb_clken_c3, + l2_cpu2_ls_ccb_req_c3, + l2_cpu2_ccb_req_id_c3, + l2_cpu2_ccb_req_type_c3, + l2_cpu2_ccb_req_info_c3, + l2_cpu2_if_ccb_clken_c3, + l2_cpu2_if_ccb_req_c3, + l2_cpu2_if_sync_req, + l2_cpu2_tlb_ccb_clken_c3, + l2_cpu2_tlb_ccb_req_c3, + l2_cpu2_tlb_sync_req, + l2_cpu2_tlb_sync_complete, + l2_cpu2_tbw_desc_vld, + l2_cpu2_tbw_ext_err, + l2_cpu2_tbw_ext_err_type, + l2_cpu2_tbw_dbl_ecc_err, + l2_cpu2_tbw_desc_data, + l2_cpu2_spr_rd_data, + l2_cpu2_l2_cache_size, + l2_cpu2_pf_throttle_q, + + l2_cpu2_wr_ex_resp, + l2_cpu2_wr_ex_fail, + + l2_cpu2_ic_base, + l2_cpu2_no_intctrl, + + l2_cpu2_pmu_events, + + ds_cpu2_l2_spr_en, + ds_cpu2_l2_spr_rd, + ds_cpu2_l2_spr_wr, + ds_cpu2_l2_spr_addr, + ds_cpu2_l2_spr_dw, + ds_cpu2_l2_spr_wr_data, + + l2_cpu2_wr_data_vld_x1_q, + l2_cpu2_wr_evict_x1_q, + l2_cpu2_wr_data, + l2_cpu2_ls_rd_haz_vld_arb_q, + l2_cpu2_ls_wr_haz_vld_arb_q, + l2_cpu2_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + l2_cpu3_cfg_ecc_en, + l2_cpu3_arb_thrshld_timeout_en, + l2_cpu3_disable_clean_evict_opt, + l2_cpu3_dext_err_r2, + l2_cpu3_dext_err_type_r2, + l2_cpu3_dsngl_ecc_err_r3, + l2_cpu3_ddbl_ecc_err_r3, + l2_cpu3_ddata_r2, + l2_cpu3_barrier_done, + l2_cpu3_spec_valid, + l2_cpu3_spec_bufid, + l2_cpu3_rvalid, + l2_cpu3_rstate, + l2_cpu3_rexfail, + l2_cpu3_rbufid, + l2_cpu3_dvalid_r1, + l2_cpu3_dlast_r1, + l2_cpu3_dbufid_r1, + l2_cpu3_iext_err_r2, + l2_cpu3_iext_err_type_r2, + l2_cpu3_isngl_ecc_err_r3, + l2_cpu3_idbl_ecc_err_r3, + l2_cpu3_idata_r2, + l2_cpu3_ivalid_r1, + l2_cpu3_ibufid_r1, + l2_cpu3_ls_sync_req, + l2_cpu3_ccb_req_addr_c3, + l2_cpu3_ccb_dbg_req_c3, + l2_cpu3_ls_ccb_clken_c3, + l2_cpu3_ls_ccb_req_c3, + l2_cpu3_ccb_req_id_c3, + l2_cpu3_ccb_req_type_c3, + l2_cpu3_ccb_req_info_c3, + l2_cpu3_if_ccb_clken_c3, + l2_cpu3_if_ccb_req_c3, + l2_cpu3_if_sync_req, + l2_cpu3_tlb_ccb_clken_c3, + l2_cpu3_tlb_ccb_req_c3, + l2_cpu3_tlb_sync_req, + l2_cpu3_tlb_sync_complete, + l2_cpu3_tbw_desc_vld, + l2_cpu3_tbw_ext_err, + l2_cpu3_tbw_ext_err_type, + l2_cpu3_tbw_dbl_ecc_err, + l2_cpu3_tbw_desc_data, + l2_cpu3_spr_rd_data, + l2_cpu3_l2_cache_size, + l2_cpu3_pf_throttle_q, + + l2_cpu3_wr_ex_resp, + l2_cpu3_wr_ex_fail, + + l2_cpu3_ic_base, + l2_cpu3_no_intctrl, + + l2_cpu3_pmu_events, + + ds_cpu3_l2_spr_en, + ds_cpu3_l2_spr_rd, + ds_cpu3_l2_spr_wr, + ds_cpu3_l2_spr_addr, + ds_cpu3_l2_spr_dw, + ds_cpu3_l2_spr_wr_data, + + l2_cpu3_wr_data_vld_x1_q, + l2_cpu3_wr_evict_x1_q, + l2_cpu3_wr_data, + l2_cpu3_ls_rd_haz_vld_arb_q, + l2_cpu3_ls_wr_haz_vld_arb_q, + l2_cpu3_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// tag_pipe / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_flsh_ls_rd_l2_dly, + l2_cpu0_flsh_ls_wr_l2_dly, + + l2_cpu0_wr_data_stall, + + l2_cpu1_flsh_ls_rd_l2_dly, + l2_cpu1_flsh_ls_wr_l2_dly, + + l2_cpu1_wr_data_stall, + + l2_cpu2_flsh_ls_rd_l2_dly, + l2_cpu2_flsh_ls_wr_l2_dly, + + l2_cpu2_wr_data_stall, + + l2_cpu3_flsh_ls_rd_l2_dly, + l2_cpu3_flsh_ls_wr_l2_dly, + + l2_cpu3_wr_data_stall, + + l2_cpu0_flsh_ls_rd_id_l2_dly, + l2_cpu0_flsh_ls_wr_id_l2_dly, + + l2_cpu1_flsh_ls_rd_id_l2_dly, + l2_cpu1_flsh_ls_wr_id_l2_dly, + + l2_cpu2_flsh_ls_rd_id_l2_dly, + l2_cpu2_flsh_ls_wr_id_l2_dly, + + l2_cpu3_flsh_ls_rd_id_l2_dly, + l2_cpu3_flsh_ls_wr_id_l2_dly, + + l2_cpu0_flsh_ls_rd_l4_dly, + l2_cpu0_flsh_if_rd_l4_dly, + l2_cpu0_flsh_tw_rd_l4_dly, + l2_cpu0_flsh_ls_wr_l4_dly, + + l2_cpu1_flsh_ls_rd_l4_dly, + l2_cpu1_flsh_if_rd_l4_dly, + l2_cpu1_flsh_tw_rd_l4_dly, + l2_cpu1_flsh_ls_wr_l4_dly, + + l2_cpu2_flsh_ls_rd_l4_dly, + l2_cpu2_flsh_if_rd_l4_dly, + l2_cpu2_flsh_tw_rd_l4_dly, + l2_cpu2_flsh_ls_wr_l4_dly, + + l2_cpu3_flsh_ls_rd_l4_dly, + l2_cpu3_flsh_if_rd_l4_dly, + l2_cpu3_flsh_tw_rd_l4_dly, + l2_cpu3_flsh_ls_wr_l4_dly, + + l2_cpu0_flsh_ls_rd_id_l4_dly, + l2_cpu0_flsh_if_rd_id_l4_dly, + l2_cpu0_flsh_ls_wr_id_l4_dly, + l2_cpu0_flsh_ls_wr_evict_l4_dly, + + l2_cpu1_flsh_ls_rd_id_l4_dly, + l2_cpu1_flsh_if_rd_id_l4_dly, + l2_cpu1_flsh_ls_wr_id_l4_dly, + l2_cpu1_flsh_ls_wr_evict_l4_dly, + + l2_cpu2_flsh_ls_rd_id_l4_dly, + l2_cpu2_flsh_if_rd_id_l4_dly, + l2_cpu2_flsh_ls_wr_id_l4_dly, + l2_cpu2_flsh_ls_wr_evict_l4_dly, + + l2_cpu3_flsh_ls_rd_id_l4_dly, + l2_cpu3_flsh_if_rd_id_l4_dly, + l2_cpu3_flsh_ls_wr_id_l4_dly, + l2_cpu3_flsh_ls_wr_evict_l4_dly, + + l2_cpu0_lrq_haz_pending, + l2_cpu1_lrq_haz_pending, + l2_cpu2_lrq_haz_pending, + l2_cpu3_lrq_haz_pending, + + l2_cpu0_ifq_haz_pending, + l2_cpu1_ifq_haz_pending, + l2_cpu2_ifq_haz_pending, + l2_cpu3_ifq_haz_pending, + + l2_cpu0_trq_haz_pending, + l2_cpu1_trq_haz_pending, + l2_cpu2_trq_haz_pending, + l2_cpu3_trq_haz_pending, + + l2_cpu0_wrq_haz_pending, + l2_cpu1_wrq_haz_pending, + l2_cpu2_wrq_haz_pending, + l2_cpu3_wrq_haz_pending, + + l2_cpu0_idle_block_reqs_q, + l2_cpu1_idle_block_reqs_q, + l2_cpu2_idle_block_reqs_q, + l2_cpu3_idle_block_reqs_q, + + l2_cpu0_ls_peq_coll_l4_dly, + l2_cpu1_ls_peq_coll_l4_dly, + l2_cpu2_ls_peq_coll_l4_dly, + l2_cpu3_ls_peq_coll_l4_dly, + +//----------------------------------------------------------------------------- +// tag_pipe +//----------------------------------------------------------------------------- + l2_tbnk0_cpu0_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu1_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu2_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu3_lrq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu1_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu2_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu3_lrq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu1_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu2_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu3_ifq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu1_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu2_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu3_ifq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_trq_clr_l4_dly2_q, + l2_tbnk0_cpu1_trq_clr_l4_dly2_q, + l2_tbnk0_cpu2_trq_clr_l4_dly2_q, + l2_tbnk0_cpu3_trq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_trq_clr_l4_dly2_q, + l2_tbnk1_cpu1_trq_clr_l4_dly2_q, + l2_tbnk1_cpu2_trq_clr_l4_dly2_q, + l2_tbnk1_cpu3_trq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu1_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu2_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu3_wrq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu1_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu2_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu3_wrq_clr_l4_dly2_q, + + +//----------------------------------------------------------------------------- +// cpu_logic / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly, + + +//----------------------------------------------------------------------------- +// feq / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_dsq_rd_data_q, + l2_cpu0_dsq_rd_byte_strb_q, + l2_cpu1_dsq_rd_data_q, + l2_cpu1_dsq_rd_byte_strb_q, + l2_cpu2_dsq_rd_data_q, + l2_cpu2_dsq_rd_byte_strb_q, + l2_cpu3_dsq_rd_data_q, + l2_cpu3_dsq_rd_byte_strb_q, + + l2_cpu0_dsq_clr_vld_q, + l2_cpu0_dsq_clr_id_q, + l2_cpu0_dsq_rd_en, + l2_cpu0_dsq_rd_en_x2, + l2_cpu0_dsq_rd_buf_id, + l2_cpu1_dsq_clr_vld_q, + l2_cpu1_dsq_clr_id_q, + l2_cpu1_dsq_rd_en, + l2_cpu1_dsq_rd_en_x2, + l2_cpu1_dsq_rd_buf_id, + l2_cpu2_dsq_clr_vld_q, + l2_cpu2_dsq_clr_id_q, + l2_cpu2_dsq_rd_en, + l2_cpu2_dsq_rd_en_x2, + l2_cpu2_dsq_rd_buf_id, + l2_cpu3_dsq_clr_vld_q, + l2_cpu3_dsq_rd_en, + l2_cpu3_dsq_rd_en_x2, + l2_cpu3_dsq_clr_id_q, + l2_cpu3_dsq_rd_buf_id, + +//----------------------------------------------------------------------------- +// arbitration +//----------------------------------------------------------------------------- + l2_cpu0_rd_vld_skid, + l2_cpu1_rd_vld_skid, + l2_cpu2_rd_vld_skid, + l2_cpu3_rd_vld_skid, + + l2_cpu0_pf_rd_vld_skid_popped, + l2_cpu1_pf_rd_vld_skid_popped, + l2_cpu2_pf_rd_vld_skid_popped, + l2_cpu3_pf_rd_vld_skid_popped, + + l2_cpu0_rd_arb, + l2_cpu1_rd_arb, + l2_cpu2_rd_arb, + l2_cpu3_rd_arb, + + l2_cpu0_wr_vld_skid, + l2_cpu1_wr_vld_skid, + l2_cpu2_wr_vld_skid, + l2_cpu3_wr_vld_skid, + + l2_cpu0_wr_arb, + l2_cpu1_wr_arb, + l2_cpu2_wr_arb, + l2_cpu3_wr_arb, + + l2_cpu0_ic_vld_skid, + l2_cpu1_ic_vld_skid, + l2_cpu2_ic_vld_skid, + l2_cpu3_ic_vld_skid, + + l2_cpu0_ic_barrier_stall_q, + l2_cpu1_ic_barrier_stall_q, + l2_cpu2_ic_barrier_stall_q, + l2_cpu3_ic_barrier_stall_q, + + l2_cpu0_blk_non_evict_wr, + l2_cpu1_blk_non_evict_wr, + l2_cpu2_blk_non_evict_wr, + l2_cpu3_blk_non_evict_wr, + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + l2_cpu0_idle_wakeup_q, + l2_cpu0_rd_arb_fast, + l2_cpu0_rd_id_arb_set, + l2_cpu0_rd_lrq_id_arb_set, + l2_cpu0_rd_type_arb_set, + l2_cpu0_rd_cache_attr_arb_set, + l2_cpu0_rd_page_attr_arb_set, + l2_cpu0_rd_elem_size_arb_set, + l2_cpu0_rd_way_arb_set, + l2_cpu0_rd_replayed_arb_set, + l2_cpu0_rd_excl_arb_set, + l2_cpu0_rd_priv_arb_set, + l2_cpu0_rd_shared_arb_set, + l2_cpu0_rd_va48_arb_set, + l2_cpu0_rd_aarch64_arb_set, + l2_cpu0_rd_asid_arb_set, + l2_cpu0_rd_prfm_arb_set, + l2_cpu0_rd_addr_arb_set, + l2_cpu0_rd_bypass_arb_set, + l2_cpu0_rd_bypass_req_can_e5, + l2_cpu0_early_rd_reqe4_e5_q, + l2_cpu0_rd_bypass_way_e5, + l2_cpu0_rd_bypass_bufid_e5, + l2_cpu0_rd_bypass_lrq_id_e5, + + l2_cpu0_wr_arb_fast, + l2_cpu0_wr_id_arb_set, + l2_cpu0_wr_partial_dw_arb_set, + l2_cpu0_wr_cache_attr_arb_set, + l2_cpu0_wr_page_attr_arb_set, + l2_cpu0_wr_elem_size_arb_set, + l2_cpu0_wr_type_arb_set, + l2_cpu0_wr_cl_id_arb_set, + l2_cpu0_wr_priv_arb_set, + l2_cpu0_wr_shared_arb_set, + l2_cpu0_wr_last_arb_set, + l2_cpu0_wr_clean_evict_arb_set, + l2_cpu0_wr_err_arb_set, + l2_cpu0_wr_way_arb_set, + l2_cpu0_wr_dirty_arb_set, + l2_cpu0_wr_1st_replayed_arb_set, + l2_cpu0_wr_addr_arb_set, + l2_cpu0_ic_arb_fast, + l2_cpu0_ic_id_arb_set, + l2_cpu0_ic_write_arb_set, + l2_cpu0_ic_excl_arb_set, + l2_cpu0_ic_elem_size_arb_set, + l2_cpu0_ic_ns_arb_set, + l2_cpu0_ic_addr_arb_set, + l2_cpu0_ic_data_arb_set, + + l2_cpu0_wrq_almost_full, + + l2_cpu0_ls_wr_req_w2a, + l2_cpu0_ls_wr_last_w2a, + l2_cpu0_ls_wr_dirty_w2a, + l2_cpu0_ls_wr_err_w2a, + l2_cpu0_ls_wr_type_w2a, + l2_cpu0_ls_wr_ccb_id_w2a, + l2_cpu0_ls_wr_data_w2a, + + l2_cpu0_ls_ccb_resp, + l2_cpu0_ls_ccb_resp_id, + l2_cpu0_ls_ccb_data_wr, + + l2_cpu0_if_ccb_resp, + l2_cpu0_if_ccb_resp_id, + + l2_cpu0_tw_ccb_resp, + l2_cpu0_tw_ccb_resp_id, + + l2_cpu0_if_sync_done_q, + l2_cpu0_tlb_sync_done_q, + + l2_cpu0_lrq_haz_clr_id_dcd_q, + l2_cpu0_wrq_haz_clr_id_dcd_q, + l2_cpu0_ls_rd_haz_id_arb_q, + l2_cpu0_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + l2_cpu1_idle_wakeup_q, + l2_cpu1_rd_arb_fast, + l2_cpu1_rd_id_arb_set, + l2_cpu1_rd_lrq_id_arb_set, + l2_cpu1_rd_type_arb_set, + l2_cpu1_rd_cache_attr_arb_set, + l2_cpu1_rd_page_attr_arb_set, + l2_cpu1_rd_elem_size_arb_set, + l2_cpu1_rd_way_arb_set, + l2_cpu1_rd_replayed_arb_set, + l2_cpu1_rd_excl_arb_set, + l2_cpu1_rd_priv_arb_set, + l2_cpu1_rd_shared_arb_set, + l2_cpu1_rd_va48_arb_set, + l2_cpu1_rd_aarch64_arb_set, + l2_cpu1_rd_asid_arb_set, + l2_cpu1_rd_prfm_arb_set, + l2_cpu1_rd_addr_arb_set, + l2_cpu1_rd_bypass_arb_set, + l2_cpu1_rd_bypass_req_can_e5, + l2_cpu1_early_rd_reqe4_e5_q, + l2_cpu1_rd_bypass_way_e5, + l2_cpu1_rd_bypass_bufid_e5, + l2_cpu1_rd_bypass_lrq_id_e5, + + l2_cpu1_wr_arb_fast, + l2_cpu1_wr_id_arb_set, + l2_cpu1_wr_partial_dw_arb_set, + l2_cpu1_wr_cache_attr_arb_set, + l2_cpu1_wr_page_attr_arb_set, + l2_cpu1_wr_elem_size_arb_set, + l2_cpu1_wr_type_arb_set, + l2_cpu1_wr_cl_id_arb_set, + l2_cpu1_wr_priv_arb_set, + l2_cpu1_wr_shared_arb_set, + l2_cpu1_wr_last_arb_set, + l2_cpu1_wr_clean_evict_arb_set, + l2_cpu1_wr_err_arb_set, + l2_cpu1_wr_way_arb_set, + l2_cpu1_wr_dirty_arb_set, + l2_cpu1_wr_1st_replayed_arb_set, + l2_cpu1_wr_addr_arb_set, + l2_cpu1_ic_arb_fast, + l2_cpu1_ic_id_arb_set, + l2_cpu1_ic_write_arb_set, + l2_cpu1_ic_excl_arb_set, + l2_cpu1_ic_elem_size_arb_set, + l2_cpu1_ic_ns_arb_set, + l2_cpu1_ic_addr_arb_set, + l2_cpu1_ic_data_arb_set, + + l2_cpu1_wrq_almost_full, + + l2_cpu1_ls_wr_req_w2a, + l2_cpu1_ls_wr_last_w2a, + l2_cpu1_ls_wr_dirty_w2a, + l2_cpu1_ls_wr_err_w2a, + l2_cpu1_ls_wr_type_w2a, + l2_cpu1_ls_wr_ccb_id_w2a, + l2_cpu1_ls_wr_data_w2a, + + l2_cpu1_ls_ccb_resp, + l2_cpu1_ls_ccb_resp_id, + l2_cpu1_ls_ccb_data_wr, + + l2_cpu1_if_ccb_resp, + l2_cpu1_if_ccb_resp_id, + + l2_cpu1_tw_ccb_resp, + l2_cpu1_tw_ccb_resp_id, + + l2_cpu1_if_sync_done_q, + l2_cpu1_tlb_sync_done_q, + + l2_cpu1_lrq_haz_clr_id_dcd_q, + l2_cpu1_wrq_haz_clr_id_dcd_q, + l2_cpu1_ls_rd_haz_id_arb_q, + l2_cpu1_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + l2_cpu2_idle_wakeup_q, + l2_cpu2_rd_arb_fast, + l2_cpu2_rd_id_arb_set, + l2_cpu2_rd_lrq_id_arb_set, + l2_cpu2_rd_type_arb_set, + l2_cpu2_rd_cache_attr_arb_set, + l2_cpu2_rd_page_attr_arb_set, + l2_cpu2_rd_elem_size_arb_set, + l2_cpu2_rd_way_arb_set, + l2_cpu2_rd_replayed_arb_set, + l2_cpu2_rd_excl_arb_set, + l2_cpu2_rd_priv_arb_set, + l2_cpu2_rd_shared_arb_set, + l2_cpu2_rd_va48_arb_set, + l2_cpu2_rd_aarch64_arb_set, + l2_cpu2_rd_asid_arb_set, + l2_cpu2_rd_prfm_arb_set, + l2_cpu2_rd_addr_arb_set, + l2_cpu2_rd_bypass_arb_set, + l2_cpu2_rd_bypass_req_can_e5, + l2_cpu2_early_rd_reqe4_e5_q, + l2_cpu2_rd_bypass_way_e5, + l2_cpu2_rd_bypass_bufid_e5, + l2_cpu2_rd_bypass_lrq_id_e5, + + l2_cpu2_wr_arb_fast, + l2_cpu2_wr_id_arb_set, + l2_cpu2_wr_partial_dw_arb_set, + l2_cpu2_wr_cache_attr_arb_set, + l2_cpu2_wr_page_attr_arb_set, + l2_cpu2_wr_elem_size_arb_set, + l2_cpu2_wr_type_arb_set, + l2_cpu2_wr_cl_id_arb_set, + l2_cpu2_wr_priv_arb_set, + l2_cpu2_wr_shared_arb_set, + l2_cpu2_wr_last_arb_set, + l2_cpu2_wr_clean_evict_arb_set, + l2_cpu2_wr_err_arb_set, + l2_cpu2_wr_way_arb_set, + l2_cpu2_wr_dirty_arb_set, + l2_cpu2_wr_1st_replayed_arb_set, + l2_cpu2_wr_addr_arb_set, + l2_cpu2_ic_arb_fast, + l2_cpu2_ic_id_arb_set, + l2_cpu2_ic_write_arb_set, + l2_cpu2_ic_excl_arb_set, + l2_cpu2_ic_elem_size_arb_set, + l2_cpu2_ic_ns_arb_set, + l2_cpu2_ic_addr_arb_set, + l2_cpu2_ic_data_arb_set, + + l2_cpu2_wrq_almost_full, + + l2_cpu2_ls_wr_req_w2a, + l2_cpu2_ls_wr_last_w2a, + l2_cpu2_ls_wr_dirty_w2a, + l2_cpu2_ls_wr_err_w2a, + l2_cpu2_ls_wr_type_w2a, + l2_cpu2_ls_wr_ccb_id_w2a, + l2_cpu2_ls_wr_data_w2a, + + l2_cpu2_ls_ccb_resp, + l2_cpu2_ls_ccb_resp_id, + l2_cpu2_ls_ccb_data_wr, + + l2_cpu2_if_ccb_resp, + l2_cpu2_if_ccb_resp_id, + + l2_cpu2_tw_ccb_resp, + l2_cpu2_tw_ccb_resp_id, + + l2_cpu2_if_sync_done_q, + l2_cpu2_tlb_sync_done_q, + + l2_cpu2_lrq_haz_clr_id_dcd_q, + l2_cpu2_wrq_haz_clr_id_dcd_q, + l2_cpu2_ls_rd_haz_id_arb_q, + l2_cpu2_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + l2_cpu3_idle_wakeup_q, + l2_cpu3_rd_arb_fast, + l2_cpu3_rd_id_arb_set, + l2_cpu3_rd_lrq_id_arb_set, + l2_cpu3_rd_type_arb_set, + l2_cpu3_rd_cache_attr_arb_set, + l2_cpu3_rd_page_attr_arb_set, + l2_cpu3_rd_elem_size_arb_set, + l2_cpu3_rd_way_arb_set, + l2_cpu3_rd_replayed_arb_set, + l2_cpu3_rd_excl_arb_set, + l2_cpu3_rd_priv_arb_set, + l2_cpu3_rd_shared_arb_set, + l2_cpu3_rd_va48_arb_set, + l2_cpu3_rd_aarch64_arb_set, + l2_cpu3_rd_asid_arb_set, + l2_cpu3_rd_prfm_arb_set, + l2_cpu3_rd_addr_arb_set, + l2_cpu3_rd_bypass_arb_set, + l2_cpu3_rd_bypass_req_can_e5, + l2_cpu3_early_rd_reqe4_e5_q, + l2_cpu3_rd_bypass_way_e5, + l2_cpu3_rd_bypass_bufid_e5, + l2_cpu3_rd_bypass_lrq_id_e5, + + l2_cpu3_wr_arb_fast, + l2_cpu3_wr_id_arb_set, + l2_cpu3_wr_partial_dw_arb_set, + l2_cpu3_wr_cache_attr_arb_set, + l2_cpu3_wr_page_attr_arb_set, + l2_cpu3_wr_elem_size_arb_set, + l2_cpu3_wr_type_arb_set, + l2_cpu3_wr_cl_id_arb_set, + l2_cpu3_wr_priv_arb_set, + l2_cpu3_wr_shared_arb_set, + l2_cpu3_wr_last_arb_set, + l2_cpu3_wr_clean_evict_arb_set, + l2_cpu3_wr_err_arb_set, + l2_cpu3_wr_way_arb_set, + l2_cpu3_wr_dirty_arb_set, + l2_cpu3_wr_1st_replayed_arb_set, + l2_cpu3_wr_addr_arb_set, + l2_cpu3_ic_arb_fast, + l2_cpu3_ic_id_arb_set, + l2_cpu3_ic_write_arb_set, + l2_cpu3_ic_excl_arb_set, + l2_cpu3_ic_elem_size_arb_set, + l2_cpu3_ic_ns_arb_set, + l2_cpu3_ic_addr_arb_set, + l2_cpu3_ic_data_arb_set, + + l2_cpu3_wrq_almost_full, + + l2_cpu3_ls_wr_req_w2a, + l2_cpu3_ls_wr_last_w2a, + l2_cpu3_ls_wr_dirty_w2a, + l2_cpu3_ls_wr_err_w2a, + l2_cpu3_ls_wr_type_w2a, + l2_cpu3_ls_wr_ccb_id_w2a, + l2_cpu3_ls_wr_data_w2a, + + l2_cpu3_ls_ccb_resp, + l2_cpu3_ls_ccb_resp_id, + l2_cpu3_ls_ccb_data_wr, + + l2_cpu3_if_ccb_resp, + l2_cpu3_if_ccb_resp_id, + + l2_cpu3_tw_ccb_resp, + l2_cpu3_tw_ccb_resp_id, + + l2_cpu3_if_sync_done_q, + l2_cpu3_tlb_sync_done_q, + + l2_cpu3_lrq_haz_clr_id_dcd_q, + l2_cpu3_wrq_haz_clr_id_dcd_q, + l2_cpu3_ls_rd_haz_id_arb_q, + l2_cpu3_ls_wr_haz_id_arb_q, + +// END L2-CPU interface + +//------------------------------------------------------------------- +// TM interface +//------------------------------------------------------------------- +// BEGIN TIMER-CPU interface + tm_cpu0_cntkctl_usr, + tm_cpu0_cnthctl_kernel, + + tm_cpu1_cntkctl_usr, + tm_cpu1_cnthctl_kernel, + + tm_cpu2_cntkctl_usr, + tm_cpu2_cnthctl_kernel, + + tm_cpu3_cntkctl_usr, + tm_cpu3_cnthctl_kernel, +// END TIMER-CPU interface + +//----------------------------------------------------------------------------- +// IC interface +//----------------------------------------------------------------------------- + ls_cpu0_imp_abort_slv, + ls_cpu0_imp_abort_ecc, + ls_cpu0_imp_abort_dec, + ls_cpu0_imp_abort_containable, + ls_cpu0_raw_eae_nonsec, + ls_cpu0_raw_eae_secure, + + ds_cpu0_ic_cpsr_mode, + ds_cpu0_ic_sample_spr, + ds_cpu0_ic_aa64naa32, + ds_cpu0_ic_hcr_change, + ds_cpu0_ic_scr_change, +// BEGIN INCLUDE FOR CPU1 + ds_cpu1_ic_cpsr_mode, + ds_cpu1_ic_sample_spr, + ds_cpu1_ic_aa64naa32, + ds_cpu1_ic_hcr_change, + ds_cpu1_ic_scr_change, + ls_cpu1_imp_abort_slv, + ls_cpu1_imp_abort_ecc, + ls_cpu1_imp_abort_dec, + ls_cpu1_imp_abort_containable, + ls_cpu1_raw_eae_nonsec, + ls_cpu1_raw_eae_secure, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ds_cpu2_ic_cpsr_mode, + ds_cpu2_ic_sample_spr, + ds_cpu2_ic_aa64naa32, + ds_cpu2_ic_hcr_change, + ds_cpu2_ic_scr_change, + ls_cpu2_imp_abort_slv, + ls_cpu2_imp_abort_ecc, + ls_cpu2_imp_abort_dec, + ls_cpu2_imp_abort_containable, + ls_cpu2_raw_eae_nonsec, + ls_cpu2_raw_eae_secure, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ds_cpu3_ic_cpsr_mode, + ds_cpu3_ic_sample_spr, + ds_cpu3_ic_aa64naa32, + ds_cpu3_ic_hcr_change, + ds_cpu3_ic_scr_change, + ls_cpu3_imp_abort_slv, + ls_cpu3_imp_abort_ecc, + ls_cpu3_imp_abort_dec, + ls_cpu3_imp_abort_containable, + ls_cpu3_raw_eae_nonsec, + ls_cpu3_raw_eae_secure, +// END INCLUDE FOR CPU3 + + ic_nfiq, + ic_nirq, + ic_nsei, + ic_nvfiq, + ic_nvirq, + ic_nvsei, + ic_p_valid, + + ic_sample_spr, + ic_hcr_change_complete, + ic_scr_change_complete, + ic_el_change_complete, + ic_ich_el2_tc, + ic_ich_el2_tall0, + ic_ich_el2_tall1, + ic_sra_el3_en, + ic_sra_el1s_en, + ic_sra_el2_en, + ic_sra_el1ns_en, + ic_sre_el1ns_hyp_trap, + ic_sre_el1ns_mon_trap, + ic_sre_el1s_mon_trap, + ic_sre_el2_mon_trap, + ic_block_eoi_sgi_wr, + +//----------------------------------------------------------------------------- +// DT interface +//----------------------------------------------------------------------------- +// BEGIN DT-CPU interface +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + dt_cpu0_et_oslock_gclk, + dt_cpu0_os_double_lock_gclk, + dt_cpu0_halt_ack_gclk, + dt_cpu0_coredbg_in_reset_gclk, + dt_cpu0_wfx_dbg_req_gclk, + dt_cpu0_hlt_dbgevt_ok_gclk, + dt_cpu0_dbif_ack_gclk, + dt_cpu0_dbif_err_gclk, + dt_cpu0_dbif_rddata_gclk, + + dt_cpu0_dbif_addr_pclk, + dt_cpu0_dbif_locked_pclk, + dt_cpu0_dbif_req_pclk, + dt_cpu0_dbif_wrdata_pclk, + dt_cpu0_dbif_write_pclk, + dt_cpu0_edecr_osuce_pclk, + dt_cpu0_edecr_rce_pclk, + dt_cpu0_edecr_ss_pclk, + dt_cpu0_edbgrq_pclk, + dt_cpu0_edacr_frc_idleack_pclk, + dt_cpu0_edprcr_corepurq_pclk, + + dt_cpu0_pmusnapshot_ack_gclk, + dt_cpu0_pmusnapshot_req_pclk, + + dt_cpu0_cti_trigin_7to4_gclk, + dt_cpu0_cti_trigin_1to0_gclk, + dt_cpu0_cti_trigoutack_7to4_gclk, + dt_cpu0_cti_trigoutack_bit1_gclk, + + dt_cpu0_cti_trigout_7to4_pclk, + dt_cpu0_cti_trigout_1to0_pclk, + dt_cpu0_cti_triginack_7to4_pclk, + dt_cpu0_cti_triginack_1to0_pclk, + + dt_cpu0_wfx_wakeup_pclk, + dt_cpu0_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + dt_cpu1_et_oslock_gclk, + dt_cpu1_os_double_lock_gclk, + dt_cpu1_halt_ack_gclk, + dt_cpu1_coredbg_in_reset_gclk, + dt_cpu1_wfx_dbg_req_gclk, + dt_cpu1_hlt_dbgevt_ok_gclk, + dt_cpu1_dbif_ack_gclk, + dt_cpu1_dbif_err_gclk, + dt_cpu1_dbif_rddata_gclk, + + dt_cpu1_dbif_addr_pclk, + dt_cpu1_dbif_locked_pclk, + dt_cpu1_dbif_req_pclk, + dt_cpu1_dbif_wrdata_pclk, + dt_cpu1_dbif_write_pclk, + dt_cpu1_edecr_osuce_pclk, + dt_cpu1_edecr_rce_pclk, + dt_cpu1_edecr_ss_pclk, + dt_cpu1_edbgrq_pclk, + dt_cpu1_edacr_frc_idleack_pclk, + dt_cpu1_edprcr_corepurq_pclk, + + dt_cpu1_pmusnapshot_ack_gclk, + dt_cpu1_pmusnapshot_req_pclk, + + dt_cpu1_cti_trigin_7to4_gclk, + dt_cpu1_cti_trigin_1to0_gclk, + dt_cpu1_cti_trigoutack_7to4_gclk, + dt_cpu1_cti_trigoutack_bit1_gclk, + + dt_cpu1_cti_trigout_7to4_pclk, + dt_cpu1_cti_trigout_1to0_pclk, + dt_cpu1_cti_triginack_7to4_pclk, + dt_cpu1_cti_triginack_1to0_pclk, + + dt_cpu1_wfx_wakeup_pclk, + dt_cpu1_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + dt_cpu2_et_oslock_gclk, + dt_cpu2_os_double_lock_gclk, + dt_cpu2_halt_ack_gclk, + dt_cpu2_coredbg_in_reset_gclk, + dt_cpu2_wfx_dbg_req_gclk, + dt_cpu2_hlt_dbgevt_ok_gclk, + dt_cpu2_dbif_ack_gclk, + dt_cpu2_dbif_err_gclk, + dt_cpu2_dbif_rddata_gclk, + + dt_cpu2_dbif_addr_pclk, + dt_cpu2_dbif_locked_pclk, + dt_cpu2_dbif_req_pclk, + dt_cpu2_dbif_wrdata_pclk, + dt_cpu2_dbif_write_pclk, + dt_cpu2_edecr_osuce_pclk, + dt_cpu2_edecr_rce_pclk, + dt_cpu2_edecr_ss_pclk, + dt_cpu2_edbgrq_pclk, + dt_cpu2_edacr_frc_idleack_pclk, + dt_cpu2_edprcr_corepurq_pclk, + + dt_cpu2_pmusnapshot_ack_gclk, + dt_cpu2_pmusnapshot_req_pclk, + + dt_cpu2_cti_trigin_7to4_gclk, + dt_cpu2_cti_trigin_1to0_gclk, + dt_cpu2_cti_trigoutack_7to4_gclk, + dt_cpu2_cti_trigoutack_bit1_gclk, + + dt_cpu2_cti_trigout_7to4_pclk, + dt_cpu2_cti_trigout_1to0_pclk, + dt_cpu2_cti_triginack_7to4_pclk, + dt_cpu2_cti_triginack_1to0_pclk, + + dt_cpu2_wfx_wakeup_pclk, + dt_cpu2_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + dt_cpu3_et_oslock_gclk, + dt_cpu3_os_double_lock_gclk, + dt_cpu3_halt_ack_gclk, + dt_cpu3_coredbg_in_reset_gclk, + dt_cpu3_wfx_dbg_req_gclk, + dt_cpu3_hlt_dbgevt_ok_gclk, + dt_cpu3_dbif_ack_gclk, + dt_cpu3_dbif_err_gclk, + dt_cpu3_dbif_rddata_gclk, + + dt_cpu3_dbif_addr_pclk, + dt_cpu3_dbif_locked_pclk, + dt_cpu3_dbif_req_pclk, + dt_cpu3_dbif_wrdata_pclk, + dt_cpu3_dbif_write_pclk, + dt_cpu3_edecr_osuce_pclk, + dt_cpu3_edecr_rce_pclk, + dt_cpu3_edecr_ss_pclk, + dt_cpu3_edbgrq_pclk, + dt_cpu3_edacr_frc_idleack_pclk, + dt_cpu3_edprcr_corepurq_pclk, + + dt_cpu3_pmusnapshot_ack_gclk, + dt_cpu3_pmusnapshot_req_pclk, + + dt_cpu3_cti_trigin_7to4_gclk, + dt_cpu3_cti_trigin_1to0_gclk, + dt_cpu3_cti_trigoutack_7to4_gclk, + dt_cpu3_cti_trigoutack_bit1_gclk, + + dt_cpu3_cti_trigout_7to4_pclk, + dt_cpu3_cti_trigout_1to0_pclk, + dt_cpu3_cti_triginack_7to4_pclk, + dt_cpu3_cti_triginack_1to0_pclk, + + dt_cpu3_wfx_wakeup_pclk, + dt_cpu3_noclkstop_pclk, +// END DT-CPU interface + +//----------------------------------------------------------------------------- +// CK interface +//----------------------------------------------------------------------------- +// BEGIN CK-CPU interface + ds_cpu0_reset_req, + ds_cpu0_wfi_req, + ds_cpu0_wfe_req, + ds_cpu0_flush, + ds_cpu0_flush_type, + ds_cpu0_imp_abrt_wfi_qual, + ds_cpu0_irq_wfi_qual, + ds_cpu0_fiq_wfi_qual, + ds_cpu0_vimp_abrt_wfi_qual, + ds_cpu0_virq_wfi_qual, + ds_cpu0_vfiq_wfi_qual, + ds_cpu0_imp_abrt_wfe_qual, + ds_cpu0_irq_wfe_qual, + ds_cpu0_fiq_wfe_qual, + ds_cpu0_vimp_abrt_wfe_qual, + ds_cpu0_virq_wfe_qual, + ds_cpu0_vfiq_wfe_qual, + ds_cpu0_hcr_va, + ds_cpu0_hcr_vi, + ds_cpu0_hcr_vf, + ds_cpu0_cpuectlr_ret, + ck_cpu0_event_reg, + ck_cpu0_wfi_ack, + ck_cpu0_wfe_ack, + ck_cpu0_crcx_clk_en_n, + + ds_cpu1_reset_req, + ds_cpu1_wfi_req, + ds_cpu1_wfe_req, + ds_cpu1_flush, + ds_cpu1_flush_type, + ds_cpu1_imp_abrt_wfi_qual, + ds_cpu1_irq_wfi_qual, + ds_cpu1_fiq_wfi_qual, + ds_cpu1_vimp_abrt_wfi_qual, + ds_cpu1_virq_wfi_qual, + ds_cpu1_vfiq_wfi_qual, + ds_cpu1_imp_abrt_wfe_qual, + ds_cpu1_irq_wfe_qual, + ds_cpu1_fiq_wfe_qual, + ds_cpu1_vimp_abrt_wfe_qual, + ds_cpu1_virq_wfe_qual, + ds_cpu1_vfiq_wfe_qual, + ds_cpu1_hcr_va, + ds_cpu1_hcr_vi, + ds_cpu1_hcr_vf, + ds_cpu1_cpuectlr_ret, + ck_cpu1_event_reg, + ck_cpu1_wfi_ack, + ck_cpu1_wfe_ack, + ck_cpu1_crcx_clk_en_n, + + ds_cpu2_reset_req, + ds_cpu2_wfi_req, + ds_cpu2_wfe_req, + ds_cpu2_flush, + ds_cpu2_flush_type, + ds_cpu2_imp_abrt_wfi_qual, + ds_cpu2_irq_wfi_qual, + ds_cpu2_fiq_wfi_qual, + ds_cpu2_vimp_abrt_wfi_qual, + ds_cpu2_virq_wfi_qual, + ds_cpu2_vfiq_wfi_qual, + ds_cpu2_imp_abrt_wfe_qual, + ds_cpu2_irq_wfe_qual, + ds_cpu2_fiq_wfe_qual, + ds_cpu2_vimp_abrt_wfe_qual, + ds_cpu2_virq_wfe_qual, + ds_cpu2_vfiq_wfe_qual, + ds_cpu2_hcr_va, + ds_cpu2_hcr_vi, + ds_cpu2_hcr_vf, + ds_cpu2_cpuectlr_ret, + ck_cpu2_event_reg, + ck_cpu2_wfi_ack, + ck_cpu2_wfe_ack, + ck_cpu2_crcx_clk_en_n, + + ds_cpu3_reset_req, + ds_cpu3_wfi_req, + ds_cpu3_wfe_req, + ds_cpu3_flush, + ds_cpu3_flush_type, + ds_cpu3_imp_abrt_wfi_qual, + ds_cpu3_irq_wfi_qual, + ds_cpu3_fiq_wfi_qual, + ds_cpu3_vimp_abrt_wfi_qual, + ds_cpu3_virq_wfi_qual, + ds_cpu3_vfiq_wfi_qual, + ds_cpu3_imp_abrt_wfe_qual, + ds_cpu3_irq_wfe_qual, + ds_cpu3_fiq_wfe_qual, + ds_cpu3_vimp_abrt_wfe_qual, + ds_cpu3_virq_wfe_qual, + ds_cpu3_vfiq_wfe_qual, + ds_cpu3_hcr_va, + ds_cpu3_hcr_vi, + ds_cpu3_hcr_vf, + ds_cpu3_cpuectlr_ret, + ck_cpu3_event_reg, + ck_cpu3_wfi_ack, + ck_cpu3_wfe_ack, + ck_cpu3_crcx_clk_en_n, + + ls_cpu0_clrexmon, + ls_cpu1_clrexmon, + ls_cpu2_clrexmon, + ls_cpu3_clrexmon, +// END CK-CPU interface + + ck_gclkt +); + +//# +//# Interface Signals +//# ================= +//# + +//----------------------------------------------------------------------------- +// Clock and Reset Signals +//----------------------------------------------------------------------------- + input CLK; // Fast Clock + input CLKEN; // Fast Clock Enable + + input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset + input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) + input nL2RESET; // L2 reset + input L2RSTDISABLE; // L2 RAMs hardware reset disable + output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request +//See also nPRESETDBG; // Debug APB reset (PCLK) + +//----------------------------------------------------------------------------- +// Static Configuration Signals +//----------------------------------------------------------------------------- +// Static configuration signals that should be tied off and not change dynamically. +// Many of the initial values specified by these inputs +// may be overridden in software using CP15 registers. + + input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) + input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors + input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) + input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers + + input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] + input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] + + input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) + input [43:2] RVBARADDR0; // RVBAR address +// BEGIN INCLUDE FOR CPU1 + input [43:2] RVBARADDR1; // RVBAR address +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input [43:2] RVBARADDR2; // RVBAR address +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input [43:2] RVBARADDR3; // RVBAR address +// END INCLUDE FOR CPU3 + input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension + +//----------------------------------------------------------------------------- +// Interrupt Controller Signals +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] nFIQ; // Fast Interrupt request + input [`MAIA_CN:0] nIRQ; // Interrupt request + input [`MAIA_CN:0] nSEI; // System Error Interrupt + input [`MAIA_CN:0] nREI; // RAM Error Interrupt + input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request + input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request + input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt + +// BEGIN NO-GIC pins + output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output +// END NO-GIC pins + input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers +// BEGIN NO-GIC pins + input GICCDISABLE; // Put GIC into bypass mode + input ICDTVALID; // Distrubuter AXI4 SP Message Valid + output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message + input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data + input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet + input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID + + output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid + input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message + output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data + output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet + output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID +// END NO-GIC pins +//----------------------------------------------------------------------------- +// Timer Signals +//----------------------------------------------------------------------------- + input [63:0] CNTVALUEB; // Counter value in binary + input CNTCLKEN; // Counter clock enable + output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event + output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event + output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event + output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event + +//----------------------------------------------------------------------------- +// Power Management Signals +//----------------------------------------------------------------------------- + input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) + output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) + input EVENTI; // Event input for processor wake-up from WFE state + output EVENTO; // Event output, signal is active when SEV instruction is executed + output [`MAIA_CN:0] STANDBYWFI; // WFI mode + output [`MAIA_CN:0] STANDBYWFE; // WFE mode + output STANDBYWFIL2; // WFI mode for L2 + output [`MAIA_CN:0] SMPEN; // CPU SMP bit + + output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE + input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn + output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn + output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY + + output L2QACTIVE; // L2 Q-channel QACTIVE + input L2QREQn; // L2 Q-channel QREQn + output L2QACCEPTn; // L2 Q-channel QACCEPTn + output L2QDENY; // L2 Q-channel QDENY + + input L2FLUSHREQ; // L2 hardware flush request + output L2FLUSHDONE; // L2 hardware flush done + +//----------------------------------------------------------------------------- +// Asynchronous Error Signals +//----------------------------------------------------------------------------- + output nINTERRIRQ; // L2 RAM dbl-bit ECC error + output nEXTERRIRQ; // Write transaction error + +//----------------------------------------------------------------------------- +// Bus Configuration Signals +//----------------------------------------------------------------------------- + input SYSBARDISABLE; // Disable broadcast of barriers + input BROADCASTINNER; // Extend Inner Shared Domain + input BROADCASTOUTER; // Extend Outer Shared Domain + input BROADCASTCACHEMAINT; // Broadcast cache maint ops + +//----------------------------------------------------------------------------- +// AMBA4 ACE Master (AXI with Coherency extensions) +//----------------------------------------------------------------------------- + input ACLKENM; // AXI Master clock enable + input ACINACTM; // ACE Snoop interface no longer active or accepting requests + +// Write Address channel signals + input AWREADYM; // Write Address ready (slave ready to accept write address) + output AWVALIDM; // Write Address valid + output [6:0] AWIDM; // Write Address ID + output [43:0] AWADDRM; // Write Address + output [7:0] AWLENM; // Write Burst Length + output [2:0] AWSIZEM; // Write Burst Size + output [1:0] AWBURSTM; // Write Burst type + output [1:0] AWBARM; // Barrier + output [1:0] AWDOMAINM; // Domain + output AWLOCKM; // Write Lock type + output [3:0] AWCACHEM; // Write Cache type + output [2:0] AWPROTM; // Write Protection type + output [2:0] AWSNOOPM; // Write Snoop Request type + output AWUNIQUEM; // Write Unique state + output [7:0] WRMEMATTR; // Write raw memory attributes + +// Write Data channel signals + input WREADYM; // Write Data ready (slave ready to accept data) + output WVALIDM; // Write Data valid + output [127:0] WDATAM; // Write Data + output [15:0] WSTRBM; // Write byte-lane strobes + output [6:0] WIDM; // Write id + output WLASTM; // Write Data last transfer indicator + +// Write Response channel signals + output BREADYM; // Write Response ready (master ready to accept response) + input BVALIDM; // Write Response Valid + input [6:0] BIDM; // Write Response ID + input [1:0] BRESPM; // Write Response + +// Read Address channel signals + input ARREADYM; // Read Address ready (slave ready to accept read address) + output ARVALIDM; // Read Address valid + output [6:0] ARIDM; // Read Address ID + output [43:0] ARADDRM; // Read Address + output [7:0] ARLENM; // Read Burst Length + output [2:0] ARSIZEM; // Read Burst Size + output [1:0] ARBURSTM; // Read Burst type + output [1:0] ARBARM; // Barrier + output [1:0] ARDOMAINM; // Domain + output ARLOCKM; // Read Lock type + output [3:0] ARCACHEM; // Read Cache type + output [2:0] ARPROTM; // Read Protection type + output [3:0] ARSNOOPM; // Read Snoop Request type + output [7:0] RDMEMATTR; // Read raw memory attributes + +// Read Data channel signals + output RREADYM; // Read Data ready (master ready to accept data) + input RVALIDM; // Read Data valid + input [6:0] RIDM; // Read Data ID + input [127:0] RDATAM; // Read Data + input [3:0] RRESPM; // Read Data response + input RLASTM; // Read Data last transfer indicator + +// Coherency Address channel signals + output ACREADYM; // master ready to accept snoop address + input ACVALIDM; // Snoop Address valid + input [43:0] ACADDRM; // Snoop Address + input [2:0] ACPROTM; // Snoop Protection type + input [3:0] ACSNOOPM; // Snoop Request type + +// Coherency Response channel signals + input CRREADYM; // slave ready to accept snoop response + output CRVALIDM; // Snoop Response valid + output [4:0] CRRESPM; // Snoop Response + +// Coherency Data handshake channel signals + input CDREADYM; // slave ready to accept snoop data + output CDVALIDM; // Snoop Data valid + output [127:0] CDDATAM; // Snoop Data + output CDLASTM; // Snoop Data last transfer indicator + +// Read/Write Acknowledge signals + output RACKM; // Read Acknowledge + output WACKM; // Write Acknowledge + +// BEGIN NO-ACP pins +//----------------------------------------------------------------------------- +// ACP AXI Slave +//----------------------------------------------------------------------------- + input ACLKENS; // AXI slave clock enable + input AINACTS; // AXI slave interface no longer active or accepting requests +// Write Address channel signals + output AWREADYS; // Write Address ready (slave ready to accept write address) + input AWVALIDS; // Write Address valid + input [4:0] AWIDS; // Write Address ID + input [43:0] AWADDRS; // Write Address + input [7:0] AWLENS; // Write Burst Length + input [3:0] AWCACHES; // Write Cache type + input [1:0] AWUSERS; // Write inner & outer shareability + input [2:0] AWPROTS; // Write Protection type + +// Write Data channel signals + output WREADYS; // Write Data ready (slave ready to accept data) + input WVALIDS; // Write Data valid + input [127:0] WDATAS; // Write Data + input [15:0] WSTRBS; // Write byte-lane strobes + input WLASTS; // Write Data last transfer indicator + +// Write Response channel signals + input BREADYS; // Write Response ready (master ready to accept response) + output BVALIDS; // Write Response Valid + output [4:0] BIDS; // Write Response ID tag + output [1:0] BRESPS; // Write Response + +// Read Address channel signals + output ARREADYS; // Read Address ready (slave ready to accept read address) + input ARVALIDS; // Read Address valid + input [4:0] ARIDS; // Read Address ID + input [43:0] ARADDRS; // Read Address + input [7:0] ARLENS; // Read Burst Length + input [3:0] ARCACHES; // Read Cache type + input [1:0] ARUSERS; // Read inner & outer shareability + input [2:0] ARPROTS; // Read Protection type + +// Read Data channel signals + input RREADYS; // Read Data ready (master ready to accept data) + output RVALIDS; // Read Data valid + output [4:0] RIDS; // Read Data ID + output [127:0] RDATAS; // Read Data + output [1:0] RRESPS; // Read Data response + output RLASTS; // Read Data last transfer indicator +// END NO-ACP pins +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (CLK) +//----------------------------------------------------------------------------- +// Debug CLK interface + input [43:12] DBGROMADDR; // Debug ROM base address + input DBGROMADDRV; // Debug ROM base address valid + + output [`MAIA_CN:0] DBGACK; // Debug acknowledge + output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt + output [`MAIA_CN:0] COMMRX; // Comms channel receive + output [`MAIA_CN:0] COMMTX; // Comms channel transmit + + output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request + output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request + + input DBGL1RSTDISABLE; // L1 DCache hardware reset disable + +// PMU CLK interface + output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request + output [24:0] PMUEVENT0; // PMU Event bus +// BEGIN INCLUDE FOR CPU1 + output [24:0] PMUEVENT1; // PMU Event bus +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + output [24:0] PMUEVENT2; // PMU Event bus +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + output [24:0] PMUEVENT3; // PMU Event bus +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (ATCLK) +//----------------------------------------------------------------------------- +// ETM ATB interface and Misc signals + input ATCLKEN; // ATB Clock Enable + input [63:0] TSVALUEB; // ATB Timestamp in binary + + input ATREADYM0; // ATDATA can be accepted + input AFVALIDM0; // ATB Fifo Flush Request + output [31:0] ATDATAM0; // ATB Data + output ATVALIDM0; // ATB Data Valid + output [1:0] ATBYTESM0; // ATB Data Size + output AFREADYM0; // ATB Fifo Flush Finished + output [6:0] ATIDM0; // ATB Trace Source ID + input SYNCREQM0; // ATB External synchronization request + +// BEGIN INCLUDE FOR CPU1 + input ATREADYM1; // ATDATA can be accepted + input AFVALIDM1; // ATB Fifo Flush Request + output [31:0] ATDATAM1; // ATB Data + output ATVALIDM1; // ATB Data Valid + output [1:0] ATBYTESM1; // ATB Data Size + output AFREADYM1; // ATB Fifo Flush Finished + output [6:0] ATIDM1; // ATB Trace Source ID + input SYNCREQM1; // ATB External synchronization request +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ATREADYM2; // ATDATA can be accepted + input AFVALIDM2; // ATB Fifo Flush Request + output [31:0] ATDATAM2; // ATB Data + output ATVALIDM2; // ATB Data Valid + output [1:0] ATBYTESM2; // ATB Data Size + output AFREADYM2; // ATB Fifo Flush Finished + output [6:0] ATIDM2; // ATB Trace Source ID + input SYNCREQM2; // ATB External synchronization request +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ATREADYM3; // ATDATA can be accepted + input AFVALIDM3; // ATB Fifo Flush Request + output [31:0] ATDATAM3; // ATB Data + output ATVALIDM3; // ATB Data Valid + output [1:0] ATBYTESM3; // ATB Data Size + output AFREADYM3; // ATB Fifo Flush Finished + output [6:0] ATIDM3; // ATB Trace Source ID + input SYNCREQM3; // ATB External synchronization request +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (PCLK) +//----------------------------------------------------------------------------- +// Debug-APBv3 port (APB) + input PCLKDBG; // APB Clock + input PCLKENDBG; // APB Clock Enable + input nPRESETDBG; // APB Reset + input PSELDBG; // Debug bus access + input [21:2] PADDRDBG; // APB address + input PADDRDBG31; // APB address bit[31] + input PENABLEDBG; // APB transfer complete flag + input PWRITEDBG; // APB read/write indicator + input [31:0] PWDATADBG; // APB write data + output [31:0] PRDATADBG; // APB read data + output PREADYDBG; // APB slave ready, used to extend a transfer + output PSLVERRDBG; // APB slave transfer error + +// Misc interface + input [`MAIA_CN:0] EDBGRQ; // External debug request + +// PMU Snapshot interface + input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request + output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge + +// Power-related interface + input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status + output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request + +// CTI interface + input [3:0] CTICHIN; // Channel In + input [3:0] CTICHOUTACK; // Channel Out acknowledge + output [3:0] CTICHOUT; // Channel Out + output [3:0] CTICHINACK; // Channel In acknowledge + input CISBYPASS; // Channel interface sync bypass + input [3:0] CIHSBYPASS; // Channel interface H/S bypass + output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt + input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge + +//----------------------------------------------------------------------------- +// Debug Authentication Interface (CLK & PCLK) +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] DBGEN; // Invasive debug enable + input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable + input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable + input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable + +//----------------------------------------------------------------------------- +// DFT Signals +//----------------------------------------------------------------------------- + input DFTSE; // Scan enable + input DFTRSTDISABLE; // Disable reset to cells during scan shift + input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr + input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 + input DFTRAMHOLD; // Holds data in RAMs + input DFTCLKBYPASS; // L2 RAM strobe clock bypass + input DFTMCPHOLD; // Disable multi-cycle RAM paths + +//----------------------------------------------------------------------------- +// MBIST Interface +//----------------------------------------------------------------------------- + input nMBISTRESET; // MBIST reset + input MBISTREQ; // MBIST mode request + +//----------------------------------------------------------------------------- +// Signals from maia -> maia_cpu_io -> maia_cpu +//----------------------------------------------------------------------------- +// Outputs to maia_cpu + output ncpuporeset_cpu0_o; + output ncorereset_cpu0_o; + + output cfgend_cpu0_o; + output cfgte_cpu0_o; + output cp15sdisable_cpu0_o; + output vinithi_cpu0_o; + output [7:0] clusteridaff1_cpu0_o; + output [7:0] clusteridaff2_cpu0_o; + output [1:0] cpuid_cpu0_o; + output aa64naa32_cpu0_o; + output [43:2] rvbaraddr_cpu0_o; + output cryptodisable_cpu0_o; + output giccdisable_cpu0_o; + + output [43:12] dbgromaddr_cpu0_o; + output dbgromaddrv_cpu0_o; + output dbgl1rstdisable_cpu0_o; + + output dbgen_cpu0_o; + output niden_cpu0_o; + output spiden_cpu0_o; + output spniden_cpu0_o; + + output [63:0] tsvalueb_cpu0_o; + + output atclken_cpu0_o; + output afvalidm_cpu0_o; + output atreadym_cpu0_o; + output syncreqm_cpu0_o; + + output dftse_cpu0_o; + output dftrstdisable_cpu0_o; + output dftcrclkdisable_cpu0_o; + output dftramhold_cpu0_o; + output nmbistreset_cpu0_o; + +// BEGIN INCLUDE FOR CPU1 + output ncpuporeset_cpu1_o; + output ncorereset_cpu1_o; + + output cfgend_cpu1_o; + output cfgte_cpu1_o; + output cp15sdisable_cpu1_o; + output vinithi_cpu1_o; + output [7:0] clusteridaff1_cpu1_o; + output [7:0] clusteridaff2_cpu1_o; + output [1:0] cpuid_cpu1_o; + output aa64naa32_cpu1_o; + output [43:2] rvbaraddr_cpu1_o; + output cryptodisable_cpu1_o; + output giccdisable_cpu1_o; + + output [43:12] dbgromaddr_cpu1_o; + output dbgromaddrv_cpu1_o; + output dbgl1rstdisable_cpu1_o; + + output dbgen_cpu1_o; + output niden_cpu1_o; + output spiden_cpu1_o; + output spniden_cpu1_o; + + output [63:0] tsvalueb_cpu1_o; + + output atclken_cpu1_o; + output afvalidm_cpu1_o; + output atreadym_cpu1_o; + output syncreqm_cpu1_o; + + output dftse_cpu1_o; + output dftrstdisable_cpu1_o; + output dftcrclkdisable_cpu1_o; + output dftramhold_cpu1_o; + output nmbistreset_cpu1_o; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + output ncpuporeset_cpu2_o; + output ncorereset_cpu2_o; + + output cfgend_cpu2_o; + output cfgte_cpu2_o; + output cp15sdisable_cpu2_o; + output vinithi_cpu2_o; + output [7:0] clusteridaff1_cpu2_o; + output [7:0] clusteridaff2_cpu2_o; + output [1:0] cpuid_cpu2_o; + output aa64naa32_cpu2_o; + output [43:2] rvbaraddr_cpu2_o; + output cryptodisable_cpu2_o; + output giccdisable_cpu2_o; + + output [43:12] dbgromaddr_cpu2_o; + output dbgromaddrv_cpu2_o; + output dbgl1rstdisable_cpu2_o; + + output dbgen_cpu2_o; + output niden_cpu2_o; + output spiden_cpu2_o; + output spniden_cpu2_o; + + output [63:0] tsvalueb_cpu2_o; + + output atclken_cpu2_o; + output afvalidm_cpu2_o; + output atreadym_cpu2_o; + output syncreqm_cpu2_o; + + output dftse_cpu2_o; + output dftrstdisable_cpu2_o; + output dftcrclkdisable_cpu2_o; + output dftramhold_cpu2_o; + output nmbistreset_cpu2_o; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + output ncpuporeset_cpu3_o; + output ncorereset_cpu3_o; + + output cfgend_cpu3_o; + output cfgte_cpu3_o; + output cp15sdisable_cpu3_o; + output vinithi_cpu3_o; + output [7:0] clusteridaff1_cpu3_o; + output [7:0] clusteridaff2_cpu3_o; + output [1:0] cpuid_cpu3_o; + output aa64naa32_cpu3_o; + output [43:2] rvbaraddr_cpu3_o; + output cryptodisable_cpu3_o; + output giccdisable_cpu3_o; + + output [43:12] dbgromaddr_cpu3_o; + output dbgromaddrv_cpu3_o; + output dbgl1rstdisable_cpu3_o; + + output dbgen_cpu3_o; + output niden_cpu3_o; + output spiden_cpu3_o; + output spniden_cpu3_o; + + output [63:0] tsvalueb_cpu3_o; + + output atclken_cpu3_o; + output afvalidm_cpu3_o; + output atreadym_cpu3_o; + output syncreqm_cpu3_o; + + output dftse_cpu3_o; + output dftrstdisable_cpu3_o; + output dftcrclkdisable_cpu3_o; + output dftramhold_cpu3_o; + output nmbistreset_cpu3_o; +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Signals from maia_cpu -> maia_cpu_io -> maia +//----------------------------------------------------------------------------- +// Inputs from maia_cpu + input ds_cpu0_sev_req; + input ds_cpu0_sevl_req; + input ds_cpu0_cpuectlr_smp; + + input ncommirq_cpu0_i; + input commrx_cpu0_i; + input commtx_cpu0_i; + input dbgack_cpu0_i; + input dbgrstreq_cpu0_i; + input dbgnopwrdwn_cpu0_i; + + input npmuirq_cpu0_i; + input [24:0] pmuevent_cpu0_i; + input pm_export_cpu0_i; + + input etclken_cpu0_i; + input afreadym_cpu0_i; + input [1:0] atbytesm_cpu0_i; + input [31:0] atdatam_cpu0_i; + input [6:0] atidm_cpu0_i; + input atvalidm_cpu0_i; + +// BEGIN INCLUDE FOR CPU1 + input ds_cpu1_sev_req; + input ds_cpu1_sevl_req; + input ds_cpu1_cpuectlr_smp; + + input ncommirq_cpu1_i; + input commrx_cpu1_i; + input commtx_cpu1_i; + input dbgack_cpu1_i; + input dbgrstreq_cpu1_i; + input dbgnopwrdwn_cpu1_i; + + input npmuirq_cpu1_i; + input [24:0] pmuevent_cpu1_i; + input pm_export_cpu1_i; + + input etclken_cpu1_i; + input afreadym_cpu1_i; + input [1:0] atbytesm_cpu1_i; + input [31:0] atdatam_cpu1_i; + input [6:0] atidm_cpu1_i; + input atvalidm_cpu1_i; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ds_cpu2_sev_req; + input ds_cpu2_sevl_req; + input ds_cpu2_cpuectlr_smp; + + input ncommirq_cpu2_i; + input commrx_cpu2_i; + input commtx_cpu2_i; + input dbgack_cpu2_i; + input dbgrstreq_cpu2_i; + input dbgnopwrdwn_cpu2_i; + + input npmuirq_cpu2_i; + input [24:0] pmuevent_cpu2_i; + input pm_export_cpu2_i; + + input etclken_cpu2_i; + input afreadym_cpu2_i; + input [1:0] atbytesm_cpu2_i; + input [31:0] atdatam_cpu2_i; + input [6:0] atidm_cpu2_i; + input atvalidm_cpu2_i; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ds_cpu3_sev_req; + input ds_cpu3_sevl_req; + input ds_cpu3_cpuectlr_smp; + + input ncommirq_cpu3_i; + input commrx_cpu3_i; + input commtx_cpu3_i; + input dbgack_cpu3_i; + input dbgrstreq_cpu3_i; + input dbgnopwrdwn_cpu3_i; + + input npmuirq_cpu3_i; + input [24:0] pmuevent_cpu3_i; + input pm_export_cpu3_i; + + input etclken_cpu3_i; + input afreadym_cpu3_i; + input [1:0] atbytesm_cpu3_i; + input [31:0] atdatam_cpu3_i; + input [6:0] atidm_cpu3_i; + input atvalidm_cpu3_i; +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// L2 interface +//----------------------------------------------------------------------------- + output [12:0] l2_cpu0_mbist1_addr_b1; + output [3:0] l2_cpu0_mbist1_array_b1; + output [7:0] l2_cpu0_mbist1_be_b1; + output l2_cpu0_mbist1_en_b1; + output l2_cpu0_mbist1_rd_en_b1; + output l2_cpu0_mbist1_wr_en_b1; + output l2_cpu0_mbist1_all_b1; + +// BEGIN INCLUDE FOR CPU1 + output [12:0] l2_cpu1_mbist1_addr_b1; + output [3:0] l2_cpu1_mbist1_array_b1; + output [7:0] l2_cpu1_mbist1_be_b1; + output l2_cpu1_mbist1_en_b1; + output l2_cpu1_mbist1_rd_en_b1; + output l2_cpu1_mbist1_wr_en_b1; + output l2_cpu1_mbist1_all_b1; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + output [12:0] l2_cpu2_mbist1_addr_b1; + output [3:0] l2_cpu2_mbist1_array_b1; + output [7:0] l2_cpu2_mbist1_be_b1; + output l2_cpu2_mbist1_en_b1; + output l2_cpu2_mbist1_rd_en_b1; + output l2_cpu2_mbist1_wr_en_b1; + output l2_cpu2_mbist1_all_b1; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + output [12:0] l2_cpu3_mbist1_addr_b1; + output [3:0] l2_cpu3_mbist1_array_b1; + output [7:0] l2_cpu3_mbist1_be_b1; + output l2_cpu3_mbist1_en_b1; + output l2_cpu3_mbist1_rd_en_b1; + output l2_cpu3_mbist1_wr_en_b1; + output l2_cpu3_mbist1_all_b1; +// END INCLUDE FOR CPU3 + +// BEGIN L2-CPU interface + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + output l2_cpu0_cfg_ecc_en; + output l2_cpu0_arb_thrshld_timeout_en; + output l2_cpu0_disable_clean_evict_opt; + output l2_cpu0_dext_err_r2; // LS external error + output l2_cpu0_dext_err_type_r2; // LS external error type + output l2_cpu0_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu0_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu0_ddata_r2; // LS read data + output l2_cpu0_barrier_done; // LS barrier complete + output l2_cpu0_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu0_spec_bufid; // LS read speculative response buffer id + output l2_cpu0_rvalid; // LS read response valid + output [1:0] l2_cpu0_rstate; // LS read response state + output l2_cpu0_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu0_rbufid; // LS read response buffer id + output l2_cpu0_dvalid_r1; // LS read data valid + output l2_cpu0_dlast_r1; // LS read last indicator + output [2:0] l2_cpu0_dbufid_r1; // LS read data fill buffer id + output l2_cpu0_iext_err_r2; // IF external error + output l2_cpu0_iext_err_type_r2; // IF external error type + output l2_cpu0_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu0_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu0_idata_r2; // IF read data + output l2_cpu0_ivalid_r1; // IF read data valid + output [1:0] l2_cpu0_ibufid_r1; // IF read data fill buffer id + output l2_cpu0_ls_sync_req; // LS sync req + output [48:0] l2_cpu0_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu0_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu0_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu0_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu0_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu0_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu0_ccb_req_info_c3; // LS ccb req info + output l2_cpu0_if_ccb_clken_c3; // IF ccb clken + output l2_cpu0_if_ccb_req_c3; // IF ccb req + output l2_cpu0_if_sync_req; // IF sync req + output l2_cpu0_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu0_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu0_tlb_sync_req; // TLB sync req + output l2_cpu0_tlb_sync_complete; // TLB sync complete + output l2_cpu0_tbw_desc_vld; // TBW descriptor valid + output l2_cpu0_tbw_ext_err; // TBW descriptor external error + output l2_cpu0_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu0_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu0_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu0_spr_rd_data; // DS spr read data + output [1:0] l2_cpu0_l2_cache_size; // DS L2 cache size + output l2_cpu0_pf_throttle_q; // PF throttling + + output l2_cpu0_wr_ex_resp; // store exclusive response + output l2_cpu0_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu0_ic_base; // PERIPHBASE + output l2_cpu0_no_intctrl; // INTCTLR not present + + + output [33:0] l2_cpu0_pmu_events; // L2 PMU events + + input ds_cpu0_l2_spr_en; // cpu0 early spr req for clk enables + input ds_cpu0_l2_spr_rd; // cpu0 spr read op + input ds_cpu0_l2_spr_wr; // cpu0 spr write op + input [8:0] ds_cpu0_l2_spr_addr; // cpu0 spr address + input ds_cpu0_l2_spr_dw; // cpu0 spr access dw + input [63:0] ds_cpu0_l2_spr_wr_data; // cpu0 spr write data + + input l2_cpu0_wr_data_vld_x1_q; // cpu0 write data vld x1 stage + input l2_cpu0_wr_evict_x1_q; // cpu0 write evict x1 stage + input [143:0] l2_cpu0_wr_data; + input l2_cpu0_ls_rd_haz_vld_arb_q; + input l2_cpu0_ls_wr_haz_vld_arb_q; + input l2_cpu0_dt_pmu_evt_en; // PMU enabled. + + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + output l2_cpu1_cfg_ecc_en; + output l2_cpu1_arb_thrshld_timeout_en; + output l2_cpu1_disable_clean_evict_opt; + output l2_cpu1_dext_err_r2; // LS external error + output l2_cpu1_dext_err_type_r2; // LS external error type + output l2_cpu1_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu1_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu1_ddata_r2; // LS read data + output l2_cpu1_barrier_done; // LS barrier complete + output l2_cpu1_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu1_spec_bufid; // LS read speculative response buffer id + output l2_cpu1_rvalid; // LS read response valid + output [1:0] l2_cpu1_rstate; // LS read response state + output l2_cpu1_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu1_rbufid; // LS read response buffer id + output l2_cpu1_dvalid_r1; // LS read data valid + output l2_cpu1_dlast_r1; // LS read last indicator + output [2:0] l2_cpu1_dbufid_r1; // LS read data fill buffer id + output l2_cpu1_iext_err_r2; // IF external error + output l2_cpu1_iext_err_type_r2; // IF external error type + output l2_cpu1_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu1_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu1_idata_r2; // IF read data + output l2_cpu1_ivalid_r1; // IF read data valid + output [1:0] l2_cpu1_ibufid_r1; // IF read data fill buffer id + output l2_cpu1_ls_sync_req; // LS sync req + output [48:0] l2_cpu1_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu1_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu1_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu1_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu1_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu1_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu1_ccb_req_info_c3; // LS ccb req info + output l2_cpu1_if_ccb_clken_c3; // IF ccb clken + output l2_cpu1_if_ccb_req_c3; // IF ccb req + output l2_cpu1_if_sync_req; // IF sync req + output l2_cpu1_tlb_ccb_clken_c3; // IF ccb clken + output l2_cpu1_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu1_tlb_sync_req; // TLB sync req + output l2_cpu1_tlb_sync_complete; // TLB sync complete + output l2_cpu1_tbw_desc_vld; // TBW descriptor valid + output l2_cpu1_tbw_ext_err; // TBW descriptor external error + output l2_cpu1_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu1_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu1_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu1_spr_rd_data; // DS spr read data + output [1:0] l2_cpu1_l2_cache_size; // DS L2 cache size + output l2_cpu1_pf_throttle_q; // PF throttling + + output l2_cpu1_wr_ex_resp; // store exclusive response + output l2_cpu1_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu1_ic_base; // PERIPHBASE + output l2_cpu1_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu1_pmu_events; // L2 PMU events + + input ds_cpu1_l2_spr_en; // cpu1 early spr req for clk enables + input ds_cpu1_l2_spr_rd; // cpu1 spr read op + input ds_cpu1_l2_spr_wr; // cpu1 spr write op + input [8:0] ds_cpu1_l2_spr_addr; // cpu1 spr address + input ds_cpu1_l2_spr_dw; // cpu1 spr access dw + input [63:0] ds_cpu1_l2_spr_wr_data; // cpu1 spr write data + + input l2_cpu1_wr_data_vld_x1_q; // cpu1 write data vld x1 stage + input l2_cpu1_wr_evict_x1_q; // cpu1 write evict x1 stage + input [143:0] l2_cpu1_wr_data; + input l2_cpu1_ls_rd_haz_vld_arb_q; + input l2_cpu1_ls_wr_haz_vld_arb_q; + input l2_cpu1_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + output l2_cpu2_cfg_ecc_en; + output l2_cpu2_arb_thrshld_timeout_en; + output l2_cpu2_disable_clean_evict_opt; + output l2_cpu2_dext_err_r2; // LS external error + output l2_cpu2_dext_err_type_r2; // LS external error type + output l2_cpu2_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu2_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu2_ddata_r2; // LS read data + output l2_cpu2_barrier_done; // LS barrier complete + output l2_cpu2_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu2_spec_bufid; // LS read speculative response buffer id + output l2_cpu2_rvalid; // LS read response valid + output [1:0] l2_cpu2_rstate; // LS read response state + output l2_cpu2_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu2_rbufid; // LS read response buffer id + output l2_cpu2_dvalid_r1; // LS read data valid + output l2_cpu2_dlast_r1; // LS read last indicator + output [2:0] l2_cpu2_dbufid_r1; // LS read data fill buffer id + output l2_cpu2_iext_err_r2; // IF external error + output l2_cpu2_iext_err_type_r2; // IF external error type + output l2_cpu2_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu2_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu2_idata_r2; // IF read data + output l2_cpu2_ivalid_r1; // IF read data valid + output [1:0] l2_cpu2_ibufid_r1; // IF read data fill buffer id + output l2_cpu2_ls_sync_req; // LS sync req + output [48:0] l2_cpu2_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu2_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu2_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu2_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu2_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu2_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu2_ccb_req_info_c3; // LS ccb req info + output l2_cpu2_if_ccb_clken_c3; // IF ccb clken + output l2_cpu2_if_ccb_req_c3; // IF ccb req + output l2_cpu2_if_sync_req; // IF sync req + output l2_cpu2_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu2_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu2_tlb_sync_req; // TLB sync req + output l2_cpu2_tlb_sync_complete; // TLB sync complete + output l2_cpu2_tbw_desc_vld; // TBW descriptor valid + output l2_cpu2_tbw_ext_err; // TBW descriptor external error + output l2_cpu2_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu2_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu2_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu2_spr_rd_data; // DS spr read data + output [1:0] l2_cpu2_l2_cache_size; // DS L2 cache size + output l2_cpu2_pf_throttle_q; // PF throttling + + output l2_cpu2_wr_ex_resp; // store exclusive response + output l2_cpu2_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu2_ic_base; // PERIPHBASE + output l2_cpu2_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu2_pmu_events; // L2 PMU events + + input ds_cpu2_l2_spr_en; // cpu2 early spr req for clk enables + input ds_cpu2_l2_spr_rd; // cpu2 spr read op + input ds_cpu2_l2_spr_wr; // cpu2 spr write op + input [8:0] ds_cpu2_l2_spr_addr; // cpu2 spr address + input ds_cpu2_l2_spr_dw; // cpu2 spr access dw + input [63:0] ds_cpu2_l2_spr_wr_data; // cpu2 spr write data + + input l2_cpu2_wr_data_vld_x1_q; // cpu2 write data vld x1 stage + input l2_cpu2_wr_evict_x1_q; // cpu2 write evict x1 stage + input [143:0] l2_cpu2_wr_data; + input l2_cpu2_ls_rd_haz_vld_arb_q; + input l2_cpu2_ls_wr_haz_vld_arb_q; + input l2_cpu2_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + output l2_cpu3_cfg_ecc_en; + output l2_cpu3_arb_thrshld_timeout_en; + output l2_cpu3_disable_clean_evict_opt; + output l2_cpu3_dext_err_r2; // LS external error + output l2_cpu3_dext_err_type_r2; // LS external error type + output l2_cpu3_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu3_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu3_ddata_r2; // LS read data + output l2_cpu3_barrier_done; // LS barrier complete + output l2_cpu3_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu3_spec_bufid; // LS read speculative response buffer id + output l2_cpu3_rvalid; // LS read response valid + output [1:0] l2_cpu3_rstate; // LS read response state + output l2_cpu3_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu3_rbufid; // LS read response buffer id + output l2_cpu3_dvalid_r1; // LS read data valid + output l2_cpu3_dlast_r1; // LS read last indicator + output [2:0] l2_cpu3_dbufid_r1; // LS read data fill buffer id + output l2_cpu3_iext_err_r2; // IF external error + output l2_cpu3_iext_err_type_r2; // IF external error type + output l2_cpu3_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu3_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu3_idata_r2; // IF read data + output l2_cpu3_ivalid_r1; // IF read data valid + output [1:0] l2_cpu3_ibufid_r1; // IF read data fill buffer id + output l2_cpu3_ls_sync_req; // LS sync req + output [48:0] l2_cpu3_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu3_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu3_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu3_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu3_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu3_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu3_ccb_req_info_c3; // LS ccb req info + output l2_cpu3_if_ccb_clken_c3; // IF ccb clken + output l2_cpu3_if_ccb_req_c3; // IF ccb req + output l2_cpu3_if_sync_req; // IF sync req + output l2_cpu3_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu3_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu3_tlb_sync_req; // TLB sync req + output l2_cpu3_tlb_sync_complete; // TLB sync complete + output l2_cpu3_tbw_desc_vld; // TBW descriptor valid + output l2_cpu3_tbw_ext_err; // TBW descriptor external error + output l2_cpu3_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu3_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu3_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu3_spr_rd_data; // DS spr read data + output [1:0] l2_cpu3_l2_cache_size; // DS L2 cache size + output l2_cpu3_pf_throttle_q; // PF throttling + + output l2_cpu3_wr_ex_resp; // store exclusive response + output l2_cpu3_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu3_ic_base; // PERIPHBASE + output l2_cpu3_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu3_pmu_events; // L2 PMU events + + input ds_cpu3_l2_spr_en; // cpu3 early spr req for clk enables + input ds_cpu3_l2_spr_rd; // cpu3 spr read op + input ds_cpu3_l2_spr_wr; // cpu3 spr write op + input [8:0] ds_cpu3_l2_spr_addr; // cpu3 spr address + input ds_cpu3_l2_spr_dw; // cpu3 spr access dw + input [63:0] ds_cpu3_l2_spr_wr_data; // cpu3 spr write data + + input l2_cpu3_wr_data_vld_x1_q; // cpu3 write data vld x1 stage + input l2_cpu3_wr_evict_x1_q; // cpu3 write evict x1 stage + input [143:0] l2_cpu3_wr_data; + input l2_cpu3_ls_rd_haz_vld_arb_q; + input l2_cpu3_ls_wr_haz_vld_arb_q; + input l2_cpu3_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// tag_pipe / cpu slave +//----------------------------------------------------------------------------- + output l2_cpu0_flsh_ls_rd_l2_dly; // cpu0 ls local hazard flush + output l2_cpu0_flsh_ls_wr_l2_dly; // cpu0 ls local hazard flush + + output l2_cpu0_wr_data_stall; // cpu0 write data stall + + output l2_cpu1_flsh_ls_rd_l2_dly; // cpu1 ls local hazard flush + output l2_cpu1_flsh_ls_wr_l2_dly; // cpu1 ls local hazard flush + + output l2_cpu1_wr_data_stall; // cpu1 write data stall + + output l2_cpu2_flsh_ls_rd_l2_dly; // cpu2 ls local hazard flush + output l2_cpu2_flsh_ls_wr_l2_dly; // cpu2 ls local hazard flush + + output l2_cpu2_wr_data_stall; // cpu2 write data stall + + output l2_cpu3_flsh_ls_rd_l2_dly; // cpu3 ls local hazard flush + output l2_cpu3_flsh_ls_wr_l2_dly; // cpu3 ls local hazard flush + + output l2_cpu3_wr_data_stall; // cpu3 write data stall + + output [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; // cpu0 ls id local hazard flush + output [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; // cpu0 ls id local hazard flush + + output [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; // cpu1 ls id local hazard flush + output [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; // cpu1 ls id local hazard flush + + output [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; // cpu2 ls id local hazard flush + output [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; // cpu2 ls id local hazard flush + + output [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; // cpu3 ls id local hazard flush + output [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; // cpu3 ls id local hazard flush + + output l2_cpu0_flsh_ls_rd_l4_dly; // cpu0 ls global hazard flush + output l2_cpu0_flsh_if_rd_l4_dly; // cpu0 if global hazard flush + output l2_cpu0_flsh_tw_rd_l4_dly; // cpu0 tw global hazard flush + output l2_cpu0_flsh_ls_wr_l4_dly; // cpu0 ls global hazard flush + + output l2_cpu1_flsh_ls_rd_l4_dly; // cpu1 ls global hazard flush + output l2_cpu1_flsh_if_rd_l4_dly; // cpu1 if global hazard flush + output l2_cpu1_flsh_tw_rd_l4_dly; // cpu1 tw global hazard flush + output l2_cpu1_flsh_ls_wr_l4_dly; // cpu1 ls global hazard flush + + output l2_cpu2_flsh_ls_rd_l4_dly; // cpu2 ls global hazard flush + output l2_cpu2_flsh_if_rd_l4_dly; // cpu2 if global hazard flush + output l2_cpu2_flsh_tw_rd_l4_dly; // cpu2 tw global hazard flush + output l2_cpu2_flsh_ls_wr_l4_dly; // cpu2 ls global hazard flush + + output l2_cpu3_flsh_ls_rd_l4_dly; // cpu3 ls global hazard flush + output l2_cpu3_flsh_if_rd_l4_dly; // cpu3 if global hazard flush + output l2_cpu3_flsh_tw_rd_l4_dly; // cpu3 tw global hazard flush + output l2_cpu3_flsh_ls_wr_l4_dly; // cpu3 ls global hazard flush + + output [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; // cpu0 ls id global hazard flush + output [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; // cpu0 if id global hazard flush + output [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; // cpu0 ls id global hazard flush + output l2_cpu0_flsh_ls_wr_evict_l4_dly; // cpu0 ls evict hazard + + output [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; // cpu1 ls id global hazard flush + output [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; // cpu1 if id global hazard flush + output [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; // cpu1 ls id global hazard flush + output l2_cpu1_flsh_ls_wr_evict_l4_dly; // cpu1 ls evict hazard + + output [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; // cpu2 ls id global hazard flush + output [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; // cpu2 if id global hazard flush + output [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; // cpu2 ls id global hazard flush + output l2_cpu2_flsh_ls_wr_evict_l4_dly; // cpu2 ls evict hazard + + output [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; // cpu3 ls id global hazard flush + output [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; // cpu3 if id global hazard flush + output [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; // cpu3 ls id global hazard flush + output l2_cpu3_flsh_ls_wr_evict_l4_dly; // cpu3 ls evict hazard + + output l2_cpu0_lrq_haz_pending; // cpu0 lrq hazard pending + output l2_cpu1_lrq_haz_pending; // cpu1 lrq hazard pending + output l2_cpu2_lrq_haz_pending; // cpu2 lrq hazard pending + output l2_cpu3_lrq_haz_pending; // cpu3 lrq hazard pending + + output l2_cpu0_ifq_haz_pending; // cpu0 ifq hazard pending + output l2_cpu1_ifq_haz_pending; // cpu1 ifq hazard pending + output l2_cpu2_ifq_haz_pending; // cpu2 ifq hazard pending + output l2_cpu3_ifq_haz_pending; // cpu3 ifq hazard pending + + output l2_cpu0_trq_haz_pending; // cpu0 trq hazard pending + output l2_cpu1_trq_haz_pending; // cpu1 trq hazard pending + output l2_cpu2_trq_haz_pending; // cpu2 trq hazard pending + output l2_cpu3_trq_haz_pending; // cpu3 trq hazard pending + + output l2_cpu0_wrq_haz_pending; // cpu0 wrq hazard pending + output l2_cpu1_wrq_haz_pending; // cpu1 wrq hazard pending + output l2_cpu2_wrq_haz_pending; // cpu2 wrq hazard pending + output l2_cpu3_wrq_haz_pending; // cpu3 wrq hazard pending + + output l2_cpu0_idle_block_reqs_q; // cpu0 idle block requests + output l2_cpu1_idle_block_reqs_q; // cpu1 idle block requests + output l2_cpu2_idle_block_reqs_q; // cpu2 idle block requests + output l2_cpu3_idle_block_reqs_q; // cpu3 idle block requests + + output l2_cpu0_ls_peq_coll_l4_dly; // cpu0 peq collision detected + output l2_cpu1_ls_peq_coll_l4_dly; // cpu1 peq collision detected + output l2_cpu2_ls_peq_coll_l4_dly; // cpu2 peq collision detected + output l2_cpu3_ls_peq_coll_l4_dly; // cpu3 peq collision detected + +//----------------------------------------------------------------------------- +// tag_pipe +//----------------------------------------------------------------------------- + output [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; // tbnk0 clear cpu0 lrq entry + output [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; // tbnk0 clear cpu1 lrq entry + output [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; // tbnk0 clear cpu2 lrq entry + output [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; // tbnk0 clear cpu3 lrq entry + + output [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; // tbnk1 clear cpu0 lrq entry + output [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; // tbnk1 clear cpu1 lrq entry + output [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; // tbnk1 clear cpu2 lrq entry + output [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; // tbnk1 clear cpu3 lrq entry + + output [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; // tbnk0 clear cpu0 ifq entry + output [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; // tbnk0 clear cpu1 ifq entry + output [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; // tbnk0 clear cpu2 ifq entry + output [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; // tbnk0 clear cpu3 ifq entry + + output [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; // tbnk1 clear cpu0 ifq entry + output [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; // tbnk1 clear cpu1 ifq entry + output [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; // tbnk1 clear cpu2 ifq entry + output [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; // tbnk1 clear cpu3 ifq entry + + output l2_tbnk0_cpu0_trq_clr_l4_dly2_q; // tbnk0 clear cpu0 trq entry + output l2_tbnk0_cpu1_trq_clr_l4_dly2_q; // tbnk0 clear cpu1 trq entry + output l2_tbnk0_cpu2_trq_clr_l4_dly2_q; // tbnk0 clear cpu2 trq entry + output l2_tbnk0_cpu3_trq_clr_l4_dly2_q; // tbnk0 clear cpu3 trq entry + + output l2_tbnk1_cpu0_trq_clr_l4_dly2_q; // tbnk1 clear cpu0 trq entry + output l2_tbnk1_cpu1_trq_clr_l4_dly2_q; // tbnk1 clear cpu1 trq entry + output l2_tbnk1_cpu2_trq_clr_l4_dly2_q; // tbnk1 clear cpu2 trq entry + output l2_tbnk1_cpu3_trq_clr_l4_dly2_q; // tbnk1 clear cpu3 trq entry + + output [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; // tbnk0 clear cpu0 wrq entry + output [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; // tbnk0 clear cpu1 wrq entry + output [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; // tbnk0 clear cpu2 wrq entry + output [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; // tbnk0 clear cpu3 wrq entry + + output [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; // tbnk1 clear cpu0 wrq entry + output [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; // tbnk1 clear cpu1 wrq entry + output [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; // tbnk1 clear cpu2 wrq entry + output [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; // tbnk1 clear cpu3 wrq entry + + +//----------------------------------------------------------------------------- +// cpu_logic / cpu slave +//----------------------------------------------------------------------------- + output l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu0 ls rd flsh l4 active + output l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu0 wr rd flsh l4 active + + output l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu1 ls rd flsh l4 active + output l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu1 wr rd flsh l4 active + + output l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu2 ls rd flsh l4 active + output l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu2 wr rd flsh l4 active + + output l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu3 ls rd flsh l4 active + output l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu3 wr rd flsh l4 active + + +//----------------------------------------------------------------------------- +// feq / cpu slave +//----------------------------------------------------------------------------- + input [129:0] l2_cpu0_dsq_rd_data_q; // cpu0 wrq/dsq data + input [15:0] l2_cpu0_dsq_rd_byte_strb_q; // cpu0 wrq/dsq byte strobes + input [129:0] l2_cpu1_dsq_rd_data_q; // cpu1 wrq/dsq data + input [15:0] l2_cpu1_dsq_rd_byte_strb_q; // cpu1 wrq/dsq byte strobes + input [129:0] l2_cpu2_dsq_rd_data_q; // cpu2 wrq/dsq data + input [15:0] l2_cpu2_dsq_rd_byte_strb_q; // cpu2 wrq/dsq byte strobes + input [129:0] l2_cpu3_dsq_rd_data_q; // cpu3 wrq/dsq data + input [15:0] l2_cpu3_dsq_rd_byte_strb_q; // cpu3 wrq/dsq byte strobes + + output l2_cpu0_dsq_clr_vld_q; // cpu0 dsq clear wrq vld entry + output [3:0] l2_cpu0_dsq_clr_id_q; // cpu0 dsq clear wrq buffer id + output l2_cpu0_dsq_rd_en; // cpu0 dsq/wrq data enable + output l2_cpu0_dsq_rd_en_x2; // cpu0 dsq/wrq data enable x2 + output [3:0] l2_cpu0_dsq_rd_buf_id; // cpu0 dsq/wrq data select + output l2_cpu1_dsq_clr_vld_q; // cpu1 dsq clear wrq vld entry + output [3:0] l2_cpu1_dsq_clr_id_q; // cpu1 dsq clear wrq buffer id + output l2_cpu1_dsq_rd_en; // cpu1 dsq/wrq data enable + output l2_cpu1_dsq_rd_en_x2; // cpu1 dsq/wrq data enable x2 + output [3:0] l2_cpu1_dsq_rd_buf_id; // cpu1 dsq/wrq data select + output l2_cpu2_dsq_clr_vld_q; // cpu2 dsq clear wrq vld entry + output [3:0] l2_cpu2_dsq_clr_id_q; // cpu2 dsq clear wrq buffer id + output l2_cpu2_dsq_rd_en; // cpu2 dsq/wrq data enable + output l2_cpu2_dsq_rd_en_x2; // cpu2 dsq/wrq data enable x2 + output [3:0] l2_cpu2_dsq_rd_buf_id; // cpu2 dsq/wrq data select + output l2_cpu3_dsq_clr_vld_q; // cpu3 dsq clear wrq vld entry + output l2_cpu3_dsq_rd_en; // cpu3 dsq/wrq data enable + output l2_cpu3_dsq_rd_en_x2; // cpu3 dsq/wrq data enable x2 + output [3:0] l2_cpu3_dsq_clr_id_q; // cpu3 dsq clear wrq buffer id + output [3:0] l2_cpu3_dsq_rd_buf_id; // cpu3 dsq/wrq data select + +//----------------------------------------------------------------------------- +// arbitration +//----------------------------------------------------------------------------- + output l2_cpu0_rd_vld_skid; // cpu0 read skid buffer valid + output l2_cpu1_rd_vld_skid; // cpu1 read skid buffer valid + output l2_cpu2_rd_vld_skid; // cpu2 read skid buffer valid + output l2_cpu3_rd_vld_skid; // cpu3 read skid buffer valid + + output l2_cpu0_pf_rd_vld_skid_popped; // cpu0 pf read skid buffer popped + output l2_cpu1_pf_rd_vld_skid_popped; // cpu1 pf read skid buffer popped + output l2_cpu2_pf_rd_vld_skid_popped; // cpu2 pf read skid buffer popped + output l2_cpu3_pf_rd_vld_skid_popped; // cpu3 pf read skid buffer popped + + output l2_cpu0_rd_arb; // + output l2_cpu1_rd_arb; // + output l2_cpu2_rd_arb; // + output l2_cpu3_rd_arb; // + + output l2_cpu0_wr_vld_skid; // cpu0 write skid buffer valid + output l2_cpu1_wr_vld_skid; // cpu1 write skid buffer valid + output l2_cpu2_wr_vld_skid; // cpu2 write skid buffer valid + output l2_cpu3_wr_vld_skid; // cpu3 write skid buffer valid + + output l2_cpu0_wr_arb; // + output l2_cpu1_wr_arb; // + output l2_cpu2_wr_arb; // + output l2_cpu3_wr_arb; // + + output l2_cpu0_ic_vld_skid; // cpu0 peripheral (ic) skid buffer valid + output l2_cpu1_ic_vld_skid; // cpu1 peripheral (ic) skid buffer valid + output l2_cpu2_ic_vld_skid; // cpu2 peripheral (ic) skid buffer valid + output l2_cpu3_ic_vld_skid; // cpu3 peripheral (ic) skid buffer valid + + output l2_cpu0_ic_barrier_stall_q; // cpu0 (ic) barrier stall + output l2_cpu1_ic_barrier_stall_q; // cpu1 (ic) barrier stall + output l2_cpu2_ic_barrier_stall_q; // cpu2 (ic) barrier stall + output l2_cpu3_ic_barrier_stall_q; // cpu3 (ic) barrier stall + + output l2_cpu0_blk_non_evict_wr; // cpu0 block non-evict writes from arbitrating + output l2_cpu1_blk_non_evict_wr; // cpu1 block non-evict writes from arbitrating + output l2_cpu2_blk_non_evict_wr; // cpu2 block non-evict writes from arbitrating + output l2_cpu3_blk_non_evict_wr; // cpu3 block non-evict writes from arbitrating + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + input l2_cpu0_idle_wakeup_q; // cpu0 idle wakeup + input l2_cpu0_rd_arb_fast; // cpu0 read arbitration fast request + input [4:0] l2_cpu0_rd_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu0_rd_lrq_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu0_rd_type_arb_set; // cpu0 read arbitration type + input [2:0] l2_cpu0_rd_cache_attr_arb_set; // cpu0 read arbitration cache attributes + input [7:0] l2_cpu0_rd_page_attr_arb_set; // cpu0 read arbitration page attributes + input [2:0] l2_cpu0_rd_elem_size_arb_set; // cpu0 read arbitration element size + input l2_cpu0_rd_way_arb_set; // cpu0 read arbitration way + input l2_cpu0_rd_replayed_arb_set; // cpu0 read arbitration replayed + input l2_cpu0_rd_excl_arb_set; // cpu0 read arbitration exclusive + input l2_cpu0_rd_priv_arb_set; // cpu0 read arbitration priv + input [1:0] l2_cpu0_rd_shared_arb_set; // cpu0 read arbitration shared + input l2_cpu0_rd_va48_arb_set; // cpu0 read arbitration va48 + input l2_cpu0_rd_aarch64_arb_set; // cpu0 read arbitration aarch64 + input [15:8] l2_cpu0_rd_asid_arb_set; // cpu0 read arbitration asid + input l2_cpu0_rd_prfm_arb_set; // cpu0 read arbitration prfm + input [44:0] l2_cpu0_rd_addr_arb_set; // cpu0 read arbitration address + input l2_cpu0_rd_bypass_arb_set; // cpu0 read arbitration bypass + input l2_cpu0_rd_bypass_req_can_e5; // cpu0 read arbitration bypass cancelled request + input l2_cpu0_early_rd_reqe4_e5_q; // cpu0 read arbitration bypass cancelled request + input l2_cpu0_rd_bypass_way_e5; // cpu0 read arbitration bypass way + input [2:0] l2_cpu0_rd_bypass_bufid_e5; // cpu0 read arbitration bypass bufid + input [2:0] l2_cpu0_rd_bypass_lrq_id_e5; // cpu0 read arbitration bypass bufid + + input l2_cpu0_wr_arb_fast; // cpu0 write arbitration fast request + input [3:0] l2_cpu0_wr_id_arb_set; // cpu0 write arbitration id for 1st qw + input [3:0] l2_cpu0_wr_partial_dw_arb_set; // cpu0 write partial qw byte strobe indicator + input [2:0] l2_cpu0_wr_cache_attr_arb_set; // cpu0 write arbitration cache attributes + input [7:0] l2_cpu0_wr_page_attr_arb_set; // cpu0 write arbitration page attributes + input [2:0] l2_cpu0_wr_elem_size_arb_set; // cpu0 write arbitration element size + input [2:0] l2_cpu0_wr_type_arb_set; // cpu0 write arbitration type + input [11:0] l2_cpu0_wr_cl_id_arb_set; // cpu0 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu0_wr_priv_arb_set; // cpu0 write arbitration priv + input [1:0] l2_cpu0_wr_shared_arb_set; // cpu0 write arbitration shared + input l2_cpu0_wr_last_arb_set; // cpu0 write arbitration last + input l2_cpu0_wr_clean_evict_arb_set; // cpu0 write arbitration clean eviction + input l2_cpu0_wr_err_arb_set; // cpu0 write arbitration error + input l2_cpu0_wr_way_arb_set; // cpu0 write arbitration way + input l2_cpu0_wr_dirty_arb_set; // cpu0 write arbitration dirty + input l2_cpu0_wr_1st_replayed_arb_set; // cpu0 write arbitration 1st replay indicator + input [44:0] l2_cpu0_wr_addr_arb_set; // cpu0 write arbitration address + input l2_cpu0_ic_arb_fast; // cpu0 peripheral (ic) arbitration fast request + input [2:0] l2_cpu0_ic_id_arb_set; // cpu0 peripheral (ic) fill buffer id + input l2_cpu0_ic_write_arb_set; // cpu0 peripheral (ic) write indicator + input l2_cpu0_ic_excl_arb_set; // cpu0 peripheral (ic) exclusive indicator + input [2:0] l2_cpu0_ic_elem_size_arb_set; // cpu0 peripheral (ic) element size + input l2_cpu0_ic_ns_arb_set; // cpu0 peripheral (ic) non-secure + input [15:0] l2_cpu0_ic_addr_arb_set; // cpu0 peripheral (ic) address + input [31:0] l2_cpu0_ic_data_arb_set; // cpu0 peripheral (ic) write data + + input l2_cpu0_wrq_almost_full; // cpu0 wrq almost full indicator + + input l2_cpu0_ls_wr_req_w2a; // cpu0 ls write request + input l2_cpu0_ls_wr_last_w2a; // cpu0 ls last indicator + input l2_cpu0_ls_wr_dirty_w2a; // cpu0 ls dirty indicator + input l2_cpu0_ls_wr_err_w2a; // cpu0 ls error indicator + input [2:0] l2_cpu0_ls_wr_type_w2a; // cpu0 ls write type + input [4:0] l2_cpu0_ls_wr_ccb_id_w2a; // cpu0 ls ccb id + input [127:0] l2_cpu0_ls_wr_data_w2a; // cpu0 ls write data + + input l2_cpu0_ls_ccb_resp; // cpu0 ls ccb resp + input [4:0] l2_cpu0_ls_ccb_resp_id; // cpu0 ls ccb id + input l2_cpu0_ls_ccb_data_wr; // cpu0 ls ccb data xfer + + input l2_cpu0_if_ccb_resp; // cpu0 if ccb resp + input [4:0] l2_cpu0_if_ccb_resp_id; // cpu0 if ccb id + + input l2_cpu0_tw_ccb_resp; // cpu0 tw ccb resp + input [4:0] l2_cpu0_tw_ccb_resp_id; // cpu0 tw ccb id + + input l2_cpu0_if_sync_done_q; // cpu0 sync response + input l2_cpu0_tlb_sync_done_q; // cpu0 tlb sync response + + input [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; // cpu0 lrq clear hazard id + input [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; // cpu0 wrq clear hazard id + input [3:0] l2_cpu0_ls_rd_haz_id_arb_q; // cpu0 ls rd wrq hazard id + input [2:0] l2_cpu0_ls_wr_haz_id_arb_q; // cpu0 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + input l2_cpu1_idle_wakeup_q; // cpu1 idle wakeup + input l2_cpu1_rd_arb_fast; // cpu1 read arbitration fast request + input [4:0] l2_cpu1_rd_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu1_rd_lrq_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu1_rd_type_arb_set; // cpu1 read arbitration type + input [2:0] l2_cpu1_rd_cache_attr_arb_set; // cpu1 read arbitration cache attributes + input [7:0] l2_cpu1_rd_page_attr_arb_set; // cpu1 read arbitration page attributes + input [2:0] l2_cpu1_rd_elem_size_arb_set; // cpu1 read arbitration element size + input l2_cpu1_rd_way_arb_set; // cpu1 read arbitration way + input l2_cpu1_rd_replayed_arb_set; // cpu1 read arbitration replayed + input l2_cpu1_rd_excl_arb_set; // cpu1 read arbitration exclusive + input l2_cpu1_rd_priv_arb_set; // cpu1 read arbitration priv + input [1:0] l2_cpu1_rd_shared_arb_set; // cpu1 read arbitration shared + input l2_cpu1_rd_va48_arb_set; // cpu1 read arbitration va48 + input l2_cpu1_rd_aarch64_arb_set; // cpu1 read arbitration aarch64 + input [15:8] l2_cpu1_rd_asid_arb_set; // cpu1 read arbitration asid + input l2_cpu1_rd_prfm_arb_set; // cpu1 read arbitration prfm + input [44:0] l2_cpu1_rd_addr_arb_set; // cpu1 read arbitration address + input l2_cpu1_rd_bypass_arb_set; // cpu1 read arbitration bypass + input l2_cpu1_rd_bypass_req_can_e5; // cpu1 read arbitration bypass cancelled request + input l2_cpu1_early_rd_reqe4_e5_q; // cpu1 read arbitration bypass cancelled request + input l2_cpu1_rd_bypass_way_e5; // cpu1 read arbitration bypass way + input [2:0] l2_cpu1_rd_bypass_bufid_e5; // cpu1 read arbitration bypass bufid + input [2:0] l2_cpu1_rd_bypass_lrq_id_e5; // cpu1 read arbitration bypass bufid + + input l2_cpu1_wr_arb_fast; // cpu1 write arbitration fast request + input [3:0] l2_cpu1_wr_id_arb_set; // cpu1 write arbitration id for 1st qw + input [3:0] l2_cpu1_wr_partial_dw_arb_set; // cpu1 write partial qw byte strobe indicator + input [2:0] l2_cpu1_wr_cache_attr_arb_set; // cpu1 write arbitration cache attributes + input [7:0] l2_cpu1_wr_page_attr_arb_set; // cpu1 write arbitration page attributes + input [2:0] l2_cpu1_wr_elem_size_arb_set; // cpu1 write arbitration element size + input [2:0] l2_cpu1_wr_type_arb_set; // cpu1 write arbitration type + input [11:0] l2_cpu1_wr_cl_id_arb_set; // cpu1 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu1_wr_priv_arb_set; // cpu1 write arbitration priv + input [1:0] l2_cpu1_wr_shared_arb_set; // cpu1 write arbitration shared + input l2_cpu1_wr_last_arb_set; // cpu1 write arbitration last + input l2_cpu1_wr_clean_evict_arb_set; // cpu1 write arbitration clean eviction + input l2_cpu1_wr_err_arb_set; // cpu1 write arbitration error + input l2_cpu1_wr_way_arb_set; // cpu1 write arbitration way + input l2_cpu1_wr_dirty_arb_set; // cpu1 write arbitration dirty + input l2_cpu1_wr_1st_replayed_arb_set; // cpu1 write arbitration 1st replay indicator + input [44:0] l2_cpu1_wr_addr_arb_set; // cpu1 write arbitration address + input l2_cpu1_ic_arb_fast; // cpu1 peripheral (ic) arbitration fast request + input [2:0] l2_cpu1_ic_id_arb_set; // cpu1 peripheral (ic) fill buffer id + input l2_cpu1_ic_write_arb_set; // cpu1 peripheral (ic) write indicator + input l2_cpu1_ic_excl_arb_set; // cpu1 peripheral (ic) exclusive indicator + input [2:0] l2_cpu1_ic_elem_size_arb_set; // cpu1 peripheral (ic) element size + input l2_cpu1_ic_ns_arb_set; // cpu1 peripheral (ic) non-secure + input [15:0] l2_cpu1_ic_addr_arb_set; // cpu1 peripheral (ic) address + input [31:0] l2_cpu1_ic_data_arb_set; // cpu1 peripheral (ic) write data + + input l2_cpu1_wrq_almost_full; // cpu1 wrq almost full indicator + + input l2_cpu1_ls_wr_req_w2a; // cpu1 ls write request + input l2_cpu1_ls_wr_last_w2a; // cpu1 ls last indicator + input l2_cpu1_ls_wr_dirty_w2a; // cpu1 ls dirty indicator + input l2_cpu1_ls_wr_err_w2a; // cpu1 ls error indicator + input [2:0] l2_cpu1_ls_wr_type_w2a; // cpu1 ls write type + input [4:0] l2_cpu1_ls_wr_ccb_id_w2a; // cpu1 ls ccb id + input [127:0] l2_cpu1_ls_wr_data_w2a; // cpu1 ls write data + + input l2_cpu1_ls_ccb_resp; // cpu1 ls ccb resp + input [4:0] l2_cpu1_ls_ccb_resp_id; // cpu1 ls ccb id + input l2_cpu1_ls_ccb_data_wr; // cpu1 ls ccb data xfer + + input l2_cpu1_if_ccb_resp; // cpu1 if ccb resp + input [4:0] l2_cpu1_if_ccb_resp_id; // cpu1 if ccb id + + input l2_cpu1_tw_ccb_resp; // cpu1 tw ccb resp + input [4:0] l2_cpu1_tw_ccb_resp_id; // cpu1 tw ccb id + + input l2_cpu1_if_sync_done_q; // cpu1 sync response + input l2_cpu1_tlb_sync_done_q; // cpu1 tlb sync response + + input [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; // cpu1 lrq clear hazard id + input [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; // cpu1 wrq clear hazard id + input [3:0] l2_cpu1_ls_rd_haz_id_arb_q; // cpu1 ls rd wrq hazard id + input [2:0] l2_cpu1_ls_wr_haz_id_arb_q; // cpu1 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + input l2_cpu2_idle_wakeup_q; // cpu2 idle wakeup + input l2_cpu2_rd_arb_fast; // cpu2 read arbitration fast request + input [4:0] l2_cpu2_rd_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu2_rd_lrq_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu2_rd_type_arb_set; // cpu2 read arbitration type + input [2:0] l2_cpu2_rd_cache_attr_arb_set; // cpu2 read arbitration cache attributes + input [7:0] l2_cpu2_rd_page_attr_arb_set; // cpu2 read arbitration page attributes + input [2:0] l2_cpu2_rd_elem_size_arb_set; // cpu2 read arbitration element size + input l2_cpu2_rd_way_arb_set; // cpu2 read arbitration way + input l2_cpu2_rd_replayed_arb_set; // cpu2 read arbitration replayed + input l2_cpu2_rd_excl_arb_set; // cpu2 read arbitration exclusive + input l2_cpu2_rd_priv_arb_set; // cpu2 read arbitration priv + input [1:0] l2_cpu2_rd_shared_arb_set; // cpu2 read arbitration shared + input l2_cpu2_rd_va48_arb_set; // cpu0 read arbitration va48 + input l2_cpu2_rd_aarch64_arb_set; // cpu2 read arbitration aarch64 + input [15:8] l2_cpu2_rd_asid_arb_set; // cpu2 read arbitration asid + input l2_cpu2_rd_prfm_arb_set; // cpu2 read arbitration prfm + input [44:0] l2_cpu2_rd_addr_arb_set; // cpu2 read arbitration address + input l2_cpu2_rd_bypass_arb_set; // cpu2 read arbitration bypass + input l2_cpu2_rd_bypass_req_can_e5; // cpu2 read arbitration bypass cancelled request + input l2_cpu2_early_rd_reqe4_e5_q; // cpu2 read arbitration bypass cancelled request + input l2_cpu2_rd_bypass_way_e5; // cpu2 read arbitration bypass way + input [2:0] l2_cpu2_rd_bypass_bufid_e5; // cpu2 read arbitration bypass bufid + input [2:0] l2_cpu2_rd_bypass_lrq_id_e5; // cpu2 read arbitration bypass bufid + + input l2_cpu2_wr_arb_fast; // cpu2 write arbitration fast request + input [3:0] l2_cpu2_wr_id_arb_set; // cpu2 write arbitration id for 1st qw + input [3:0] l2_cpu2_wr_partial_dw_arb_set; // cpu2 write partial qw byte strobe indicator + input [2:0] l2_cpu2_wr_cache_attr_arb_set; // cpu2 write arbitration cache attributes + input [7:0] l2_cpu2_wr_page_attr_arb_set; // cpu2 write arbitration page attributes + input [2:0] l2_cpu2_wr_elem_size_arb_set; // cpu2 write arbitration element size + input [2:0] l2_cpu2_wr_type_arb_set; // cpu2 write arbitration type + input [11:0] l2_cpu2_wr_cl_id_arb_set; // cpu2 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu2_wr_priv_arb_set; // cpu2 write arbitration priv + input [1:0] l2_cpu2_wr_shared_arb_set; // cpu2 write arbitration shared + input l2_cpu2_wr_last_arb_set; // cpu2 write arbitration last + input l2_cpu2_wr_clean_evict_arb_set; // cpu2 write arbitration clean eviction + input l2_cpu2_wr_err_arb_set; // cpu2 write arbitration error + input l2_cpu2_wr_way_arb_set; // cpu2 write arbitration way + input l2_cpu2_wr_dirty_arb_set; // cpu2 write arbitration dirty + input l2_cpu2_wr_1st_replayed_arb_set; // cpu2 write arbitration 1st replay indicator + input [44:0] l2_cpu2_wr_addr_arb_set; // cpu2 write arbitration address + input l2_cpu2_ic_arb_fast; // cpu2 peripheral (ic) arbitration fast request + input [2:0] l2_cpu2_ic_id_arb_set; // cpu2 peripheral (ic) fill buffer id + input l2_cpu2_ic_write_arb_set; // cpu2 peripheral (ic) write indicator + input l2_cpu2_ic_excl_arb_set; // cpu2 peripheral (ic) exclusive indicator + input [2:0] l2_cpu2_ic_elem_size_arb_set; // cpu2 peripheral (ic) element size + input l2_cpu2_ic_ns_arb_set; // cpu2 peripheral (ic) non-secure + input [15:0] l2_cpu2_ic_addr_arb_set; // cpu2 peripheral (ic) address + input [31:0] l2_cpu2_ic_data_arb_set; // cpu2 peripheral (ic) write data + + input l2_cpu2_wrq_almost_full; // cpu2 wrq almost full indicator + + input l2_cpu2_ls_wr_req_w2a; // cpu2 ls write request + input l2_cpu2_ls_wr_last_w2a; // cpu2 ls last indicator + input l2_cpu2_ls_wr_dirty_w2a; // cpu2 ls dirty indicator + input l2_cpu2_ls_wr_err_w2a; // cpu2 ls error indicator + input [2:0] l2_cpu2_ls_wr_type_w2a; // cpu2 ls write type + input [4:0] l2_cpu2_ls_wr_ccb_id_w2a; // cpu2 ls ccb id + input [127:0] l2_cpu2_ls_wr_data_w2a; // cpu2 ls write data + + input l2_cpu2_ls_ccb_resp; // cpu2 ls ccb resp + input [4:0] l2_cpu2_ls_ccb_resp_id; // cpu2 ls ccb id + input l2_cpu2_ls_ccb_data_wr; // cpu2 ls ccb data xfer + + input l2_cpu2_if_ccb_resp; // cpu2 if ccb resp + input [4:0] l2_cpu2_if_ccb_resp_id; // cpu2 if ccb id + + input l2_cpu2_tw_ccb_resp; // cpu2 tw ccb resp + input [4:0] l2_cpu2_tw_ccb_resp_id; // cpu2 tw ccb id + + input l2_cpu2_if_sync_done_q; // cpu2 sync response + input l2_cpu2_tlb_sync_done_q; // cpu2 tlb sync response + + input [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; // cpu2 lrq clear hazard id + input [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; // cpu2 wrq clear hazard id + input [3:0] l2_cpu2_ls_rd_haz_id_arb_q; // cpu2 ls rd wrq hazard id + input [2:0] l2_cpu2_ls_wr_haz_id_arb_q; // cpu2 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + input l2_cpu3_idle_wakeup_q; // cpu3 idle wakeup + input l2_cpu3_rd_arb_fast; // cpu3 read arbitration fast request + input [4:0] l2_cpu3_rd_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu3_rd_lrq_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu3_rd_type_arb_set; // cpu3 read arbitration type + input [2:0] l2_cpu3_rd_cache_attr_arb_set; // cpu3 read arbitration cache attributes + input [7:0] l2_cpu3_rd_page_attr_arb_set; // cpu3 read arbitration page attributes + input [2:0] l2_cpu3_rd_elem_size_arb_set; // cpu3 read arbitration element size + input l2_cpu3_rd_way_arb_set; // cpu3 read arbitration way + input l2_cpu3_rd_replayed_arb_set; // cpu3 read arbitration replayed + input l2_cpu3_rd_excl_arb_set; // cpu3 read arbitration exclusive + input l2_cpu3_rd_priv_arb_set; // cpu3 read arbitration priv + input [1:0] l2_cpu3_rd_shared_arb_set; // cpu3 read arbitration shared + input l2_cpu3_rd_va48_arb_set; // cpu3 read arbitration va48 + input l2_cpu3_rd_aarch64_arb_set; // cpu3 read arbitration aarch64 + input [15:8] l2_cpu3_rd_asid_arb_set; // cpu3 read arbitration asid + input l2_cpu3_rd_prfm_arb_set; // cpu3 read arbitration prfm + input [44:0] l2_cpu3_rd_addr_arb_set; // cpu3 read arbitration address + input l2_cpu3_rd_bypass_arb_set; // cpu3 read arbitration bypass + input l2_cpu3_rd_bypass_req_can_e5; // cpu3 read arbitration bypass cancelled request + input l2_cpu3_early_rd_reqe4_e5_q; // cpu3 read arbitration bypass cancelled request + input l2_cpu3_rd_bypass_way_e5; // cpu3 read arbitration bypass way + input [2:0] l2_cpu3_rd_bypass_bufid_e5; // cpu3 read arbitration bypass bufid + input [2:0] l2_cpu3_rd_bypass_lrq_id_e5; // cpu3 read arbitration bypass bufid + + input l2_cpu3_wr_arb_fast; // cpu3 write arbitration fast request + input [3:0] l2_cpu3_wr_id_arb_set; // cpu3 write arbitration id for 1st qw + input [3:0] l2_cpu3_wr_partial_dw_arb_set; // cpu3 write partial qw byte strobe indicator + input [2:0] l2_cpu3_wr_cache_attr_arb_set; // cpu3 write arbitration cache attributes + input [7:0] l2_cpu3_wr_page_attr_arb_set; // cpu3 write arbitration page attributes + input [2:0] l2_cpu3_wr_elem_size_arb_set; // cpu3 write arbitration element size + input [2:0] l2_cpu3_wr_type_arb_set; // cpu3 write arbitration type + input [11:0] l2_cpu3_wr_cl_id_arb_set; // cpu3 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu3_wr_priv_arb_set; // cpu3 write arbitration priv + input [1:0] l2_cpu3_wr_shared_arb_set; // cpu3 write arbitration shared + input l2_cpu3_wr_last_arb_set; // cpu3 write arbitration last + input l2_cpu3_wr_clean_evict_arb_set; // cpu3 write arbitration clean eviction + input l2_cpu3_wr_err_arb_set; // cpu3 write arbitration error + input l2_cpu3_wr_way_arb_set; // cpu3 write arbitration way + input l2_cpu3_wr_dirty_arb_set; // cpu3 write arbitration dirty + input l2_cpu3_wr_1st_replayed_arb_set; // cpu3 write arbitration 1st replay indicator + input [44:0] l2_cpu3_wr_addr_arb_set; // cpu3 write arbitration address + input l2_cpu3_ic_arb_fast; // cpu3 peripheral (ic) arbitration fast request + input [2:0] l2_cpu3_ic_id_arb_set; // cpu3 peripheral (ic) fill buffer id + input l2_cpu3_ic_write_arb_set; // cpu3 peripheral (ic) write indicator + input l2_cpu3_ic_excl_arb_set; // cpu3 peripheral (ic) exclusive indicator + input [2:0] l2_cpu3_ic_elem_size_arb_set; // cpu3 peripheral (ic) element size + input l2_cpu3_ic_ns_arb_set; // cpu3 peripheral (ic) non-secure + input [15:0] l2_cpu3_ic_addr_arb_set; // cpu3 peripheral (ic) address + input [31:0] l2_cpu3_ic_data_arb_set; // cpu3 peripheral (ic) write data + + input l2_cpu3_wrq_almost_full; // cpu3 wrq almost full indicator + + input l2_cpu3_ls_wr_req_w2a; // cpu3 ls write request + input l2_cpu3_ls_wr_last_w2a; // cpu3 ls last indicator + input l2_cpu3_ls_wr_dirty_w2a; // cpu3 ls dirty indicator + input l2_cpu3_ls_wr_err_w2a; // cpu3 ls error indicator + input [2:0] l2_cpu3_ls_wr_type_w2a; // cpu3 ls write type + input [4:0] l2_cpu3_ls_wr_ccb_id_w2a; // cpu3 ls ccb id + input [127:0] l2_cpu3_ls_wr_data_w2a; // cpu3 ls write data + + input l2_cpu3_ls_ccb_resp; // cpu3 ls ccb resp + input [4:0] l2_cpu3_ls_ccb_resp_id; // cpu3 ls ccb id + input l2_cpu3_ls_ccb_data_wr; // cpu3 ls ccb data xfer + + input l2_cpu3_if_ccb_resp; // cpu3 if ccb resp + input [4:0] l2_cpu3_if_ccb_resp_id; // cpu3 if ccb id + + input l2_cpu3_tw_ccb_resp; // cpu3 tw ccb resp + input [4:0] l2_cpu3_tw_ccb_resp_id; // cpu3 tw ccb id + + input l2_cpu3_if_sync_done_q; // cpu3 sync response + input l2_cpu3_tlb_sync_done_q; // cpu3 tlb sync response + + input [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; // cpu3 lrq clear hazard id + input [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; // cpu3 wrq clear hazard id + input [3:0] l2_cpu3_ls_rd_haz_id_arb_q; // cpu3 ls rd wrq hazard id + input [2:0] l2_cpu3_ls_wr_haz_id_arb_q; // cpu3 ls wr lrq hazard id + +// END L2-CPU interface + +//------------------------------------------------------------------- +// TM interface +//------------------------------------------------------------------- +// BEGIN TIMER-CPU interface + output [3:0] tm_cpu0_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu0_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu1_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu1_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu2_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu2_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu3_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu3_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> +// END TIMER-CPU interface + +//----------------------------------------------------------------------------- +// IC interface +//----------------------------------------------------------------------------- + input ls_cpu0_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu0_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu0_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu0_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu0_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu0_raw_eae_secure; // LS S LPAE to IC + + input ds_cpu0_ic_sample_spr; + input [4:0] ds_cpu0_ic_cpsr_mode; + input ds_cpu0_ic_aa64naa32; + input ds_cpu0_ic_hcr_change; + input ds_cpu0_ic_scr_change; +// BEGIN INCLUDE FOR CPU1 + input ds_cpu1_ic_sample_spr; + input [4:0] ds_cpu1_ic_cpsr_mode; + input ds_cpu1_ic_aa64naa32; + input ds_cpu1_ic_hcr_change; + input ds_cpu1_ic_scr_change; + input ls_cpu1_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu1_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu1_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu1_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu1_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu1_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input ds_cpu2_ic_sample_spr; + input [4:0] ds_cpu2_ic_cpsr_mode; + input ds_cpu2_ic_aa64naa32; + input ds_cpu2_ic_hcr_change; + input ds_cpu2_ic_scr_change; + input ls_cpu2_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu2_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu2_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu2_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu2_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu2_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input ds_cpu3_ic_sample_spr; + input [4:0] ds_cpu3_ic_cpsr_mode; + input ds_cpu3_ic_aa64naa32; + input ds_cpu3_ic_hcr_change; + input ds_cpu3_ic_scr_change; + input ls_cpu3_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu3_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu3_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu3_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu3_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu3_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU3 + + output [`MAIA_CN:0] ic_nfiq; // IC physical FIQ + output [`MAIA_CN:0] ic_nirq; // IC physical IRQ + output [`MAIA_CN:0] ic_nsei; // IC physical SEI + output [`MAIA_CN:0] ic_nvfiq; // IC virtual FIQ + output [`MAIA_CN:0] ic_nvirq; // IC virtual IRQ + output [`MAIA_CN:0] ic_nvsei; // IC virtual SEI + output [`MAIA_CN:0] ic_p_valid; // IC is present + + output [`MAIA_CN:0] ic_sample_spr; // IC sample signal for TC, TALL*, EL* signals + output [`MAIA_CN:0] ic_hcr_change_complete; + output [`MAIA_CN:0] ic_scr_change_complete; + output [`MAIA_CN:0] ic_el_change_complete; + output [`MAIA_CN:0] ic_ich_el2_tc; // IC trap common + output [`MAIA_CN:0] ic_ich_el2_tall0; // IC trap all grp0 + output [`MAIA_CN:0] ic_ich_el2_tall1; // IC trap all grp1 + output [`MAIA_CN:0] ic_sra_el3_en; // IC System Registers enabled in EL3 + output [`MAIA_CN:0] ic_sra_el1s_en; // IC System Registers enabled in EL1S + output [`MAIA_CN:0] ic_sra_el2_en; // IC System Registers enabled in EL2 + output [`MAIA_CN:0] ic_sra_el1ns_en; // IC System Registers enabled in EL1NS + output [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; // IC HYP_TRAP EL1NS accesses + output [`MAIA_CN:0] ic_sre_el1ns_mon_trap; // IC MON_TRAP EL1NS accesses + output [`MAIA_CN:0] ic_sre_el1s_mon_trap; // IC MON_TRAP EL1S accesses + output [`MAIA_CN:0] ic_sre_el2_mon_trap; // IC MON_TRAP EL2 accesses + output [`MAIA_CN:0] ic_block_eoi_sgi_wr; // IC Block all EOI and SGI write accesses + +//----------------------------------------------------------------------------- +// DT interface +//----------------------------------------------------------------------------- +// BEGIN DT-CPU interface +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + output dt_cpu0_dbif_req_pclk; // Debug Interface Req + output dt_cpu0_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu0_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu0_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu0_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu0_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu0_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu0_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu0_edbgrq_pclk; // External Debug Request + output dt_cpu0_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu0_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu0_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu0_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu0_et_oslock_gclk; // ETM OS Lock + input dt_cpu0_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu0_halt_ack_gclk; // Core Halted + input dt_cpu0_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu0_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu0_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu0_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu0_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu0_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu0_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu0_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu0_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu0_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu0_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu0_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu0_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu0_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu0_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + output dt_cpu1_dbif_req_pclk; // Debug Interface Req + output dt_cpu1_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu1_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu1_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu1_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu1_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu1_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu1_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu1_edbgrq_pclk; // External Debug Request + output dt_cpu1_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu1_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu1_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu1_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu1_et_oslock_gclk; // ETM OS Lock + input dt_cpu1_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu1_halt_ack_gclk; // Core Halted + input dt_cpu1_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu1_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu1_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu1_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu1_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu1_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu1_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu1_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu1_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu1_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu1_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu1_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu1_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu1_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu1_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + output dt_cpu2_dbif_req_pclk; // Debug Interface Req + output dt_cpu2_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu2_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu2_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu2_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu2_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu2_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu2_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu2_edbgrq_pclk; // External Debug Request + output dt_cpu2_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu2_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu2_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu2_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu2_et_oslock_gclk; // ETM OS Lock + input dt_cpu2_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu2_halt_ack_gclk; // Core Halted + input dt_cpu2_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu2_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu2_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu2_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu2_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu2_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu2_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu2_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu2_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu2_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu2_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu2_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu2_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu2_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu2_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + output dt_cpu3_dbif_req_pclk; // Debug Interface Req + output dt_cpu3_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu3_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu3_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu3_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu3_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu3_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu3_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu3_edbgrq_pclk; // External Debug Request + output dt_cpu3_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu3_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu3_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu3_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu3_et_oslock_gclk; // ETM OS Lock + input dt_cpu3_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu3_halt_ack_gclk; // Core Halted + input dt_cpu3_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu3_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu3_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu3_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu3_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu3_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu3_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu3_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu3_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu3_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu3_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu3_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu3_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu3_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu3_noclkstop_pclk; // force CPU clock on from DT-PCLK +// END DT-CPU interface + +//----------------------------------------------------------------------------- +// CK interface +//----------------------------------------------------------------------------- +// BEGIN CK-CPU interface + input ds_cpu0_reset_req; // Warm Reset request + input ds_cpu0_wfi_req; // WFI request + input ds_cpu0_wfe_req; // WFI request + input ds_cpu0_flush; // flush for exception rtn + input [5:0] ds_cpu0_flush_type; // flush type + input ds_cpu0_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu0_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu0_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu0_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu0_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu0_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu0_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu0_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu0_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu0_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu0_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu0_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu0_hcr_va; // virtual abort + input ds_cpu0_hcr_vi; // virtual IRQ + input ds_cpu0_hcr_vf; // virtual FIQ + input [2:0] ds_cpu0_cpuectlr_ret; // CPU Retention control + output ck_cpu0_event_reg; // WFE event reg + output ck_cpu0_wfi_ack; // WFI acknowledge to DS + output ck_cpu0_wfe_ack; // WFE acknowledge to DS + output ck_cpu0_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu1_reset_req; // Warm Reset request + input ds_cpu1_wfi_req; // WFI request + input ds_cpu1_wfe_req; // WFI request + input ds_cpu1_flush; // flush for exception rtn + input [5:0] ds_cpu1_flush_type; // flush type + input ds_cpu1_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu1_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu1_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu1_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu1_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu1_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu1_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu1_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu1_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu1_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu1_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu1_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu1_hcr_va; // virtual abort + input ds_cpu1_hcr_vi; // virtual IRQ + input ds_cpu1_hcr_vf; // virtual FIQ + input [2:0] ds_cpu1_cpuectlr_ret; // CPU Retention control + output ck_cpu1_event_reg; // WFE event reg + output ck_cpu1_wfi_ack; // WFI acknowledge to DS + output ck_cpu1_wfe_ack; // WFE acknowledge to DS + output ck_cpu1_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu2_reset_req; // Warm Reset request + input ds_cpu2_wfi_req; // WFI request + input ds_cpu2_wfe_req; // WFI request + input ds_cpu2_flush; // flush for exception rtn + input [5:0] ds_cpu2_flush_type; // flush type + input ds_cpu2_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu2_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu2_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu2_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu2_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu2_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu2_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu2_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu2_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu2_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu2_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu2_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu2_hcr_va; // virtual abort + input ds_cpu2_hcr_vi; // virtual IRQ + input ds_cpu2_hcr_vf; // virtual FIQ + input [2:0] ds_cpu2_cpuectlr_ret; // CPU Retention control + output ck_cpu2_event_reg; // WFE event reg + output ck_cpu2_wfi_ack; // WFI acknowledge to DS + output ck_cpu2_wfe_ack; // WFE acknowledge to DS + output ck_cpu2_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu3_reset_req; // Warm Reset request + input ds_cpu3_wfi_req; // WFI request + input ds_cpu3_wfe_req; // WFI request + input ds_cpu3_flush; // flush for exception rtn + input [5:0] ds_cpu3_flush_type; // flush type + input ds_cpu3_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu3_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu3_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu3_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu3_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu3_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu3_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu3_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu3_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu3_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu3_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu3_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu3_hcr_va; // virtual abort + input ds_cpu3_hcr_vi; // virtual IRQ + input ds_cpu3_hcr_vf; // virtual FIQ + input [2:0] ds_cpu3_cpuectlr_ret; // CPU Retention control + output ck_cpu3_event_reg; // WFE event reg + output ck_cpu3_wfi_ack; // WFI acknowledge to DS + output ck_cpu3_wfe_ack; // WFE acknowledge to DS + output ck_cpu3_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ls_cpu0_clrexmon; // LS global exclusive monitor + input ls_cpu1_clrexmon; // LS global exclusive monitor + input ls_cpu2_clrexmon; // LS global exclusive monitor + input ls_cpu3_clrexmon; // LS global exclusive monitor + +// END CK-CPU interface + + output [`MAIA_CN:0] ck_gclkt; + + + + // wires + wire STANDBYWFIL2; + wire ck_areset_l2; + wire ck_cpu0_areset_l2cpu; + wire ck_cpu0_areset_l2dt; + wire ck_cpu0_commrx; + wire ck_cpu0_commtx; + wire ck_cpu0_crcx_clk_en_n_ic; + wire ck_cpu0_dbgnopwrdwn; + wire ck_cpu0_dbgrstreq; + wire ck_cpu0_dt_standbywfx; + wire ck_cpu0_dt_wfx_ack; + wire ck_cpu0_l2_standbywfi; + wire ck_cpu0_l2_standbywfx; + wire ck_cpu0_ncommirq; + wire ck_cpu0_npmuirq; + wire ck_cpu0_poreset_status; + wire ck_cpu0_reset1_n_l2cpu; + wire ck_cpu0_reset1_n_l2dt; + wire ck_cpu1_areset_l2cpu; + wire ck_cpu1_areset_l2dt; + wire ck_cpu1_commrx; + wire ck_cpu1_commtx; + wire ck_cpu1_crcx_clk_en_n_ic; + wire ck_cpu1_dbgnopwrdwn; + wire ck_cpu1_dbgrstreq; + wire ck_cpu1_dt_standbywfx; + wire ck_cpu1_dt_wfx_ack; + wire ck_cpu1_l2_standbywfi; + wire ck_cpu1_l2_standbywfx; + wire ck_cpu1_ncommirq; + wire ck_cpu1_npmuirq; + wire ck_cpu1_poreset_status; + wire ck_cpu1_reset1_n_l2cpu; + wire ck_cpu1_reset1_n_l2dt; + wire ck_cpu2_areset_l2cpu; + wire ck_cpu2_areset_l2dt; + wire ck_cpu2_commrx; + wire ck_cpu2_commtx; + wire ck_cpu2_crcx_clk_en_n_ic; + wire ck_cpu2_dbgnopwrdwn; + wire ck_cpu2_dbgrstreq; + wire ck_cpu2_dt_standbywfx; + wire ck_cpu2_dt_wfx_ack; + wire ck_cpu2_l2_standbywfi; + wire ck_cpu2_l2_standbywfx; + wire ck_cpu2_ncommirq; + wire ck_cpu2_npmuirq; + wire ck_cpu2_poreset_status; + wire ck_cpu2_reset1_n_l2cpu; + wire ck_cpu2_reset1_n_l2dt; + wire ck_cpu3_areset_l2cpu; + wire ck_cpu3_areset_l2dt; + wire ck_cpu3_commrx; + wire ck_cpu3_commtx; + wire ck_cpu3_crcx_clk_en_n_ic; + wire ck_cpu3_dbgnopwrdwn; + wire ck_cpu3_dbgrstreq; + wire ck_cpu3_dt_standbywfx; + wire ck_cpu3_dt_wfx_ack; + wire ck_cpu3_l2_standbywfi; + wire ck_cpu3_l2_standbywfx; + wire ck_cpu3_ncommirq; + wire ck_cpu3_npmuirq; + wire ck_cpu3_poreset_status; + wire ck_cpu3_reset1_n_l2cpu; + wire ck_cpu3_reset1_n_l2dt; + wire ck_dt_cpu0_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu0_cti_trigin_1to0_gclk; + wire ck_dt_cpu0_et_oslock_gclk; + wire ck_dt_cpu0_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu0_os_double_lock_gclk; + wire ck_dt_cpu0_pmusnapshot_ack_gclk; + wire ck_dt_cpu0_wfx_dbg_req_gclk; + wire ck_dt_cpu1_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu1_cti_trigin_1to0_gclk; + wire ck_dt_cpu1_et_oslock_gclk; + wire ck_dt_cpu1_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu1_os_double_lock_gclk; + wire ck_dt_cpu1_pmusnapshot_ack_gclk; + wire ck_dt_cpu1_wfx_dbg_req_gclk; + wire ck_dt_cpu2_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu2_cti_trigin_1to0_gclk; + wire ck_dt_cpu2_et_oslock_gclk; + wire ck_dt_cpu2_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu2_os_double_lock_gclk; + wire ck_dt_cpu2_pmusnapshot_ack_gclk; + wire ck_dt_cpu2_wfx_dbg_req_gclk; + wire ck_dt_cpu3_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu3_cti_trigin_1to0_gclk; + wire ck_dt_cpu3_et_oslock_gclk; + wire ck_dt_cpu3_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu3_os_double_lock_gclk; + wire ck_dt_cpu3_pmusnapshot_ack_gclk; + wire ck_dt_cpu3_wfx_dbg_req_gclk; + wire ck_gclkb0; + wire ck_gclkb1; + wire ck_gclkfr; + wire ck_gclkl2; + wire ck_gclktl2; + wire ck_l2_ace_inactive; + wire ck_l2_acp_inactive; + wire ck_l2_logic_clk_en; + wire ck_l2_sky_link_deactivate; + wire ck_l2_tbnk0_clk_en; + wire ck_l2_tbnk1_clk_en; + wire ck_reset1_n_l2; + wire clrexmon_c1; + wire ds_cpu0_ic_aa64naa32_i; + wire [4:0] ds_cpu0_ic_cpsr_mode_i; + wire ds_cpu0_ic_hcr_change_i; + wire ds_cpu0_ic_sample_spr_i; + wire ds_cpu0_ic_scr_change_i; + wire ds_cpu1_ic_aa64naa32_i; + wire [4:0] ds_cpu1_ic_cpsr_mode_i; + wire ds_cpu1_ic_hcr_change_i; + wire ds_cpu1_ic_sample_spr_i; + wire ds_cpu1_ic_scr_change_i; + wire ds_cpu2_ic_aa64naa32_i; + wire [4:0] ds_cpu2_ic_cpsr_mode_i; + wire ds_cpu2_ic_hcr_change_i; + wire ds_cpu2_ic_sample_spr_i; + wire ds_cpu2_ic_scr_change_i; + wire ds_cpu3_ic_aa64naa32_i; + wire [4:0] ds_cpu3_ic_cpsr_mode_i; + wire ds_cpu3_ic_hcr_change_i; + wire ds_cpu3_ic_sample_spr_i; + wire ds_cpu3_ic_scr_change_i; + wire dt_cpu0_apb_active_pclk; + wire dt_cpu0_poreset_status_ack_pclk; + wire dt_cpu0_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu0_wfx_wakeup_pclk; + wire dt_cpu1_apb_active_pclk; + wire dt_cpu1_poreset_status_ack_pclk; + wire dt_cpu1_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu1_wfx_wakeup_pclk; + wire dt_cpu2_apb_active_pclk; + wire dt_cpu2_poreset_status_ack_pclk; + wire dt_cpu2_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu2_wfx_wakeup_pclk; + wire dt_cpu3_apb_active_pclk; + wire dt_cpu3_poreset_status_ack_pclk; + wire dt_cpu3_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu3_wfx_wakeup_pclk; + wire eventi_sev; + wire [`MAIA_CN:0] ic_block_eoi_sgi_wr_o; + wire ic_cpu0_l2_dsb_block; + wire [63:0] ic_cpu0_spr_rd_data; + wire ic_cpu1_l2_dsb_block; + wire [63:0] ic_cpu1_spr_rd_data; + wire ic_cpu2_l2_dsb_block; + wire [63:0] ic_cpu2_spr_rd_data; + wire ic_cpu3_l2_dsb_block; + wire [63:0] ic_cpu3_spr_rd_data; + wire [`MAIA_CN:0] ic_el_change_complete_o; + wire [`MAIA_CN:0] ic_hcr_change_complete_o; + wire [`MAIA_CN:0] ic_ich_el2_tall0_o; + wire [`MAIA_CN:0] ic_ich_el2_tall1_o; + wire [`MAIA_CN:0] ic_ich_el2_tc_o; + wire [`MAIA_CN:0] ic_nfiq_o; + wire [`MAIA_CN:0] ic_nirq_o; + wire [`MAIA_CN:0] ic_nsei_o; + wire [`MAIA_CN:0] ic_nvfiq_o; + wire [`MAIA_CN:0] ic_nvirq_o; + wire [`MAIA_CN:0] ic_nvsei_o; + wire [31:0] ic_p_rdata; + wire ic_p_rdata_valid; + wire ic_p_ready; + wire [`MAIA_CN:0] ic_sample_spr_o; + wire [`MAIA_CN:0] ic_scr_change_complete_o; + wire [`MAIA_CN:0] ic_sra_el1ns_en_o; + wire [`MAIA_CN:0] ic_sra_el1s_en_o; + wire [`MAIA_CN:0] ic_sra_el2_en_o; + wire [`MAIA_CN:0] ic_sra_el3_en_o; + wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap_o; + wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap_o; + wire [`MAIA_CN:0] ic_sre_el1s_mon_trap_o; + wire [`MAIA_CN:0] ic_sre_el2_mon_trap_o; + wire l2_acp_flsh_rd_cnt_active_glb_l2_dly; + wire l2_acp_flsh_wr_cnt_active_glb_l2_dly; + wire l2_acp_rd_haz_vld_l2_dly_q; + wire l2_acp_wr_haz_vld_l2_dly_q; + wire l2_actlr_disable_b2b_setway_hzd_opt_x2_ns; + wire l2_actlr_disable_setway_opt; + wire l2_actlr_ncpu_rcg_enable; + wire l2_actlr_plru_dynamic; + wire l2_actlr_plru_en; + wire [1:0] l2_actlr_plru_mode; + wire l2_actlr_writeunique_disable; + wire l2_cfg_broadcastinner; + wire l2_cfg_broadcastouter; + wire l2_cpu0_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu0_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu0_snp_active; + wire l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_wr_decerr_q; + wire l2_cpu0_wr_slverr_q; + wire l2_cpu1_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu1_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu1_snp_active; + wire l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_wr_decerr_q; + wire l2_cpu1_wr_slverr_q; + wire l2_cpu2_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu2_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu2_snp_active; + wire l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_wr_decerr_q; + wire l2_cpu2_wr_slverr_q; + wire l2_cpu3_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu3_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu3_snp_active; + wire l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_wr_decerr_q; + wire l2_cpu3_wr_slverr_q; + wire l2_ctlr_x1_wr_q; + wire [9:0] l2_ctlr_x2_ns; + wire l2_idle; + wire [`MAIA_CN:0] l2_mbist1_en_b1; + wire [16:0] l2_mbist2_tbnk0_addr_b1; + wire l2_mbist2_tbnk0_all_b1; + wire [2:0] l2_mbist2_tbnk0_array_b1; + wire [17:0] l2_mbist2_tbnk0_be_b1; + wire l2_mbist2_tbnk0_en_b1; + wire [143:0] l2_mbist2_tbnk0_indata_b1; + wire [143:0] l2_mbist2_tbnk0_outdata_b3; + wire l2_mbist2_tbnk0_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp0_outdata_b2; + wire l2_mbist2_tbnk0_snp0_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp0_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp1_outdata_b2; + wire l2_mbist2_tbnk0_snp1_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp1_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp2_outdata_b2; + wire l2_mbist2_tbnk0_snp2_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp2_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp3_outdata_b2; + wire l2_mbist2_tbnk0_snp3_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp3_sel_b1; + wire l2_mbist2_tbnk0_wr_en_b1; + wire [16:0] l2_mbist2_tbnk1_addr_b1; + wire l2_mbist2_tbnk1_all_b1; + wire [2:0] l2_mbist2_tbnk1_array_b1; + wire [17:0] l2_mbist2_tbnk1_be_b1; + wire l2_mbist2_tbnk1_en_b1; + wire [143:0] l2_mbist2_tbnk1_indata_b1; + wire [143:0] l2_mbist2_tbnk1_outdata_b3; + wire l2_mbist2_tbnk1_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp0_outdata_b2; + wire l2_mbist2_tbnk1_snp0_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp0_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp1_outdata_b2; + wire l2_mbist2_tbnk1_snp1_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp1_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp2_outdata_b2; + wire l2_mbist2_tbnk1_snp2_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp2_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp3_outdata_b2; + wire l2_mbist2_tbnk1_snp3_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp3_sel_b1; + wire l2_mbist2_tbnk1_wr_en_b1; + wire l2_no_ram_acc_nxt_cycle; + wire [13:0] l2_p_addr; + wire [1:0] l2_p_cpu; + wire l2_p_nsecure; + wire [2:0] l2_p_sel; + wire [31:0] l2_p_wdata; + wire l2_p_write; + wire l2_reset3; + wire l2_rstdisable_x1_q; + wire l2_tbnk0_addr44_l3_q; + wire [44:0] l2_tbnk0_addr_l1; + wire [5:2] l2_tbnk0_addr_l6; + wire l2_tbnk0_all_tag_incl_active_l3; + wire l2_tbnk0_asq_cmp_evict_l3_q; + wire l2_tbnk0_asq_full_flsh; + wire l2_tbnk0_asq_nc_so_dev_limit; + wire [2:0] l2_tbnk0_cache_attr_l1; + wire l2_tbnk0_cfg_ecc_en; + wire l2_tbnk0_cmo_setway_l2_inv_incl_l4; + wire l2_tbnk0_cpu0_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu0_hit_l4; + wire l2_tbnk0_cpu0_l2_inv_l4_dly2; + wire l2_tbnk0_cpu0_l2hit_e_l4; + wire l2_tbnk0_cpu0_l2hit_s_l4; + wire l2_tbnk0_cpu0_peq_full_q; + wire l2_tbnk0_cpu0_peq_hit_q; + wire l2_tbnk0_cpu0_peq_self_evict_l3_q; + wire l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu0_rd_access_l4_dly; + wire l2_tbnk0_cpu0_self_evict_l4_dly_q; + wire l2_tbnk0_cpu0_single_ecc_err_l7_q; + wire l2_tbnk0_cpu0_snp_hit_e_l3; + wire l2_tbnk0_cpu0_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu0_snp_setway_addr_l3; + wire l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu0_vld_nxt_l5; + wire l2_tbnk0_cpu0_wr_access_l4_dly; + wire l2_tbnk0_cpu1_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu1_hit_l4; + wire l2_tbnk0_cpu1_l2_inv_l4_dly2; + wire l2_tbnk0_cpu1_l2hit_e_l4; + wire l2_tbnk0_cpu1_l2hit_s_l4; + wire l2_tbnk0_cpu1_peq_full_q; + wire l2_tbnk0_cpu1_peq_hit_q; + wire l2_tbnk0_cpu1_peq_self_evict_l3_q; + wire l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu1_rd_access_l4_dly; + wire l2_tbnk0_cpu1_self_evict_l4_dly_q; + wire l2_tbnk0_cpu1_single_ecc_err_l7_q; + wire l2_tbnk0_cpu1_snp_hit_e_l3; + wire l2_tbnk0_cpu1_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu1_snp_setway_addr_l3; + wire l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu1_vld_nxt_l5; + wire l2_tbnk0_cpu1_wr_access_l4_dly; + wire l2_tbnk0_cpu2_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu2_hit_l4; + wire l2_tbnk0_cpu2_l2_inv_l4_dly2; + wire l2_tbnk0_cpu2_l2hit_e_l4; + wire l2_tbnk0_cpu2_l2hit_s_l4; + wire l2_tbnk0_cpu2_peq_full_q; + wire l2_tbnk0_cpu2_peq_hit_q; + wire l2_tbnk0_cpu2_peq_self_evict_l3_q; + wire l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu2_rd_access_l4_dly; + wire l2_tbnk0_cpu2_self_evict_l4_dly_q; + wire l2_tbnk0_cpu2_single_ecc_err_l7_q; + wire l2_tbnk0_cpu2_snp_hit_e_l3; + wire l2_tbnk0_cpu2_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu2_snp_setway_addr_l3; + wire l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu2_vld_nxt_l5; + wire l2_tbnk0_cpu2_wr_access_l4_dly; + wire l2_tbnk0_cpu3_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu3_hit_l4; + wire l2_tbnk0_cpu3_l2_inv_l4_dly2; + wire l2_tbnk0_cpu3_l2hit_e_l4; + wire l2_tbnk0_cpu3_l2hit_s_l4; + wire l2_tbnk0_cpu3_peq_full_q; + wire l2_tbnk0_cpu3_peq_hit_q; + wire l2_tbnk0_cpu3_peq_self_evict_l3_q; + wire l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu3_rd_access_l4_dly; + wire l2_tbnk0_cpu3_self_evict_l4_dly_q; + wire l2_tbnk0_cpu3_single_ecc_err_l7_q; + wire l2_tbnk0_cpu3_snp_hit_e_l3; + wire l2_tbnk0_cpu3_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu3_snp_setway_addr_l3; + wire l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu3_vld_nxt_l5; + wire l2_tbnk0_cpu3_wr_access_l4_dly; + wire [3:0] l2_tbnk0_cpu_rvalid_init_nxt_l5; + wire [3:0] l2_tbnk0_cpu_rvalid_nxt_l5; + wire [3:0] l2_tbnk0_cpu_snp_hit_e_l4_q; + wire l2_tbnk0_crit_qw_nxt_l5; + wire [143:0] l2_tbnk0_data_corrected_l7_q; + wire [127:0] l2_tbnk0_data_l6; + wire l2_tbnk0_dbg_ram_acc_l5a; + wire [2:0] l2_tbnk0_dbg_ram_acc_unit_nxt; + wire [7:0] l2_tbnk0_dbg_ram_id_nxt_l5; + wire l2_tbnk0_dirty_l1; + wire l2_tbnk0_dirty_l3_q; + wire l2_tbnk0_dis_ns_dbg_arr_acc_x2; + wire l2_tbnk0_double_ecc_err_l7_q; + wire l2_tbnk0_early_rvalid_l4_q; + wire l2_tbnk0_ecc_fixup_blk_arb; + wire l2_tbnk0_ecc_fixup_inprog_dly_q; + wire l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q; + wire [31:0] l2_tbnk0_ecc_syndrome_reg_q; + wire l2_tbnk0_evict_special_hazard_l3_q; + wire l2_tbnk0_evict_special_hazard_rwvic_l3_q; + wire l2_tbnk0_excl_l1; + wire l2_tbnk0_excl_l4_q; + wire [44:6] l2_tbnk0_feq_addr_upd; + wire l2_tbnk0_feq_alloc_failed_l4; + wire l2_tbnk0_feq_axi_wr_vld_not_popped; + wire l2_tbnk0_feq_clr_l4; + wire [15:0] l2_tbnk0_feq_frc_incl_l3a; + wire l2_tbnk0_feq_kill_l3; + wire [4:0] l2_tbnk0_feq_last_id_q; + wire l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3; + wire l2_tbnk0_feq_tbnk_id_update_or_l3; + wire l2_tbnk0_full_miss_l4_q; + wire l2_tbnk0_hit_l4; + wire l2_tbnk0_hit_l7_q; + wire [3:0] l2_tbnk0_hit_way_l4_q; + wire [9:0] l2_tbnk0_id_l1; + wire [9:0] l2_tbnk0_id_l6_q; + wire [9:0] l2_tbnk0_id_nxt_l5; + wire l2_tbnk0_idle; + wire l2_tbnk0_init_req_l1; + wire l2_tbnk0_kill_l2; + wire l2_tbnk0_l2bb_fake_wr_l1; + wire l2_tbnk0_l2bb_wr_l1; + wire l2_tbnk0_l2hit_e_l4; + wire l2_tbnk0_l2hit_s_l4; + wire l2_tbnk0_l2v_s_q; + wire l2_tbnk0_l2v_vld_q; + wire l2_tbnk0_last_qw_l1; + wire l2_tbnk0_last_qw_l6_q; + wire l2_tbnk0_last_qw_nxt_l5; + wire [2:0] l2_tbnk0_lock_l1; + wire [2:0] l2_tbnk0_lock_l4; + wire [32:0] l2_tbnk0_merrsr_data; + wire [9:0] l2_tbnk0_page_attr_l1; + wire l2_tbnk0_partial_dw_wr_l1; + wire l2_tbnk0_pf_cnt_dec_l4_dly; + wire l2_tbnk0_pf_hazard_l3; + wire l2_tbnk0_pf_req_sel_for_fwd_l4; + wire l2_tbnk0_prfm_l1; + wire l2_tbnk0_prfm_nxt_l5; + wire [3:0] l2_tbnk0_prot_l1; + wire [3:0] l2_tbnk0_prot_l4_q; + wire [1:0] l2_tbnk0_qw_cnt_l1; + wire [1:0] l2_tbnk0_qw_cnt_l3_q; + wire l2_tbnk0_raw_hit_l4_q; + wire [2:0] l2_tbnk0_rbufid_nxt_l5; + wire l2_tbnk0_rd_en_nxt_l5; + wire l2_tbnk0_rd_fail_hazchk_feq_l3; + wire l2_tbnk0_rwvic_axi_read_err_l1; + wire l2_tbnk0_rwvic_axi_read_err_l3_q; + wire l2_tbnk0_rwvic_ccb_dirty_l6_q; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l1; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l3_q; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l6_q; + wire [3:0] l2_tbnk0_rwvic_ccb_way_l1; + wire l2_tbnk0_rwvic_cmo_clean_l1; + wire l2_tbnk0_rwvic_cmo_inv_l1; + wire l2_tbnk0_rwvic_cmo_inv_l7_q; + wire l2_tbnk0_rwvic_cmo_l7_q; + wire l2_tbnk0_rwvic_cmo_pou_l1; + wire l2_tbnk0_rwvic_cmo_pou_l6_q; + wire l2_tbnk0_rwvic_cmo_setway_l1; + wire l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1; + wire l2_tbnk0_rwvic_cmo_setway_ls_l6_q; + wire [2:0] l2_tbnk0_rwvic_cpu_fb_id_l1; + wire [3:0] l2_tbnk0_rwvic_cpu_id_dcd_l1; + wire l2_tbnk0_rwvic_ddi_l6_q; + wire l2_tbnk0_rwvic_feq_cmp_l3_q; + wire l2_tbnk0_rwvic_frc_l2hit_fwd_l1; + wire l2_tbnk0_rwvic_l2hit_e_l1; + wire l2_tbnk0_rwvic_l2hit_e_l3_q; + wire l2_tbnk0_rwvic_l2hit_e_l7_q; + wire l2_tbnk0_rwvic_l2v_dirty_l7_q; + wire [3:0] l2_tbnk0_rwvic_l2v_page_attr_l7_q; + wire l2_tbnk0_rwvic_l2v_vld_l6_q; + wire l2_tbnk0_rwvic_mesi_sh_l1; + wire l2_tbnk0_rwvic_non_snp_fail_hazchk_l3; + wire [2:0] l2_tbnk0_rwvic_owner_l1; + wire [2:0] l2_tbnk0_rwvic_owner_l7_q; + wire l2_tbnk0_rwvic_rd_type_l6_q; + wire l2_tbnk0_rwvic_snp_clr_dirty_l1; + wire l2_tbnk0_rwvic_snp_inv_l1; + wire l2_tbnk0_rwvic_snp_l1; + wire l2_tbnk0_rwvic_snp_l3_q; + wire l2_tbnk0_rwvic_snp_l6_q; + wire l2_tbnk0_rwvic_tag_wr_l0; + wire [3:0] l2_tbnk0_rwvic_type_l1; + wire l2_tbnk0_rwvic_wa_l1; + wire l2_tbnk0_rwvic_wa_l6_q; + wire [13:0] l2_tbnk0_sel_l1; + wire [2:0] l2_tbnk0_size_l1; + wire [2:0] l2_tbnk0_size_l4_q; + wire l2_tbnk0_snp_byp_peq_haz_pending_q; + wire l2_tbnk0_snp_dvm_cmpl_l1; + wire l2_tbnk0_snp_hit_e_l4_q; + wire l2_tbnk0_snp_hit_feq_evict_l4_dly; + wire l2_tbnk0_snp_hit_s_l4_q; + wire [4:0] l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q; + wire [7:0] l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q; + wire [7:0] l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q; + wire [44:7] l2_tbnk0_snp_tag_wr_l2_hit_addr_l1; + wire [1:0] l2_tbnk0_snp_tag_wr_l2_hit_state_l1; + wire l2_tbnk0_snp_tag_wr_l2_hit_way_l1; + wire l2_tbnk0_special_evict_hazard_l3; + wire l2_tbnk0_special_hazard_l3_q; + wire l2_tbnk0_sync_l1; + wire l2_tbnk0_tag_ecc_dbl_rmw_wr_l1; + wire l2_tbnk0_tag_ecc_err_cpu0_l4; + wire l2_tbnk0_tag_ecc_err_cpu1_l4; + wire l2_tbnk0_tag_ecc_err_cpu2_l4; + wire l2_tbnk0_tag_ecc_err_cpu3_l4; + wire l2_tbnk0_tag_ecc_err_l4; + wire [6:0] l2_tbnk0_type_l1; + wire [1:0] l2_tbnk0_ulen_l1; + wire [1:0] l2_tbnk0_ulen_l4_q; + wire l2_tbnk0_vld_init_l6_q; + wire l2_tbnk0_vld_l6_q; + wire l2_tbnk0_way_l1; + wire l2_tbnk0_way_l4_q; + wire l2_tbnk0_way_nxt_l3a; + wire [143:0] l2_tbnk0_wr_data_l3; + wire [127:0] l2_tbnk0_wr_data_l3a_q; + wire l2_tbnk0_wr_data_l4_en; + wire l2_tbnk0_wr_err_l1; + wire l2_tbnk0_wr_fail_feq_full_l3; + wire l2_tbnk0_wr_fail_hazchk_feq_l3; + wire [11:0] l2_tbnk0_wr_non_crit_id_l1; + wire [11:0] l2_tbnk0_wr_non_crit_id_l4_q; + wire [15:0] l2_tbnk0_wr_strb_mask_l3a_q; + wire l2_tbnk1_addr44_l3_q; + wire [44:0] l2_tbnk1_addr_l1; + wire [5:2] l2_tbnk1_addr_l6; + wire l2_tbnk1_all_tag_incl_active_l3; + wire l2_tbnk1_asq_cmp_evict_l3_q; + wire l2_tbnk1_asq_full_flsh; + wire l2_tbnk1_asq_nc_so_dev_limit; + wire [2:0] l2_tbnk1_cache_attr_l1; + wire l2_tbnk1_cfg_ecc_en; + wire l2_tbnk1_cmo_setway_l2_inv_incl_l4; + wire l2_tbnk1_cpu0_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu0_hit_l4; + wire l2_tbnk1_cpu0_l2_inv_l4_dly2; + wire l2_tbnk1_cpu0_l2hit_e_l4; + wire l2_tbnk1_cpu0_l2hit_s_l4; + wire l2_tbnk1_cpu0_peq_full_q; + wire l2_tbnk1_cpu0_peq_hit_q; + wire l2_tbnk1_cpu0_peq_self_evict_l3_q; + wire l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu0_rd_access_l4_dly; + wire l2_tbnk1_cpu0_self_evict_l4_dly_q; + wire l2_tbnk1_cpu0_single_ecc_err_l7_q; + wire l2_tbnk1_cpu0_snp_hit_e_l3; + wire l2_tbnk1_cpu0_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu0_snp_setway_addr_l3; + wire l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu0_vld_nxt_l5; + wire l2_tbnk1_cpu0_wr_access_l4_dly; + wire l2_tbnk1_cpu1_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu1_hit_l4; + wire l2_tbnk1_cpu1_l2_inv_l4_dly2; + wire l2_tbnk1_cpu1_l2hit_e_l4; + wire l2_tbnk1_cpu1_l2hit_s_l4; + wire l2_tbnk1_cpu1_peq_full_q; + wire l2_tbnk1_cpu1_peq_hit_q; + wire l2_tbnk1_cpu1_peq_self_evict_l3_q; + wire l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu1_rd_access_l4_dly; + wire l2_tbnk1_cpu1_self_evict_l4_dly_q; + wire l2_tbnk1_cpu1_single_ecc_err_l7_q; + wire l2_tbnk1_cpu1_snp_hit_e_l3; + wire l2_tbnk1_cpu1_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu1_snp_setway_addr_l3; + wire l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu1_vld_nxt_l5; + wire l2_tbnk1_cpu1_wr_access_l4_dly; + wire l2_tbnk1_cpu2_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu2_hit_l4; + wire l2_tbnk1_cpu2_l2_inv_l4_dly2; + wire l2_tbnk1_cpu2_l2hit_e_l4; + wire l2_tbnk1_cpu2_l2hit_s_l4; + wire l2_tbnk1_cpu2_peq_full_q; + wire l2_tbnk1_cpu2_peq_hit_q; + wire l2_tbnk1_cpu2_peq_self_evict_l3_q; + wire l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu2_rd_access_l4_dly; + wire l2_tbnk1_cpu2_self_evict_l4_dly_q; + wire l2_tbnk1_cpu2_single_ecc_err_l7_q; + wire l2_tbnk1_cpu2_snp_hit_e_l3; + wire l2_tbnk1_cpu2_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu2_snp_setway_addr_l3; + wire l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu2_vld_nxt_l5; + wire l2_tbnk1_cpu2_wr_access_l4_dly; + wire l2_tbnk1_cpu3_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu3_hit_l4; + wire l2_tbnk1_cpu3_l2_inv_l4_dly2; + wire l2_tbnk1_cpu3_l2hit_e_l4; + wire l2_tbnk1_cpu3_l2hit_s_l4; + wire l2_tbnk1_cpu3_peq_full_q; + wire l2_tbnk1_cpu3_peq_hit_q; + wire l2_tbnk1_cpu3_peq_self_evict_l3_q; + wire l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu3_rd_access_l4_dly; + wire l2_tbnk1_cpu3_self_evict_l4_dly_q; + wire l2_tbnk1_cpu3_single_ecc_err_l7_q; + wire l2_tbnk1_cpu3_snp_hit_e_l3; + wire l2_tbnk1_cpu3_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu3_snp_setway_addr_l3; + wire l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu3_vld_nxt_l5; + wire l2_tbnk1_cpu3_wr_access_l4_dly; + wire [3:0] l2_tbnk1_cpu_rvalid_init_nxt_l5; + wire [3:0] l2_tbnk1_cpu_rvalid_nxt_l5; + wire [3:0] l2_tbnk1_cpu_snp_hit_e_l4_q; + wire l2_tbnk1_crit_qw_nxt_l5; + wire [143:0] l2_tbnk1_data_corrected_l7_q; + wire [127:0] l2_tbnk1_data_l6; + wire l2_tbnk1_dbg_ram_acc_l5a; + wire [2:0] l2_tbnk1_dbg_ram_acc_unit_nxt; + wire [7:0] l2_tbnk1_dbg_ram_id_nxt_l5; + wire l2_tbnk1_dirty_l1; + wire l2_tbnk1_dirty_l3_q; + wire l2_tbnk1_dis_ns_dbg_arr_acc_x2; + wire l2_tbnk1_double_ecc_err_l7_q; + wire l2_tbnk1_early_rvalid_l4_q; + wire l2_tbnk1_ecc_fixup_blk_arb; + wire l2_tbnk1_ecc_fixup_inprog_dly_q; + wire l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q; + wire [31:0] l2_tbnk1_ecc_syndrome_reg_q; + wire l2_tbnk1_evict_special_hazard_l3_q; + wire l2_tbnk1_evict_special_hazard_rwvic_l3_q; + wire l2_tbnk1_excl_l1; + wire l2_tbnk1_excl_l4_q; + wire [44:6] l2_tbnk1_feq_addr_upd; + wire l2_tbnk1_feq_alloc_failed_l4; + wire l2_tbnk1_feq_axi_wr_vld_not_popped; + wire l2_tbnk1_feq_clr_l4; + wire [15:0] l2_tbnk1_feq_frc_incl_l3a; + wire l2_tbnk1_feq_kill_l3; + wire [4:0] l2_tbnk1_feq_last_id_q; + wire l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3; + wire l2_tbnk1_feq_tbnk_id_update_or_l3; + wire l2_tbnk1_full_miss_l4_q; + wire l2_tbnk1_hit_l4; + wire l2_tbnk1_hit_l7_q; + wire [3:0] l2_tbnk1_hit_way_l4_q; + wire [9:0] l2_tbnk1_id_l1; + wire [9:0] l2_tbnk1_id_l6_q; + wire [9:0] l2_tbnk1_id_nxt_l5; + wire l2_tbnk1_idle; + wire l2_tbnk1_init_req_l1; + wire l2_tbnk1_kill_l2; + wire l2_tbnk1_l2bb_fake_wr_l1; + wire l2_tbnk1_l2bb_wr_l1; + wire l2_tbnk1_l2hit_e_l4; + wire l2_tbnk1_l2hit_s_l4; + wire l2_tbnk1_l2v_s_q; + wire l2_tbnk1_l2v_vld_q; + wire l2_tbnk1_last_qw_l1; + wire l2_tbnk1_last_qw_l6_q; + wire l2_tbnk1_last_qw_nxt_l5; + wire [2:0] l2_tbnk1_lock_l1; + wire [2:0] l2_tbnk1_lock_l4; + wire [32:0] l2_tbnk1_merrsr_data; + wire [9:0] l2_tbnk1_page_attr_l1; + wire l2_tbnk1_partial_dw_wr_l1; + wire l2_tbnk1_pf_cnt_dec_l4_dly; + wire l2_tbnk1_pf_hazard_l3; + wire l2_tbnk1_pf_req_sel_for_fwd_l4; + wire l2_tbnk1_prfm_l1; + wire l2_tbnk1_prfm_nxt_l5; + wire [3:0] l2_tbnk1_prot_l1; + wire [3:0] l2_tbnk1_prot_l4_q; + wire [1:0] l2_tbnk1_qw_cnt_l1; + wire [1:0] l2_tbnk1_qw_cnt_l3_q; + wire l2_tbnk1_raw_hit_l4_q; + wire [2:0] l2_tbnk1_rbufid_nxt_l5; + wire l2_tbnk1_rd_en_nxt_l5; + wire l2_tbnk1_rd_fail_hazchk_feq_l3; + wire l2_tbnk1_rwvic_axi_read_err_l1; + wire l2_tbnk1_rwvic_axi_read_err_l3_q; + wire l2_tbnk1_rwvic_ccb_dirty_l6_q; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l1; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l3_q; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l6_q; + wire [3:0] l2_tbnk1_rwvic_ccb_way_l1; + wire l2_tbnk1_rwvic_cmo_clean_l1; + wire l2_tbnk1_rwvic_cmo_inv_l1; + wire l2_tbnk1_rwvic_cmo_inv_l7_q; + wire l2_tbnk1_rwvic_cmo_l7_q; + wire l2_tbnk1_rwvic_cmo_pou_l1; + wire l2_tbnk1_rwvic_cmo_pou_l6_q; + wire l2_tbnk1_rwvic_cmo_setway_l1; + wire l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1; + wire l2_tbnk1_rwvic_cmo_setway_ls_l6_q; + wire [2:0] l2_tbnk1_rwvic_cpu_fb_id_l1; + wire [3:0] l2_tbnk1_rwvic_cpu_id_dcd_l1; + wire l2_tbnk1_rwvic_ddi_l6_q; + wire l2_tbnk1_rwvic_feq_cmp_l3_q; + wire l2_tbnk1_rwvic_frc_l2hit_fwd_l1; + wire l2_tbnk1_rwvic_l2hit_e_l1; + wire l2_tbnk1_rwvic_l2hit_e_l3_q; + wire l2_tbnk1_rwvic_l2hit_e_l7_q; + wire l2_tbnk1_rwvic_l2v_dirty_l7_q; + wire [3:0] l2_tbnk1_rwvic_l2v_page_attr_l7_q; + wire l2_tbnk1_rwvic_l2v_vld_l6_q; + wire l2_tbnk1_rwvic_mesi_sh_l1; + wire l2_tbnk1_rwvic_non_snp_fail_hazchk_l3; + wire [2:0] l2_tbnk1_rwvic_owner_l1; + wire [2:0] l2_tbnk1_rwvic_owner_l7_q; + wire l2_tbnk1_rwvic_rd_type_l6_q; + wire l2_tbnk1_rwvic_snp_clr_dirty_l1; + wire l2_tbnk1_rwvic_snp_inv_l1; + wire l2_tbnk1_rwvic_snp_l1; + wire l2_tbnk1_rwvic_snp_l3_q; + wire l2_tbnk1_rwvic_snp_l6_q; + wire l2_tbnk1_rwvic_tag_wr_l0; + wire [3:0] l2_tbnk1_rwvic_type_l1; + wire l2_tbnk1_rwvic_wa_l1; + wire l2_tbnk1_rwvic_wa_l6_q; + wire [13:0] l2_tbnk1_sel_l1; + wire [2:0] l2_tbnk1_size_l1; + wire [2:0] l2_tbnk1_size_l4_q; + wire l2_tbnk1_snp_byp_peq_haz_pending_q; + wire l2_tbnk1_snp_dvm_cmpl_l1; + wire l2_tbnk1_snp_hit_e_l4_q; + wire l2_tbnk1_snp_hit_feq_evict_l4_dly; + wire l2_tbnk1_snp_hit_s_l4_q; + wire [4:0] l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q; + wire [7:0] l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q; + wire [7:0] l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q; + wire [44:7] l2_tbnk1_snp_tag_wr_l2_hit_addr_l1; + wire [1:0] l2_tbnk1_snp_tag_wr_l2_hit_state_l1; + wire l2_tbnk1_snp_tag_wr_l2_hit_way_l1; + wire l2_tbnk1_special_evict_hazard_l3; + wire l2_tbnk1_special_hazard_l3_q; + wire l2_tbnk1_sync_l1; + wire l2_tbnk1_tag_ecc_dbl_rmw_wr_l1; + wire l2_tbnk1_tag_ecc_err_cpu0_l4; + wire l2_tbnk1_tag_ecc_err_cpu1_l4; + wire l2_tbnk1_tag_ecc_err_cpu2_l4; + wire l2_tbnk1_tag_ecc_err_cpu3_l4; + wire l2_tbnk1_tag_ecc_err_l4; + wire [6:0] l2_tbnk1_type_l1; + wire [1:0] l2_tbnk1_ulen_l1; + wire [1:0] l2_tbnk1_ulen_l4_q; + wire l2_tbnk1_vld_init_l6_q; + wire l2_tbnk1_vld_l6_q; + wire l2_tbnk1_way_l1; + wire l2_tbnk1_way_l4_q; + wire l2_tbnk1_way_nxt_l3a; + wire [143:0] l2_tbnk1_wr_data_l3; + wire [127:0] l2_tbnk1_wr_data_l3a_q; + wire l2_tbnk1_wr_data_l4_en; + wire l2_tbnk1_wr_err_l1; + wire l2_tbnk1_wr_fail_feq_full_l3; + wire l2_tbnk1_wr_fail_hazchk_feq_l3; + wire [11:0] l2_tbnk1_wr_non_crit_id_l1; + wire [11:0] l2_tbnk1_wr_non_crit_id_l4_q; + wire [15:0] l2_tbnk1_wr_strb_mask_l3a_q; + wire l2_tbnk_hwrst_done_x2; + wire [13:0] l2_tbnk_hwrst_idx_x1_q; + wire [8:0] tm_cntpct_q; + wire tm_cpu0_event_sev; + wire [63:0] tm_cpu0_spr_rd_data; + wire tm_cpu1_event_sev; + wire [63:0] tm_cpu1_spr_rd_data; + wire tm_cpu2_event_sev; + wire [63:0] tm_cpu2_spr_rd_data; + wire tm_cpu3_event_sev; + wire [63:0] tm_cpu3_spr_rd_data; + wire [63:0] tm_tval_cpu0_spr_rd_data; + wire [63:0] tm_tval_cpu1_spr_rd_data; + wire [63:0] tm_tval_cpu2_spr_rd_data; + wire [63:0] tm_tval_cpu3_spr_rd_data; + + maia_timer utm( // outputs + .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), + .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), + .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), + .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tm_cpu0_event_sev (tm_cpu0_event_sev), + .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), + .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tm_cpu1_event_sev (tm_cpu1_event_sev), + .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), + .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tm_cpu2_event_sev (tm_cpu2_event_sev), + .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), + .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tm_cpu3_event_sev (tm_cpu3_event_sev), + .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), + .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), + .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), + .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), + .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]), + + // inputs + .CNTCLKEN (CNTCLKEN), + .CNTVALUEB (CNTVALUEB[63:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .ck_areset_l2 (ck_areset_l2), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .eventi_sev (eventi_sev), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable) + ); // utm + + maia_l2_logic ul2_logic( // outputs + .ACREADYM (ACREADYM), + .ARADDRM (ARADDRM[43:0]), + .ARBARM (ARBARM[1:0]), + .ARBURSTM (ARBURSTM[1:0]), + .ARCACHEM (ARCACHEM[3:0]), + .ARDOMAINM (ARDOMAINM[1:0]), + .ARIDM (ARIDM[6:0]), + .ARLENM (ARLENM[7:0]), + .ARLOCKM (ARLOCKM), + .ARPROTM (ARPROTM[2:0]), + .ARREADYS (ARREADYS), + .ARSIZEM (ARSIZEM[2:0]), + .ARSNOOPM (ARSNOOPM[3:0]), + .ARVALIDM (ARVALIDM), + .AWADDRM (AWADDRM[43:0]), + .AWBARM (AWBARM[1:0]), + .AWBURSTM (AWBURSTM[1:0]), + .AWCACHEM (AWCACHEM[3:0]), + .AWDOMAINM (AWDOMAINM[1:0]), + .AWIDM (AWIDM[6:0]), + .AWLENM (AWLENM[7:0]), + .AWLOCKM (AWLOCKM), + .AWPROTM (AWPROTM[2:0]), + .AWREADYS (AWREADYS), + .AWSIZEM (AWSIZEM[2:0]), + .AWSNOOPM (AWSNOOPM[2:0]), + .AWUNIQUEM (AWUNIQUEM), + .AWVALIDM (AWVALIDM), + .BIDS (BIDS[4:0]), + .BREADYM (BREADYM), + .BRESPS (BRESPS[1:0]), + .BVALIDS (BVALIDS), + .CDDATAM (CDDATAM[127:0]), + .CDLASTM (CDLASTM), + .CDVALIDM (CDVALIDM), + .CRRESPM (CRRESPM[4:0]), + .CRVALIDM (CRVALIDM), + .L2FLUSHDONE (L2FLUSHDONE), + .L2QACCEPTn (L2QACCEPTn), + .L2QACTIVE (L2QACTIVE), + .L2QDENY (L2QDENY), + .RACKM (RACKM), + .RDATAS (RDATAS[127:0]), + .RDMEMATTR (RDMEMATTR[7:0]), + .RIDS (RIDS[4:0]), + .RLASTS (RLASTS), + .RREADYM (RREADYM), + .RRESPS (RRESPS[1:0]), + .RVALIDS (RVALIDS), + .WACKM (WACKM), + .WDATAM (WDATAM[127:0]), + .WIDM (WIDM[6:0]), + .WLASTM (WLASTM), + .WREADYS (WREADYS), + .WRMEMATTR (WRMEMATTR[7:0]), + .WSTRBM (WSTRBM[15:0]), + .WVALIDM (WVALIDM), + .ck_areset_l2 (ck_areset_l2), + .ck_l2_logic_clk_en (ck_l2_logic_clk_en), + .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), + .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu0_barrier_done (l2_cpu0_barrier_done), + .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddbl_ecc_err_r3), + .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idbl_ecc_err_r3), + .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu0_rd_arb (l2_cpu0_rd_arb), + .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu0_rexfail (l2_cpu0_rexfail), + .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu0_rvalid (l2_cpu0_rvalid), + .l2_cpu0_snp_active (l2_cpu0_snp_active), + .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu0_spec_valid (l2_cpu0_spec_valid), + .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu0_wr_arb (l2_cpu0_wr_arb), + .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu0_wr_decerr_q (l2_cpu0_wr_decerr_q), + .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu0_wr_slverr_q (l2_cpu0_wr_slverr_q), + .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu1_barrier_done (l2_cpu1_barrier_done), + .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddbl_ecc_err_r3), + .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idbl_ecc_err_r3), + .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu1_rd_arb (l2_cpu1_rd_arb), + .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu1_rexfail (l2_cpu1_rexfail), + .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu1_rvalid (l2_cpu1_rvalid), + .l2_cpu1_snp_active (l2_cpu1_snp_active), + .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu1_spec_valid (l2_cpu1_spec_valid), + .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu1_wr_arb (l2_cpu1_wr_arb), + .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu1_wr_decerr_q (l2_cpu1_wr_decerr_q), + .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu1_wr_slverr_q (l2_cpu1_wr_slverr_q), + .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu2_barrier_done (l2_cpu2_barrier_done), + .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddbl_ecc_err_r3), + .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idbl_ecc_err_r3), + .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu2_rd_arb (l2_cpu2_rd_arb), + .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu2_rexfail (l2_cpu2_rexfail), + .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu2_rvalid (l2_cpu2_rvalid), + .l2_cpu2_snp_active (l2_cpu2_snp_active), + .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu2_spec_valid (l2_cpu2_spec_valid), + .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu2_wr_arb (l2_cpu2_wr_arb), + .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu2_wr_decerr_q (l2_cpu2_wr_decerr_q), + .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu2_wr_slverr_q (l2_cpu2_wr_slverr_q), + .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu3_barrier_done (l2_cpu3_barrier_done), + .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddbl_ecc_err_r3), + .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idbl_ecc_err_r3), + .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu3_rd_arb (l2_cpu3_rd_arb), + .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu3_rexfail (l2_cpu3_rexfail), + .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu3_rvalid (l2_cpu3_rvalid), + .l2_cpu3_snp_active (l2_cpu3_snp_active), + .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu3_spec_valid (l2_cpu3_spec_valid), + .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu3_wr_arb (l2_cpu3_wr_arb), + .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu3_wr_decerr_q (l2_cpu3_wr_decerr_q), + .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu3_wr_slverr_q (l2_cpu3_wr_slverr_q), + .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_idle (l2_idle), + .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), + .l2_mbist2_tbnk0_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), + .l2_mbist2_tbnk0_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), + .l2_mbist2_tbnk0_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), + .l2_mbist2_tbnk0_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), + .l2_mbist2_tbnk1_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), + .l2_mbist2_tbnk1_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), + .l2_mbist2_tbnk1_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), + .l2_mbist2_tbnk1_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_p_addr (l2_p_addr[13:0]), + .l2_p_cpu (l2_p_cpu[1:0]), + .l2_p_nsecure (l2_p_nsecure), + .l2_p_sel (l2_p_sel[2:0]), + .l2_p_wdata (l2_p_wdata[31:0]), + .l2_p_write (l2_p_write), + .l2_reset3 (l2_reset3), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_tbnk0_addr_l1 (l2_tbnk0_addr_l1[44:0]), + .l2_tbnk0_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), + .l2_tbnk0_asq_full_flsh (l2_tbnk0_asq_full_flsh), + .l2_tbnk0_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), + .l2_tbnk0_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), + .l2_tbnk0_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), + .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), + .l2_tbnk0_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), + .l2_tbnk0_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), + .l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), + .l2_tbnk0_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), + .l2_tbnk0_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), + .l2_tbnk0_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), + .l2_tbnk0_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), + .l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), + .l2_tbnk0_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), + .l2_tbnk0_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), + .l2_tbnk0_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), + .l2_tbnk0_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), + .l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), + .l2_tbnk0_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), + .l2_tbnk0_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), + .l2_tbnk0_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), + .l2_tbnk0_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), + .l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), + .l2_tbnk0_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), + .l2_tbnk0_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_dirty_l1 (l2_tbnk0_dirty_l1), + .l2_tbnk0_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), + .l2_tbnk0_excl_l1 (l2_tbnk0_excl_l1), + .l2_tbnk0_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), + .l2_tbnk0_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), + .l2_tbnk0_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), + .l2_tbnk0_feq_kill_l3 (l2_tbnk0_feq_kill_l3), + .l2_tbnk0_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), + .l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk0_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), + .l2_tbnk0_id_l1 (l2_tbnk0_id_l1[9:0]), + .l2_tbnk0_init_req_l1 (l2_tbnk0_init_req_l1), + .l2_tbnk0_kill_l2 (l2_tbnk0_kill_l2), + .l2_tbnk0_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), + .l2_tbnk0_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), + .l2_tbnk0_last_qw_l1 (l2_tbnk0_last_qw_l1), + .l2_tbnk0_lock_l1 (l2_tbnk0_lock_l1[2:0]), + .l2_tbnk0_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), + .l2_tbnk0_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), + .l2_tbnk0_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), + .l2_tbnk0_prfm_l1 (l2_tbnk0_prfm_l1), + .l2_tbnk0_prot_l1 (l2_tbnk0_prot_l1[3:0]), + .l2_tbnk0_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), + .l2_tbnk0_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), + .l2_tbnk0_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), + .l2_tbnk0_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), + .l2_tbnk0_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), + .l2_tbnk0_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), + .l2_tbnk0_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), + .l2_tbnk0_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), + .l2_tbnk0_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), + .l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk0_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk0_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk0_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), + .l2_tbnk0_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk0_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), + .l2_tbnk0_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), + .l2_tbnk0_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), + .l2_tbnk0_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), + .l2_tbnk0_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), + .l2_tbnk0_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), + .l2_tbnk0_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), + .l2_tbnk0_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), + .l2_tbnk0_sel_l1 (l2_tbnk0_sel_l1[13:0]), + .l2_tbnk0_size_l1 (l2_tbnk0_size_l1[2:0]), + .l2_tbnk0_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), + .l2_tbnk0_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), + .l2_tbnk0_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), + .l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk0_sync_l1 (l2_tbnk0_sync_l1), + .l2_tbnk0_type_l1 (l2_tbnk0_type_l1[6:0]), + .l2_tbnk0_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), + .l2_tbnk0_way_l1 (l2_tbnk0_way_l1), + .l2_tbnk0_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), + .l2_tbnk0_wr_err_l1 (l2_tbnk0_wr_err_l1), + .l2_tbnk0_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), + .l2_tbnk0_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), + .l2_tbnk0_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), + .l2_tbnk0_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]), + .l2_tbnk1_addr_l1 (l2_tbnk1_addr_l1[44:0]), + .l2_tbnk1_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), + .l2_tbnk1_asq_full_flsh (l2_tbnk1_asq_full_flsh), + .l2_tbnk1_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), + .l2_tbnk1_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), + .l2_tbnk1_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), + .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), + .l2_tbnk1_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), + .l2_tbnk1_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), + .l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), + .l2_tbnk1_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), + .l2_tbnk1_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), + .l2_tbnk1_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), + .l2_tbnk1_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), + .l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), + .l2_tbnk1_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), + .l2_tbnk1_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), + .l2_tbnk1_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), + .l2_tbnk1_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), + .l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), + .l2_tbnk1_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), + .l2_tbnk1_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), + .l2_tbnk1_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), + .l2_tbnk1_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), + .l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), + .l2_tbnk1_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), + .l2_tbnk1_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_dirty_l1 (l2_tbnk1_dirty_l1), + .l2_tbnk1_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), + .l2_tbnk1_excl_l1 (l2_tbnk1_excl_l1), + .l2_tbnk1_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), + .l2_tbnk1_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), + .l2_tbnk1_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), + .l2_tbnk1_feq_kill_l3 (l2_tbnk1_feq_kill_l3), + .l2_tbnk1_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), + .l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk1_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), + .l2_tbnk1_id_l1 (l2_tbnk1_id_l1[9:0]), + .l2_tbnk1_init_req_l1 (l2_tbnk1_init_req_l1), + .l2_tbnk1_kill_l2 (l2_tbnk1_kill_l2), + .l2_tbnk1_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), + .l2_tbnk1_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), + .l2_tbnk1_last_qw_l1 (l2_tbnk1_last_qw_l1), + .l2_tbnk1_lock_l1 (l2_tbnk1_lock_l1[2:0]), + .l2_tbnk1_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), + .l2_tbnk1_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), + .l2_tbnk1_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), + .l2_tbnk1_prfm_l1 (l2_tbnk1_prfm_l1), + .l2_tbnk1_prot_l1 (l2_tbnk1_prot_l1[3:0]), + .l2_tbnk1_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), + .l2_tbnk1_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), + .l2_tbnk1_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), + .l2_tbnk1_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), + .l2_tbnk1_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), + .l2_tbnk1_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), + .l2_tbnk1_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), + .l2_tbnk1_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), + .l2_tbnk1_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), + .l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk1_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk1_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk1_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), + .l2_tbnk1_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk1_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), + .l2_tbnk1_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), + .l2_tbnk1_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), + .l2_tbnk1_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), + .l2_tbnk1_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), + .l2_tbnk1_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), + .l2_tbnk1_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), + .l2_tbnk1_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), + .l2_tbnk1_sel_l1 (l2_tbnk1_sel_l1[13:0]), + .l2_tbnk1_size_l1 (l2_tbnk1_size_l1[2:0]), + .l2_tbnk1_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), + .l2_tbnk1_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), + .l2_tbnk1_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), + .l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk1_sync_l1 (l2_tbnk1_sync_l1), + .l2_tbnk1_type_l1 (l2_tbnk1_type_l1[6:0]), + .l2_tbnk1_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), + .l2_tbnk1_way_l1 (l2_tbnk1_way_l1), + .l2_tbnk1_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), + .l2_tbnk1_wr_err_l1 (l2_tbnk1_wr_err_l1), + .l2_tbnk1_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), + .l2_tbnk1_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), + .l2_tbnk1_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), + .l2_tbnk1_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .nEXTERRIRQ (nEXTERRIRQ), + .nINTERRIRQ (nINTERRIRQ), + + // inputs + .ACADDRM (ACADDRM[43:0]), + .ACLKENM (ACLKENM), + .ACLKENS (ACLKENS), + .ACPROTM (ACPROTM[2:0]), + .ACSNOOPM (ACSNOOPM[3:0]), + .ACVALIDM (ACVALIDM), + .ARADDRS (ARADDRS[43:0]), + .ARCACHES (ARCACHES[3:0]), + .ARIDS (ARIDS[4:0]), + .ARLENS (ARLENS[7:0]), + .ARPROTS (ARPROTS[2:0]), + .ARREADYM (ARREADYM), + .ARUSERS (ARUSERS[1:0]), + .ARVALIDS (ARVALIDS), + .AWADDRS (AWADDRS[43:0]), + .AWCACHES (AWCACHES[3:0]), + .AWIDS (AWIDS[4:0]), + .AWLENS (AWLENS[7:0]), + .AWPROTS (AWPROTS[2:0]), + .AWREADYM (AWREADYM), + .AWUSERS (AWUSERS[1:0]), + .AWVALIDS (AWVALIDS), + .BIDM (BIDM[6:0]), + .BREADYS (BREADYS), + .BRESPM (BRESPM[1:0]), + .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), + .BROADCASTINNER (BROADCASTINNER), + .BROADCASTOUTER (BROADCASTOUTER), + .BVALIDM (BVALIDM), + .CDREADYM (CDREADYM), + .CRREADYM (CRREADYM), + .DBGL1RSTDISABLE (DBGL1RSTDISABLE), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .L2FLUSHREQ (L2FLUSHREQ), + .L2QREQn (L2QREQn), + .L2RSTDISABLE (L2RSTDISABLE), + .MBISTREQ (MBISTREQ), + .PERIPHBASE (PERIPHBASE[43:18]), + .RDATAM (RDATAM[127:0]), + .RIDM (RIDM[6:0]), + .RLASTM (RLASTM), + .RREADYS (RREADYS), + .RRESPM (RRESPM[3:0]), + .RVALIDM (RVALIDM), + .STANDBYWFIL2 (STANDBYWFIL2), + .SYSBARDISABLE (SYSBARDISABLE), + .WDATAS (WDATAS[127:0]), + .WLASTS (WLASTS), + .WREADYM (WREADYM), + .WSTRBS (WSTRBS[15:0]), + .WVALIDS (WVALIDS), + .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), + .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), + .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), + .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), + .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), + .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), + .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), + .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), + .ck_gclkfr (ck_gclkfr), + .ck_gclkl2 (ck_gclkl2), + .ck_l2_ace_inactive (ck_l2_ace_inactive), + .ck_l2_acp_inactive (ck_l2_acp_inactive), + .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), + .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), + .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), + .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), + .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), + .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), + .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), + .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), + .ic_p_rdata (ic_p_rdata[31:0]), + .ic_p_rdata_valid (ic_p_rdata_valid), + .ic_p_ready (ic_p_ready), + .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .l2_mbist2_tbnk0_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), + .l2_mbist2_tbnk0_all_b1 (l2_mbist2_tbnk0_all_b1), + .l2_mbist2_tbnk0_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), + .l2_mbist2_tbnk0_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), + .l2_mbist2_tbnk0_en_b1 (l2_mbist2_tbnk0_en_b1), + .l2_mbist2_tbnk0_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), + .l2_mbist2_tbnk0_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), + .l2_mbist2_tbnk0_sel_b1 (l2_mbist2_tbnk0_sel_b1), + .l2_mbist2_tbnk0_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), + .l2_mbist2_tbnk0_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), + .l2_mbist2_tbnk0_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), + .l2_mbist2_tbnk0_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), + .l2_mbist2_tbnk0_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), + .l2_mbist2_tbnk1_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), + .l2_mbist2_tbnk1_all_b1 (l2_mbist2_tbnk1_all_b1), + .l2_mbist2_tbnk1_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), + .l2_mbist2_tbnk1_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), + .l2_mbist2_tbnk1_en_b1 (l2_mbist2_tbnk1_en_b1), + .l2_mbist2_tbnk1_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), + .l2_mbist2_tbnk1_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), + .l2_mbist2_tbnk1_sel_b1 (l2_mbist2_tbnk1_sel_b1), + .l2_mbist2_tbnk1_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), + .l2_mbist2_tbnk1_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), + .l2_mbist2_tbnk1_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), + .l2_mbist2_tbnk1_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), + .l2_mbist2_tbnk1_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), + .l2_tbnk0_addr44_l3_q (l2_tbnk0_addr44_l3_q), + .l2_tbnk0_addr_l6 (l2_tbnk0_addr_l6[5:2]), + .l2_tbnk0_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), + .l2_tbnk0_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), + .l2_tbnk0_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), + .l2_tbnk0_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), + .l2_tbnk0_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), + .l2_tbnk0_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), + .l2_tbnk0_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), + .l2_tbnk0_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), + .l2_tbnk0_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), + .l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), + .l2_tbnk0_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), + .l2_tbnk0_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), + .l2_tbnk0_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), + .l2_tbnk0_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), + .l2_tbnk0_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), + .l2_tbnk0_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), + .l2_tbnk0_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), + .l2_tbnk0_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), + .l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), + .l2_tbnk0_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), + .l2_tbnk0_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), + .l2_tbnk0_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), + .l2_tbnk0_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), + .l2_tbnk0_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), + .l2_tbnk0_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), + .l2_tbnk0_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), + .l2_tbnk0_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), + .l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), + .l2_tbnk0_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), + .l2_tbnk0_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), + .l2_tbnk0_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), + .l2_tbnk0_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), + .l2_tbnk0_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), + .l2_tbnk0_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), + .l2_tbnk0_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), + .l2_tbnk0_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), + .l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), + .l2_tbnk0_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), + .l2_tbnk0_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk0_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk0_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk0_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), + .l2_tbnk0_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), + .l2_tbnk0_data_l6 (l2_tbnk0_data_l6[127:0]), + .l2_tbnk0_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), + .l2_tbnk0_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk0_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk0_dirty_l3_q (l2_tbnk0_dirty_l3_q), + .l2_tbnk0_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), + .l2_tbnk0_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), + .l2_tbnk0_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), + .l2_tbnk0_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), + .l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk0_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), + .l2_tbnk0_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), + .l2_tbnk0_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), + .l2_tbnk0_excl_l4_q (l2_tbnk0_excl_l4_q), + .l2_tbnk0_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), + .l2_tbnk0_feq_clr_l4 (l2_tbnk0_feq_clr_l4), + .l2_tbnk0_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), + .l2_tbnk0_hit_l4 (l2_tbnk0_hit_l4), + .l2_tbnk0_hit_l7_q (l2_tbnk0_hit_l7_q), + .l2_tbnk0_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), + .l2_tbnk0_id_l6_q (l2_tbnk0_id_l6_q[9:0]), + .l2_tbnk0_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), + .l2_tbnk0_idle (l2_tbnk0_idle), + .l2_tbnk0_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), + .l2_tbnk0_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), + .l2_tbnk0_l2v_s_q (l2_tbnk0_l2v_s_q), + .l2_tbnk0_l2v_vld_q (l2_tbnk0_l2v_vld_q), + .l2_tbnk0_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), + .l2_tbnk0_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), + .l2_tbnk0_lock_l4 (l2_tbnk0_lock_l4[2:0]), + .l2_tbnk0_merrsr_data (l2_tbnk0_merrsr_data[32:0]), + .l2_tbnk0_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), + .l2_tbnk0_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), + .l2_tbnk0_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), + .l2_tbnk0_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), + .l2_tbnk0_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), + .l2_tbnk0_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), + .l2_tbnk0_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), + .l2_tbnk0_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), + .l2_tbnk0_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), + .l2_tbnk0_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), + .l2_tbnk0_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk0_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk0_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), + .l2_tbnk0_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), + .l2_tbnk0_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), + .l2_tbnk0_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk0_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), + .l2_tbnk0_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), + .l2_tbnk0_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), + .l2_tbnk0_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), + .l2_tbnk0_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk0_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), + .l2_tbnk0_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk0_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), + .l2_tbnk0_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), + .l2_tbnk0_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), + .l2_tbnk0_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), + .l2_tbnk0_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), + .l2_tbnk0_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), + .l2_tbnk0_size_l4_q (l2_tbnk0_size_l4_q[2:0]), + .l2_tbnk0_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), + .l2_tbnk0_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), + .l2_tbnk0_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk0_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk0_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk0_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), + .l2_tbnk0_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), + .l2_tbnk0_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk0_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), + .l2_tbnk0_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), + .l2_tbnk0_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), + .l2_tbnk0_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), + .l2_tbnk0_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), + .l2_tbnk0_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), + .l2_tbnk0_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), + .l2_tbnk0_vld_l6_q (l2_tbnk0_vld_l6_q), + .l2_tbnk0_way_l4_q (l2_tbnk0_way_l4_q), + .l2_tbnk0_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), + .l2_tbnk0_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), + .l2_tbnk0_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), + .l2_tbnk0_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), + .l2_tbnk1_addr44_l3_q (l2_tbnk1_addr44_l3_q), + .l2_tbnk1_addr_l6 (l2_tbnk1_addr_l6[5:2]), + .l2_tbnk1_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), + .l2_tbnk1_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), + .l2_tbnk1_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), + .l2_tbnk1_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), + .l2_tbnk1_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), + .l2_tbnk1_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), + .l2_tbnk1_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), + .l2_tbnk1_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), + .l2_tbnk1_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), + .l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), + .l2_tbnk1_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), + .l2_tbnk1_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), + .l2_tbnk1_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), + .l2_tbnk1_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), + .l2_tbnk1_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), + .l2_tbnk1_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), + .l2_tbnk1_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), + .l2_tbnk1_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), + .l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), + .l2_tbnk1_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), + .l2_tbnk1_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), + .l2_tbnk1_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), + .l2_tbnk1_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), + .l2_tbnk1_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), + .l2_tbnk1_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), + .l2_tbnk1_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), + .l2_tbnk1_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), + .l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), + .l2_tbnk1_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), + .l2_tbnk1_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), + .l2_tbnk1_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), + .l2_tbnk1_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), + .l2_tbnk1_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), + .l2_tbnk1_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), + .l2_tbnk1_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), + .l2_tbnk1_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), + .l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), + .l2_tbnk1_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), + .l2_tbnk1_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk1_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk1_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk1_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), + .l2_tbnk1_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), + .l2_tbnk1_data_l6 (l2_tbnk1_data_l6[127:0]), + .l2_tbnk1_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), + .l2_tbnk1_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk1_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk1_dirty_l3_q (l2_tbnk1_dirty_l3_q), + .l2_tbnk1_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), + .l2_tbnk1_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), + .l2_tbnk1_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), + .l2_tbnk1_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), + .l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk1_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), + .l2_tbnk1_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), + .l2_tbnk1_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), + .l2_tbnk1_excl_l4_q (l2_tbnk1_excl_l4_q), + .l2_tbnk1_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), + .l2_tbnk1_feq_clr_l4 (l2_tbnk1_feq_clr_l4), + .l2_tbnk1_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), + .l2_tbnk1_hit_l4 (l2_tbnk1_hit_l4), + .l2_tbnk1_hit_l7_q (l2_tbnk1_hit_l7_q), + .l2_tbnk1_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), + .l2_tbnk1_id_l6_q (l2_tbnk1_id_l6_q[9:0]), + .l2_tbnk1_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), + .l2_tbnk1_idle (l2_tbnk1_idle), + .l2_tbnk1_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), + .l2_tbnk1_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), + .l2_tbnk1_l2v_s_q (l2_tbnk1_l2v_s_q), + .l2_tbnk1_l2v_vld_q (l2_tbnk1_l2v_vld_q), + .l2_tbnk1_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), + .l2_tbnk1_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), + .l2_tbnk1_lock_l4 (l2_tbnk1_lock_l4[2:0]), + .l2_tbnk1_merrsr_data (l2_tbnk1_merrsr_data[32:0]), + .l2_tbnk1_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), + .l2_tbnk1_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), + .l2_tbnk1_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), + .l2_tbnk1_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), + .l2_tbnk1_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), + .l2_tbnk1_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), + .l2_tbnk1_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), + .l2_tbnk1_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), + .l2_tbnk1_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), + .l2_tbnk1_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), + .l2_tbnk1_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk1_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk1_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), + .l2_tbnk1_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), + .l2_tbnk1_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), + .l2_tbnk1_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk1_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), + .l2_tbnk1_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), + .l2_tbnk1_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), + .l2_tbnk1_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), + .l2_tbnk1_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk1_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), + .l2_tbnk1_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk1_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), + .l2_tbnk1_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), + .l2_tbnk1_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), + .l2_tbnk1_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), + .l2_tbnk1_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), + .l2_tbnk1_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), + .l2_tbnk1_size_l4_q (l2_tbnk1_size_l4_q[2:0]), + .l2_tbnk1_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), + .l2_tbnk1_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), + .l2_tbnk1_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk1_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk1_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk1_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), + .l2_tbnk1_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), + .l2_tbnk1_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk1_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), + .l2_tbnk1_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), + .l2_tbnk1_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), + .l2_tbnk1_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), + .l2_tbnk1_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), + .l2_tbnk1_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), + .l2_tbnk1_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), + .l2_tbnk1_vld_l6_q (l2_tbnk1_vld_l6_q), + .l2_tbnk1_way_l4_q (l2_tbnk1_way_l4_q), + .l2_tbnk1_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), + .l2_tbnk1_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), + .l2_tbnk1_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), + .l2_tbnk1_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), + .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), + .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), + .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), + .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), + .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), + .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), + .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]) + ); // ul2_logic + + maia_l2_tbnk ul2_tbnk0( // outputs + .l2_mbist2_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), + .l2_mbist2_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), + .l2_mbist2_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), + .l2_mbist2_en_b1 (l2_mbist2_tbnk0_en_b1), + .l2_mbist2_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), + .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk0_all_b1), + .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), + .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk0_sel_b1), + .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), + .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), + .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), + .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), + .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), + .l2_tbnk_addr44_l3_q (l2_tbnk0_addr44_l3_q), + .l2_tbnk_addr_l6 (l2_tbnk0_addr_l6[5:2]), + .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), + .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), + .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), + .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), + .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), + .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), + .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), + .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), + .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), + .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), + .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), + .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), + .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), + .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), + .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), + .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), + .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), + .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), + .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), + .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), + .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), + .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), + .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), + .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), + .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), + .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), + .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), + .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), + .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), + .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), + .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), + .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), + .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), + .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), + .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), + .l2_tbnk_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), + .l2_tbnk_data_l6 (l2_tbnk0_data_l6[127:0]), + .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), + .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk_dirty_l3_q (l2_tbnk0_dirty_l3_q), + .l2_tbnk_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), + .l2_tbnk_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), + .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), + .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), + .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), + .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), + .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), + .l2_tbnk_excl_l4_q (l2_tbnk0_excl_l4_q), + .l2_tbnk_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), + .l2_tbnk_feq_clr_l4 (l2_tbnk0_feq_clr_l4), + .l2_tbnk_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), + .l2_tbnk_hit_l4 (l2_tbnk0_hit_l4), + .l2_tbnk_hit_l7_q (l2_tbnk0_hit_l7_q), + .l2_tbnk_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), + .l2_tbnk_id_l6_q (l2_tbnk0_id_l6_q[9:0]), + .l2_tbnk_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), + .l2_tbnk_idle (l2_tbnk0_idle), + .l2_tbnk_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), + .l2_tbnk_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), + .l2_tbnk_l2v_s_q (l2_tbnk0_l2v_s_q), + .l2_tbnk_l2v_vld_q (l2_tbnk0_l2v_vld_q), + .l2_tbnk_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), + .l2_tbnk_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), + .l2_tbnk_lock_l4 (l2_tbnk0_lock_l4[2:0]), + .l2_tbnk_merrsr_data (l2_tbnk0_merrsr_data[32:0]), + .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), + .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), + .l2_tbnk_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), + .l2_tbnk_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), + .l2_tbnk_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), + .l2_tbnk_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), + .l2_tbnk_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), + .l2_tbnk_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), + .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), + .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), + .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), + .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), + .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), + .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), + .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), + .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), + .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), + .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), + .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), + .l2_tbnk_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), + .l2_tbnk_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), + .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), + .l2_tbnk_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), + .l2_tbnk_size_l4_q (l2_tbnk0_size_l4_q[2:0]), + .l2_tbnk_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), + .l2_tbnk_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), + .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), + .l2_tbnk_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), + .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), + .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), + .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), + .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), + .l2_tbnk_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), + .l2_tbnk_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), + .l2_tbnk_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), + .l2_tbnk_vld_l6_q (l2_tbnk0_vld_l6_q), + .l2_tbnk_way_l4_q (l2_tbnk0_way_l4_q), + .l2_tbnk_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), + .l2_tbnk_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), + .l2_tbnk_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), + .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), + + // inputs + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ), + .ck_areset_l2 (ck_areset_l2), + .ck_gclkl2 (ck_gclkb0), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), + .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), + .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), + .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), + .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), + .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), + .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), + .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_skyros_intf (1'b0), + .l2_tbnk_addr_l1 (l2_tbnk0_addr_l1[44:0]), + .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), + .l2_tbnk_asq_full_flsh (l2_tbnk0_asq_full_flsh), + .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), + .l2_tbnk_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), + .l2_tbnk_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), + .l2_tbnk_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), + .l2_tbnk_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), + .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), + .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), + .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), + .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), + .l2_tbnk_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), + .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), + .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), + .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), + .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), + .l2_tbnk_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), + .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), + .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), + .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), + .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), + .l2_tbnk_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), + .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), + .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), + .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), + .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_dirty_l1 (l2_tbnk0_dirty_l1), + .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), + .l2_tbnk_excl_l1 (l2_tbnk0_excl_l1), + .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), + .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), + .l2_tbnk_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), + .l2_tbnk_feq_kill_l3 (l2_tbnk0_feq_kill_l3), + .l2_tbnk_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), + .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .l2_tbnk_id_l1 (l2_tbnk0_id_l1[9:0]), + .l2_tbnk_init_req_l1 (l2_tbnk0_init_req_l1), + .l2_tbnk_kill_l2 (l2_tbnk0_kill_l2), + .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), + .l2_tbnk_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), + .l2_tbnk_last_qw_l1 (l2_tbnk0_last_qw_l1), + .l2_tbnk_lock_l1 (l2_tbnk0_lock_l1[2:0]), + .l2_tbnk_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), + .l2_tbnk_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), + .l2_tbnk_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), + .l2_tbnk_prfm_l1 (l2_tbnk0_prfm_l1), + .l2_tbnk_prot_l1 (l2_tbnk0_prot_l1[3:0]), + .l2_tbnk_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), + .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), + .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), + .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), + .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), + .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), + .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), + .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), + .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), + .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), + .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), + .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), + .l2_tbnk_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), + .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), + .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), + .l2_tbnk_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), + .l2_tbnk_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), + .l2_tbnk_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), + .l2_tbnk_sel_l1 (l2_tbnk0_sel_l1[13:0]), + .l2_tbnk_size_l1 (l2_tbnk0_size_l1[2:0]), + .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), + .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), + .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), + .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_sync_l1 (l2_tbnk0_sync_l1), + .l2_tbnk_type_l1 (l2_tbnk0_type_l1[6:0]), + .l2_tbnk_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), + .l2_tbnk_way_l1 (l2_tbnk0_way_l1), + .l2_tbnk_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), + .l2_tbnk_wr_err_l1 (l2_tbnk0_wr_err_l1), + .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), + .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), + .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), + .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]) + ); // ul2_tbnk0 + + maia_l2_tbnk ul2_tbnk1( // outputs + .l2_mbist2_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), + .l2_mbist2_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), + .l2_mbist2_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), + .l2_mbist2_en_b1 (l2_mbist2_tbnk1_en_b1), + .l2_mbist2_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), + .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk1_all_b1), + .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), + .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk1_sel_b1), + .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), + .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), + .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), + .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), + .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), + .l2_tbnk_addr44_l3_q (l2_tbnk1_addr44_l3_q), + .l2_tbnk_addr_l6 (l2_tbnk1_addr_l6[5:2]), + .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), + .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), + .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), + .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), + .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), + .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), + .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), + .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), + .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), + .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), + .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), + .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), + .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), + .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), + .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), + .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), + .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), + .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), + .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), + .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), + .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), + .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), + .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), + .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), + .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), + .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), + .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), + .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), + .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), + .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), + .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), + .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), + .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), + .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), + .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), + .l2_tbnk_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), + .l2_tbnk_data_l6 (l2_tbnk1_data_l6[127:0]), + .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), + .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk_dirty_l3_q (l2_tbnk1_dirty_l3_q), + .l2_tbnk_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), + .l2_tbnk_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), + .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), + .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), + .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), + .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), + .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), + .l2_tbnk_excl_l4_q (l2_tbnk1_excl_l4_q), + .l2_tbnk_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), + .l2_tbnk_feq_clr_l4 (l2_tbnk1_feq_clr_l4), + .l2_tbnk_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), + .l2_tbnk_hit_l4 (l2_tbnk1_hit_l4), + .l2_tbnk_hit_l7_q (l2_tbnk1_hit_l7_q), + .l2_tbnk_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), + .l2_tbnk_id_l6_q (l2_tbnk1_id_l6_q[9:0]), + .l2_tbnk_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), + .l2_tbnk_idle (l2_tbnk1_idle), + .l2_tbnk_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), + .l2_tbnk_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), + .l2_tbnk_l2v_s_q (l2_tbnk1_l2v_s_q), + .l2_tbnk_l2v_vld_q (l2_tbnk1_l2v_vld_q), + .l2_tbnk_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), + .l2_tbnk_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), + .l2_tbnk_lock_l4 (l2_tbnk1_lock_l4[2:0]), + .l2_tbnk_merrsr_data (l2_tbnk1_merrsr_data[32:0]), + .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), + .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), + .l2_tbnk_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), + .l2_tbnk_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), + .l2_tbnk_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), + .l2_tbnk_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), + .l2_tbnk_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), + .l2_tbnk_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), + .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), + .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), + .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), + .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), + .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), + .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), + .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), + .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), + .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), + .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), + .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), + .l2_tbnk_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), + .l2_tbnk_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), + .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), + .l2_tbnk_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), + .l2_tbnk_size_l4_q (l2_tbnk1_size_l4_q[2:0]), + .l2_tbnk_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), + .l2_tbnk_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), + .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), + .l2_tbnk_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), + .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), + .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), + .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), + .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), + .l2_tbnk_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), + .l2_tbnk_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), + .l2_tbnk_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), + .l2_tbnk_vld_l6_q (l2_tbnk1_vld_l6_q), + .l2_tbnk_way_l4_q (l2_tbnk1_way_l4_q), + .l2_tbnk_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), + .l2_tbnk_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), + .l2_tbnk_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), + .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), + + // inputs + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ), + .ck_areset_l2 (ck_areset_l2), + .ck_gclkl2 (ck_gclkb1), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), + .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), + .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), + .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), + .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), + .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), + .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), + .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_skyros_intf (1'b0), + .l2_tbnk_addr_l1 (l2_tbnk1_addr_l1[44:0]), + .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), + .l2_tbnk_asq_full_flsh (l2_tbnk1_asq_full_flsh), + .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), + .l2_tbnk_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), + .l2_tbnk_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), + .l2_tbnk_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), + .l2_tbnk_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), + .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), + .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), + .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), + .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), + .l2_tbnk_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), + .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), + .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), + .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), + .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), + .l2_tbnk_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), + .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), + .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), + .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), + .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), + .l2_tbnk_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), + .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), + .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), + .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), + .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_dirty_l1 (l2_tbnk1_dirty_l1), + .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), + .l2_tbnk_excl_l1 (l2_tbnk1_excl_l1), + .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), + .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), + .l2_tbnk_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), + .l2_tbnk_feq_kill_l3 (l2_tbnk1_feq_kill_l3), + .l2_tbnk_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), + .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .l2_tbnk_id_l1 (l2_tbnk1_id_l1[9:0]), + .l2_tbnk_init_req_l1 (l2_tbnk1_init_req_l1), + .l2_tbnk_kill_l2 (l2_tbnk1_kill_l2), + .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), + .l2_tbnk_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), + .l2_tbnk_last_qw_l1 (l2_tbnk1_last_qw_l1), + .l2_tbnk_lock_l1 (l2_tbnk1_lock_l1[2:0]), + .l2_tbnk_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), + .l2_tbnk_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), + .l2_tbnk_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), + .l2_tbnk_prfm_l1 (l2_tbnk1_prfm_l1), + .l2_tbnk_prot_l1 (l2_tbnk1_prot_l1[3:0]), + .l2_tbnk_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), + .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), + .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), + .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), + .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), + .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), + .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), + .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), + .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), + .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), + .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), + .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), + .l2_tbnk_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), + .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), + .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), + .l2_tbnk_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), + .l2_tbnk_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), + .l2_tbnk_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), + .l2_tbnk_sel_l1 (l2_tbnk1_sel_l1[13:0]), + .l2_tbnk_size_l1 (l2_tbnk1_size_l1[2:0]), + .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), + .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), + .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), + .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_sync_l1 (l2_tbnk1_sync_l1), + .l2_tbnk_type_l1 (l2_tbnk1_type_l1[6:0]), + .l2_tbnk_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), + .l2_tbnk_way_l1 (l2_tbnk1_way_l1), + .l2_tbnk_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), + .l2_tbnk_wr_err_l1 (l2_tbnk1_wr_err_l1), + .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), + .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), + .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), + .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]) + ); // ul2_tbnk1 + + maia_dt_pclk udt_pclk( // outputs + .CTICHINACK (CTICHINACK[3:0]), + .CTICHOUT (CTICHOUT[3:0]), + .CTIIRQ (CTIIRQ[`MAIA_CN:0]), + .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), + .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), + .PRDATADBG (PRDATADBG[31:0]), + .PREADYDBG (PREADYDBG), + .PSLVERRDBG (PSLVERRDBG), + .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), + .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), + .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), + .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), + .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), + .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), + .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), + .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), + .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + + // inputs + .CIHSBYPASS (CIHSBYPASS[3:0]), + .CISBYPASS (CISBYPASS), + .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), + .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), + .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), + .CTICHIN (CTICHIN[3:0]), + .CTICHOUTACK (CTICHOUTACK[3:0]), + .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), + .DBGEN (DBGEN[`MAIA_CN:0]), + .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .EDBGRQ (EDBGRQ[`MAIA_CN:0]), + .GICCDISABLE (GICCDISABLE), + .NIDEN (NIDEN[`MAIA_CN:0]), + .PADDRDBG (PADDRDBG[21:2]), + .PADDRDBG31 (PADDRDBG31), + .PCLKDBG (PCLKDBG), + .PCLKENDBG (PCLKENDBG), + .PENABLEDBG (PENABLEDBG), + .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), + .PSELDBG (PSELDBG), + .PWDATADBG (PWDATADBG[31:0]), + .PWRITEDBG (PWRITEDBG), + .SPIDEN (SPIDEN[`MAIA_CN:0]), + .SPNIDEN (SPNIDEN[`MAIA_CN:0]), + .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), + .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), + .ck_cpu0_poreset_status (ck_cpu0_poreset_status), + .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), + .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), + .ck_cpu1_poreset_status (ck_cpu1_poreset_status), + .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), + .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), + .ck_cpu2_poreset_status (ck_cpu2_poreset_status), + .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), + .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), + .ck_cpu3_poreset_status (ck_cpu3_poreset_status), + .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), + .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), + .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), + .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), + .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), + .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), + .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), + .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), + .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), + .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), + .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), + .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), + .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), + .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), + .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), + .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), + .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), + .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), + .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), + .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), + .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), + .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), + .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), + .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), + .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .nPRESETDBG (nPRESETDBG) + ); // udt_pclk + + maia_intctrl uic( // outputs + .ICCTDATA (ICCTDATA[15:0]), + .ICCTID (ICCTID[1:0]), + .ICCTLAST (ICCTLAST), + .ICCTVALID (ICCTVALID), + .ICDTREADY (ICDTREADY), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), + .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), + .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), + .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), + .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), + .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), + .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), + .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), + .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), + .ic_el_change_complete_o (ic_el_change_complete_o[`MAIA_CN:0]), + .ic_hcr_change_complete_o (ic_hcr_change_complete_o[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .ic_p_rdata (ic_p_rdata[31:0]), + .ic_p_rdata_valid (ic_p_rdata_valid), + .ic_p_ready (ic_p_ready), + .ic_p_valid (ic_p_valid[`MAIA_CN:0]), + .ic_sample_spr_o (ic_sample_spr_o[`MAIA_CN:0]), + .ic_scr_change_complete_o (ic_scr_change_complete_o[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]), + .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), + + // inputs + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .GICCDISABLE (GICCDISABLE), + .ICCTREADY (ICCTREADY), + .ICDTDATA (ICDTDATA[15:0]), + .ICDTDEST (ICDTDEST[1:0]), + .ICDTLAST (ICDTLAST), + .ICDTVALID (ICDTVALID), + .ck_areset_l2 (ck_areset_l2), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_aa64naa32_i (ds_cpu0_ic_aa64naa32_i), + .ds_cpu0_cpsr_mode_i (ds_cpu0_ic_cpsr_mode_i[4:0]), + .ds_cpu0_hcr_change_i (ds_cpu0_ic_hcr_change_i), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu0_sample_spr_i (ds_cpu0_ic_sample_spr_i), + .ds_cpu0_scr_change_i (ds_cpu0_ic_scr_change_i), + .ds_cpu1_aa64naa32_i (ds_cpu1_ic_aa64naa32_i), + .ds_cpu1_cpsr_mode_i (ds_cpu1_ic_cpsr_mode_i[4:0]), + .ds_cpu1_hcr_change_i (ds_cpu1_ic_hcr_change_i), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu1_sample_spr_i (ds_cpu1_ic_sample_spr_i), + .ds_cpu1_scr_change_i (ds_cpu1_ic_scr_change_i), + .ds_cpu2_aa64naa32_i (ds_cpu2_ic_aa64naa32_i), + .ds_cpu2_cpsr_mode_i (ds_cpu2_ic_cpsr_mode_i[4:0]), + .ds_cpu2_hcr_change_i (ds_cpu2_ic_hcr_change_i), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu2_sample_spr_i (ds_cpu2_ic_sample_spr_i), + .ds_cpu2_scr_change_i (ds_cpu2_ic_scr_change_i), + .ds_cpu3_aa64naa32_i (ds_cpu3_ic_aa64naa32_i), + .ds_cpu3_cpsr_mode_i (ds_cpu3_ic_cpsr_mode_i[4:0]), + .ds_cpu3_hcr_change_i (ds_cpu3_ic_hcr_change_i), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_cpu3_sample_spr_i (ds_cpu3_ic_sample_spr_i), + .ds_cpu3_scr_change_i (ds_cpu3_ic_scr_change_i), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_cpu0_wr_decerr_i (l2_cpu0_wr_decerr_q), + .l2_cpu0_wr_slverr_i (l2_cpu0_wr_slverr_q), + .l2_cpu1_wr_decerr_i (l2_cpu1_wr_decerr_q), + .l2_cpu1_wr_slverr_i (l2_cpu1_wr_slverr_q), + .l2_cpu2_wr_decerr_i (l2_cpu2_wr_decerr_q), + .l2_cpu2_wr_slverr_i (l2_cpu2_wr_slverr_q), + .l2_cpu3_wr_decerr_i (l2_cpu3_wr_decerr_q), + .l2_cpu3_wr_slverr_i (l2_cpu3_wr_slverr_q), + .l2_p_addr (l2_p_addr[13:0]), + .l2_p_cpu (l2_p_cpu[1:0]), + .l2_p_nsecure (l2_p_nsecure), + .l2_p_sel (l2_p_sel[2:0]), + .l2_p_wdata (l2_p_wdata[31:0]), + .l2_p_write (l2_p_write), + .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), + .nFIQ (nFIQ[`MAIA_CN:0]), + .nIRQ (nIRQ[`MAIA_CN:0]), + .nREI (nREI[`MAIA_CN:0]), + .nSEI (nSEI[`MAIA_CN:0]), + .nVFIQ (nVFIQ[`MAIA_CN:0]), + .nVIRQ (nVIRQ[`MAIA_CN:0]), + .nVSEI (nVSEI[`MAIA_CN:0]) + ); // uic + + maia_ck_l2 uck_l2( // outputs + .ck_gclkb0 (ck_gclkb0), + .ck_gclkb1 (ck_gclkb1), + .ck_gclkfr (ck_gclkfr), + .ck_gclkl2 (ck_gclkl2), + + // inputs + .DFTL2CLKDISABLE (DFTL2CLKDISABLE), + .DFTSE (DFTSE), + .ck_gclktl2 (ck_gclktl2), + .ck_l2_logic_clk_en (ck_l2_logic_clk_en), + .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), + .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), + .l2_reset3 (l2_reset3) + ); // uck_l2 + + maia_ck_top uck_top( // outputs + .ck_gclkt (ck_gclkt[`MAIA_CN:0]), + .ck_gclktl2 (ck_gclktl2), + + // inputs + .CLK (CLK), + .CLKEN (CLKEN), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ) + ); // uck_top + + maia_ck_logic uck_logic( // outputs + .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), + .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), + .CPUQDENY (CPUQDENY[`MAIA_CN:0]), + .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), + .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), + .STANDBYWFIL2 (STANDBYWFIL2), + .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), + .ck_cpu0_commrx (ck_cpu0_commrx), + .ck_cpu0_commtx (ck_cpu0_commtx), + .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), + .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), + .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), + .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), + .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), + .ck_cpu0_event_reg (ck_cpu0_event_reg), + .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), + .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), + .ck_cpu0_ncommirq (ck_cpu0_ncommirq), + .ck_cpu0_npmuirq (ck_cpu0_npmuirq), + .ck_cpu0_poreset_status (ck_cpu0_poreset_status), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), + .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), + .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), + .ck_cpu1_commrx (ck_cpu1_commrx), + .ck_cpu1_commtx (ck_cpu1_commtx), + .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), + .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), + .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), + .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), + .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), + .ck_cpu1_event_reg (ck_cpu1_event_reg), + .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), + .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), + .ck_cpu1_ncommirq (ck_cpu1_ncommirq), + .ck_cpu1_npmuirq (ck_cpu1_npmuirq), + .ck_cpu1_poreset_status (ck_cpu1_poreset_status), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), + .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), + .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), + .ck_cpu2_commrx (ck_cpu2_commrx), + .ck_cpu2_commtx (ck_cpu2_commtx), + .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), + .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), + .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), + .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), + .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), + .ck_cpu2_event_reg (ck_cpu2_event_reg), + .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), + .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), + .ck_cpu2_ncommirq (ck_cpu2_ncommirq), + .ck_cpu2_npmuirq (ck_cpu2_npmuirq), + .ck_cpu2_poreset_status (ck_cpu2_poreset_status), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), + .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), + .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), + .ck_cpu3_commrx (ck_cpu3_commrx), + .ck_cpu3_commtx (ck_cpu3_commtx), + .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), + .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), + .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), + .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), + .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), + .ck_cpu3_event_reg (ck_cpu3_event_reg), + .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), + .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), + .ck_cpu3_ncommirq (ck_cpu3_ncommirq), + .ck_cpu3_npmuirq (ck_cpu3_npmuirq), + .ck_cpu3_poreset_status (ck_cpu3_poreset_status), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), + .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), + .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), + .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), + .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), + .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), + .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), + .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), + .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), + .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), + .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), + .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), + .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), + .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), + .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), + .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), + .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), + .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), + .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), + .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), + .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), + .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), + .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), + .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), + .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), + .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), + .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), + .ck_l2_ace_inactive (ck_l2_ace_inactive), + .ck_l2_acp_inactive (ck_l2_acp_inactive), + .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), + + // inputs + .ACINACTM (ACINACTM), + .AINACTS (AINACTS), + .CPUQREQn (CPUQREQn[`MAIA_CN:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .ck_gclkfr (ck_gclkfr), + .clrexmon_c1 (clrexmon_c1), + .commrx_cpu0_i (commrx_cpu0_i), + .commrx_cpu1_i (commrx_cpu1_i), + .commrx_cpu2_i (commrx_cpu2_i), + .commrx_cpu3_i (commrx_cpu3_i), + .commtx_cpu0_i (commtx_cpu0_i), + .commtx_cpu1_i (commtx_cpu1_i), + .commtx_cpu2_i (commtx_cpu2_i), + .commtx_cpu3_i (commtx_cpu3_i), + .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), + .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), + .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), + .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), + .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), + .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), + .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), + .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_cpu0_flush (ds_cpu0_flush), + .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), + .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), + .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_cpu0_reset_req (ds_cpu0_reset_req), + .ds_cpu0_sevl_req (ds_cpu0_sevl_req), + .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_cpu0_wfe_req (ds_cpu0_wfe_req), + .ds_cpu0_wfi_req (ds_cpu0_wfi_req), + .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_cpu1_flush (ds_cpu1_flush), + .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), + .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), + .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_cpu1_reset_req (ds_cpu1_reset_req), + .ds_cpu1_sevl_req (ds_cpu1_sevl_req), + .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_cpu1_wfe_req (ds_cpu1_wfe_req), + .ds_cpu1_wfi_req (ds_cpu1_wfi_req), + .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_cpu2_flush (ds_cpu2_flush), + .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), + .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), + .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_cpu2_reset_req (ds_cpu2_reset_req), + .ds_cpu2_sevl_req (ds_cpu2_sevl_req), + .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_cpu2_wfe_req (ds_cpu2_wfe_req), + .ds_cpu2_wfi_req (ds_cpu2_wfi_req), + .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_cpu3_flush (ds_cpu3_flush), + .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), + .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), + .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_cpu3_reset_req (ds_cpu3_reset_req), + .ds_cpu3_sevl_req (ds_cpu3_sevl_req), + .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_cpu3_wfe_req (ds_cpu3_wfe_req), + .ds_cpu3_wfi_req (ds_cpu3_wfi_req), + .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), + .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), + .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), + .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), + .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), + .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), + .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), + .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), + .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_cpu0_snp_active (l2_cpu0_snp_active), + .l2_cpu1_snp_active (l2_cpu1_snp_active), + .l2_cpu2_snp_active (l2_cpu2_snp_active), + .l2_cpu3_snp_active (l2_cpu3_snp_active), + .l2_idle (l2_idle), + .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), + .l2_reset3 (l2_reset3), + .l2_sky_link_stopped (1'b1), + .ls_cpu0_clrexmon (ls_cpu0_clrexmon), + .ls_cpu1_clrexmon (ls_cpu1_clrexmon), + .ls_cpu2_clrexmon (ls_cpu2_clrexmon), + .ls_cpu3_clrexmon (ls_cpu3_clrexmon), + .nCORERESET (nCORERESET[`MAIA_CN:0]), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .ncommirq_cpu0_i (ncommirq_cpu0_i), + .ncommirq_cpu1_i (ncommirq_cpu1_i), + .ncommirq_cpu2_i (ncommirq_cpu2_i), + .ncommirq_cpu3_i (ncommirq_cpu3_i), + .npmuirq_cpu0_i (npmuirq_cpu0_i), + .npmuirq_cpu1_i (npmuirq_cpu1_i), + .npmuirq_cpu2_i (npmuirq_cpu2_i), + .npmuirq_cpu3_i (npmuirq_cpu3_i), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_event_sev (tm_cpu0_event_sev), + .tm_cpu1_event_sev (tm_cpu1_event_sev), + .tm_cpu2_event_sev (tm_cpu2_event_sev), + .tm_cpu3_event_sev (tm_cpu3_event_sev) + ); // uck_logic + + maia_cpu_io ucpu_io( // outputs + .aa64naa32_cpu0_o (aa64naa32_cpu0_o), + .aa64naa32_cpu1_o (aa64naa32_cpu1_o), + .aa64naa32_cpu2_o (aa64naa32_cpu2_o), + .aa64naa32_cpu3_o (aa64naa32_cpu3_o), + .cfgend_cpu0_o (cfgend_cpu0_o), + .cfgend_cpu1_o (cfgend_cpu1_o), + .cfgend_cpu2_o (cfgend_cpu2_o), + .cfgend_cpu3_o (cfgend_cpu3_o), + .cfgte_cpu0_o (cfgte_cpu0_o), + .cfgte_cpu1_o (cfgte_cpu1_o), + .cfgte_cpu2_o (cfgte_cpu2_o), + .cfgte_cpu3_o (cfgte_cpu3_o), + .clrexmon_c1 (clrexmon_c1), + .clrexmonack_o (CLREXMONACK), + .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), + .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), + .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), + .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), + .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), + .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), + .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), + .commrx_o (COMMRX[`MAIA_CN:0]), + .commtx_o (COMMTX[`MAIA_CN:0]), + .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), + .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), + .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), + .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), + .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), + .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), + .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), + .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu0_o (cryptodisable_cpu0_o), + .cryptodisable_cpu1_o (cryptodisable_cpu1_o), + .cryptodisable_cpu2_o (cryptodisable_cpu2_o), + .cryptodisable_cpu3_o (cryptodisable_cpu3_o), + .dbgack_o (DBGACK[`MAIA_CN:0]), + .dbgen_cpu0_o (dbgen_cpu0_o), + .dbgen_cpu1_o (dbgen_cpu1_o), + .dbgen_cpu2_o (dbgen_cpu2_o), + .dbgen_cpu3_o (dbgen_cpu3_o), + .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), + .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), + .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), + .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), + .dbgnopwrdwn_o (DBGNOPWRDWN[`MAIA_CN:0]), + .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), + .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), + .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), + .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), + .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), + .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), + .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), + .dbgrstreq_o (DBGRSTREQ[`MAIA_CN:0]), + .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), + .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), + .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), + .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), + .dftramhold_cpu0_o (dftramhold_cpu0_o), + .dftramhold_cpu1_o (dftramhold_cpu1_o), + .dftramhold_cpu2_o (dftramhold_cpu2_o), + .dftramhold_cpu3_o (dftramhold_cpu3_o), + .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), + .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), + .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), + .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), + .dftse_cpu0_o (dftse_cpu0_o), + .dftse_cpu1_o (dftse_cpu1_o), + .dftse_cpu2_o (dftse_cpu2_o), + .dftse_cpu3_o (dftse_cpu3_o), + .eventi_sev (eventi_sev), + .evento_o (EVENTO), + .giccdisable_cpu0_o (giccdisable_cpu0_o), + .giccdisable_cpu1_o (giccdisable_cpu1_o), + .giccdisable_cpu2_o (giccdisable_cpu2_o), + .giccdisable_cpu3_o (giccdisable_cpu3_o), + .ncommirq_o (nCOMMIRQ[`MAIA_CN:0]), + .ncorereset_cpu0_o (ncorereset_cpu0_o), + .ncorereset_cpu1_o (ncorereset_cpu1_o), + .ncorereset_cpu2_o (ncorereset_cpu2_o), + .ncorereset_cpu3_o (ncorereset_cpu3_o), + .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), + .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), + .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), + .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), + .niden_cpu0_o (niden_cpu0_o), + .niden_cpu1_o (niden_cpu1_o), + .niden_cpu2_o (niden_cpu2_o), + .niden_cpu3_o (niden_cpu3_o), + .nmbistreset_cpu0_o (nmbistreset_cpu0_o), + .nmbistreset_cpu1_o (nmbistreset_cpu1_o), + .nmbistreset_cpu2_o (nmbistreset_cpu2_o), + .nmbistreset_cpu3_o (nmbistreset_cpu3_o), + .npmuirq_o (nPMUIRQ[`MAIA_CN:0]), + .pmuevent0_o (PMUEVENT0[24:0]), + .pmuevent1_o (PMUEVENT1[24:0]), + .pmuevent2_o (PMUEVENT2[24:0]), + .pmuevent3_o (PMUEVENT3[24:0]), + .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), + .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), + .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), + .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), + .smpen_o (SMPEN[`MAIA_CN:0]), + .spiden_cpu0_o (spiden_cpu0_o), + .spiden_cpu1_o (spiden_cpu1_o), + .spiden_cpu2_o (spiden_cpu2_o), + .spiden_cpu3_o (spiden_cpu3_o), + .spniden_cpu0_o (spniden_cpu0_o), + .spniden_cpu1_o (spniden_cpu1_o), + .spniden_cpu2_o (spniden_cpu2_o), + .spniden_cpu3_o (spniden_cpu3_o), + .vinithi_cpu0_o (vinithi_cpu0_o), + .vinithi_cpu1_o (vinithi_cpu1_o), + .vinithi_cpu2_o (vinithi_cpu2_o), + .vinithi_cpu3_o (vinithi_cpu3_o), + + // inputs + .aa64naa32_i (AA64nAA32[`MAIA_CN:0]), + .cfgend_i (CFGEND[`MAIA_CN:0]), + .cfgte_i (CFGTE[`MAIA_CN:0]), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), + .ck_cpu0_commrx (ck_cpu0_commrx), + .ck_cpu0_commtx (ck_cpu0_commtx), + .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), + .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), + .ck_cpu0_ncommirq (ck_cpu0_ncommirq), + .ck_cpu0_npmuirq (ck_cpu0_npmuirq), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), + .ck_cpu1_commrx (ck_cpu1_commrx), + .ck_cpu1_commtx (ck_cpu1_commtx), + .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), + .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), + .ck_cpu1_ncommirq (ck_cpu1_ncommirq), + .ck_cpu1_npmuirq (ck_cpu1_npmuirq), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), + .ck_cpu2_commrx (ck_cpu2_commrx), + .ck_cpu2_commtx (ck_cpu2_commtx), + .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), + .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), + .ck_cpu2_ncommirq (ck_cpu2_ncommirq), + .ck_cpu2_npmuirq (ck_cpu2_npmuirq), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), + .ck_cpu3_commrx (ck_cpu3_commrx), + .ck_cpu3_commtx (ck_cpu3_commtx), + .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), + .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), + .ck_cpu3_ncommirq (ck_cpu3_ncommirq), + .ck_cpu3_npmuirq (ck_cpu3_npmuirq), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), + .ck_gclkfr (ck_gclkfr), + .clrexmonreq_i (CLREXMONREQ), + .clusteridaff1_i (CLUSTERIDAFF1[7:0]), + .clusteridaff2_i (CLUSTERIDAFF2[7:0]), + .cp15sdisable_i (CP15SDISABLE[`MAIA_CN:0]), + .cryptodisable_i (CRYPTODISABLE[`MAIA_CN:0]), + .dbgack_cpu0_i (dbgack_cpu0_i), + .dbgack_cpu1_i (dbgack_cpu1_i), + .dbgack_cpu2_i (dbgack_cpu2_i), + .dbgack_cpu3_i (dbgack_cpu3_i), + .dbgen_i (DBGEN[`MAIA_CN:0]), + .dbgl1rstdisable_i (DBGL1RSTDISABLE), + .dbgromaddr_i (DBGROMADDR[43:12]), + .dbgromaddrv_i (DBGROMADDRV), + .dftcrclkdisable_i (DFTCRCLKDISABLE[`MAIA_CN:0]), + .dftramhold_i (DFTRAMHOLD), + .dftrstdisable_i (DFTRSTDISABLE), + .dftse_i (DFTSE), + .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_cpu0_sev_req (ds_cpu0_sev_req), + .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_cpu1_sev_req (ds_cpu1_sev_req), + .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_cpu2_sev_req (ds_cpu2_sev_req), + .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_cpu3_sev_req (ds_cpu3_sev_req), + .eventi_i (EVENTI), + .giccdisable_i (GICCDISABLE), + .l2_reset3 (l2_reset3), + .ncorereset_i (nCORERESET[`MAIA_CN:0]), + .ncpuporeset_i (nCPUPORESET[`MAIA_CN:0]), + .niden_i (NIDEN[`MAIA_CN:0]), + .nmbistreset_i (nMBISTRESET), + .pm_export_cpu0_i (pm_export_cpu0_i), + .pm_export_cpu1_i (pm_export_cpu1_i), + .pm_export_cpu2_i (pm_export_cpu2_i), + .pm_export_cpu3_i (pm_export_cpu3_i), + .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), + .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), + .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), + .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]), + .rvbaraddr0_i (RVBARADDR0[43:2]), + .rvbaraddr1_i (RVBARADDR1[43:2]), + .rvbaraddr2_i (RVBARADDR2[43:2]), + .rvbaraddr3_i (RVBARADDR3[43:2]), + .spiden_i (SPIDEN[`MAIA_CN:0]), + .spniden_i (SPNIDEN[`MAIA_CN:0]), + .vinithi_i (VINITHI[`MAIA_CN:0]) + ); // ucpu_io + + maia_dt_sb udt_sb( // outputs + .afreadym0_o (AFREADYM0), + .afreadym1_o (AFREADYM1), + .afreadym2_o (AFREADYM2), + .afreadym3_o (AFREADYM3), + .afvalidm_cpu0_o (afvalidm_cpu0_o), + .afvalidm_cpu1_o (afvalidm_cpu1_o), + .afvalidm_cpu2_o (afvalidm_cpu2_o), + .afvalidm_cpu3_o (afvalidm_cpu3_o), + .atbytesm0_o (ATBYTESM0[1:0]), + .atbytesm1_o (ATBYTESM1[1:0]), + .atbytesm2_o (ATBYTESM2[1:0]), + .atbytesm3_o (ATBYTESM3[1:0]), + .atclken_cpu0_o (atclken_cpu0_o), + .atclken_cpu1_o (atclken_cpu1_o), + .atclken_cpu2_o (atclken_cpu2_o), + .atclken_cpu3_o (atclken_cpu3_o), + .atdatam0_o (ATDATAM0[31:0]), + .atdatam1_o (ATDATAM1[31:0]), + .atdatam2_o (ATDATAM2[31:0]), + .atdatam3_o (ATDATAM3[31:0]), + .atidm0_o (ATIDM0[6:0]), + .atidm1_o (ATIDM1[6:0]), + .atidm2_o (ATIDM2[6:0]), + .atidm3_o (ATIDM3[6:0]), + .atreadym_cpu0_o (atreadym_cpu0_o), + .atreadym_cpu1_o (atreadym_cpu1_o), + .atreadym_cpu2_o (atreadym_cpu2_o), + .atreadym_cpu3_o (atreadym_cpu3_o), + .atvalidm0_o (ATVALIDM0), + .atvalidm1_o (ATVALIDM1), + .atvalidm2_o (ATVALIDM2), + .atvalidm3_o (ATVALIDM3), + .syncreqm_cpu0_o (syncreqm_cpu0_o), + .syncreqm_cpu1_o (syncreqm_cpu1_o), + .syncreqm_cpu2_o (syncreqm_cpu2_o), + .syncreqm_cpu3_o (syncreqm_cpu3_o), + .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), + .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), + .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), + .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), + + // inputs + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .TSVALUEB (TSVALUEB[63:0]), + .afreadym_cpu0_i (afreadym_cpu0_i), + .afreadym_cpu1_i (afreadym_cpu1_i), + .afreadym_cpu2_i (afreadym_cpu2_i), + .afreadym_cpu3_i (afreadym_cpu3_i), + .afvalidm0_i (AFVALIDM0), + .afvalidm1_i (AFVALIDM1), + .afvalidm2_i (AFVALIDM2), + .afvalidm3_i (AFVALIDM3), + .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), + .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), + .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), + .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), + .atclken_i (ATCLKEN), + .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), + .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), + .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), + .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), + .atidm_cpu0_i (atidm_cpu0_i[6:0]), + .atidm_cpu1_i (atidm_cpu1_i[6:0]), + .atidm_cpu2_i (atidm_cpu2_i[6:0]), + .atidm_cpu3_i (atidm_cpu3_i[6:0]), + .atreadym0_i (ATREADYM0), + .atreadym1_i (ATREADYM1), + .atreadym2_i (ATREADYM2), + .atreadym3_i (ATREADYM3), + .atvalidm_cpu0_i (atvalidm_cpu0_i), + .atvalidm_cpu1_i (atvalidm_cpu1_i), + .atvalidm_cpu2_i (atvalidm_cpu2_i), + .atvalidm_cpu3_i (atvalidm_cpu3_i), + .ck_gclkfr (ck_gclkfr), + .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), + .etclken_cpu0_i (etclken_cpu0_i), + .etclken_cpu1_i (etclken_cpu1_i), + .etclken_cpu2_i (etclken_cpu2_i), + .etclken_cpu3_i (etclken_cpu3_i), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nMBISTRESET (nMBISTRESET), + .syncreqm0_i (SYNCREQM0), + .syncreqm1_i (SYNCREQM1), + .syncreqm2_i (SYNCREQM2), + .syncreqm3_i (SYNCREQM3) + ); // udt_sb + + maia_ncpu_reg_rep uncpu_reg_rep( // outputs + .ds_cpu0_ic_aa64naa32_reg_o (ds_cpu0_ic_aa64naa32_i), + .ds_cpu0_ic_cpsr_mode_reg_o (ds_cpu0_ic_cpsr_mode_i[4:0]), + .ds_cpu0_ic_hcr_change_reg_o (ds_cpu0_ic_hcr_change_i), + .ds_cpu0_ic_sample_spr_reg_o (ds_cpu0_ic_sample_spr_i), + .ds_cpu0_ic_scr_change_reg_o (ds_cpu0_ic_scr_change_i), + .ds_cpu1_ic_aa64naa32_reg_o (ds_cpu1_ic_aa64naa32_i), + .ds_cpu1_ic_cpsr_mode_reg_o (ds_cpu1_ic_cpsr_mode_i[4:0]), + .ds_cpu1_ic_hcr_change_reg_o (ds_cpu1_ic_hcr_change_i), + .ds_cpu1_ic_sample_spr_reg_o (ds_cpu1_ic_sample_spr_i), + .ds_cpu1_ic_scr_change_reg_o (ds_cpu1_ic_scr_change_i), + .ds_cpu2_ic_aa64naa32_reg_o (ds_cpu2_ic_aa64naa32_i), + .ds_cpu2_ic_cpsr_mode_reg_o (ds_cpu2_ic_cpsr_mode_i[4:0]), + .ds_cpu2_ic_hcr_change_reg_o (ds_cpu2_ic_hcr_change_i), + .ds_cpu2_ic_sample_spr_reg_o (ds_cpu2_ic_sample_spr_i), + .ds_cpu2_ic_scr_change_reg_o (ds_cpu2_ic_scr_change_i), + .ds_cpu3_ic_aa64naa32_reg_o (ds_cpu3_ic_aa64naa32_i), + .ds_cpu3_ic_cpsr_mode_reg_o (ds_cpu3_ic_cpsr_mode_i[4:0]), + .ds_cpu3_ic_hcr_change_reg_o (ds_cpu3_ic_hcr_change_i), + .ds_cpu3_ic_sample_spr_reg_o (ds_cpu3_ic_sample_spr_i), + .ds_cpu3_ic_scr_change_reg_o (ds_cpu3_ic_scr_change_i), + .ic_block_eoi_sgi_wr_reg_o (ic_block_eoi_sgi_wr[`MAIA_CN:0]), + .ic_el_change_complete_reg_o (ic_el_change_complete[`MAIA_CN:0]), + .ic_hcr_change_complete_reg_o (ic_hcr_change_complete[`MAIA_CN:0]), + .ic_ich_el2_tall0_reg_o (ic_ich_el2_tall0[`MAIA_CN:0]), + .ic_ich_el2_tall1_reg_o (ic_ich_el2_tall1[`MAIA_CN:0]), + .ic_ich_el2_tc_reg_o (ic_ich_el2_tc[`MAIA_CN:0]), + .ic_nfiq_reg_o (ic_nfiq[`MAIA_CN:0]), + .ic_nirq_reg_o (ic_nirq[`MAIA_CN:0]), + .ic_nsei_reg_o (ic_nsei[`MAIA_CN:0]), + .ic_nvfiq_reg_o (ic_nvfiq[`MAIA_CN:0]), + .ic_nvirq_reg_o (ic_nvirq[`MAIA_CN:0]), + .ic_nvsei_reg_o (ic_nvsei[`MAIA_CN:0]), + .ic_sample_spr_reg_o (ic_sample_spr[`MAIA_CN:0]), + .ic_scr_change_complete_reg_o (ic_scr_change_complete[`MAIA_CN:0]), + .ic_sra_el1ns_en_reg_o (ic_sra_el1ns_en[`MAIA_CN:0]), + .ic_sra_el1s_en_reg_o (ic_sra_el1s_en[`MAIA_CN:0]), + .ic_sra_el2_en_reg_o (ic_sra_el2_en[`MAIA_CN:0]), + .ic_sra_el3_en_reg_o (ic_sra_el3_en[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap_reg_o (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap_reg_o (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap_reg_o (ic_sre_el1s_mon_trap[`MAIA_CN:0]), + .ic_sre_el2_mon_trap_reg_o (ic_sre_el2_mon_trap[`MAIA_CN:0]), + + // inputs + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), + .ic_el_change_complete (ic_el_change_complete_o[`MAIA_CN:0]), + .ic_hcr_change_complete (ic_hcr_change_complete_o[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .ic_sample_spr (ic_sample_spr_o[`MAIA_CN:0]), + .ic_scr_change_complete (ic_scr_change_complete_o[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]) + ); // uncpu_reg_rep + +//----------------------------------------------------------------------------- +// OVL Assertions +//----------------------------------------------------------------------------- +`ifdef ARM_ASSERT_ON + `include "maia_noncpu_val.v" +`endif + +endmodule // maia_noncpu + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20.v b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20.v new file mode 100644 index 0000000000..84a47bdbe3 --- /dev/null +++ b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20.v @@ -0,0 +1,7934 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: maia_noncpu_feq20.v $ +// Checked In : $Date: 2015-05-06 10:47:09 -0500 (Wed, 06 May 2015) $ +// Revision : $Revision: 73443 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// +// This is top-level interconnect layer for the non-CPU blocks at the Maia top-level. +// + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +`define MAIA_CN 3 + +module maia_noncpu_feq20 ( + CLK, + CLKEN, + nCPUPORESET, + nCORERESET, + nL2RESET, + L2RSTDISABLE, + WARMRSTREQ, + CFGEND, + VINITHI, + CFGTE, + CP15SDISABLE, + CLUSTERIDAFF1, + CLUSTERIDAFF2, + AA64nAA32, + RVBARADDR0, +// BEGIN INCLUDE FOR CPU1 + RVBARADDR1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + RVBARADDR2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + RVBARADDR3, +// END INCLUDE FOR CPU3 + CRYPTODISABLE, + nFIQ, + nIRQ, + nSEI, + nREI, + nVFIQ, + nVIRQ, + nVSEI, +// BEGIN NO-GIC pins + nVCPUMNTIRQ, +// END NO-GIC pins + PERIPHBASE, +// BEGIN NO-GIC pins + GICCDISABLE, + ICDTVALID, + ICDTREADY, + ICDTDATA, + ICDTLAST, + ICDTDEST, + ICCTVALID, + ICCTREADY, + ICCTDATA, + ICCTLAST, + ICCTID, +// END NO-GIC pins + CNTVALUEB, + CNTCLKEN, + nCNTPNSIRQ, + nCNTPSIRQ, + nCNTVIRQ, + nCNTHPIRQ, + CLREXMONREQ, + CLREXMONACK, + EVENTI, + EVENTO, + STANDBYWFI, + STANDBYWFE, + STANDBYWFIL2, + SMPEN, + CPUQACTIVE, + CPUQREQn, + CPUQACCEPTn, + CPUQDENY, + L2QACTIVE, + L2QREQn, + L2QACCEPTn, + L2QDENY, + L2FLUSHREQ, + L2FLUSHDONE, + nINTERRIRQ, + nEXTERRIRQ, + SYSBARDISABLE, + BROADCASTINNER, + BROADCASTOUTER, + BROADCASTCACHEMAINT, + ACLKENM, + ACINACTM, + AWREADYM, + AWVALIDM, + AWIDM, + AWADDRM, + AWLENM, + AWSIZEM, + AWBURSTM, + AWBARM, + AWDOMAINM, + AWLOCKM, + AWCACHEM, + AWPROTM, + AWSNOOPM, + AWUNIQUEM, + WRMEMATTR, + WREADYM, + WVALIDM, + WDATAM, + WSTRBM, + WIDM, + WLASTM, + BREADYM, + BVALIDM, + BIDM, + BRESPM, + ARREADYM, + ARVALIDM, + ARIDM, + ARADDRM, + ARLENM, + ARSIZEM, + ARBURSTM, + ARBARM, + ARDOMAINM, + ARLOCKM, + ARCACHEM, + ARPROTM, + ARSNOOPM, + RDMEMATTR, + RREADYM, + RVALIDM, + RIDM, + RDATAM, + RRESPM, + RLASTM, + ACREADYM, + ACVALIDM, + ACADDRM, + ACPROTM, + ACSNOOPM, + CRREADYM, + CRVALIDM, + CRRESPM, + CDREADYM, + CDVALIDM, + CDDATAM, + CDLASTM, + RACKM, + WACKM, + ACLKENS, + AINACTS, +// BEGIN NO-ACP pins + AWREADYS, + AWVALIDS, + AWIDS, + AWADDRS, + AWLENS, + AWCACHES, + AWUSERS, + AWPROTS, + WREADYS, + WVALIDS, + WDATAS, + WSTRBS, + WLASTS, + BREADYS, + BVALIDS, + BIDS, + BRESPS, + ARREADYS, + ARVALIDS, + ARIDS, + ARADDRS, + ARLENS, + ARCACHES, + ARUSERS, + ARPROTS, + RREADYS, + RVALIDS, + RIDS, + RDATAS, + RRESPS, + RLASTS, +// END NO-ACP pins + DBGROMADDR, + DBGROMADDRV, + DBGACK, + nCOMMIRQ, + COMMRX, + COMMTX, + DBGRSTREQ, + DBGNOPWRDWN, + DBGL1RSTDISABLE, + nPMUIRQ, + PMUEVENT0, +// BEGIN INCLUDE FOR CPU1 + PMUEVENT1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + PMUEVENT2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + PMUEVENT3, +// END INCLUDE FOR CPU3 + ATCLKEN, + TSVALUEB, + ATREADYM0, + AFVALIDM0, + ATDATAM0, + ATVALIDM0, + ATBYTESM0, + AFREADYM0, + ATIDM0, + SYNCREQM0, +// BEGIN INCLUDE FOR CPU1 + ATREADYM1, + AFVALIDM1, + ATDATAM1, + ATVALIDM1, + ATBYTESM1, + AFREADYM1, + ATIDM1, + SYNCREQM1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ATREADYM2, + AFVALIDM2, + ATDATAM2, + ATVALIDM2, + ATBYTESM2, + AFREADYM2, + ATIDM2, + SYNCREQM2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ATREADYM3, + AFVALIDM3, + ATDATAM3, + ATVALIDM3, + ATBYTESM3, + AFREADYM3, + ATIDM3, + SYNCREQM3, +// END INCLUDE FOR CPU3 + PCLKDBG, + PCLKENDBG, + nPRESETDBG, + PSELDBG, + PADDRDBG, + PADDRDBG31, + PENABLEDBG, + PWRITEDBG, + PWDATADBG, + PRDATADBG, + PREADYDBG, + PSLVERRDBG, + EDBGRQ, + PMUSNAPSHOTREQ, + PMUSNAPSHOTACK, + DBGPWRDUP, + DBGPWRUPREQ, + CTICHIN, + CTICHOUTACK, + CTICHOUT, + CTICHINACK, + CISBYPASS, + CIHSBYPASS, + CTIIRQ, + CTIIRQACK, + DBGEN, + NIDEN, + SPIDEN, + SPNIDEN, + DFTSE, + DFTRSTDISABLE, + DFTCRCLKDISABLE, + DFTL2CLKDISABLE, + DFTRAMHOLD, + DFTCLKBYPASS, + DFTMCPHOLD, + nMBISTRESET, + MBISTREQ, + +//----------------------------------------------------------------------------- +// Signals from maia -> maia_cpu_io -> maia_cpu +//----------------------------------------------------------------------------- +// Outputs to maia_cpu + ncpuporeset_cpu0_o, + ncorereset_cpu0_o, + + cfgend_cpu0_o, + cfgte_cpu0_o, + cp15sdisable_cpu0_o, + vinithi_cpu0_o, + clusteridaff1_cpu0_o, + clusteridaff2_cpu0_o, + cpuid_cpu0_o, + aa64naa32_cpu0_o, + rvbaraddr_cpu0_o, + cryptodisable_cpu0_o, + giccdisable_cpu0_o, + + dbgromaddr_cpu0_o, + dbgromaddrv_cpu0_o, + dbgl1rstdisable_cpu0_o, + + dbgen_cpu0_o, + niden_cpu0_o, + spiden_cpu0_o, + spniden_cpu0_o, + + tsvalueb_cpu0_o, + + atclken_cpu0_o, + afvalidm_cpu0_o, + atreadym_cpu0_o, + syncreqm_cpu0_o, + + dftse_cpu0_o, + dftrstdisable_cpu0_o, + dftcrclkdisable_cpu0_o, + dftramhold_cpu0_o, + + nmbistreset_cpu0_o, + +// BEGIN INCLUDE FOR CPU1 + ncpuporeset_cpu1_o, + ncorereset_cpu1_o, + + cfgend_cpu1_o, + cfgte_cpu1_o, + cp15sdisable_cpu1_o, + vinithi_cpu1_o, + clusteridaff1_cpu1_o, + clusteridaff2_cpu1_o, + cpuid_cpu1_o, + aa64naa32_cpu1_o, + rvbaraddr_cpu1_o, + cryptodisable_cpu1_o, + giccdisable_cpu1_o, + + dbgromaddr_cpu1_o, + dbgromaddrv_cpu1_o, + dbgl1rstdisable_cpu1_o, + + dbgen_cpu1_o, + niden_cpu1_o, + spiden_cpu1_o, + spniden_cpu1_o, + + tsvalueb_cpu1_o, + + atclken_cpu1_o, + afvalidm_cpu1_o, + atreadym_cpu1_o, + syncreqm_cpu1_o, + + dftse_cpu1_o, + dftrstdisable_cpu1_o, + dftcrclkdisable_cpu1_o, + dftramhold_cpu1_o, + + nmbistreset_cpu1_o, +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + ncpuporeset_cpu2_o, + ncorereset_cpu2_o, + + cfgend_cpu2_o, + cfgte_cpu2_o, + cp15sdisable_cpu2_o, + vinithi_cpu2_o, + clusteridaff1_cpu2_o, + clusteridaff2_cpu2_o, + cpuid_cpu2_o, + aa64naa32_cpu2_o, + rvbaraddr_cpu2_o, + cryptodisable_cpu2_o, + giccdisable_cpu2_o, + + dbgromaddr_cpu2_o, + dbgromaddrv_cpu2_o, + dbgl1rstdisable_cpu2_o, + + dbgen_cpu2_o, + niden_cpu2_o, + spiden_cpu2_o, + spniden_cpu2_o, + + tsvalueb_cpu2_o, + + atclken_cpu2_o, + afvalidm_cpu2_o, + atreadym_cpu2_o, + syncreqm_cpu2_o, + + dftse_cpu2_o, + dftrstdisable_cpu2_o, + dftcrclkdisable_cpu2_o, + dftramhold_cpu2_o, + + nmbistreset_cpu2_o, +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + ncpuporeset_cpu3_o, + ncorereset_cpu3_o, + + cfgend_cpu3_o, + cfgte_cpu3_o, + cp15sdisable_cpu3_o, + vinithi_cpu3_o, + clusteridaff1_cpu3_o, + clusteridaff2_cpu3_o, + cpuid_cpu3_o, + aa64naa32_cpu3_o, + rvbaraddr_cpu3_o, + cryptodisable_cpu3_o, + giccdisable_cpu3_o, + + dbgromaddr_cpu3_o, + dbgromaddrv_cpu3_o, + dbgl1rstdisable_cpu3_o, + + dbgen_cpu3_o, + niden_cpu3_o, + spiden_cpu3_o, + spniden_cpu3_o, + + tsvalueb_cpu3_o, + + atclken_cpu3_o, + afvalidm_cpu3_o, + atreadym_cpu3_o, + syncreqm_cpu3_o, + + dftse_cpu3_o, + dftrstdisable_cpu3_o, + dftcrclkdisable_cpu3_o, + dftramhold_cpu3_o, + + nmbistreset_cpu3_o, +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Signals from maia_cpu -> maia_cpu_io -> maia +//----------------------------------------------------------------------------- +// Inputs from maia_cpu + ds_cpu0_sev_req, + ds_cpu0_sevl_req, + ds_cpu0_cpuectlr_smp, + + ncommirq_cpu0_i, + commrx_cpu0_i, + commtx_cpu0_i, + dbgack_cpu0_i, + dbgrstreq_cpu0_i, + dbgnopwrdwn_cpu0_i, + + npmuirq_cpu0_i, + pmuevent_cpu0_i, + pm_export_cpu0_i, + + etclken_cpu0_i, + afreadym_cpu0_i, + atbytesm_cpu0_i, + atdatam_cpu0_i, + atidm_cpu0_i, + atvalidm_cpu0_i, + +// BEGIN INCLUDE FOR CPU1 + ds_cpu1_sev_req, + ds_cpu1_sevl_req, + ds_cpu1_cpuectlr_smp, + + ncommirq_cpu1_i, + commrx_cpu1_i, + commtx_cpu1_i, + dbgack_cpu1_i, + dbgrstreq_cpu1_i, + dbgnopwrdwn_cpu1_i, + + npmuirq_cpu1_i, + pmuevent_cpu1_i, + pm_export_cpu1_i, + + etclken_cpu1_i, + afreadym_cpu1_i, + atbytesm_cpu1_i, + atdatam_cpu1_i, + atidm_cpu1_i, + atvalidm_cpu1_i, +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + ds_cpu2_sev_req, + ds_cpu2_sevl_req, + ds_cpu2_cpuectlr_smp, + + ncommirq_cpu2_i, + commrx_cpu2_i, + commtx_cpu2_i, + dbgack_cpu2_i, + dbgrstreq_cpu2_i, + dbgnopwrdwn_cpu2_i, + + npmuirq_cpu2_i, + pmuevent_cpu2_i, + pm_export_cpu2_i, + + etclken_cpu2_i, + afreadym_cpu2_i, + atbytesm_cpu2_i, + atdatam_cpu2_i, + atidm_cpu2_i, + atvalidm_cpu2_i, +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + ds_cpu3_sev_req, + ds_cpu3_sevl_req, + ds_cpu3_cpuectlr_smp, + + ncommirq_cpu3_i, + commrx_cpu3_i, + commtx_cpu3_i, + dbgack_cpu3_i, + dbgrstreq_cpu3_i, + dbgnopwrdwn_cpu3_i, + + npmuirq_cpu3_i, + pmuevent_cpu3_i, + pm_export_cpu3_i, + + etclken_cpu3_i, + afreadym_cpu3_i, + atbytesm_cpu3_i, + atdatam_cpu3_i, + atidm_cpu3_i, + atvalidm_cpu3_i, +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// L2 interface +//----------------------------------------------------------------------------- + l2_cpu0_mbist1_addr_b1, + l2_cpu0_mbist1_array_b1, + l2_cpu0_mbist1_be_b1, + l2_cpu0_mbist1_en_b1, + l2_cpu0_mbist1_rd_en_b1, + l2_cpu0_mbist1_wr_en_b1, + l2_cpu0_mbist1_all_b1, +// BEGIN INCLUDE FOR CPU1 + l2_cpu1_mbist1_addr_b1, + l2_cpu1_mbist1_array_b1, + l2_cpu1_mbist1_be_b1, + l2_cpu1_mbist1_en_b1, + l2_cpu1_mbist1_rd_en_b1, + l2_cpu1_mbist1_wr_en_b1, + l2_cpu1_mbist1_all_b1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + l2_cpu2_mbist1_addr_b1, + l2_cpu2_mbist1_array_b1, + l2_cpu2_mbist1_be_b1, + l2_cpu2_mbist1_en_b1, + l2_cpu2_mbist1_rd_en_b1, + l2_cpu2_mbist1_wr_en_b1, + l2_cpu2_mbist1_all_b1, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + l2_cpu3_mbist1_addr_b1, + l2_cpu3_mbist1_array_b1, + l2_cpu3_mbist1_be_b1, + l2_cpu3_mbist1_en_b1, + l2_cpu3_mbist1_rd_en_b1, + l2_cpu3_mbist1_wr_en_b1, + l2_cpu3_mbist1_all_b1, +// END INCLUDE FOR CPU3 + +// BEGIN L2-CPU interface + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + l2_cpu0_cfg_ecc_en, + l2_cpu0_arb_thrshld_timeout_en, + l2_cpu0_disable_clean_evict_opt, + l2_cpu0_dext_err_r2, + l2_cpu0_dext_err_type_r2, + l2_cpu0_dsngl_ecc_err_r3, + l2_cpu0_ddbl_ecc_err_r3, + l2_cpu0_ddata_r2, + l2_cpu0_barrier_done, + l2_cpu0_spec_valid, + l2_cpu0_spec_bufid, + l2_cpu0_rvalid, + l2_cpu0_rstate, + l2_cpu0_rexfail, + l2_cpu0_rbufid, + l2_cpu0_dvalid_r1, + l2_cpu0_dlast_r1, + l2_cpu0_dbufid_r1, + l2_cpu0_iext_err_r2, + l2_cpu0_iext_err_type_r2, + l2_cpu0_isngl_ecc_err_r3, + l2_cpu0_idbl_ecc_err_r3, + l2_cpu0_idata_r2, + l2_cpu0_ivalid_r1, + l2_cpu0_ibufid_r1, + l2_cpu0_ls_sync_req, + l2_cpu0_ccb_req_addr_c3, + l2_cpu0_ccb_dbg_req_c3, + l2_cpu0_ls_ccb_clken_c3, + l2_cpu0_ls_ccb_req_c3, + l2_cpu0_ccb_req_id_c3, + l2_cpu0_ccb_req_type_c3, + l2_cpu0_ccb_req_info_c3, + l2_cpu0_if_ccb_clken_c3, + l2_cpu0_if_ccb_req_c3, + l2_cpu0_if_sync_req, + l2_cpu0_tlb_ccb_clken_c3, + l2_cpu0_tlb_ccb_req_c3, + l2_cpu0_tlb_sync_req, + l2_cpu0_tlb_sync_complete, + l2_cpu0_tbw_desc_vld, + l2_cpu0_tbw_ext_err, + l2_cpu0_tbw_ext_err_type, + l2_cpu0_tbw_dbl_ecc_err, + l2_cpu0_tbw_desc_data, + l2_cpu0_spr_rd_data, + l2_cpu0_l2_cache_size, + l2_cpu0_pf_throttle_q, + + l2_cpu0_wr_ex_resp, + l2_cpu0_wr_ex_fail, + + l2_cpu0_ic_base, + l2_cpu0_no_intctrl, + + + l2_cpu0_pmu_events, + + ds_cpu0_l2_spr_en, + ds_cpu0_l2_spr_rd, + ds_cpu0_l2_spr_wr, + ds_cpu0_l2_spr_addr, + ds_cpu0_l2_spr_dw, + ds_cpu0_l2_spr_wr_data, + + l2_cpu0_wr_data_vld_x1_q, + l2_cpu0_wr_evict_x1_q, + l2_cpu0_wr_data, + l2_cpu0_ls_rd_haz_vld_arb_q, + l2_cpu0_ls_wr_haz_vld_arb_q, + l2_cpu0_dt_pmu_evt_en, + + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + l2_cpu1_cfg_ecc_en, + l2_cpu1_arb_thrshld_timeout_en, + l2_cpu1_disable_clean_evict_opt, + l2_cpu1_dext_err_r2, + l2_cpu1_dext_err_type_r2, + l2_cpu1_dsngl_ecc_err_r3, + l2_cpu1_ddbl_ecc_err_r3, + l2_cpu1_ddata_r2, + l2_cpu1_barrier_done, + l2_cpu1_spec_valid, + l2_cpu1_spec_bufid, + l2_cpu1_rvalid, + l2_cpu1_rstate, + l2_cpu1_rexfail, + l2_cpu1_rbufid, + l2_cpu1_dvalid_r1, + l2_cpu1_dlast_r1, + l2_cpu1_dbufid_r1, + l2_cpu1_iext_err_r2, + l2_cpu1_iext_err_type_r2, + l2_cpu1_isngl_ecc_err_r3, + l2_cpu1_idbl_ecc_err_r3, + l2_cpu1_idata_r2, + l2_cpu1_ivalid_r1, + l2_cpu1_ibufid_r1, + l2_cpu1_ls_sync_req, + l2_cpu1_ccb_req_addr_c3, + l2_cpu1_ccb_dbg_req_c3, + l2_cpu1_ls_ccb_clken_c3, + l2_cpu1_ls_ccb_req_c3, + l2_cpu1_ccb_req_id_c3, + l2_cpu1_ccb_req_type_c3, + l2_cpu1_ccb_req_info_c3, + l2_cpu1_if_ccb_clken_c3, + l2_cpu1_if_ccb_req_c3, + l2_cpu1_if_sync_req, + l2_cpu1_tlb_ccb_clken_c3, + l2_cpu1_tlb_ccb_req_c3, + l2_cpu1_tlb_sync_req, + l2_cpu1_tlb_sync_complete, + l2_cpu1_tbw_desc_vld, + l2_cpu1_tbw_ext_err, + l2_cpu1_tbw_ext_err_type, + l2_cpu1_tbw_dbl_ecc_err, + l2_cpu1_tbw_desc_data, + l2_cpu1_spr_rd_data, + l2_cpu1_l2_cache_size, + l2_cpu1_pf_throttle_q, + + l2_cpu1_wr_ex_resp, + l2_cpu1_wr_ex_fail, + + l2_cpu1_ic_base, + l2_cpu1_no_intctrl, + + l2_cpu1_pmu_events, + + ds_cpu1_l2_spr_en, + ds_cpu1_l2_spr_rd, + ds_cpu1_l2_spr_wr, + ds_cpu1_l2_spr_addr, + ds_cpu1_l2_spr_dw, + ds_cpu1_l2_spr_wr_data, + + l2_cpu1_wr_data_vld_x1_q, + l2_cpu1_wr_evict_x1_q, + l2_cpu1_wr_data, + l2_cpu1_ls_rd_haz_vld_arb_q, + l2_cpu1_ls_wr_haz_vld_arb_q, + l2_cpu1_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + l2_cpu2_cfg_ecc_en, + l2_cpu2_arb_thrshld_timeout_en, + l2_cpu2_disable_clean_evict_opt, + l2_cpu2_dext_err_r2, + l2_cpu2_dext_err_type_r2, + l2_cpu2_dsngl_ecc_err_r3, + l2_cpu2_ddbl_ecc_err_r3, + l2_cpu2_ddata_r2, + l2_cpu2_barrier_done, + l2_cpu2_spec_valid, + l2_cpu2_spec_bufid, + l2_cpu2_rvalid, + l2_cpu2_rstate, + l2_cpu2_rexfail, + l2_cpu2_rbufid, + l2_cpu2_dvalid_r1, + l2_cpu2_dlast_r1, + l2_cpu2_dbufid_r1, + l2_cpu2_iext_err_r2, + l2_cpu2_iext_err_type_r2, + l2_cpu2_isngl_ecc_err_r3, + l2_cpu2_idbl_ecc_err_r3, + l2_cpu2_idata_r2, + l2_cpu2_ivalid_r1, + l2_cpu2_ibufid_r1, + l2_cpu2_ls_sync_req, + l2_cpu2_ccb_req_addr_c3, + l2_cpu2_ccb_dbg_req_c3, + l2_cpu2_ls_ccb_clken_c3, + l2_cpu2_ls_ccb_req_c3, + l2_cpu2_ccb_req_id_c3, + l2_cpu2_ccb_req_type_c3, + l2_cpu2_ccb_req_info_c3, + l2_cpu2_if_ccb_clken_c3, + l2_cpu2_if_ccb_req_c3, + l2_cpu2_if_sync_req, + l2_cpu2_tlb_ccb_clken_c3, + l2_cpu2_tlb_ccb_req_c3, + l2_cpu2_tlb_sync_req, + l2_cpu2_tlb_sync_complete, + l2_cpu2_tbw_desc_vld, + l2_cpu2_tbw_ext_err, + l2_cpu2_tbw_ext_err_type, + l2_cpu2_tbw_dbl_ecc_err, + l2_cpu2_tbw_desc_data, + l2_cpu2_spr_rd_data, + l2_cpu2_l2_cache_size, + l2_cpu2_pf_throttle_q, + + l2_cpu2_wr_ex_resp, + l2_cpu2_wr_ex_fail, + + l2_cpu2_ic_base, + l2_cpu2_no_intctrl, + + l2_cpu2_pmu_events, + + ds_cpu2_l2_spr_en, + ds_cpu2_l2_spr_rd, + ds_cpu2_l2_spr_wr, + ds_cpu2_l2_spr_addr, + ds_cpu2_l2_spr_dw, + ds_cpu2_l2_spr_wr_data, + + l2_cpu2_wr_data_vld_x1_q, + l2_cpu2_wr_evict_x1_q, + l2_cpu2_wr_data, + l2_cpu2_ls_rd_haz_vld_arb_q, + l2_cpu2_ls_wr_haz_vld_arb_q, + l2_cpu2_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + l2_cpu3_cfg_ecc_en, + l2_cpu3_arb_thrshld_timeout_en, + l2_cpu3_disable_clean_evict_opt, + l2_cpu3_dext_err_r2, + l2_cpu3_dext_err_type_r2, + l2_cpu3_dsngl_ecc_err_r3, + l2_cpu3_ddbl_ecc_err_r3, + l2_cpu3_ddata_r2, + l2_cpu3_barrier_done, + l2_cpu3_spec_valid, + l2_cpu3_spec_bufid, + l2_cpu3_rvalid, + l2_cpu3_rstate, + l2_cpu3_rexfail, + l2_cpu3_rbufid, + l2_cpu3_dvalid_r1, + l2_cpu3_dlast_r1, + l2_cpu3_dbufid_r1, + l2_cpu3_iext_err_r2, + l2_cpu3_iext_err_type_r2, + l2_cpu3_isngl_ecc_err_r3, + l2_cpu3_idbl_ecc_err_r3, + l2_cpu3_idata_r2, + l2_cpu3_ivalid_r1, + l2_cpu3_ibufid_r1, + l2_cpu3_ls_sync_req, + l2_cpu3_ccb_req_addr_c3, + l2_cpu3_ccb_dbg_req_c3, + l2_cpu3_ls_ccb_clken_c3, + l2_cpu3_ls_ccb_req_c3, + l2_cpu3_ccb_req_id_c3, + l2_cpu3_ccb_req_type_c3, + l2_cpu3_ccb_req_info_c3, + l2_cpu3_if_ccb_clken_c3, + l2_cpu3_if_ccb_req_c3, + l2_cpu3_if_sync_req, + l2_cpu3_tlb_ccb_clken_c3, + l2_cpu3_tlb_ccb_req_c3, + l2_cpu3_tlb_sync_req, + l2_cpu3_tlb_sync_complete, + l2_cpu3_tbw_desc_vld, + l2_cpu3_tbw_ext_err, + l2_cpu3_tbw_ext_err_type, + l2_cpu3_tbw_dbl_ecc_err, + l2_cpu3_tbw_desc_data, + l2_cpu3_spr_rd_data, + l2_cpu3_l2_cache_size, + l2_cpu3_pf_throttle_q, + + l2_cpu3_wr_ex_resp, + l2_cpu3_wr_ex_fail, + + l2_cpu3_ic_base, + l2_cpu3_no_intctrl, + + l2_cpu3_pmu_events, + + ds_cpu3_l2_spr_en, + ds_cpu3_l2_spr_rd, + ds_cpu3_l2_spr_wr, + ds_cpu3_l2_spr_addr, + ds_cpu3_l2_spr_dw, + ds_cpu3_l2_spr_wr_data, + + l2_cpu3_wr_data_vld_x1_q, + l2_cpu3_wr_evict_x1_q, + l2_cpu3_wr_data, + l2_cpu3_ls_rd_haz_vld_arb_q, + l2_cpu3_ls_wr_haz_vld_arb_q, + l2_cpu3_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// tag_pipe / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_flsh_ls_rd_l2_dly, + l2_cpu0_flsh_ls_wr_l2_dly, + + l2_cpu0_wr_data_stall, + + l2_cpu1_flsh_ls_rd_l2_dly, + l2_cpu1_flsh_ls_wr_l2_dly, + + l2_cpu1_wr_data_stall, + + l2_cpu2_flsh_ls_rd_l2_dly, + l2_cpu2_flsh_ls_wr_l2_dly, + + l2_cpu2_wr_data_stall, + + l2_cpu3_flsh_ls_rd_l2_dly, + l2_cpu3_flsh_ls_wr_l2_dly, + + l2_cpu3_wr_data_stall, + + l2_cpu0_flsh_ls_rd_id_l2_dly, + l2_cpu0_flsh_ls_wr_id_l2_dly, + + l2_cpu1_flsh_ls_rd_id_l2_dly, + l2_cpu1_flsh_ls_wr_id_l2_dly, + + l2_cpu2_flsh_ls_rd_id_l2_dly, + l2_cpu2_flsh_ls_wr_id_l2_dly, + + l2_cpu3_flsh_ls_rd_id_l2_dly, + l2_cpu3_flsh_ls_wr_id_l2_dly, + + l2_cpu0_flsh_ls_rd_l4_dly, + l2_cpu0_flsh_if_rd_l4_dly, + l2_cpu0_flsh_tw_rd_l4_dly, + l2_cpu0_flsh_ls_wr_l4_dly, + + l2_cpu1_flsh_ls_rd_l4_dly, + l2_cpu1_flsh_if_rd_l4_dly, + l2_cpu1_flsh_tw_rd_l4_dly, + l2_cpu1_flsh_ls_wr_l4_dly, + + l2_cpu2_flsh_ls_rd_l4_dly, + l2_cpu2_flsh_if_rd_l4_dly, + l2_cpu2_flsh_tw_rd_l4_dly, + l2_cpu2_flsh_ls_wr_l4_dly, + + l2_cpu3_flsh_ls_rd_l4_dly, + l2_cpu3_flsh_if_rd_l4_dly, + l2_cpu3_flsh_tw_rd_l4_dly, + l2_cpu3_flsh_ls_wr_l4_dly, + + l2_cpu0_flsh_ls_rd_id_l4_dly, + l2_cpu0_flsh_if_rd_id_l4_dly, + l2_cpu0_flsh_ls_wr_id_l4_dly, + l2_cpu0_flsh_ls_wr_evict_l4_dly, + + l2_cpu1_flsh_ls_rd_id_l4_dly, + l2_cpu1_flsh_if_rd_id_l4_dly, + l2_cpu1_flsh_ls_wr_id_l4_dly, + l2_cpu1_flsh_ls_wr_evict_l4_dly, + + l2_cpu2_flsh_ls_rd_id_l4_dly, + l2_cpu2_flsh_if_rd_id_l4_dly, + l2_cpu2_flsh_ls_wr_id_l4_dly, + l2_cpu2_flsh_ls_wr_evict_l4_dly, + + l2_cpu3_flsh_ls_rd_id_l4_dly, + l2_cpu3_flsh_if_rd_id_l4_dly, + l2_cpu3_flsh_ls_wr_id_l4_dly, + l2_cpu3_flsh_ls_wr_evict_l4_dly, + + l2_cpu0_lrq_haz_pending, + l2_cpu1_lrq_haz_pending, + l2_cpu2_lrq_haz_pending, + l2_cpu3_lrq_haz_pending, + + l2_cpu0_ifq_haz_pending, + l2_cpu1_ifq_haz_pending, + l2_cpu2_ifq_haz_pending, + l2_cpu3_ifq_haz_pending, + + l2_cpu0_trq_haz_pending, + l2_cpu1_trq_haz_pending, + l2_cpu2_trq_haz_pending, + l2_cpu3_trq_haz_pending, + + l2_cpu0_wrq_haz_pending, + l2_cpu1_wrq_haz_pending, + l2_cpu2_wrq_haz_pending, + l2_cpu3_wrq_haz_pending, + + l2_cpu0_idle_block_reqs_q, + l2_cpu1_idle_block_reqs_q, + l2_cpu2_idle_block_reqs_q, + l2_cpu3_idle_block_reqs_q, + + l2_cpu0_ls_peq_coll_l4_dly, + l2_cpu1_ls_peq_coll_l4_dly, + l2_cpu2_ls_peq_coll_l4_dly, + l2_cpu3_ls_peq_coll_l4_dly, + +//----------------------------------------------------------------------------- +// tag_pipe +//----------------------------------------------------------------------------- + l2_tbnk0_cpu0_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu1_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu2_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu3_lrq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu1_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu2_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu3_lrq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu1_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu2_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu3_ifq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu1_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu2_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu3_ifq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_trq_clr_l4_dly2_q, + l2_tbnk0_cpu1_trq_clr_l4_dly2_q, + l2_tbnk0_cpu2_trq_clr_l4_dly2_q, + l2_tbnk0_cpu3_trq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_trq_clr_l4_dly2_q, + l2_tbnk1_cpu1_trq_clr_l4_dly2_q, + l2_tbnk1_cpu2_trq_clr_l4_dly2_q, + l2_tbnk1_cpu3_trq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu1_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu2_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu3_wrq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu1_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu2_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu3_wrq_clr_l4_dly2_q, + + +//----------------------------------------------------------------------------- +// cpu_logic / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly, + + +//----------------------------------------------------------------------------- +// feq / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_dsq_rd_data_q, + l2_cpu0_dsq_rd_byte_strb_q, + l2_cpu1_dsq_rd_data_q, + l2_cpu1_dsq_rd_byte_strb_q, + l2_cpu2_dsq_rd_data_q, + l2_cpu2_dsq_rd_byte_strb_q, + l2_cpu3_dsq_rd_data_q, + l2_cpu3_dsq_rd_byte_strb_q, + + l2_cpu0_dsq_clr_vld_q, + l2_cpu0_dsq_clr_id_q, + l2_cpu0_dsq_rd_en, + l2_cpu0_dsq_rd_en_x2, + l2_cpu0_dsq_rd_buf_id, + l2_cpu1_dsq_clr_vld_q, + l2_cpu1_dsq_clr_id_q, + l2_cpu1_dsq_rd_en, + l2_cpu1_dsq_rd_en_x2, + l2_cpu1_dsq_rd_buf_id, + l2_cpu2_dsq_clr_vld_q, + l2_cpu2_dsq_clr_id_q, + l2_cpu2_dsq_rd_en, + l2_cpu2_dsq_rd_en_x2, + l2_cpu2_dsq_rd_buf_id, + l2_cpu3_dsq_clr_vld_q, + l2_cpu3_dsq_rd_en, + l2_cpu3_dsq_rd_en_x2, + l2_cpu3_dsq_clr_id_q, + l2_cpu3_dsq_rd_buf_id, + +//----------------------------------------------------------------------------- +// arbitration +//----------------------------------------------------------------------------- + l2_cpu0_rd_vld_skid, + l2_cpu1_rd_vld_skid, + l2_cpu2_rd_vld_skid, + l2_cpu3_rd_vld_skid, + + l2_cpu0_pf_rd_vld_skid_popped, + l2_cpu1_pf_rd_vld_skid_popped, + l2_cpu2_pf_rd_vld_skid_popped, + l2_cpu3_pf_rd_vld_skid_popped, + + l2_cpu0_rd_arb, + l2_cpu1_rd_arb, + l2_cpu2_rd_arb, + l2_cpu3_rd_arb, + + l2_cpu0_wr_vld_skid, + l2_cpu1_wr_vld_skid, + l2_cpu2_wr_vld_skid, + l2_cpu3_wr_vld_skid, + + l2_cpu0_wr_arb, + l2_cpu1_wr_arb, + l2_cpu2_wr_arb, + l2_cpu3_wr_arb, + + l2_cpu0_ic_vld_skid, + l2_cpu1_ic_vld_skid, + l2_cpu2_ic_vld_skid, + l2_cpu3_ic_vld_skid, + + l2_cpu0_ic_barrier_stall_q, + l2_cpu1_ic_barrier_stall_q, + l2_cpu2_ic_barrier_stall_q, + l2_cpu3_ic_barrier_stall_q, + + l2_cpu0_blk_non_evict_wr, + l2_cpu1_blk_non_evict_wr, + l2_cpu2_blk_non_evict_wr, + l2_cpu3_blk_non_evict_wr, + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + l2_cpu0_idle_wakeup_q, + l2_cpu0_rd_arb_fast, + l2_cpu0_rd_id_arb_set, + l2_cpu0_rd_lrq_id_arb_set, + l2_cpu0_rd_type_arb_set, + l2_cpu0_rd_cache_attr_arb_set, + l2_cpu0_rd_page_attr_arb_set, + l2_cpu0_rd_elem_size_arb_set, + l2_cpu0_rd_way_arb_set, + l2_cpu0_rd_replayed_arb_set, + l2_cpu0_rd_excl_arb_set, + l2_cpu0_rd_priv_arb_set, + l2_cpu0_rd_shared_arb_set, + l2_cpu0_rd_va48_arb_set, + l2_cpu0_rd_aarch64_arb_set, + l2_cpu0_rd_asid_arb_set, + l2_cpu0_rd_prfm_arb_set, + l2_cpu0_rd_addr_arb_set, + l2_cpu0_rd_bypass_arb_set, + l2_cpu0_rd_bypass_req_can_e5, + l2_cpu0_early_rd_reqe4_e5_q, + l2_cpu0_rd_bypass_way_e5, + l2_cpu0_rd_bypass_bufid_e5, + l2_cpu0_rd_bypass_lrq_id_e5, + + l2_cpu0_wr_arb_fast, + l2_cpu0_wr_id_arb_set, + l2_cpu0_wr_partial_dw_arb_set, + l2_cpu0_wr_cache_attr_arb_set, + l2_cpu0_wr_page_attr_arb_set, + l2_cpu0_wr_elem_size_arb_set, + l2_cpu0_wr_type_arb_set, + l2_cpu0_wr_cl_id_arb_set, + l2_cpu0_wr_priv_arb_set, + l2_cpu0_wr_shared_arb_set, + l2_cpu0_wr_last_arb_set, + l2_cpu0_wr_clean_evict_arb_set, + l2_cpu0_wr_err_arb_set, + l2_cpu0_wr_way_arb_set, + l2_cpu0_wr_dirty_arb_set, + l2_cpu0_wr_1st_replayed_arb_set, + l2_cpu0_wr_addr_arb_set, + l2_cpu0_ic_arb_fast, + l2_cpu0_ic_id_arb_set, + l2_cpu0_ic_write_arb_set, + l2_cpu0_ic_excl_arb_set, + l2_cpu0_ic_elem_size_arb_set, + l2_cpu0_ic_ns_arb_set, + l2_cpu0_ic_addr_arb_set, + l2_cpu0_ic_data_arb_set, + + l2_cpu0_wrq_almost_full, + + l2_cpu0_ls_wr_req_w2a, + l2_cpu0_ls_wr_last_w2a, + l2_cpu0_ls_wr_dirty_w2a, + l2_cpu0_ls_wr_err_w2a, + l2_cpu0_ls_wr_type_w2a, + l2_cpu0_ls_wr_ccb_id_w2a, + l2_cpu0_ls_wr_data_w2a, + + l2_cpu0_ls_ccb_resp, + l2_cpu0_ls_ccb_resp_id, + l2_cpu0_ls_ccb_data_wr, + + l2_cpu0_if_ccb_resp, + l2_cpu0_if_ccb_resp_id, + + l2_cpu0_tw_ccb_resp, + l2_cpu0_tw_ccb_resp_id, + + l2_cpu0_if_sync_done_q, + l2_cpu0_tlb_sync_done_q, + + l2_cpu0_lrq_haz_clr_id_dcd_q, + l2_cpu0_wrq_haz_clr_id_dcd_q, + l2_cpu0_ls_rd_haz_id_arb_q, + l2_cpu0_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + l2_cpu1_idle_wakeup_q, + l2_cpu1_rd_arb_fast, + l2_cpu1_rd_id_arb_set, + l2_cpu1_rd_lrq_id_arb_set, + l2_cpu1_rd_type_arb_set, + l2_cpu1_rd_cache_attr_arb_set, + l2_cpu1_rd_page_attr_arb_set, + l2_cpu1_rd_elem_size_arb_set, + l2_cpu1_rd_way_arb_set, + l2_cpu1_rd_replayed_arb_set, + l2_cpu1_rd_excl_arb_set, + l2_cpu1_rd_priv_arb_set, + l2_cpu1_rd_shared_arb_set, + l2_cpu1_rd_va48_arb_set, + l2_cpu1_rd_aarch64_arb_set, + l2_cpu1_rd_asid_arb_set, + l2_cpu1_rd_prfm_arb_set, + l2_cpu1_rd_addr_arb_set, + l2_cpu1_rd_bypass_arb_set, + l2_cpu1_rd_bypass_req_can_e5, + l2_cpu1_early_rd_reqe4_e5_q, + l2_cpu1_rd_bypass_way_e5, + l2_cpu1_rd_bypass_bufid_e5, + l2_cpu1_rd_bypass_lrq_id_e5, + + l2_cpu1_wr_arb_fast, + l2_cpu1_wr_id_arb_set, + l2_cpu1_wr_partial_dw_arb_set, + l2_cpu1_wr_cache_attr_arb_set, + l2_cpu1_wr_page_attr_arb_set, + l2_cpu1_wr_elem_size_arb_set, + l2_cpu1_wr_type_arb_set, + l2_cpu1_wr_cl_id_arb_set, + l2_cpu1_wr_priv_arb_set, + l2_cpu1_wr_shared_arb_set, + l2_cpu1_wr_last_arb_set, + l2_cpu1_wr_clean_evict_arb_set, + l2_cpu1_wr_err_arb_set, + l2_cpu1_wr_way_arb_set, + l2_cpu1_wr_dirty_arb_set, + l2_cpu1_wr_1st_replayed_arb_set, + l2_cpu1_wr_addr_arb_set, + l2_cpu1_ic_arb_fast, + l2_cpu1_ic_id_arb_set, + l2_cpu1_ic_write_arb_set, + l2_cpu1_ic_excl_arb_set, + l2_cpu1_ic_elem_size_arb_set, + l2_cpu1_ic_ns_arb_set, + l2_cpu1_ic_addr_arb_set, + l2_cpu1_ic_data_arb_set, + + l2_cpu1_wrq_almost_full, + + l2_cpu1_ls_wr_req_w2a, + l2_cpu1_ls_wr_last_w2a, + l2_cpu1_ls_wr_dirty_w2a, + l2_cpu1_ls_wr_err_w2a, + l2_cpu1_ls_wr_type_w2a, + l2_cpu1_ls_wr_ccb_id_w2a, + l2_cpu1_ls_wr_data_w2a, + + l2_cpu1_ls_ccb_resp, + l2_cpu1_ls_ccb_resp_id, + l2_cpu1_ls_ccb_data_wr, + + l2_cpu1_if_ccb_resp, + l2_cpu1_if_ccb_resp_id, + + l2_cpu1_tw_ccb_resp, + l2_cpu1_tw_ccb_resp_id, + + l2_cpu1_if_sync_done_q, + l2_cpu1_tlb_sync_done_q, + + l2_cpu1_lrq_haz_clr_id_dcd_q, + l2_cpu1_wrq_haz_clr_id_dcd_q, + l2_cpu1_ls_rd_haz_id_arb_q, + l2_cpu1_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + l2_cpu2_idle_wakeup_q, + l2_cpu2_rd_arb_fast, + l2_cpu2_rd_id_arb_set, + l2_cpu2_rd_lrq_id_arb_set, + l2_cpu2_rd_type_arb_set, + l2_cpu2_rd_cache_attr_arb_set, + l2_cpu2_rd_page_attr_arb_set, + l2_cpu2_rd_elem_size_arb_set, + l2_cpu2_rd_way_arb_set, + l2_cpu2_rd_replayed_arb_set, + l2_cpu2_rd_excl_arb_set, + l2_cpu2_rd_priv_arb_set, + l2_cpu2_rd_shared_arb_set, + l2_cpu2_rd_va48_arb_set, + l2_cpu2_rd_aarch64_arb_set, + l2_cpu2_rd_asid_arb_set, + l2_cpu2_rd_prfm_arb_set, + l2_cpu2_rd_addr_arb_set, + l2_cpu2_rd_bypass_arb_set, + l2_cpu2_rd_bypass_req_can_e5, + l2_cpu2_early_rd_reqe4_e5_q, + l2_cpu2_rd_bypass_way_e5, + l2_cpu2_rd_bypass_bufid_e5, + l2_cpu2_rd_bypass_lrq_id_e5, + + l2_cpu2_wr_arb_fast, + l2_cpu2_wr_id_arb_set, + l2_cpu2_wr_partial_dw_arb_set, + l2_cpu2_wr_cache_attr_arb_set, + l2_cpu2_wr_page_attr_arb_set, + l2_cpu2_wr_elem_size_arb_set, + l2_cpu2_wr_type_arb_set, + l2_cpu2_wr_cl_id_arb_set, + l2_cpu2_wr_priv_arb_set, + l2_cpu2_wr_shared_arb_set, + l2_cpu2_wr_last_arb_set, + l2_cpu2_wr_clean_evict_arb_set, + l2_cpu2_wr_err_arb_set, + l2_cpu2_wr_way_arb_set, + l2_cpu2_wr_dirty_arb_set, + l2_cpu2_wr_1st_replayed_arb_set, + l2_cpu2_wr_addr_arb_set, + l2_cpu2_ic_arb_fast, + l2_cpu2_ic_id_arb_set, + l2_cpu2_ic_write_arb_set, + l2_cpu2_ic_excl_arb_set, + l2_cpu2_ic_elem_size_arb_set, + l2_cpu2_ic_ns_arb_set, + l2_cpu2_ic_addr_arb_set, + l2_cpu2_ic_data_arb_set, + + l2_cpu2_wrq_almost_full, + + l2_cpu2_ls_wr_req_w2a, + l2_cpu2_ls_wr_last_w2a, + l2_cpu2_ls_wr_dirty_w2a, + l2_cpu2_ls_wr_err_w2a, + l2_cpu2_ls_wr_type_w2a, + l2_cpu2_ls_wr_ccb_id_w2a, + l2_cpu2_ls_wr_data_w2a, + + l2_cpu2_ls_ccb_resp, + l2_cpu2_ls_ccb_resp_id, + l2_cpu2_ls_ccb_data_wr, + + l2_cpu2_if_ccb_resp, + l2_cpu2_if_ccb_resp_id, + + l2_cpu2_tw_ccb_resp, + l2_cpu2_tw_ccb_resp_id, + + l2_cpu2_if_sync_done_q, + l2_cpu2_tlb_sync_done_q, + + l2_cpu2_lrq_haz_clr_id_dcd_q, + l2_cpu2_wrq_haz_clr_id_dcd_q, + l2_cpu2_ls_rd_haz_id_arb_q, + l2_cpu2_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + l2_cpu3_idle_wakeup_q, + l2_cpu3_rd_arb_fast, + l2_cpu3_rd_id_arb_set, + l2_cpu3_rd_lrq_id_arb_set, + l2_cpu3_rd_type_arb_set, + l2_cpu3_rd_cache_attr_arb_set, + l2_cpu3_rd_page_attr_arb_set, + l2_cpu3_rd_elem_size_arb_set, + l2_cpu3_rd_way_arb_set, + l2_cpu3_rd_replayed_arb_set, + l2_cpu3_rd_excl_arb_set, + l2_cpu3_rd_priv_arb_set, + l2_cpu3_rd_shared_arb_set, + l2_cpu3_rd_va48_arb_set, + l2_cpu3_rd_aarch64_arb_set, + l2_cpu3_rd_asid_arb_set, + l2_cpu3_rd_prfm_arb_set, + l2_cpu3_rd_addr_arb_set, + l2_cpu3_rd_bypass_arb_set, + l2_cpu3_rd_bypass_req_can_e5, + l2_cpu3_early_rd_reqe4_e5_q, + l2_cpu3_rd_bypass_way_e5, + l2_cpu3_rd_bypass_bufid_e5, + l2_cpu3_rd_bypass_lrq_id_e5, + + l2_cpu3_wr_arb_fast, + l2_cpu3_wr_id_arb_set, + l2_cpu3_wr_partial_dw_arb_set, + l2_cpu3_wr_cache_attr_arb_set, + l2_cpu3_wr_page_attr_arb_set, + l2_cpu3_wr_elem_size_arb_set, + l2_cpu3_wr_type_arb_set, + l2_cpu3_wr_cl_id_arb_set, + l2_cpu3_wr_priv_arb_set, + l2_cpu3_wr_shared_arb_set, + l2_cpu3_wr_last_arb_set, + l2_cpu3_wr_clean_evict_arb_set, + l2_cpu3_wr_err_arb_set, + l2_cpu3_wr_way_arb_set, + l2_cpu3_wr_dirty_arb_set, + l2_cpu3_wr_1st_replayed_arb_set, + l2_cpu3_wr_addr_arb_set, + l2_cpu3_ic_arb_fast, + l2_cpu3_ic_id_arb_set, + l2_cpu3_ic_write_arb_set, + l2_cpu3_ic_excl_arb_set, + l2_cpu3_ic_elem_size_arb_set, + l2_cpu3_ic_ns_arb_set, + l2_cpu3_ic_addr_arb_set, + l2_cpu3_ic_data_arb_set, + + l2_cpu3_wrq_almost_full, + + l2_cpu3_ls_wr_req_w2a, + l2_cpu3_ls_wr_last_w2a, + l2_cpu3_ls_wr_dirty_w2a, + l2_cpu3_ls_wr_err_w2a, + l2_cpu3_ls_wr_type_w2a, + l2_cpu3_ls_wr_ccb_id_w2a, + l2_cpu3_ls_wr_data_w2a, + + l2_cpu3_ls_ccb_resp, + l2_cpu3_ls_ccb_resp_id, + l2_cpu3_ls_ccb_data_wr, + + l2_cpu3_if_ccb_resp, + l2_cpu3_if_ccb_resp_id, + + l2_cpu3_tw_ccb_resp, + l2_cpu3_tw_ccb_resp_id, + + l2_cpu3_if_sync_done_q, + l2_cpu3_tlb_sync_done_q, + + l2_cpu3_lrq_haz_clr_id_dcd_q, + l2_cpu3_wrq_haz_clr_id_dcd_q, + l2_cpu3_ls_rd_haz_id_arb_q, + l2_cpu3_ls_wr_haz_id_arb_q, + +// END L2-CPU interface + +//------------------------------------------------------------------- +// TM interface +//------------------------------------------------------------------- +// BEGIN TIMER-CPU interface + tm_cpu0_cntkctl_usr, + tm_cpu0_cnthctl_kernel, + + tm_cpu1_cntkctl_usr, + tm_cpu1_cnthctl_kernel, + + tm_cpu2_cntkctl_usr, + tm_cpu2_cnthctl_kernel, + + tm_cpu3_cntkctl_usr, + tm_cpu3_cnthctl_kernel, +// END TIMER-CPU interface + +//----------------------------------------------------------------------------- +// IC interface +//----------------------------------------------------------------------------- + ls_cpu0_imp_abort_slv, + ls_cpu0_imp_abort_ecc, + ls_cpu0_imp_abort_dec, + ls_cpu0_imp_abort_containable, + ls_cpu0_raw_eae_nonsec, + ls_cpu0_raw_eae_secure, + + ds_cpu0_ic_cpsr_mode, + ds_cpu0_ic_sample_spr, + ds_cpu0_ic_aa64naa32, + ds_cpu0_ic_hcr_change, + ds_cpu0_ic_scr_change, +// BEGIN INCLUDE FOR CPU1 + ds_cpu1_ic_cpsr_mode, + ds_cpu1_ic_sample_spr, + ds_cpu1_ic_aa64naa32, + ds_cpu1_ic_hcr_change, + ds_cpu1_ic_scr_change, + ls_cpu1_imp_abort_slv, + ls_cpu1_imp_abort_ecc, + ls_cpu1_imp_abort_dec, + ls_cpu1_imp_abort_containable, + ls_cpu1_raw_eae_nonsec, + ls_cpu1_raw_eae_secure, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ds_cpu2_ic_cpsr_mode, + ds_cpu2_ic_sample_spr, + ds_cpu2_ic_aa64naa32, + ds_cpu2_ic_hcr_change, + ds_cpu2_ic_scr_change, + ls_cpu2_imp_abort_slv, + ls_cpu2_imp_abort_ecc, + ls_cpu2_imp_abort_dec, + ls_cpu2_imp_abort_containable, + ls_cpu2_raw_eae_nonsec, + ls_cpu2_raw_eae_secure, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ds_cpu3_ic_cpsr_mode, + ds_cpu3_ic_sample_spr, + ds_cpu3_ic_aa64naa32, + ds_cpu3_ic_hcr_change, + ds_cpu3_ic_scr_change, + ls_cpu3_imp_abort_slv, + ls_cpu3_imp_abort_ecc, + ls_cpu3_imp_abort_dec, + ls_cpu3_imp_abort_containable, + ls_cpu3_raw_eae_nonsec, + ls_cpu3_raw_eae_secure, +// END INCLUDE FOR CPU3 + + ic_nfiq, + ic_nirq, + ic_nsei, + ic_nvfiq, + ic_nvirq, + ic_nvsei, + ic_p_valid, + + ic_sample_spr, + ic_hcr_change_complete, + ic_scr_change_complete, + ic_el_change_complete, + ic_ich_el2_tc, + ic_ich_el2_tall0, + ic_ich_el2_tall1, + ic_sra_el3_en, + ic_sra_el1s_en, + ic_sra_el2_en, + ic_sra_el1ns_en, + ic_sre_el1ns_hyp_trap, + ic_sre_el1ns_mon_trap, + ic_sre_el1s_mon_trap, + ic_sre_el2_mon_trap, + ic_block_eoi_sgi_wr, + +//----------------------------------------------------------------------------- +// DT interface +//----------------------------------------------------------------------------- +// BEGIN DT-CPU interface +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + dt_cpu0_et_oslock_gclk, + dt_cpu0_os_double_lock_gclk, + dt_cpu0_halt_ack_gclk, + dt_cpu0_coredbg_in_reset_gclk, + dt_cpu0_wfx_dbg_req_gclk, + dt_cpu0_hlt_dbgevt_ok_gclk, + dt_cpu0_dbif_ack_gclk, + dt_cpu0_dbif_err_gclk, + dt_cpu0_dbif_rddata_gclk, + + dt_cpu0_dbif_addr_pclk, + dt_cpu0_dbif_locked_pclk, + dt_cpu0_dbif_req_pclk, + dt_cpu0_dbif_wrdata_pclk, + dt_cpu0_dbif_write_pclk, + dt_cpu0_edecr_osuce_pclk, + dt_cpu0_edecr_rce_pclk, + dt_cpu0_edecr_ss_pclk, + dt_cpu0_edbgrq_pclk, + dt_cpu0_edacr_frc_idleack_pclk, + dt_cpu0_edprcr_corepurq_pclk, + + dt_cpu0_pmusnapshot_ack_gclk, + dt_cpu0_pmusnapshot_req_pclk, + + dt_cpu0_cti_trigin_7to4_gclk, + dt_cpu0_cti_trigin_1to0_gclk, + dt_cpu0_cti_trigoutack_7to4_gclk, + dt_cpu0_cti_trigoutack_bit1_gclk, + + dt_cpu0_cti_trigout_7to4_pclk, + dt_cpu0_cti_trigout_1to0_pclk, + dt_cpu0_cti_triginack_7to4_pclk, + dt_cpu0_cti_triginack_1to0_pclk, + + dt_cpu0_wfx_wakeup_pclk, + dt_cpu0_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + dt_cpu1_et_oslock_gclk, + dt_cpu1_os_double_lock_gclk, + dt_cpu1_halt_ack_gclk, + dt_cpu1_coredbg_in_reset_gclk, + dt_cpu1_wfx_dbg_req_gclk, + dt_cpu1_hlt_dbgevt_ok_gclk, + dt_cpu1_dbif_ack_gclk, + dt_cpu1_dbif_err_gclk, + dt_cpu1_dbif_rddata_gclk, + + dt_cpu1_dbif_addr_pclk, + dt_cpu1_dbif_locked_pclk, + dt_cpu1_dbif_req_pclk, + dt_cpu1_dbif_wrdata_pclk, + dt_cpu1_dbif_write_pclk, + dt_cpu1_edecr_osuce_pclk, + dt_cpu1_edecr_rce_pclk, + dt_cpu1_edecr_ss_pclk, + dt_cpu1_edbgrq_pclk, + dt_cpu1_edacr_frc_idleack_pclk, + dt_cpu1_edprcr_corepurq_pclk, + + dt_cpu1_pmusnapshot_ack_gclk, + dt_cpu1_pmusnapshot_req_pclk, + + dt_cpu1_cti_trigin_7to4_gclk, + dt_cpu1_cti_trigin_1to0_gclk, + dt_cpu1_cti_trigoutack_7to4_gclk, + dt_cpu1_cti_trigoutack_bit1_gclk, + + dt_cpu1_cti_trigout_7to4_pclk, + dt_cpu1_cti_trigout_1to0_pclk, + dt_cpu1_cti_triginack_7to4_pclk, + dt_cpu1_cti_triginack_1to0_pclk, + + dt_cpu1_wfx_wakeup_pclk, + dt_cpu1_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + dt_cpu2_et_oslock_gclk, + dt_cpu2_os_double_lock_gclk, + dt_cpu2_halt_ack_gclk, + dt_cpu2_coredbg_in_reset_gclk, + dt_cpu2_wfx_dbg_req_gclk, + dt_cpu2_hlt_dbgevt_ok_gclk, + dt_cpu2_dbif_ack_gclk, + dt_cpu2_dbif_err_gclk, + dt_cpu2_dbif_rddata_gclk, + + dt_cpu2_dbif_addr_pclk, + dt_cpu2_dbif_locked_pclk, + dt_cpu2_dbif_req_pclk, + dt_cpu2_dbif_wrdata_pclk, + dt_cpu2_dbif_write_pclk, + dt_cpu2_edecr_osuce_pclk, + dt_cpu2_edecr_rce_pclk, + dt_cpu2_edecr_ss_pclk, + dt_cpu2_edbgrq_pclk, + dt_cpu2_edacr_frc_idleack_pclk, + dt_cpu2_edprcr_corepurq_pclk, + + dt_cpu2_pmusnapshot_ack_gclk, + dt_cpu2_pmusnapshot_req_pclk, + + dt_cpu2_cti_trigin_7to4_gclk, + dt_cpu2_cti_trigin_1to0_gclk, + dt_cpu2_cti_trigoutack_7to4_gclk, + dt_cpu2_cti_trigoutack_bit1_gclk, + + dt_cpu2_cti_trigout_7to4_pclk, + dt_cpu2_cti_trigout_1to0_pclk, + dt_cpu2_cti_triginack_7to4_pclk, + dt_cpu2_cti_triginack_1to0_pclk, + + dt_cpu2_wfx_wakeup_pclk, + dt_cpu2_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + dt_cpu3_et_oslock_gclk, + dt_cpu3_os_double_lock_gclk, + dt_cpu3_halt_ack_gclk, + dt_cpu3_coredbg_in_reset_gclk, + dt_cpu3_wfx_dbg_req_gclk, + dt_cpu3_hlt_dbgevt_ok_gclk, + dt_cpu3_dbif_ack_gclk, + dt_cpu3_dbif_err_gclk, + dt_cpu3_dbif_rddata_gclk, + + dt_cpu3_dbif_addr_pclk, + dt_cpu3_dbif_locked_pclk, + dt_cpu3_dbif_req_pclk, + dt_cpu3_dbif_wrdata_pclk, + dt_cpu3_dbif_write_pclk, + dt_cpu3_edecr_osuce_pclk, + dt_cpu3_edecr_rce_pclk, + dt_cpu3_edecr_ss_pclk, + dt_cpu3_edbgrq_pclk, + dt_cpu3_edacr_frc_idleack_pclk, + dt_cpu3_edprcr_corepurq_pclk, + + dt_cpu3_pmusnapshot_ack_gclk, + dt_cpu3_pmusnapshot_req_pclk, + + dt_cpu3_cti_trigin_7to4_gclk, + dt_cpu3_cti_trigin_1to0_gclk, + dt_cpu3_cti_trigoutack_7to4_gclk, + dt_cpu3_cti_trigoutack_bit1_gclk, + + dt_cpu3_cti_trigout_7to4_pclk, + dt_cpu3_cti_trigout_1to0_pclk, + dt_cpu3_cti_triginack_7to4_pclk, + dt_cpu3_cti_triginack_1to0_pclk, + + dt_cpu3_wfx_wakeup_pclk, + dt_cpu3_noclkstop_pclk, +// END DT-CPU interface + +//----------------------------------------------------------------------------- +// CK interface +//----------------------------------------------------------------------------- +// BEGIN CK-CPU interface + ds_cpu0_reset_req, + ds_cpu0_wfi_req, + ds_cpu0_wfe_req, + ds_cpu0_flush, + ds_cpu0_flush_type, + ds_cpu0_imp_abrt_wfi_qual, + ds_cpu0_irq_wfi_qual, + ds_cpu0_fiq_wfi_qual, + ds_cpu0_vimp_abrt_wfi_qual, + ds_cpu0_virq_wfi_qual, + ds_cpu0_vfiq_wfi_qual, + ds_cpu0_imp_abrt_wfe_qual, + ds_cpu0_irq_wfe_qual, + ds_cpu0_fiq_wfe_qual, + ds_cpu0_vimp_abrt_wfe_qual, + ds_cpu0_virq_wfe_qual, + ds_cpu0_vfiq_wfe_qual, + ds_cpu0_hcr_va, + ds_cpu0_hcr_vi, + ds_cpu0_hcr_vf, + ds_cpu0_cpuectlr_ret, + ck_cpu0_event_reg, + ck_cpu0_wfi_ack, + ck_cpu0_wfe_ack, + ck_cpu0_crcx_clk_en_n, + + ds_cpu1_reset_req, + ds_cpu1_wfi_req, + ds_cpu1_wfe_req, + ds_cpu1_flush, + ds_cpu1_flush_type, + ds_cpu1_imp_abrt_wfi_qual, + ds_cpu1_irq_wfi_qual, + ds_cpu1_fiq_wfi_qual, + ds_cpu1_vimp_abrt_wfi_qual, + ds_cpu1_virq_wfi_qual, + ds_cpu1_vfiq_wfi_qual, + ds_cpu1_imp_abrt_wfe_qual, + ds_cpu1_irq_wfe_qual, + ds_cpu1_fiq_wfe_qual, + ds_cpu1_vimp_abrt_wfe_qual, + ds_cpu1_virq_wfe_qual, + ds_cpu1_vfiq_wfe_qual, + ds_cpu1_hcr_va, + ds_cpu1_hcr_vi, + ds_cpu1_hcr_vf, + ds_cpu1_cpuectlr_ret, + ck_cpu1_event_reg, + ck_cpu1_wfi_ack, + ck_cpu1_wfe_ack, + ck_cpu1_crcx_clk_en_n, + + ds_cpu2_reset_req, + ds_cpu2_wfi_req, + ds_cpu2_wfe_req, + ds_cpu2_flush, + ds_cpu2_flush_type, + ds_cpu2_imp_abrt_wfi_qual, + ds_cpu2_irq_wfi_qual, + ds_cpu2_fiq_wfi_qual, + ds_cpu2_vimp_abrt_wfi_qual, + ds_cpu2_virq_wfi_qual, + ds_cpu2_vfiq_wfi_qual, + ds_cpu2_imp_abrt_wfe_qual, + ds_cpu2_irq_wfe_qual, + ds_cpu2_fiq_wfe_qual, + ds_cpu2_vimp_abrt_wfe_qual, + ds_cpu2_virq_wfe_qual, + ds_cpu2_vfiq_wfe_qual, + ds_cpu2_hcr_va, + ds_cpu2_hcr_vi, + ds_cpu2_hcr_vf, + ds_cpu2_cpuectlr_ret, + ck_cpu2_event_reg, + ck_cpu2_wfi_ack, + ck_cpu2_wfe_ack, + ck_cpu2_crcx_clk_en_n, + + ds_cpu3_reset_req, + ds_cpu3_wfi_req, + ds_cpu3_wfe_req, + ds_cpu3_flush, + ds_cpu3_flush_type, + ds_cpu3_imp_abrt_wfi_qual, + ds_cpu3_irq_wfi_qual, + ds_cpu3_fiq_wfi_qual, + ds_cpu3_vimp_abrt_wfi_qual, + ds_cpu3_virq_wfi_qual, + ds_cpu3_vfiq_wfi_qual, + ds_cpu3_imp_abrt_wfe_qual, + ds_cpu3_irq_wfe_qual, + ds_cpu3_fiq_wfe_qual, + ds_cpu3_vimp_abrt_wfe_qual, + ds_cpu3_virq_wfe_qual, + ds_cpu3_vfiq_wfe_qual, + ds_cpu3_hcr_va, + ds_cpu3_hcr_vi, + ds_cpu3_hcr_vf, + ds_cpu3_cpuectlr_ret, + ck_cpu3_event_reg, + ck_cpu3_wfi_ack, + ck_cpu3_wfe_ack, + ck_cpu3_crcx_clk_en_n, + + ls_cpu0_clrexmon, + ls_cpu1_clrexmon, + ls_cpu2_clrexmon, + ls_cpu3_clrexmon, +// END CK-CPU interface + + ck_gclkt +); + +//# +//# Interface Signals +//# ================= +//# + +//----------------------------------------------------------------------------- +// Clock and Reset Signals +//----------------------------------------------------------------------------- + input CLK; // Fast Clock + input CLKEN; // Fast Clock Enable + + input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset + input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) + input nL2RESET; // L2 reset + input L2RSTDISABLE; // L2 RAMs hardware reset disable + output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request +//See also nPRESETDBG; // Debug APB reset (PCLK) + +//----------------------------------------------------------------------------- +// Static Configuration Signals +//----------------------------------------------------------------------------- +// Static configuration signals that should be tied off and not change dynamically. +// Many of the initial values specified by these inputs +// may be overridden in software using CP15 registers. + + input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) + input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors + input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) + input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers + + input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] + input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] + + input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) + input [43:2] RVBARADDR0; // RVBAR address +// BEGIN INCLUDE FOR CPU1 + input [43:2] RVBARADDR1; // RVBAR address +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input [43:2] RVBARADDR2; // RVBAR address +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input [43:2] RVBARADDR3; // RVBAR address +// END INCLUDE FOR CPU3 + input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension + +//----------------------------------------------------------------------------- +// Interrupt Controller Signals +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] nFIQ; // Fast Interrupt request + input [`MAIA_CN:0] nIRQ; // Interrupt request + input [`MAIA_CN:0] nSEI; // System Error Interrupt + input [`MAIA_CN:0] nREI; // RAM Error Interrupt + input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request + input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request + input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt + +// BEGIN NO-GIC pins + output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output +// END NO-GIC pins + + input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers +// BEGIN NO-GIC pins + input GICCDISABLE; // Put GIC into bypass mode + + input ICDTVALID; // Distrubuter AXI4 SP Message Valid + output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message + input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data + input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet + input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID + + output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid + input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message + output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data + output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet + output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID +// END NO-GIC pins + +//----------------------------------------------------------------------------- +// Timer Signals +//----------------------------------------------------------------------------- + input [63:0] CNTVALUEB; // Counter value in binary + input CNTCLKEN; // Counter clock enable + output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event + output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event + output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event + output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event + +//----------------------------------------------------------------------------- +// Power Management Signals +//----------------------------------------------------------------------------- + input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) + output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) + input EVENTI; // Event input for processor wake-up from WFE state + output EVENTO; // Event output, signal is active when SEV instruction is executed + output [`MAIA_CN:0] STANDBYWFI; // WFI mode + output [`MAIA_CN:0] STANDBYWFE; // WFE mode + output STANDBYWFIL2; // WFI mode for L2 + output [`MAIA_CN:0] SMPEN; // CPU SMP bit + + output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE + input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn + output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn + output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY + + output L2QACTIVE; // L2 Q-channel QACTIVE + input L2QREQn; // L2 Q-channel QREQn + output L2QACCEPTn; // L2 Q-channel QACCEPTn + output L2QDENY; // L2 Q-channel QDENY + + input L2FLUSHREQ; // L2 hardware flush request + output L2FLUSHDONE; // L2 hardware flush done + +//----------------------------------------------------------------------------- +// Asynchronous Error Signals +//----------------------------------------------------------------------------- + output nINTERRIRQ; // L2 RAM dbl-bit ECC error + output nEXTERRIRQ; // Write transaction error + +//----------------------------------------------------------------------------- +// Bus Configuration Signals +//----------------------------------------------------------------------------- + input SYSBARDISABLE; // Disable broadcast of barriers + input BROADCASTINNER; // Extend Inner Shared Domain + input BROADCASTOUTER; // Extend Outer Shared Domain + input BROADCASTCACHEMAINT; // Broadcast cache maint ops + +//----------------------------------------------------------------------------- +// AMBA4 ACE Master (AXI with Coherency extensions) +//----------------------------------------------------------------------------- + input ACLKENM; // AXI Master clock enable + input ACINACTM; // ACE Snoop interface no longer active or accepting requests + +// Write Address channel signals + input AWREADYM; // Write Address ready (slave ready to accept write address) + output AWVALIDM; // Write Address valid + output [6:0] AWIDM; // Write Address ID + output [43:0] AWADDRM; // Write Address + output [7:0] AWLENM; // Write Burst Length + output [2:0] AWSIZEM; // Write Burst Size + output [1:0] AWBURSTM; // Write Burst type + output [1:0] AWBARM; // Barrier + output [1:0] AWDOMAINM; // Domain + output AWLOCKM; // Write Lock type + output [3:0] AWCACHEM; // Write Cache type + output [2:0] AWPROTM; // Write Protection type + output [2:0] AWSNOOPM; // Write Snoop Request type + output AWUNIQUEM; // Write Unique state + output [7:0] WRMEMATTR; // Write raw memory attributes + +// Write Data channel signals + input WREADYM; // Write Data ready (slave ready to accept data) + output WVALIDM; // Write Data valid + output [127:0] WDATAM; // Write Data + output [15:0] WSTRBM; // Write byte-lane strobes + output [6:0] WIDM; // Write id + output WLASTM; // Write Data last transfer indicator + +// Write Response channel signals + output BREADYM; // Write Response ready (master ready to accept response) + input BVALIDM; // Write Response Valid + input [6:0] BIDM; // Write Response ID + input [1:0] BRESPM; // Write Response + +// Read Address channel signals + input ARREADYM; // Read Address ready (slave ready to accept read address) + output ARVALIDM; // Read Address valid + output [6:0] ARIDM; // Read Address ID + output [43:0] ARADDRM; // Read Address + output [7:0] ARLENM; // Read Burst Length + output [2:0] ARSIZEM; // Read Burst Size + output [1:0] ARBURSTM; // Read Burst type + output [1:0] ARBARM; // Barrier + output [1:0] ARDOMAINM; // Domain + output ARLOCKM; // Read Lock type + output [3:0] ARCACHEM; // Read Cache type + output [2:0] ARPROTM; // Read Protection type + output [3:0] ARSNOOPM; // Read Snoop Request type + output [7:0] RDMEMATTR; // Read raw memory attributes + +// Read Data channel signals + output RREADYM; // Read Data ready (master ready to accept data) + input RVALIDM; // Read Data valid + input [6:0] RIDM; // Read Data ID + input [127:0] RDATAM; // Read Data + input [3:0] RRESPM; // Read Data response + input RLASTM; // Read Data last transfer indicator + +// Coherency Address channel signals + output ACREADYM; // master ready to accept snoop address + input ACVALIDM; // Snoop Address valid + input [43:0] ACADDRM; // Snoop Address + input [2:0] ACPROTM; // Snoop Protection type + input [3:0] ACSNOOPM; // Snoop Request type + +// Coherency Response channel signals + input CRREADYM; // slave ready to accept snoop response + output CRVALIDM; // Snoop Response valid + output [4:0] CRRESPM; // Snoop Response + +// Coherency Data handshake channel signals + input CDREADYM; // slave ready to accept snoop data + output CDVALIDM; // Snoop Data valid + output [127:0] CDDATAM; // Snoop Data + output CDLASTM; // Snoop Data last transfer indicator + +// Read/Write Acknowledge signals + output RACKM; // Read Acknowledge + output WACKM; // Write Acknowledge + +//----------------------------------------------------------------------------- +// ACP AXI Slave +//----------------------------------------------------------------------------- + input ACLKENS; // AXI slave clock enable + input AINACTS; // AXI slave interface no longer active or accepting requests + +// Write Address channel signals + output AWREADYS; // Write Address ready (slave ready to accept write address) + input AWVALIDS; // Write Address valid + input [4:0] AWIDS; // Write Address ID + input [43:0] AWADDRS; // Write Address + input [7:0] AWLENS; // Write Burst Length + input [3:0] AWCACHES; // Write Cache type + input [1:0] AWUSERS; // Write inner & outer shareability + input [2:0] AWPROTS; // Write Protection type + +// Write Data channel signals + output WREADYS; // Write Data ready (slave ready to accept data) + input WVALIDS; // Write Data valid + input [127:0] WDATAS; // Write Data + input [15:0] WSTRBS; // Write byte-lane strobes + input WLASTS; // Write Data last transfer indicator + +// Write Response channel signals + input BREADYS; // Write Response ready (master ready to accept response) + output BVALIDS; // Write Response Valid + output [4:0] BIDS; // Write Response ID tag + output [1:0] BRESPS; // Write Response + +// Read Address channel signals + output ARREADYS; // Read Address ready (slave ready to accept read address) + input ARVALIDS; // Read Address valid + input [4:0] ARIDS; // Read Address ID + input [43:0] ARADDRS; // Read Address + input [7:0] ARLENS; // Read Burst Length + input [3:0] ARCACHES; // Read Cache type + input [1:0] ARUSERS; // Read inner & outer shareability + input [2:0] ARPROTS; // Read Protection type + +// Read Data channel signals + input RREADYS; // Read Data ready (master ready to accept data) + output RVALIDS; // Read Data valid + output [4:0] RIDS; // Read Data ID + output [127:0] RDATAS; // Read Data + output [1:0] RRESPS; // Read Data response + output RLASTS; // Read Data last transfer indicator + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (CLK) +//----------------------------------------------------------------------------- +// Debug CLK interface + input [43:12] DBGROMADDR; // Debug ROM base address + input DBGROMADDRV; // Debug ROM base address valid + + output [`MAIA_CN:0] DBGACK; // Debug acknowledge + output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt + output [`MAIA_CN:0] COMMRX; // Comms channel receive + output [`MAIA_CN:0] COMMTX; // Comms channel transmit + + output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request + output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request + + input DBGL1RSTDISABLE; // L1 DCache hardware reset disable + +// PMU CLK interface + output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request + output [24:0] PMUEVENT0; // PMU Event bus +// BEGIN INCLUDE FOR CPU1 + output [24:0] PMUEVENT1; // PMU Event bus +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + output [24:0] PMUEVENT2; // PMU Event bus +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + output [24:0] PMUEVENT3; // PMU Event bus +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (ATCLK) +//----------------------------------------------------------------------------- +// ETM ATB interface and Misc signals + input ATCLKEN; // ATB Clock Enable + input [63:0] TSVALUEB; // ATB Timestamp in binary + + input ATREADYM0; // ATDATA can be accepted + input AFVALIDM0; // ATB Fifo Flush Request + output [31:0] ATDATAM0; // ATB Data + output ATVALIDM0; // ATB Data Valid + output [1:0] ATBYTESM0; // ATB Data Size + output AFREADYM0; // ATB Fifo Flush Finished + output [6:0] ATIDM0; // ATB Trace Source ID + input SYNCREQM0; // ATB External synchronization request + +// BEGIN INCLUDE FOR CPU1 + input ATREADYM1; // ATDATA can be accepted + input AFVALIDM1; // ATB Fifo Flush Request + output [31:0] ATDATAM1; // ATB Data + output ATVALIDM1; // ATB Data Valid + output [1:0] ATBYTESM1; // ATB Data Size + output AFREADYM1; // ATB Fifo Flush Finished + output [6:0] ATIDM1; // ATB Trace Source ID + input SYNCREQM1; // ATB External synchronization request +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ATREADYM2; // ATDATA can be accepted + input AFVALIDM2; // ATB Fifo Flush Request + output [31:0] ATDATAM2; // ATB Data + output ATVALIDM2; // ATB Data Valid + output [1:0] ATBYTESM2; // ATB Data Size + output AFREADYM2; // ATB Fifo Flush Finished + output [6:0] ATIDM2; // ATB Trace Source ID + input SYNCREQM2; // ATB External synchronization request +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ATREADYM3; // ATDATA can be accepted + input AFVALIDM3; // ATB Fifo Flush Request + output [31:0] ATDATAM3; // ATB Data + output ATVALIDM3; // ATB Data Valid + output [1:0] ATBYTESM3; // ATB Data Size + output AFREADYM3; // ATB Fifo Flush Finished + output [6:0] ATIDM3; // ATB Trace Source ID + input SYNCREQM3; // ATB External synchronization request +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (PCLK) +//----------------------------------------------------------------------------- +// Debug-APBv3 port (APB) + input PCLKDBG; // APB Clock + input PCLKENDBG; // APB Clock Enable + input nPRESETDBG; // APB Reset + input PSELDBG; // Debug bus access + input [21:2] PADDRDBG; // APB address + input PADDRDBG31; // APB address bit[31] + input PENABLEDBG; // APB transfer complete flag + input PWRITEDBG; // APB read/write indicator + input [31:0] PWDATADBG; // APB write data + output [31:0] PRDATADBG; // APB read data + output PREADYDBG; // APB slave ready, used to extend a transfer + output PSLVERRDBG; // APB slave transfer error + +// Misc interface + input [`MAIA_CN:0] EDBGRQ; // External debug request + +// PMU Snapshot interface + input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request + output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge + +// Power-related interface + input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status + output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request + +// CTI interface + input [3:0] CTICHIN; // Channel In + input [3:0] CTICHOUTACK; // Channel Out acknowledge + output [3:0] CTICHOUT; // Channel Out + output [3:0] CTICHINACK; // Channel In acknowledge + input CISBYPASS; // Channel interface sync bypass + input [3:0] CIHSBYPASS; // Channel interface H/S bypass + output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt + input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge + +//----------------------------------------------------------------------------- +// Debug Authentication Interface (CLK & PCLK) +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] DBGEN; // Invasive debug enable + input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable + input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable + input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable + +//----------------------------------------------------------------------------- +// DFT Signals +//----------------------------------------------------------------------------- + input DFTSE; // Scan enable + input DFTRSTDISABLE; // Disable reset to cells during scan shift + input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr + input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 + input DFTRAMHOLD; // Holds data in RAMs + input DFTCLKBYPASS; // L2 RAM strobe clock bypass + input DFTMCPHOLD; // Disable multi-cycle RAM paths + +//----------------------------------------------------------------------------- +// MBIST Interface +//----------------------------------------------------------------------------- + input nMBISTRESET; // MBIST reset + input MBISTREQ; // MBIST mode request + +//----------------------------------------------------------------------------- +// Signals from maia -> maia_cpu_io -> maia_cpu +//----------------------------------------------------------------------------- +// Outputs to maia_cpu + output ncpuporeset_cpu0_o; + output ncorereset_cpu0_o; + + output cfgend_cpu0_o; + output cfgte_cpu0_o; + output cp15sdisable_cpu0_o; + output vinithi_cpu0_o; + output [7:0] clusteridaff1_cpu0_o; + output [7:0] clusteridaff2_cpu0_o; + output [1:0] cpuid_cpu0_o; + output aa64naa32_cpu0_o; + output [43:2] rvbaraddr_cpu0_o; + output cryptodisable_cpu0_o; + output giccdisable_cpu0_o; + + output [43:12] dbgromaddr_cpu0_o; + output dbgromaddrv_cpu0_o; + output dbgl1rstdisable_cpu0_o; + + output dbgen_cpu0_o; + output niden_cpu0_o; + output spiden_cpu0_o; + output spniden_cpu0_o; + + output [63:0] tsvalueb_cpu0_o; + + output atclken_cpu0_o; + output afvalidm_cpu0_o; + output atreadym_cpu0_o; + output syncreqm_cpu0_o; + + output dftse_cpu0_o; + output dftrstdisable_cpu0_o; + output dftcrclkdisable_cpu0_o; + output dftramhold_cpu0_o; + output nmbistreset_cpu0_o; + +// BEGIN INCLUDE FOR CPU1 + output ncpuporeset_cpu1_o; + output ncorereset_cpu1_o; + + output cfgend_cpu1_o; + output cfgte_cpu1_o; + output cp15sdisable_cpu1_o; + output vinithi_cpu1_o; + output [7:0] clusteridaff1_cpu1_o; + output [7:0] clusteridaff2_cpu1_o; + output [1:0] cpuid_cpu1_o; + output aa64naa32_cpu1_o; + output [43:2] rvbaraddr_cpu1_o; + output cryptodisable_cpu1_o; + output giccdisable_cpu1_o; + + output [43:12] dbgromaddr_cpu1_o; + output dbgromaddrv_cpu1_o; + output dbgl1rstdisable_cpu1_o; + + output dbgen_cpu1_o; + output niden_cpu1_o; + output spiden_cpu1_o; + output spniden_cpu1_o; + + output [63:0] tsvalueb_cpu1_o; + + output atclken_cpu1_o; + output afvalidm_cpu1_o; + output atreadym_cpu1_o; + output syncreqm_cpu1_o; + + output dftse_cpu1_o; + output dftrstdisable_cpu1_o; + output dftcrclkdisable_cpu1_o; + output dftramhold_cpu1_o; + output nmbistreset_cpu1_o; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + output ncpuporeset_cpu2_o; + output ncorereset_cpu2_o; + + output cfgend_cpu2_o; + output cfgte_cpu2_o; + output cp15sdisable_cpu2_o; + output vinithi_cpu2_o; + output [7:0] clusteridaff1_cpu2_o; + output [7:0] clusteridaff2_cpu2_o; + output [1:0] cpuid_cpu2_o; + output aa64naa32_cpu2_o; + output [43:2] rvbaraddr_cpu2_o; + output cryptodisable_cpu2_o; + output giccdisable_cpu2_o; + + output [43:12] dbgromaddr_cpu2_o; + output dbgromaddrv_cpu2_o; + output dbgl1rstdisable_cpu2_o; + + output dbgen_cpu2_o; + output niden_cpu2_o; + output spiden_cpu2_o; + output spniden_cpu2_o; + + output [63:0] tsvalueb_cpu2_o; + + output atclken_cpu2_o; + output afvalidm_cpu2_o; + output atreadym_cpu2_o; + output syncreqm_cpu2_o; + + output dftse_cpu2_o; + output dftrstdisable_cpu2_o; + output dftcrclkdisable_cpu2_o; + output dftramhold_cpu2_o; + output nmbistreset_cpu2_o; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + output ncpuporeset_cpu3_o; + output ncorereset_cpu3_o; + + output cfgend_cpu3_o; + output cfgte_cpu3_o; + output cp15sdisable_cpu3_o; + output vinithi_cpu3_o; + output [7:0] clusteridaff1_cpu3_o; + output [7:0] clusteridaff2_cpu3_o; + output [1:0] cpuid_cpu3_o; + output aa64naa32_cpu3_o; + output [43:2] rvbaraddr_cpu3_o; + output cryptodisable_cpu3_o; + output giccdisable_cpu3_o; + + output [43:12] dbgromaddr_cpu3_o; + output dbgromaddrv_cpu3_o; + output dbgl1rstdisable_cpu3_o; + + output dbgen_cpu3_o; + output niden_cpu3_o; + output spiden_cpu3_o; + output spniden_cpu3_o; + + output [63:0] tsvalueb_cpu3_o; + + output atclken_cpu3_o; + output afvalidm_cpu3_o; + output atreadym_cpu3_o; + output syncreqm_cpu3_o; + + output dftse_cpu3_o; + output dftrstdisable_cpu3_o; + output dftcrclkdisable_cpu3_o; + output dftramhold_cpu3_o; + output nmbistreset_cpu3_o; +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Signals from maia_cpu -> maia_cpu_io -> maia +//----------------------------------------------------------------------------- +// Inputs from maia_cpu + input ds_cpu0_sev_req; + input ds_cpu0_sevl_req; + input ds_cpu0_cpuectlr_smp; + + input ncommirq_cpu0_i; + input commrx_cpu0_i; + input commtx_cpu0_i; + input dbgack_cpu0_i; + input dbgrstreq_cpu0_i; + input dbgnopwrdwn_cpu0_i; + + input npmuirq_cpu0_i; + input [24:0] pmuevent_cpu0_i; + input pm_export_cpu0_i; + + input etclken_cpu0_i; + input afreadym_cpu0_i; + input [1:0] atbytesm_cpu0_i; + input [31:0] atdatam_cpu0_i; + input [6:0] atidm_cpu0_i; + input atvalidm_cpu0_i; + +// BEGIN INCLUDE FOR CPU1 + input ds_cpu1_sev_req; + input ds_cpu1_sevl_req; + input ds_cpu1_cpuectlr_smp; + + input ncommirq_cpu1_i; + input commrx_cpu1_i; + input commtx_cpu1_i; + input dbgack_cpu1_i; + input dbgrstreq_cpu1_i; + input dbgnopwrdwn_cpu1_i; + + input npmuirq_cpu1_i; + input [24:0] pmuevent_cpu1_i; + input pm_export_cpu1_i; + + input etclken_cpu1_i; + input afreadym_cpu1_i; + input [1:0] atbytesm_cpu1_i; + input [31:0] atdatam_cpu1_i; + input [6:0] atidm_cpu1_i; + input atvalidm_cpu1_i; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ds_cpu2_sev_req; + input ds_cpu2_sevl_req; + input ds_cpu2_cpuectlr_smp; + + input ncommirq_cpu2_i; + input commrx_cpu2_i; + input commtx_cpu2_i; + input dbgack_cpu2_i; + input dbgrstreq_cpu2_i; + input dbgnopwrdwn_cpu2_i; + + input npmuirq_cpu2_i; + input [24:0] pmuevent_cpu2_i; + input pm_export_cpu2_i; + + input etclken_cpu2_i; + input afreadym_cpu2_i; + input [1:0] atbytesm_cpu2_i; + input [31:0] atdatam_cpu2_i; + input [6:0] atidm_cpu2_i; + input atvalidm_cpu2_i; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ds_cpu3_sev_req; + input ds_cpu3_sevl_req; + input ds_cpu3_cpuectlr_smp; + + input ncommirq_cpu3_i; + input commrx_cpu3_i; + input commtx_cpu3_i; + input dbgack_cpu3_i; + input dbgrstreq_cpu3_i; + input dbgnopwrdwn_cpu3_i; + + input npmuirq_cpu3_i; + input [24:0] pmuevent_cpu3_i; + input pm_export_cpu3_i; + + input etclken_cpu3_i; + input afreadym_cpu3_i; + input [1:0] atbytesm_cpu3_i; + input [31:0] atdatam_cpu3_i; + input [6:0] atidm_cpu3_i; + input atvalidm_cpu3_i; +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// L2 interface +//----------------------------------------------------------------------------- + output [12:0] l2_cpu0_mbist1_addr_b1; + output [3:0] l2_cpu0_mbist1_array_b1; + output [7:0] l2_cpu0_mbist1_be_b1; + output l2_cpu0_mbist1_en_b1; + output l2_cpu0_mbist1_rd_en_b1; + output l2_cpu0_mbist1_wr_en_b1; + output l2_cpu0_mbist1_all_b1; + +// BEGIN INCLUDE FOR CPU1 + output [12:0] l2_cpu1_mbist1_addr_b1; + output [3:0] l2_cpu1_mbist1_array_b1; + output [7:0] l2_cpu1_mbist1_be_b1; + output l2_cpu1_mbist1_en_b1; + output l2_cpu1_mbist1_rd_en_b1; + output l2_cpu1_mbist1_wr_en_b1; + output l2_cpu1_mbist1_all_b1; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + output [12:0] l2_cpu2_mbist1_addr_b1; + output [3:0] l2_cpu2_mbist1_array_b1; + output [7:0] l2_cpu2_mbist1_be_b1; + output l2_cpu2_mbist1_en_b1; + output l2_cpu2_mbist1_rd_en_b1; + output l2_cpu2_mbist1_wr_en_b1; + output l2_cpu2_mbist1_all_b1; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + output [12:0] l2_cpu3_mbist1_addr_b1; + output [3:0] l2_cpu3_mbist1_array_b1; + output [7:0] l2_cpu3_mbist1_be_b1; + output l2_cpu3_mbist1_en_b1; + output l2_cpu3_mbist1_rd_en_b1; + output l2_cpu3_mbist1_wr_en_b1; + output l2_cpu3_mbist1_all_b1; +// END INCLUDE FOR CPU3 + +// BEGIN L2-CPU interface + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + output l2_cpu0_cfg_ecc_en; + output l2_cpu0_arb_thrshld_timeout_en; + output l2_cpu0_disable_clean_evict_opt; + output l2_cpu0_dext_err_r2; // LS external error + output l2_cpu0_dext_err_type_r2; // LS external error type + output l2_cpu0_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu0_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu0_ddata_r2; // LS read data + output l2_cpu0_barrier_done; // LS barrier complete + output l2_cpu0_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu0_spec_bufid; // LS read speculative response buffer id + output l2_cpu0_rvalid; // LS read response valid + output [1:0] l2_cpu0_rstate; // LS read response state + output l2_cpu0_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu0_rbufid; // LS read response buffer id + output l2_cpu0_dvalid_r1; // LS read data valid + output l2_cpu0_dlast_r1; // LS read last indicator + output [2:0] l2_cpu0_dbufid_r1; // LS read data fill buffer id + output l2_cpu0_iext_err_r2; // IF external error + output l2_cpu0_iext_err_type_r2; // IF external error type + output l2_cpu0_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu0_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu0_idata_r2; // IF read data + output l2_cpu0_ivalid_r1; // IF read data valid + output [1:0] l2_cpu0_ibufid_r1; // IF read data fill buffer id + output l2_cpu0_ls_sync_req; // LS sync req + output [48:0] l2_cpu0_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu0_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu0_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu0_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu0_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu0_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu0_ccb_req_info_c3; // LS ccb req info + output l2_cpu0_if_ccb_clken_c3; // IF ccb clken + output l2_cpu0_if_ccb_req_c3; // IF ccb req + output l2_cpu0_if_sync_req; // IF sync req + output l2_cpu0_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu0_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu0_tlb_sync_req; // TLB sync req + output l2_cpu0_tlb_sync_complete; // TLB sync complete + output l2_cpu0_tbw_desc_vld; // TBW descriptor valid + output l2_cpu0_tbw_ext_err; // TBW descriptor external error + output l2_cpu0_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu0_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu0_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu0_spr_rd_data; // DS spr read data + output [1:0] l2_cpu0_l2_cache_size; // DS L2 cache size + output l2_cpu0_pf_throttle_q; // PF throttling + + output l2_cpu0_wr_ex_resp; // store exclusive response + output l2_cpu0_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu0_ic_base; // PERIPHBASE + output l2_cpu0_no_intctrl; // INTCTLR not present + + + output [33:0] l2_cpu0_pmu_events; // L2 PMU events + + input ds_cpu0_l2_spr_en; // cpu0 early spr req for clk enables + input ds_cpu0_l2_spr_rd; // cpu0 spr read op + input ds_cpu0_l2_spr_wr; // cpu0 spr write op + input [8:0] ds_cpu0_l2_spr_addr; // cpu0 spr address + input ds_cpu0_l2_spr_dw; // cpu0 spr access dw + input [63:0] ds_cpu0_l2_spr_wr_data; // cpu0 spr write data + + input l2_cpu0_wr_data_vld_x1_q; // cpu0 write data vld x1 stage + input l2_cpu0_wr_evict_x1_q; // cpu0 write evict x1 stage + input [143:0] l2_cpu0_wr_data; + input l2_cpu0_ls_rd_haz_vld_arb_q; + input l2_cpu0_ls_wr_haz_vld_arb_q; + input l2_cpu0_dt_pmu_evt_en; // PMU enabled. + + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + output l2_cpu1_cfg_ecc_en; + output l2_cpu1_arb_thrshld_timeout_en; + output l2_cpu1_disable_clean_evict_opt; + output l2_cpu1_dext_err_r2; // LS external error + output l2_cpu1_dext_err_type_r2; // LS external error type + output l2_cpu1_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu1_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu1_ddata_r2; // LS read data + output l2_cpu1_barrier_done; // LS barrier complete + output l2_cpu1_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu1_spec_bufid; // LS read speculative response buffer id + output l2_cpu1_rvalid; // LS read response valid + output [1:0] l2_cpu1_rstate; // LS read response state + output l2_cpu1_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu1_rbufid; // LS read response buffer id + output l2_cpu1_dvalid_r1; // LS read data valid + output l2_cpu1_dlast_r1; // LS read last indicator + output [2:0] l2_cpu1_dbufid_r1; // LS read data fill buffer id + output l2_cpu1_iext_err_r2; // IF external error + output l2_cpu1_iext_err_type_r2; // IF external error type + output l2_cpu1_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu1_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu1_idata_r2; // IF read data + output l2_cpu1_ivalid_r1; // IF read data valid + output [1:0] l2_cpu1_ibufid_r1; // IF read data fill buffer id + output l2_cpu1_ls_sync_req; // LS sync req + output [48:0] l2_cpu1_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu1_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu1_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu1_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu1_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu1_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu1_ccb_req_info_c3; // LS ccb req info + output l2_cpu1_if_ccb_clken_c3; // IF ccb clken + output l2_cpu1_if_ccb_req_c3; // IF ccb req + output l2_cpu1_if_sync_req; // IF sync req + output l2_cpu1_tlb_ccb_clken_c3; // IF ccb clken + output l2_cpu1_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu1_tlb_sync_req; // TLB sync req + output l2_cpu1_tlb_sync_complete; // TLB sync complete + output l2_cpu1_tbw_desc_vld; // TBW descriptor valid + output l2_cpu1_tbw_ext_err; // TBW descriptor external error + output l2_cpu1_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu1_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu1_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu1_spr_rd_data; // DS spr read data + output [1:0] l2_cpu1_l2_cache_size; // DS L2 cache size + output l2_cpu1_pf_throttle_q; // PF throttling + + output l2_cpu1_wr_ex_resp; // store exclusive response + output l2_cpu1_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu1_ic_base; // PERIPHBASE + output l2_cpu1_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu1_pmu_events; // L2 PMU events + + input ds_cpu1_l2_spr_en; // cpu1 early spr req for clk enables + input ds_cpu1_l2_spr_rd; // cpu1 spr read op + input ds_cpu1_l2_spr_wr; // cpu1 spr write op + input [8:0] ds_cpu1_l2_spr_addr; // cpu1 spr address + input ds_cpu1_l2_spr_dw; // cpu1 spr access dw + input [63:0] ds_cpu1_l2_spr_wr_data; // cpu1 spr write data + + input l2_cpu1_wr_data_vld_x1_q; // cpu1 write data vld x1 stage + input l2_cpu1_wr_evict_x1_q; // cpu1 write evict x1 stage + input [143:0] l2_cpu1_wr_data; + input l2_cpu1_ls_rd_haz_vld_arb_q; + input l2_cpu1_ls_wr_haz_vld_arb_q; + input l2_cpu1_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + output l2_cpu2_cfg_ecc_en; + output l2_cpu2_arb_thrshld_timeout_en; + output l2_cpu2_disable_clean_evict_opt; + output l2_cpu2_dext_err_r2; // LS external error + output l2_cpu2_dext_err_type_r2; // LS external error type + output l2_cpu2_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu2_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu2_ddata_r2; // LS read data + output l2_cpu2_barrier_done; // LS barrier complete + output l2_cpu2_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu2_spec_bufid; // LS read speculative response buffer id + output l2_cpu2_rvalid; // LS read response valid + output [1:0] l2_cpu2_rstate; // LS read response state + output l2_cpu2_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu2_rbufid; // LS read response buffer id + output l2_cpu2_dvalid_r1; // LS read data valid + output l2_cpu2_dlast_r1; // LS read last indicator + output [2:0] l2_cpu2_dbufid_r1; // LS read data fill buffer id + output l2_cpu2_iext_err_r2; // IF external error + output l2_cpu2_iext_err_type_r2; // IF external error type + output l2_cpu2_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu2_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu2_idata_r2; // IF read data + output l2_cpu2_ivalid_r1; // IF read data valid + output [1:0] l2_cpu2_ibufid_r1; // IF read data fill buffer id + output l2_cpu2_ls_sync_req; // LS sync req + output [48:0] l2_cpu2_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu2_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu2_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu2_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu2_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu2_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu2_ccb_req_info_c3; // LS ccb req info + output l2_cpu2_if_ccb_clken_c3; // IF ccb clken + output l2_cpu2_if_ccb_req_c3; // IF ccb req + output l2_cpu2_if_sync_req; // IF sync req + output l2_cpu2_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu2_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu2_tlb_sync_req; // TLB sync req + output l2_cpu2_tlb_sync_complete; // TLB sync complete + output l2_cpu2_tbw_desc_vld; // TBW descriptor valid + output l2_cpu2_tbw_ext_err; // TBW descriptor external error + output l2_cpu2_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu2_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu2_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu2_spr_rd_data; // DS spr read data + output [1:0] l2_cpu2_l2_cache_size; // DS L2 cache size + output l2_cpu2_pf_throttle_q; // PF throttling + + output l2_cpu2_wr_ex_resp; // store exclusive response + output l2_cpu2_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu2_ic_base; // PERIPHBASE + output l2_cpu2_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu2_pmu_events; // L2 PMU events + + input ds_cpu2_l2_spr_en; // cpu2 early spr req for clk enables + input ds_cpu2_l2_spr_rd; // cpu2 spr read op + input ds_cpu2_l2_spr_wr; // cpu2 spr write op + input [8:0] ds_cpu2_l2_spr_addr; // cpu2 spr address + input ds_cpu2_l2_spr_dw; // cpu2 spr access dw + input [63:0] ds_cpu2_l2_spr_wr_data; // cpu2 spr write data + + input l2_cpu2_wr_data_vld_x1_q; // cpu2 write data vld x1 stage + input l2_cpu2_wr_evict_x1_q; // cpu2 write evict x1 stage + input [143:0] l2_cpu2_wr_data; + input l2_cpu2_ls_rd_haz_vld_arb_q; + input l2_cpu2_ls_wr_haz_vld_arb_q; + input l2_cpu2_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + output l2_cpu3_cfg_ecc_en; + output l2_cpu3_arb_thrshld_timeout_en; + output l2_cpu3_disable_clean_evict_opt; + output l2_cpu3_dext_err_r2; // LS external error + output l2_cpu3_dext_err_type_r2; // LS external error type + output l2_cpu3_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu3_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu3_ddata_r2; // LS read data + output l2_cpu3_barrier_done; // LS barrier complete + output l2_cpu3_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu3_spec_bufid; // LS read speculative response buffer id + output l2_cpu3_rvalid; // LS read response valid + output [1:0] l2_cpu3_rstate; // LS read response state + output l2_cpu3_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu3_rbufid; // LS read response buffer id + output l2_cpu3_dvalid_r1; // LS read data valid + output l2_cpu3_dlast_r1; // LS read last indicator + output [2:0] l2_cpu3_dbufid_r1; // LS read data fill buffer id + output l2_cpu3_iext_err_r2; // IF external error + output l2_cpu3_iext_err_type_r2; // IF external error type + output l2_cpu3_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu3_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu3_idata_r2; // IF read data + output l2_cpu3_ivalid_r1; // IF read data valid + output [1:0] l2_cpu3_ibufid_r1; // IF read data fill buffer id + output l2_cpu3_ls_sync_req; // LS sync req + output [48:0] l2_cpu3_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu3_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu3_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu3_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu3_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu3_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu3_ccb_req_info_c3; // LS ccb req info + output l2_cpu3_if_ccb_clken_c3; // IF ccb clken + output l2_cpu3_if_ccb_req_c3; // IF ccb req + output l2_cpu3_if_sync_req; // IF sync req + output l2_cpu3_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu3_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu3_tlb_sync_req; // TLB sync req + output l2_cpu3_tlb_sync_complete; // TLB sync complete + output l2_cpu3_tbw_desc_vld; // TBW descriptor valid + output l2_cpu3_tbw_ext_err; // TBW descriptor external error + output l2_cpu3_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu3_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu3_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu3_spr_rd_data; // DS spr read data + output [1:0] l2_cpu3_l2_cache_size; // DS L2 cache size + output l2_cpu3_pf_throttle_q; // PF throttling + + output l2_cpu3_wr_ex_resp; // store exclusive response + output l2_cpu3_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu3_ic_base; // PERIPHBASE + output l2_cpu3_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu3_pmu_events; // L2 PMU events + + input ds_cpu3_l2_spr_en; // cpu3 early spr req for clk enables + input ds_cpu3_l2_spr_rd; // cpu3 spr read op + input ds_cpu3_l2_spr_wr; // cpu3 spr write op + input [8:0] ds_cpu3_l2_spr_addr; // cpu3 spr address + input ds_cpu3_l2_spr_dw; // cpu3 spr access dw + input [63:0] ds_cpu3_l2_spr_wr_data; // cpu3 spr write data + + input l2_cpu3_wr_data_vld_x1_q; // cpu3 write data vld x1 stage + input l2_cpu3_wr_evict_x1_q; // cpu3 write evict x1 stage + input [143:0] l2_cpu3_wr_data; + input l2_cpu3_ls_rd_haz_vld_arb_q; + input l2_cpu3_ls_wr_haz_vld_arb_q; + input l2_cpu3_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// tag_pipe / cpu slave +//----------------------------------------------------------------------------- + output l2_cpu0_flsh_ls_rd_l2_dly; // cpu0 ls local hazard flush + output l2_cpu0_flsh_ls_wr_l2_dly; // cpu0 ls local hazard flush + + output l2_cpu0_wr_data_stall; // cpu0 write data stall + + output l2_cpu1_flsh_ls_rd_l2_dly; // cpu1 ls local hazard flush + output l2_cpu1_flsh_ls_wr_l2_dly; // cpu1 ls local hazard flush + + output l2_cpu1_wr_data_stall; // cpu1 write data stall + + output l2_cpu2_flsh_ls_rd_l2_dly; // cpu2 ls local hazard flush + output l2_cpu2_flsh_ls_wr_l2_dly; // cpu2 ls local hazard flush + + output l2_cpu2_wr_data_stall; // cpu2 write data stall + + output l2_cpu3_flsh_ls_rd_l2_dly; // cpu3 ls local hazard flush + output l2_cpu3_flsh_ls_wr_l2_dly; // cpu3 ls local hazard flush + + output l2_cpu3_wr_data_stall; // cpu3 write data stall + + output [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; // cpu0 ls id local hazard flush + output [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; // cpu0 ls id local hazard flush + + output [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; // cpu1 ls id local hazard flush + output [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; // cpu1 ls id local hazard flush + + output [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; // cpu2 ls id local hazard flush + output [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; // cpu2 ls id local hazard flush + + output [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; // cpu3 ls id local hazard flush + output [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; // cpu3 ls id local hazard flush + + output l2_cpu0_flsh_ls_rd_l4_dly; // cpu0 ls global hazard flush + output l2_cpu0_flsh_if_rd_l4_dly; // cpu0 if global hazard flush + output l2_cpu0_flsh_tw_rd_l4_dly; // cpu0 tw global hazard flush + output l2_cpu0_flsh_ls_wr_l4_dly; // cpu0 ls global hazard flush + + output l2_cpu1_flsh_ls_rd_l4_dly; // cpu1 ls global hazard flush + output l2_cpu1_flsh_if_rd_l4_dly; // cpu1 if global hazard flush + output l2_cpu1_flsh_tw_rd_l4_dly; // cpu1 tw global hazard flush + output l2_cpu1_flsh_ls_wr_l4_dly; // cpu1 ls global hazard flush + + output l2_cpu2_flsh_ls_rd_l4_dly; // cpu2 ls global hazard flush + output l2_cpu2_flsh_if_rd_l4_dly; // cpu2 if global hazard flush + output l2_cpu2_flsh_tw_rd_l4_dly; // cpu2 tw global hazard flush + output l2_cpu2_flsh_ls_wr_l4_dly; // cpu2 ls global hazard flush + + output l2_cpu3_flsh_ls_rd_l4_dly; // cpu3 ls global hazard flush + output l2_cpu3_flsh_if_rd_l4_dly; // cpu3 if global hazard flush + output l2_cpu3_flsh_tw_rd_l4_dly; // cpu3 tw global hazard flush + output l2_cpu3_flsh_ls_wr_l4_dly; // cpu3 ls global hazard flush + + output [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; // cpu0 ls id global hazard flush + output [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; // cpu0 if id global hazard flush + output [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; // cpu0 ls id global hazard flush + output l2_cpu0_flsh_ls_wr_evict_l4_dly; // cpu0 ls evict hazard + + output [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; // cpu1 ls id global hazard flush + output [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; // cpu1 if id global hazard flush + output [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; // cpu1 ls id global hazard flush + output l2_cpu1_flsh_ls_wr_evict_l4_dly; // cpu1 ls evict hazard + + output [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; // cpu2 ls id global hazard flush + output [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; // cpu2 if id global hazard flush + output [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; // cpu2 ls id global hazard flush + output l2_cpu2_flsh_ls_wr_evict_l4_dly; // cpu2 ls evict hazard + + output [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; // cpu3 ls id global hazard flush + output [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; // cpu3 if id global hazard flush + output [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; // cpu3 ls id global hazard flush + output l2_cpu3_flsh_ls_wr_evict_l4_dly; // cpu3 ls evict hazard + + output l2_cpu0_lrq_haz_pending; // cpu0 lrq hazard pending + output l2_cpu1_lrq_haz_pending; // cpu1 lrq hazard pending + output l2_cpu2_lrq_haz_pending; // cpu2 lrq hazard pending + output l2_cpu3_lrq_haz_pending; // cpu3 lrq hazard pending + + output l2_cpu0_ifq_haz_pending; // cpu0 ifq hazard pending + output l2_cpu1_ifq_haz_pending; // cpu1 ifq hazard pending + output l2_cpu2_ifq_haz_pending; // cpu2 ifq hazard pending + output l2_cpu3_ifq_haz_pending; // cpu3 ifq hazard pending + + output l2_cpu0_trq_haz_pending; // cpu0 trq hazard pending + output l2_cpu1_trq_haz_pending; // cpu1 trq hazard pending + output l2_cpu2_trq_haz_pending; // cpu2 trq hazard pending + output l2_cpu3_trq_haz_pending; // cpu3 trq hazard pending + + output l2_cpu0_wrq_haz_pending; // cpu0 wrq hazard pending + output l2_cpu1_wrq_haz_pending; // cpu1 wrq hazard pending + output l2_cpu2_wrq_haz_pending; // cpu2 wrq hazard pending + output l2_cpu3_wrq_haz_pending; // cpu3 wrq hazard pending + + output l2_cpu0_idle_block_reqs_q; // cpu0 idle block requests + output l2_cpu1_idle_block_reqs_q; // cpu1 idle block requests + output l2_cpu2_idle_block_reqs_q; // cpu2 idle block requests + output l2_cpu3_idle_block_reqs_q; // cpu3 idle block requests + + output l2_cpu0_ls_peq_coll_l4_dly; // cpu0 peq collision detected + output l2_cpu1_ls_peq_coll_l4_dly; // cpu1 peq collision detected + output l2_cpu2_ls_peq_coll_l4_dly; // cpu2 peq collision detected + output l2_cpu3_ls_peq_coll_l4_dly; // cpu3 peq collision detected + +//----------------------------------------------------------------------------- +// tag_pipe +//----------------------------------------------------------------------------- + output [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; // tbnk0 clear cpu0 lrq entry + output [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; // tbnk0 clear cpu1 lrq entry + output [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; // tbnk0 clear cpu2 lrq entry + output [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; // tbnk0 clear cpu3 lrq entry + + output [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; // tbnk1 clear cpu0 lrq entry + output [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; // tbnk1 clear cpu1 lrq entry + output [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; // tbnk1 clear cpu2 lrq entry + output [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; // tbnk1 clear cpu3 lrq entry + + output [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; // tbnk0 clear cpu0 ifq entry + output [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; // tbnk0 clear cpu1 ifq entry + output [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; // tbnk0 clear cpu2 ifq entry + output [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; // tbnk0 clear cpu3 ifq entry + + output [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; // tbnk1 clear cpu0 ifq entry + output [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; // tbnk1 clear cpu1 ifq entry + output [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; // tbnk1 clear cpu2 ifq entry + output [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; // tbnk1 clear cpu3 ifq entry + + output l2_tbnk0_cpu0_trq_clr_l4_dly2_q; // tbnk0 clear cpu0 trq entry + output l2_tbnk0_cpu1_trq_clr_l4_dly2_q; // tbnk0 clear cpu1 trq entry + output l2_tbnk0_cpu2_trq_clr_l4_dly2_q; // tbnk0 clear cpu2 trq entry + output l2_tbnk0_cpu3_trq_clr_l4_dly2_q; // tbnk0 clear cpu3 trq entry + + output l2_tbnk1_cpu0_trq_clr_l4_dly2_q; // tbnk1 clear cpu0 trq entry + output l2_tbnk1_cpu1_trq_clr_l4_dly2_q; // tbnk1 clear cpu1 trq entry + output l2_tbnk1_cpu2_trq_clr_l4_dly2_q; // tbnk1 clear cpu2 trq entry + output l2_tbnk1_cpu3_trq_clr_l4_dly2_q; // tbnk1 clear cpu3 trq entry + + output [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; // tbnk0 clear cpu0 wrq entry + output [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; // tbnk0 clear cpu1 wrq entry + output [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; // tbnk0 clear cpu2 wrq entry + output [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; // tbnk0 clear cpu3 wrq entry + + output [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; // tbnk1 clear cpu0 wrq entry + output [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; // tbnk1 clear cpu1 wrq entry + output [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; // tbnk1 clear cpu2 wrq entry + output [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; // tbnk1 clear cpu3 wrq entry + + +//----------------------------------------------------------------------------- +// cpu_logic / cpu slave +//----------------------------------------------------------------------------- + output l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu0 ls rd flsh l4 active + output l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu0 wr rd flsh l4 active + + output l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu1 ls rd flsh l4 active + output l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu1 wr rd flsh l4 active + + output l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu2 ls rd flsh l4 active + output l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu2 wr rd flsh l4 active + + output l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu3 ls rd flsh l4 active + output l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu3 wr rd flsh l4 active + + +//----------------------------------------------------------------------------- +// feq / cpu slave +//----------------------------------------------------------------------------- + input [129:0] l2_cpu0_dsq_rd_data_q; // cpu0 wrq/dsq data + input [15:0] l2_cpu0_dsq_rd_byte_strb_q; // cpu0 wrq/dsq byte strobes + input [129:0] l2_cpu1_dsq_rd_data_q; // cpu1 wrq/dsq data + input [15:0] l2_cpu1_dsq_rd_byte_strb_q; // cpu1 wrq/dsq byte strobes + input [129:0] l2_cpu2_dsq_rd_data_q; // cpu2 wrq/dsq data + input [15:0] l2_cpu2_dsq_rd_byte_strb_q; // cpu2 wrq/dsq byte strobes + input [129:0] l2_cpu3_dsq_rd_data_q; // cpu3 wrq/dsq data + input [15:0] l2_cpu3_dsq_rd_byte_strb_q; // cpu3 wrq/dsq byte strobes + + output l2_cpu0_dsq_clr_vld_q; // cpu0 dsq clear wrq vld entry + output [3:0] l2_cpu0_dsq_clr_id_q; // cpu0 dsq clear wrq buffer id + output l2_cpu0_dsq_rd_en; // cpu0 dsq/wrq data enable + output l2_cpu0_dsq_rd_en_x2; // cpu0 dsq/wrq data enable x2 + output [3:0] l2_cpu0_dsq_rd_buf_id; // cpu0 dsq/wrq data select + output l2_cpu1_dsq_clr_vld_q; // cpu1 dsq clear wrq vld entry + output [3:0] l2_cpu1_dsq_clr_id_q; // cpu1 dsq clear wrq buffer id + output l2_cpu1_dsq_rd_en; // cpu1 dsq/wrq data enable + output l2_cpu1_dsq_rd_en_x2; // cpu1 dsq/wrq data enable x2 + output [3:0] l2_cpu1_dsq_rd_buf_id; // cpu1 dsq/wrq data select + output l2_cpu2_dsq_clr_vld_q; // cpu2 dsq clear wrq vld entry + output [3:0] l2_cpu2_dsq_clr_id_q; // cpu2 dsq clear wrq buffer id + output l2_cpu2_dsq_rd_en; // cpu2 dsq/wrq data enable + output l2_cpu2_dsq_rd_en_x2; // cpu2 dsq/wrq data enable x2 + output [3:0] l2_cpu2_dsq_rd_buf_id; // cpu2 dsq/wrq data select + output l2_cpu3_dsq_clr_vld_q; // cpu3 dsq clear wrq vld entry + output l2_cpu3_dsq_rd_en; // cpu3 dsq/wrq data enable + output l2_cpu3_dsq_rd_en_x2; // cpu3 dsq/wrq data enable x2 + output [3:0] l2_cpu3_dsq_clr_id_q; // cpu3 dsq clear wrq buffer id + output [3:0] l2_cpu3_dsq_rd_buf_id; // cpu3 dsq/wrq data select + +//----------------------------------------------------------------------------- +// arbitration +//----------------------------------------------------------------------------- + output l2_cpu0_rd_vld_skid; // cpu0 read skid buffer valid + output l2_cpu1_rd_vld_skid; // cpu1 read skid buffer valid + output l2_cpu2_rd_vld_skid; // cpu2 read skid buffer valid + output l2_cpu3_rd_vld_skid; // cpu3 read skid buffer valid + + output l2_cpu0_pf_rd_vld_skid_popped; // cpu0 pf read skid buffer popped + output l2_cpu1_pf_rd_vld_skid_popped; // cpu1 pf read skid buffer popped + output l2_cpu2_pf_rd_vld_skid_popped; // cpu2 pf read skid buffer popped + output l2_cpu3_pf_rd_vld_skid_popped; // cpu3 pf read skid buffer popped + + output l2_cpu0_rd_arb; // + output l2_cpu1_rd_arb; // + output l2_cpu2_rd_arb; // + output l2_cpu3_rd_arb; // + + output l2_cpu0_wr_vld_skid; // cpu0 write skid buffer valid + output l2_cpu1_wr_vld_skid; // cpu1 write skid buffer valid + output l2_cpu2_wr_vld_skid; // cpu2 write skid buffer valid + output l2_cpu3_wr_vld_skid; // cpu3 write skid buffer valid + + output l2_cpu0_wr_arb; // + output l2_cpu1_wr_arb; // + output l2_cpu2_wr_arb; // + output l2_cpu3_wr_arb; // + + output l2_cpu0_ic_vld_skid; // cpu0 peripheral (ic) skid buffer valid + output l2_cpu1_ic_vld_skid; // cpu1 peripheral (ic) skid buffer valid + output l2_cpu2_ic_vld_skid; // cpu2 peripheral (ic) skid buffer valid + output l2_cpu3_ic_vld_skid; // cpu3 peripheral (ic) skid buffer valid + + output l2_cpu0_ic_barrier_stall_q; // cpu0 (ic) barrier stall + output l2_cpu1_ic_barrier_stall_q; // cpu1 (ic) barrier stall + output l2_cpu2_ic_barrier_stall_q; // cpu2 (ic) barrier stall + output l2_cpu3_ic_barrier_stall_q; // cpu3 (ic) barrier stall + + output l2_cpu0_blk_non_evict_wr; // cpu0 block non-evict writes from arbitrating + output l2_cpu1_blk_non_evict_wr; // cpu1 block non-evict writes from arbitrating + output l2_cpu2_blk_non_evict_wr; // cpu2 block non-evict writes from arbitrating + output l2_cpu3_blk_non_evict_wr; // cpu3 block non-evict writes from arbitrating + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + input l2_cpu0_idle_wakeup_q; // cpu0 idle wakeup + input l2_cpu0_rd_arb_fast; // cpu0 read arbitration fast request + input [4:0] l2_cpu0_rd_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu0_rd_lrq_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu0_rd_type_arb_set; // cpu0 read arbitration type + input [2:0] l2_cpu0_rd_cache_attr_arb_set; // cpu0 read arbitration cache attributes + input [7:0] l2_cpu0_rd_page_attr_arb_set; // cpu0 read arbitration page attributes + input [2:0] l2_cpu0_rd_elem_size_arb_set; // cpu0 read arbitration element size + input l2_cpu0_rd_way_arb_set; // cpu0 read arbitration way + input l2_cpu0_rd_replayed_arb_set; // cpu0 read arbitration replayed + input l2_cpu0_rd_excl_arb_set; // cpu0 read arbitration exclusive + input l2_cpu0_rd_priv_arb_set; // cpu0 read arbitration priv + input [1:0] l2_cpu0_rd_shared_arb_set; // cpu0 read arbitration shared + input l2_cpu0_rd_va48_arb_set; // cpu0 read arbitration va48 + input l2_cpu0_rd_aarch64_arb_set; // cpu0 read arbitration aarch64 + input [15:8] l2_cpu0_rd_asid_arb_set; // cpu0 read arbitration asid + input l2_cpu0_rd_prfm_arb_set; // cpu0 read arbitration prfm + input [44:0] l2_cpu0_rd_addr_arb_set; // cpu0 read arbitration address + input l2_cpu0_rd_bypass_arb_set; // cpu0 read arbitration bypass + input l2_cpu0_rd_bypass_req_can_e5; // cpu0 read arbitration bypass cancelled request + input l2_cpu0_early_rd_reqe4_e5_q; // cpu0 read arbitration bypass cancelled request + input l2_cpu0_rd_bypass_way_e5; // cpu0 read arbitration bypass way + input [2:0] l2_cpu0_rd_bypass_bufid_e5; // cpu0 read arbitration bypass bufid + input [2:0] l2_cpu0_rd_bypass_lrq_id_e5; // cpu0 read arbitration bypass bufid + + input l2_cpu0_wr_arb_fast; // cpu0 write arbitration fast request + input [3:0] l2_cpu0_wr_id_arb_set; // cpu0 write arbitration id for 1st qw + input [3:0] l2_cpu0_wr_partial_dw_arb_set; // cpu0 write partial qw byte strobe indicator + input [2:0] l2_cpu0_wr_cache_attr_arb_set; // cpu0 write arbitration cache attributes + input [7:0] l2_cpu0_wr_page_attr_arb_set; // cpu0 write arbitration page attributes + input [2:0] l2_cpu0_wr_elem_size_arb_set; // cpu0 write arbitration element size + input [2:0] l2_cpu0_wr_type_arb_set; // cpu0 write arbitration type + input [11:0] l2_cpu0_wr_cl_id_arb_set; // cpu0 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu0_wr_priv_arb_set; // cpu0 write arbitration priv + input [1:0] l2_cpu0_wr_shared_arb_set; // cpu0 write arbitration shared + input l2_cpu0_wr_last_arb_set; // cpu0 write arbitration last + input l2_cpu0_wr_clean_evict_arb_set; // cpu0 write arbitration clean eviction + input l2_cpu0_wr_err_arb_set; // cpu0 write arbitration error + input l2_cpu0_wr_way_arb_set; // cpu0 write arbitration way + input l2_cpu0_wr_dirty_arb_set; // cpu0 write arbitration dirty + input l2_cpu0_wr_1st_replayed_arb_set; // cpu0 write arbitration 1st replay indicator + input [44:0] l2_cpu0_wr_addr_arb_set; // cpu0 write arbitration address + input l2_cpu0_ic_arb_fast; // cpu0 peripheral (ic) arbitration fast request + input [2:0] l2_cpu0_ic_id_arb_set; // cpu0 peripheral (ic) fill buffer id + input l2_cpu0_ic_write_arb_set; // cpu0 peripheral (ic) write indicator + input l2_cpu0_ic_excl_arb_set; // cpu0 peripheral (ic) exclusive indicator + input [2:0] l2_cpu0_ic_elem_size_arb_set; // cpu0 peripheral (ic) element size + input l2_cpu0_ic_ns_arb_set; // cpu0 peripheral (ic) non-secure + input [15:0] l2_cpu0_ic_addr_arb_set; // cpu0 peripheral (ic) address + input [31:0] l2_cpu0_ic_data_arb_set; // cpu0 peripheral (ic) write data + + input l2_cpu0_wrq_almost_full; // cpu0 wrq almost full indicator + + input l2_cpu0_ls_wr_req_w2a; // cpu0 ls write request + input l2_cpu0_ls_wr_last_w2a; // cpu0 ls last indicator + input l2_cpu0_ls_wr_dirty_w2a; // cpu0 ls dirty indicator + input l2_cpu0_ls_wr_err_w2a; // cpu0 ls error indicator + input [2:0] l2_cpu0_ls_wr_type_w2a; // cpu0 ls write type + input [4:0] l2_cpu0_ls_wr_ccb_id_w2a; // cpu0 ls ccb id + input [127:0] l2_cpu0_ls_wr_data_w2a; // cpu0 ls write data + + input l2_cpu0_ls_ccb_resp; // cpu0 ls ccb resp + input [4:0] l2_cpu0_ls_ccb_resp_id; // cpu0 ls ccb id + input l2_cpu0_ls_ccb_data_wr; // cpu0 ls ccb data xfer + + input l2_cpu0_if_ccb_resp; // cpu0 if ccb resp + input [4:0] l2_cpu0_if_ccb_resp_id; // cpu0 if ccb id + + input l2_cpu0_tw_ccb_resp; // cpu0 tw ccb resp + input [4:0] l2_cpu0_tw_ccb_resp_id; // cpu0 tw ccb id + + input l2_cpu0_if_sync_done_q; // cpu0 sync response + input l2_cpu0_tlb_sync_done_q; // cpu0 tlb sync response + + input [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; // cpu0 lrq clear hazard id + input [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; // cpu0 wrq clear hazard id + input [3:0] l2_cpu0_ls_rd_haz_id_arb_q; // cpu0 ls rd wrq hazard id + input [2:0] l2_cpu0_ls_wr_haz_id_arb_q; // cpu0 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + input l2_cpu1_idle_wakeup_q; // cpu1 idle wakeup + input l2_cpu1_rd_arb_fast; // cpu1 read arbitration fast request + input [4:0] l2_cpu1_rd_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu1_rd_lrq_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu1_rd_type_arb_set; // cpu1 read arbitration type + input [2:0] l2_cpu1_rd_cache_attr_arb_set; // cpu1 read arbitration cache attributes + input [7:0] l2_cpu1_rd_page_attr_arb_set; // cpu1 read arbitration page attributes + input [2:0] l2_cpu1_rd_elem_size_arb_set; // cpu1 read arbitration element size + input l2_cpu1_rd_way_arb_set; // cpu1 read arbitration way + input l2_cpu1_rd_replayed_arb_set; // cpu1 read arbitration replayed + input l2_cpu1_rd_excl_arb_set; // cpu1 read arbitration exclusive + input l2_cpu1_rd_priv_arb_set; // cpu1 read arbitration priv + input [1:0] l2_cpu1_rd_shared_arb_set; // cpu1 read arbitration shared + input l2_cpu1_rd_va48_arb_set; // cpu1 read arbitration va48 + input l2_cpu1_rd_aarch64_arb_set; // cpu1 read arbitration aarch64 + input [15:8] l2_cpu1_rd_asid_arb_set; // cpu1 read arbitration asid + input l2_cpu1_rd_prfm_arb_set; // cpu1 read arbitration prfm + input [44:0] l2_cpu1_rd_addr_arb_set; // cpu1 read arbitration address + input l2_cpu1_rd_bypass_arb_set; // cpu1 read arbitration bypass + input l2_cpu1_rd_bypass_req_can_e5; // cpu1 read arbitration bypass cancelled request + input l2_cpu1_early_rd_reqe4_e5_q; // cpu1 read arbitration bypass cancelled request + input l2_cpu1_rd_bypass_way_e5; // cpu1 read arbitration bypass way + input [2:0] l2_cpu1_rd_bypass_bufid_e5; // cpu1 read arbitration bypass bufid + input [2:0] l2_cpu1_rd_bypass_lrq_id_e5; // cpu1 read arbitration bypass bufid + + input l2_cpu1_wr_arb_fast; // cpu1 write arbitration fast request + input [3:0] l2_cpu1_wr_id_arb_set; // cpu1 write arbitration id for 1st qw + input [3:0] l2_cpu1_wr_partial_dw_arb_set; // cpu1 write partial qw byte strobe indicator + input [2:0] l2_cpu1_wr_cache_attr_arb_set; // cpu1 write arbitration cache attributes + input [7:0] l2_cpu1_wr_page_attr_arb_set; // cpu1 write arbitration page attributes + input [2:0] l2_cpu1_wr_elem_size_arb_set; // cpu1 write arbitration element size + input [2:0] l2_cpu1_wr_type_arb_set; // cpu1 write arbitration type + input [11:0] l2_cpu1_wr_cl_id_arb_set; // cpu1 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu1_wr_priv_arb_set; // cpu1 write arbitration priv + input [1:0] l2_cpu1_wr_shared_arb_set; // cpu1 write arbitration shared + input l2_cpu1_wr_last_arb_set; // cpu1 write arbitration last + input l2_cpu1_wr_clean_evict_arb_set; // cpu1 write arbitration clean eviction + input l2_cpu1_wr_err_arb_set; // cpu1 write arbitration error + input l2_cpu1_wr_way_arb_set; // cpu1 write arbitration way + input l2_cpu1_wr_dirty_arb_set; // cpu1 write arbitration dirty + input l2_cpu1_wr_1st_replayed_arb_set; // cpu1 write arbitration 1st replay indicator + input [44:0] l2_cpu1_wr_addr_arb_set; // cpu1 write arbitration address + input l2_cpu1_ic_arb_fast; // cpu1 peripheral (ic) arbitration fast request + input [2:0] l2_cpu1_ic_id_arb_set; // cpu1 peripheral (ic) fill buffer id + input l2_cpu1_ic_write_arb_set; // cpu1 peripheral (ic) write indicator + input l2_cpu1_ic_excl_arb_set; // cpu1 peripheral (ic) exclusive indicator + input [2:0] l2_cpu1_ic_elem_size_arb_set; // cpu1 peripheral (ic) element size + input l2_cpu1_ic_ns_arb_set; // cpu1 peripheral (ic) non-secure + input [15:0] l2_cpu1_ic_addr_arb_set; // cpu1 peripheral (ic) address + input [31:0] l2_cpu1_ic_data_arb_set; // cpu1 peripheral (ic) write data + + input l2_cpu1_wrq_almost_full; // cpu1 wrq almost full indicator + + input l2_cpu1_ls_wr_req_w2a; // cpu1 ls write request + input l2_cpu1_ls_wr_last_w2a; // cpu1 ls last indicator + input l2_cpu1_ls_wr_dirty_w2a; // cpu1 ls dirty indicator + input l2_cpu1_ls_wr_err_w2a; // cpu1 ls error indicator + input [2:0] l2_cpu1_ls_wr_type_w2a; // cpu1 ls write type + input [4:0] l2_cpu1_ls_wr_ccb_id_w2a; // cpu1 ls ccb id + input [127:0] l2_cpu1_ls_wr_data_w2a; // cpu1 ls write data + + input l2_cpu1_ls_ccb_resp; // cpu1 ls ccb resp + input [4:0] l2_cpu1_ls_ccb_resp_id; // cpu1 ls ccb id + input l2_cpu1_ls_ccb_data_wr; // cpu1 ls ccb data xfer + + input l2_cpu1_if_ccb_resp; // cpu1 if ccb resp + input [4:0] l2_cpu1_if_ccb_resp_id; // cpu1 if ccb id + + input l2_cpu1_tw_ccb_resp; // cpu1 tw ccb resp + input [4:0] l2_cpu1_tw_ccb_resp_id; // cpu1 tw ccb id + + input l2_cpu1_if_sync_done_q; // cpu1 sync response + input l2_cpu1_tlb_sync_done_q; // cpu1 tlb sync response + + input [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; // cpu1 lrq clear hazard id + input [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; // cpu1 wrq clear hazard id + input [3:0] l2_cpu1_ls_rd_haz_id_arb_q; // cpu1 ls rd wrq hazard id + input [2:0] l2_cpu1_ls_wr_haz_id_arb_q; // cpu1 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + input l2_cpu2_idle_wakeup_q; // cpu2 idle wakeup + input l2_cpu2_rd_arb_fast; // cpu2 read arbitration fast request + input [4:0] l2_cpu2_rd_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu2_rd_lrq_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu2_rd_type_arb_set; // cpu2 read arbitration type + input [2:0] l2_cpu2_rd_cache_attr_arb_set; // cpu2 read arbitration cache attributes + input [7:0] l2_cpu2_rd_page_attr_arb_set; // cpu2 read arbitration page attributes + input [2:0] l2_cpu2_rd_elem_size_arb_set; // cpu2 read arbitration element size + input l2_cpu2_rd_way_arb_set; // cpu2 read arbitration way + input l2_cpu2_rd_replayed_arb_set; // cpu2 read arbitration replayed + input l2_cpu2_rd_excl_arb_set; // cpu2 read arbitration exclusive + input l2_cpu2_rd_priv_arb_set; // cpu2 read arbitration priv + input [1:0] l2_cpu2_rd_shared_arb_set; // cpu2 read arbitration shared + input l2_cpu2_rd_va48_arb_set; // cpu0 read arbitration va48 + input l2_cpu2_rd_aarch64_arb_set; // cpu2 read arbitration aarch64 + input [15:8] l2_cpu2_rd_asid_arb_set; // cpu2 read arbitration asid + input l2_cpu2_rd_prfm_arb_set; // cpu2 read arbitration prfm + input [44:0] l2_cpu2_rd_addr_arb_set; // cpu2 read arbitration address + input l2_cpu2_rd_bypass_arb_set; // cpu2 read arbitration bypass + input l2_cpu2_rd_bypass_req_can_e5; // cpu2 read arbitration bypass cancelled request + input l2_cpu2_early_rd_reqe4_e5_q; // cpu2 read arbitration bypass cancelled request + input l2_cpu2_rd_bypass_way_e5; // cpu2 read arbitration bypass way + input [2:0] l2_cpu2_rd_bypass_bufid_e5; // cpu2 read arbitration bypass bufid + input [2:0] l2_cpu2_rd_bypass_lrq_id_e5; // cpu2 read arbitration bypass bufid + + input l2_cpu2_wr_arb_fast; // cpu2 write arbitration fast request + input [3:0] l2_cpu2_wr_id_arb_set; // cpu2 write arbitration id for 1st qw + input [3:0] l2_cpu2_wr_partial_dw_arb_set; // cpu2 write partial qw byte strobe indicator + input [2:0] l2_cpu2_wr_cache_attr_arb_set; // cpu2 write arbitration cache attributes + input [7:0] l2_cpu2_wr_page_attr_arb_set; // cpu2 write arbitration page attributes + input [2:0] l2_cpu2_wr_elem_size_arb_set; // cpu2 write arbitration element size + input [2:0] l2_cpu2_wr_type_arb_set; // cpu2 write arbitration type + input [11:0] l2_cpu2_wr_cl_id_arb_set; // cpu2 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu2_wr_priv_arb_set; // cpu2 write arbitration priv + input [1:0] l2_cpu2_wr_shared_arb_set; // cpu2 write arbitration shared + input l2_cpu2_wr_last_arb_set; // cpu2 write arbitration last + input l2_cpu2_wr_clean_evict_arb_set; // cpu2 write arbitration clean eviction + input l2_cpu2_wr_err_arb_set; // cpu2 write arbitration error + input l2_cpu2_wr_way_arb_set; // cpu2 write arbitration way + input l2_cpu2_wr_dirty_arb_set; // cpu2 write arbitration dirty + input l2_cpu2_wr_1st_replayed_arb_set; // cpu2 write arbitration 1st replay indicator + input [44:0] l2_cpu2_wr_addr_arb_set; // cpu2 write arbitration address + input l2_cpu2_ic_arb_fast; // cpu2 peripheral (ic) arbitration fast request + input [2:0] l2_cpu2_ic_id_arb_set; // cpu2 peripheral (ic) fill buffer id + input l2_cpu2_ic_write_arb_set; // cpu2 peripheral (ic) write indicator + input l2_cpu2_ic_excl_arb_set; // cpu2 peripheral (ic) exclusive indicator + input [2:0] l2_cpu2_ic_elem_size_arb_set; // cpu2 peripheral (ic) element size + input l2_cpu2_ic_ns_arb_set; // cpu2 peripheral (ic) non-secure + input [15:0] l2_cpu2_ic_addr_arb_set; // cpu2 peripheral (ic) address + input [31:0] l2_cpu2_ic_data_arb_set; // cpu2 peripheral (ic) write data + + input l2_cpu2_wrq_almost_full; // cpu2 wrq almost full indicator + + input l2_cpu2_ls_wr_req_w2a; // cpu2 ls write request + input l2_cpu2_ls_wr_last_w2a; // cpu2 ls last indicator + input l2_cpu2_ls_wr_dirty_w2a; // cpu2 ls dirty indicator + input l2_cpu2_ls_wr_err_w2a; // cpu2 ls error indicator + input [2:0] l2_cpu2_ls_wr_type_w2a; // cpu2 ls write type + input [4:0] l2_cpu2_ls_wr_ccb_id_w2a; // cpu2 ls ccb id + input [127:0] l2_cpu2_ls_wr_data_w2a; // cpu2 ls write data + + input l2_cpu2_ls_ccb_resp; // cpu2 ls ccb resp + input [4:0] l2_cpu2_ls_ccb_resp_id; // cpu2 ls ccb id + input l2_cpu2_ls_ccb_data_wr; // cpu2 ls ccb data xfer + + input l2_cpu2_if_ccb_resp; // cpu2 if ccb resp + input [4:0] l2_cpu2_if_ccb_resp_id; // cpu2 if ccb id + + input l2_cpu2_tw_ccb_resp; // cpu2 tw ccb resp + input [4:0] l2_cpu2_tw_ccb_resp_id; // cpu2 tw ccb id + + input l2_cpu2_if_sync_done_q; // cpu2 sync response + input l2_cpu2_tlb_sync_done_q; // cpu2 tlb sync response + + input [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; // cpu2 lrq clear hazard id + input [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; // cpu2 wrq clear hazard id + input [3:0] l2_cpu2_ls_rd_haz_id_arb_q; // cpu2 ls rd wrq hazard id + input [2:0] l2_cpu2_ls_wr_haz_id_arb_q; // cpu2 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + input l2_cpu3_idle_wakeup_q; // cpu3 idle wakeup + input l2_cpu3_rd_arb_fast; // cpu3 read arbitration fast request + input [4:0] l2_cpu3_rd_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu3_rd_lrq_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu3_rd_type_arb_set; // cpu3 read arbitration type + input [2:0] l2_cpu3_rd_cache_attr_arb_set; // cpu3 read arbitration cache attributes + input [7:0] l2_cpu3_rd_page_attr_arb_set; // cpu3 read arbitration page attributes + input [2:0] l2_cpu3_rd_elem_size_arb_set; // cpu3 read arbitration element size + input l2_cpu3_rd_way_arb_set; // cpu3 read arbitration way + input l2_cpu3_rd_replayed_arb_set; // cpu3 read arbitration replayed + input l2_cpu3_rd_excl_arb_set; // cpu3 read arbitration exclusive + input l2_cpu3_rd_priv_arb_set; // cpu3 read arbitration priv + input [1:0] l2_cpu3_rd_shared_arb_set; // cpu3 read arbitration shared + input l2_cpu3_rd_va48_arb_set; // cpu3 read arbitration va48 + input l2_cpu3_rd_aarch64_arb_set; // cpu3 read arbitration aarch64 + input [15:8] l2_cpu3_rd_asid_arb_set; // cpu3 read arbitration asid + input l2_cpu3_rd_prfm_arb_set; // cpu3 read arbitration prfm + input [44:0] l2_cpu3_rd_addr_arb_set; // cpu3 read arbitration address + input l2_cpu3_rd_bypass_arb_set; // cpu3 read arbitration bypass + input l2_cpu3_rd_bypass_req_can_e5; // cpu3 read arbitration bypass cancelled request + input l2_cpu3_early_rd_reqe4_e5_q; // cpu3 read arbitration bypass cancelled request + input l2_cpu3_rd_bypass_way_e5; // cpu3 read arbitration bypass way + input [2:0] l2_cpu3_rd_bypass_bufid_e5; // cpu3 read arbitration bypass bufid + input [2:0] l2_cpu3_rd_bypass_lrq_id_e5; // cpu3 read arbitration bypass bufid + + input l2_cpu3_wr_arb_fast; // cpu3 write arbitration fast request + input [3:0] l2_cpu3_wr_id_arb_set; // cpu3 write arbitration id for 1st qw + input [3:0] l2_cpu3_wr_partial_dw_arb_set; // cpu3 write partial qw byte strobe indicator + input [2:0] l2_cpu3_wr_cache_attr_arb_set; // cpu3 write arbitration cache attributes + input [7:0] l2_cpu3_wr_page_attr_arb_set; // cpu3 write arbitration page attributes + input [2:0] l2_cpu3_wr_elem_size_arb_set; // cpu3 write arbitration element size + input [2:0] l2_cpu3_wr_type_arb_set; // cpu3 write arbitration type + input [11:0] l2_cpu3_wr_cl_id_arb_set; // cpu3 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu3_wr_priv_arb_set; // cpu3 write arbitration priv + input [1:0] l2_cpu3_wr_shared_arb_set; // cpu3 write arbitration shared + input l2_cpu3_wr_last_arb_set; // cpu3 write arbitration last + input l2_cpu3_wr_clean_evict_arb_set; // cpu3 write arbitration clean eviction + input l2_cpu3_wr_err_arb_set; // cpu3 write arbitration error + input l2_cpu3_wr_way_arb_set; // cpu3 write arbitration way + input l2_cpu3_wr_dirty_arb_set; // cpu3 write arbitration dirty + input l2_cpu3_wr_1st_replayed_arb_set; // cpu3 write arbitration 1st replay indicator + input [44:0] l2_cpu3_wr_addr_arb_set; // cpu3 write arbitration address + input l2_cpu3_ic_arb_fast; // cpu3 peripheral (ic) arbitration fast request + input [2:0] l2_cpu3_ic_id_arb_set; // cpu3 peripheral (ic) fill buffer id + input l2_cpu3_ic_write_arb_set; // cpu3 peripheral (ic) write indicator + input l2_cpu3_ic_excl_arb_set; // cpu3 peripheral (ic) exclusive indicator + input [2:0] l2_cpu3_ic_elem_size_arb_set; // cpu3 peripheral (ic) element size + input l2_cpu3_ic_ns_arb_set; // cpu3 peripheral (ic) non-secure + input [15:0] l2_cpu3_ic_addr_arb_set; // cpu3 peripheral (ic) address + input [31:0] l2_cpu3_ic_data_arb_set; // cpu3 peripheral (ic) write data + + input l2_cpu3_wrq_almost_full; // cpu3 wrq almost full indicator + + input l2_cpu3_ls_wr_req_w2a; // cpu3 ls write request + input l2_cpu3_ls_wr_last_w2a; // cpu3 ls last indicator + input l2_cpu3_ls_wr_dirty_w2a; // cpu3 ls dirty indicator + input l2_cpu3_ls_wr_err_w2a; // cpu3 ls error indicator + input [2:0] l2_cpu3_ls_wr_type_w2a; // cpu3 ls write type + input [4:0] l2_cpu3_ls_wr_ccb_id_w2a; // cpu3 ls ccb id + input [127:0] l2_cpu3_ls_wr_data_w2a; // cpu3 ls write data + + input l2_cpu3_ls_ccb_resp; // cpu3 ls ccb resp + input [4:0] l2_cpu3_ls_ccb_resp_id; // cpu3 ls ccb id + input l2_cpu3_ls_ccb_data_wr; // cpu3 ls ccb data xfer + + input l2_cpu3_if_ccb_resp; // cpu3 if ccb resp + input [4:0] l2_cpu3_if_ccb_resp_id; // cpu3 if ccb id + + input l2_cpu3_tw_ccb_resp; // cpu3 tw ccb resp + input [4:0] l2_cpu3_tw_ccb_resp_id; // cpu3 tw ccb id + + input l2_cpu3_if_sync_done_q; // cpu3 sync response + input l2_cpu3_tlb_sync_done_q; // cpu3 tlb sync response + + input [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; // cpu3 lrq clear hazard id + input [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; // cpu3 wrq clear hazard id + input [3:0] l2_cpu3_ls_rd_haz_id_arb_q; // cpu3 ls rd wrq hazard id + input [2:0] l2_cpu3_ls_wr_haz_id_arb_q; // cpu3 ls wr lrq hazard id + +// END L2-CPU interface + +//------------------------------------------------------------------- +// TM interface +//------------------------------------------------------------------- +// BEGIN TIMER-CPU interface + output [3:0] tm_cpu0_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu0_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu1_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu1_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu2_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu2_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu3_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu3_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> +// END TIMER-CPU interface + +//----------------------------------------------------------------------------- +// IC interface +//----------------------------------------------------------------------------- + input ls_cpu0_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu0_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu0_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu0_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu0_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu0_raw_eae_secure; // LS S LPAE to IC + + input ds_cpu0_ic_sample_spr; + input [4:0] ds_cpu0_ic_cpsr_mode; + input ds_cpu0_ic_aa64naa32; + input ds_cpu0_ic_hcr_change; + input ds_cpu0_ic_scr_change; +// BEGIN INCLUDE FOR CPU1 + input ds_cpu1_ic_sample_spr; + input [4:0] ds_cpu1_ic_cpsr_mode; + input ds_cpu1_ic_aa64naa32; + input ds_cpu1_ic_hcr_change; + input ds_cpu1_ic_scr_change; + input ls_cpu1_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu1_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu1_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu1_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu1_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu1_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input ds_cpu2_ic_sample_spr; + input [4:0] ds_cpu2_ic_cpsr_mode; + input ds_cpu2_ic_aa64naa32; + input ds_cpu2_ic_hcr_change; + input ds_cpu2_ic_scr_change; + input ls_cpu2_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu2_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu2_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu2_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu2_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu2_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input ds_cpu3_ic_sample_spr; + input [4:0] ds_cpu3_ic_cpsr_mode; + input ds_cpu3_ic_aa64naa32; + input ds_cpu3_ic_hcr_change; + input ds_cpu3_ic_scr_change; + input ls_cpu3_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu3_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu3_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu3_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu3_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu3_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU3 + + output [`MAIA_CN:0] ic_nfiq; // IC physical FIQ + output [`MAIA_CN:0] ic_nirq; // IC physical IRQ + output [`MAIA_CN:0] ic_nsei; // IC physical SEI + output [`MAIA_CN:0] ic_nvfiq; // IC virtual FIQ + output [`MAIA_CN:0] ic_nvirq; // IC virtual IRQ + output [`MAIA_CN:0] ic_nvsei; // IC virtual SEI + output [`MAIA_CN:0] ic_p_valid; // IC is present + + output [`MAIA_CN:0] ic_sample_spr; // IC sample signal for TC, TALL*, EL* signals + output [`MAIA_CN:0] ic_hcr_change_complete; + output [`MAIA_CN:0] ic_scr_change_complete; + output [`MAIA_CN:0] ic_el_change_complete; + output [`MAIA_CN:0] ic_ich_el2_tc; // IC trap common + output [`MAIA_CN:0] ic_ich_el2_tall0; // IC trap all grp0 + output [`MAIA_CN:0] ic_ich_el2_tall1; // IC trap all grp1 + output [`MAIA_CN:0] ic_sra_el3_en; // IC System Registers enabled in EL3 + output [`MAIA_CN:0] ic_sra_el1s_en; // IC System Registers enabled in EL1S + output [`MAIA_CN:0] ic_sra_el2_en; // IC System Registers enabled in EL2 + output [`MAIA_CN:0] ic_sra_el1ns_en; // IC System Registers enabled in EL1NS + output [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; // IC HYP_TRAP EL1NS accesses + output [`MAIA_CN:0] ic_sre_el1ns_mon_trap; // IC MON_TRAP EL1NS accesses + output [`MAIA_CN:0] ic_sre_el1s_mon_trap; // IC MON_TRAP EL1S accesses + output [`MAIA_CN:0] ic_sre_el2_mon_trap; // IC MON_TRAP EL2 accesses + output [`MAIA_CN:0] ic_block_eoi_sgi_wr; // IC Block all EOI and SGI write accesses + +//----------------------------------------------------------------------------- +// DT interface +//----------------------------------------------------------------------------- +// BEGIN DT-CPU interface +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + output dt_cpu0_dbif_req_pclk; // Debug Interface Req + output dt_cpu0_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu0_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu0_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu0_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu0_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu0_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu0_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu0_edbgrq_pclk; // External Debug Request + output dt_cpu0_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu0_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu0_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu0_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu0_et_oslock_gclk; // ETM OS Lock + input dt_cpu0_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu0_halt_ack_gclk; // Core Halted + input dt_cpu0_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu0_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu0_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu0_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu0_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu0_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu0_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu0_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu0_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu0_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu0_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu0_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu0_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu0_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu0_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + output dt_cpu1_dbif_req_pclk; // Debug Interface Req + output dt_cpu1_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu1_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu1_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu1_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu1_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu1_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu1_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu1_edbgrq_pclk; // External Debug Request + output dt_cpu1_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu1_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu1_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu1_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu1_et_oslock_gclk; // ETM OS Lock + input dt_cpu1_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu1_halt_ack_gclk; // Core Halted + input dt_cpu1_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu1_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu1_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu1_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu1_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu1_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu1_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu1_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu1_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu1_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu1_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu1_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu1_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu1_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu1_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + output dt_cpu2_dbif_req_pclk; // Debug Interface Req + output dt_cpu2_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu2_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu2_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu2_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu2_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu2_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu2_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu2_edbgrq_pclk; // External Debug Request + output dt_cpu2_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu2_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu2_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu2_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu2_et_oslock_gclk; // ETM OS Lock + input dt_cpu2_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu2_halt_ack_gclk; // Core Halted + input dt_cpu2_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu2_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu2_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu2_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu2_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu2_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu2_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu2_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu2_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu2_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu2_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu2_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu2_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu2_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu2_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + output dt_cpu3_dbif_req_pclk; // Debug Interface Req + output dt_cpu3_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu3_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu3_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu3_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu3_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu3_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu3_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu3_edbgrq_pclk; // External Debug Request + output dt_cpu3_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu3_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu3_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu3_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu3_et_oslock_gclk; // ETM OS Lock + input dt_cpu3_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu3_halt_ack_gclk; // Core Halted + input dt_cpu3_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu3_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu3_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu3_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu3_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu3_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu3_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu3_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu3_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu3_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu3_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu3_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu3_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu3_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu3_noclkstop_pclk; // force CPU clock on from DT-PCLK +// END DT-CPU interface + +//----------------------------------------------------------------------------- +// CK interface +//----------------------------------------------------------------------------- +// BEGIN CK-CPU interface + input ds_cpu0_reset_req; // Warm Reset request + input ds_cpu0_wfi_req; // WFI request + input ds_cpu0_wfe_req; // WFI request + input ds_cpu0_flush; // flush for exception rtn + input [5:0] ds_cpu0_flush_type; // flush type + input ds_cpu0_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu0_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu0_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu0_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu0_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu0_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu0_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu0_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu0_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu0_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu0_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu0_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu0_hcr_va; // virtual abort + input ds_cpu0_hcr_vi; // virtual IRQ + input ds_cpu0_hcr_vf; // virtual FIQ + input [2:0] ds_cpu0_cpuectlr_ret; // CPU Retention control + output ck_cpu0_event_reg; // WFE event reg + output ck_cpu0_wfi_ack; // WFI acknowledge to DS + output ck_cpu0_wfe_ack; // WFE acknowledge to DS + output ck_cpu0_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu1_reset_req; // Warm Reset request + input ds_cpu1_wfi_req; // WFI request + input ds_cpu1_wfe_req; // WFI request + input ds_cpu1_flush; // flush for exception rtn + input [5:0] ds_cpu1_flush_type; // flush type + input ds_cpu1_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu1_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu1_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu1_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu1_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu1_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu1_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu1_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu1_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu1_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu1_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu1_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu1_hcr_va; // virtual abort + input ds_cpu1_hcr_vi; // virtual IRQ + input ds_cpu1_hcr_vf; // virtual FIQ + input [2:0] ds_cpu1_cpuectlr_ret; // CPU Retention control + output ck_cpu1_event_reg; // WFE event reg + output ck_cpu1_wfi_ack; // WFI acknowledge to DS + output ck_cpu1_wfe_ack; // WFE acknowledge to DS + output ck_cpu1_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu2_reset_req; // Warm Reset request + input ds_cpu2_wfi_req; // WFI request + input ds_cpu2_wfe_req; // WFI request + input ds_cpu2_flush; // flush for exception rtn + input [5:0] ds_cpu2_flush_type; // flush type + input ds_cpu2_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu2_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu2_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu2_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu2_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu2_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu2_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu2_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu2_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu2_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu2_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu2_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu2_hcr_va; // virtual abort + input ds_cpu2_hcr_vi; // virtual IRQ + input ds_cpu2_hcr_vf; // virtual FIQ + input [2:0] ds_cpu2_cpuectlr_ret; // CPU Retention control + output ck_cpu2_event_reg; // WFE event reg + output ck_cpu2_wfi_ack; // WFI acknowledge to DS + output ck_cpu2_wfe_ack; // WFE acknowledge to DS + output ck_cpu2_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu3_reset_req; // Warm Reset request + input ds_cpu3_wfi_req; // WFI request + input ds_cpu3_wfe_req; // WFI request + input ds_cpu3_flush; // flush for exception rtn + input [5:0] ds_cpu3_flush_type; // flush type + input ds_cpu3_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu3_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu3_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu3_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu3_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu3_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu3_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu3_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu3_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu3_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu3_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu3_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu3_hcr_va; // virtual abort + input ds_cpu3_hcr_vi; // virtual IRQ + input ds_cpu3_hcr_vf; // virtual FIQ + input [2:0] ds_cpu3_cpuectlr_ret; // CPU Retention control + output ck_cpu3_event_reg; // WFE event reg + output ck_cpu3_wfi_ack; // WFI acknowledge to DS + output ck_cpu3_wfe_ack; // WFE acknowledge to DS + output ck_cpu3_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ls_cpu0_clrexmon; // LS global exclusive monitor + input ls_cpu1_clrexmon; // LS global exclusive monitor + input ls_cpu2_clrexmon; // LS global exclusive monitor + input ls_cpu3_clrexmon; // LS global exclusive monitor + +// END CK-CPU interface + + output [`MAIA_CN:0] ck_gclkt; + + + + // wires + wire STANDBYWFIL2; + wire ck_areset_l2; + wire ck_cpu0_areset_l2cpu; + wire ck_cpu0_areset_l2dt; + wire ck_cpu0_commrx; + wire ck_cpu0_commtx; + wire ck_cpu0_crcx_clk_en_n_ic; + wire ck_cpu0_dbgnopwrdwn; + wire ck_cpu0_dbgrstreq; + wire ck_cpu0_dt_standbywfx; + wire ck_cpu0_dt_wfx_ack; + wire ck_cpu0_l2_standbywfi; + wire ck_cpu0_l2_standbywfx; + wire ck_cpu0_ncommirq; + wire ck_cpu0_npmuirq; + wire ck_cpu0_poreset_status; + wire ck_cpu0_reset1_n_l2cpu; + wire ck_cpu0_reset1_n_l2dt; + wire ck_cpu1_areset_l2cpu; + wire ck_cpu1_areset_l2dt; + wire ck_cpu1_commrx; + wire ck_cpu1_commtx; + wire ck_cpu1_crcx_clk_en_n_ic; + wire ck_cpu1_dbgnopwrdwn; + wire ck_cpu1_dbgrstreq; + wire ck_cpu1_dt_standbywfx; + wire ck_cpu1_dt_wfx_ack; + wire ck_cpu1_l2_standbywfi; + wire ck_cpu1_l2_standbywfx; + wire ck_cpu1_ncommirq; + wire ck_cpu1_npmuirq; + wire ck_cpu1_poreset_status; + wire ck_cpu1_reset1_n_l2cpu; + wire ck_cpu1_reset1_n_l2dt; + wire ck_cpu2_areset_l2cpu; + wire ck_cpu2_areset_l2dt; + wire ck_cpu2_commrx; + wire ck_cpu2_commtx; + wire ck_cpu2_crcx_clk_en_n_ic; + wire ck_cpu2_dbgnopwrdwn; + wire ck_cpu2_dbgrstreq; + wire ck_cpu2_dt_standbywfx; + wire ck_cpu2_dt_wfx_ack; + wire ck_cpu2_l2_standbywfi; + wire ck_cpu2_l2_standbywfx; + wire ck_cpu2_ncommirq; + wire ck_cpu2_npmuirq; + wire ck_cpu2_poreset_status; + wire ck_cpu2_reset1_n_l2cpu; + wire ck_cpu2_reset1_n_l2dt; + wire ck_cpu3_areset_l2cpu; + wire ck_cpu3_areset_l2dt; + wire ck_cpu3_commrx; + wire ck_cpu3_commtx; + wire ck_cpu3_crcx_clk_en_n_ic; + wire ck_cpu3_dbgnopwrdwn; + wire ck_cpu3_dbgrstreq; + wire ck_cpu3_dt_standbywfx; + wire ck_cpu3_dt_wfx_ack; + wire ck_cpu3_l2_standbywfi; + wire ck_cpu3_l2_standbywfx; + wire ck_cpu3_ncommirq; + wire ck_cpu3_npmuirq; + wire ck_cpu3_poreset_status; + wire ck_cpu3_reset1_n_l2cpu; + wire ck_cpu3_reset1_n_l2dt; + wire ck_dt_cpu0_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu0_cti_trigin_1to0_gclk; + wire ck_dt_cpu0_et_oslock_gclk; + wire ck_dt_cpu0_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu0_os_double_lock_gclk; + wire ck_dt_cpu0_pmusnapshot_ack_gclk; + wire ck_dt_cpu0_wfx_dbg_req_gclk; + wire ck_dt_cpu1_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu1_cti_trigin_1to0_gclk; + wire ck_dt_cpu1_et_oslock_gclk; + wire ck_dt_cpu1_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu1_os_double_lock_gclk; + wire ck_dt_cpu1_pmusnapshot_ack_gclk; + wire ck_dt_cpu1_wfx_dbg_req_gclk; + wire ck_dt_cpu2_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu2_cti_trigin_1to0_gclk; + wire ck_dt_cpu2_et_oslock_gclk; + wire ck_dt_cpu2_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu2_os_double_lock_gclk; + wire ck_dt_cpu2_pmusnapshot_ack_gclk; + wire ck_dt_cpu2_wfx_dbg_req_gclk; + wire ck_dt_cpu3_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu3_cti_trigin_1to0_gclk; + wire ck_dt_cpu3_et_oslock_gclk; + wire ck_dt_cpu3_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu3_os_double_lock_gclk; + wire ck_dt_cpu3_pmusnapshot_ack_gclk; + wire ck_dt_cpu3_wfx_dbg_req_gclk; + wire ck_gclkb0; + wire ck_gclkb1; + wire ck_gclkfr; + wire ck_gclkl2; + wire ck_gclktl2; + wire ck_l2_ace_inactive; + wire ck_l2_acp_inactive; + wire ck_l2_logic_clk_en; + wire ck_l2_sky_link_deactivate; + wire ck_l2_tbnk0_clk_en; + wire ck_l2_tbnk1_clk_en; + wire ck_reset1_n_l2; + wire clrexmon_c1; + wire ds_cpu0_ic_aa64naa32_i; + wire [4:0] ds_cpu0_ic_cpsr_mode_i; + wire ds_cpu0_ic_hcr_change_i; + wire ds_cpu0_ic_sample_spr_i; + wire ds_cpu0_ic_scr_change_i; + wire ds_cpu1_ic_aa64naa32_i; + wire [4:0] ds_cpu1_ic_cpsr_mode_i; + wire ds_cpu1_ic_hcr_change_i; + wire ds_cpu1_ic_sample_spr_i; + wire ds_cpu1_ic_scr_change_i; + wire ds_cpu2_ic_aa64naa32_i; + wire [4:0] ds_cpu2_ic_cpsr_mode_i; + wire ds_cpu2_ic_hcr_change_i; + wire ds_cpu2_ic_sample_spr_i; + wire ds_cpu2_ic_scr_change_i; + wire ds_cpu3_ic_aa64naa32_i; + wire [4:0] ds_cpu3_ic_cpsr_mode_i; + wire ds_cpu3_ic_hcr_change_i; + wire ds_cpu3_ic_sample_spr_i; + wire ds_cpu3_ic_scr_change_i; + wire dt_cpu0_apb_active_pclk; + wire dt_cpu0_poreset_status_ack_pclk; + wire dt_cpu0_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu0_wfx_wakeup_pclk; + wire dt_cpu1_apb_active_pclk; + wire dt_cpu1_poreset_status_ack_pclk; + wire dt_cpu1_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu1_wfx_wakeup_pclk; + wire dt_cpu2_apb_active_pclk; + wire dt_cpu2_poreset_status_ack_pclk; + wire dt_cpu2_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu2_wfx_wakeup_pclk; + wire dt_cpu3_apb_active_pclk; + wire dt_cpu3_poreset_status_ack_pclk; + wire dt_cpu3_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu3_wfx_wakeup_pclk; + wire eventi_sev; + wire [`MAIA_CN:0] ic_block_eoi_sgi_wr_o; + wire ic_cpu0_l2_dsb_block; + wire [63:0] ic_cpu0_spr_rd_data; + wire ic_cpu1_l2_dsb_block; + wire [63:0] ic_cpu1_spr_rd_data; + wire ic_cpu2_l2_dsb_block; + wire [63:0] ic_cpu2_spr_rd_data; + wire ic_cpu3_l2_dsb_block; + wire [63:0] ic_cpu3_spr_rd_data; + wire [`MAIA_CN:0] ic_el_change_complete_o; + wire [`MAIA_CN:0] ic_hcr_change_complete_o; + wire [`MAIA_CN:0] ic_ich_el2_tall0_o; + wire [`MAIA_CN:0] ic_ich_el2_tall1_o; + wire [`MAIA_CN:0] ic_ich_el2_tc_o; + wire [`MAIA_CN:0] ic_nfiq_o; + wire [`MAIA_CN:0] ic_nirq_o; + wire [`MAIA_CN:0] ic_nsei_o; + wire [`MAIA_CN:0] ic_nvfiq_o; + wire [`MAIA_CN:0] ic_nvirq_o; + wire [`MAIA_CN:0] ic_nvsei_o; + wire [31:0] ic_p_rdata; + wire ic_p_rdata_valid; + wire ic_p_ready; + wire [`MAIA_CN:0] ic_sample_spr_o; + wire [`MAIA_CN:0] ic_scr_change_complete_o; + wire [`MAIA_CN:0] ic_sra_el1ns_en_o; + wire [`MAIA_CN:0] ic_sra_el1s_en_o; + wire [`MAIA_CN:0] ic_sra_el2_en_o; + wire [`MAIA_CN:0] ic_sra_el3_en_o; + wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap_o; + wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap_o; + wire [`MAIA_CN:0] ic_sre_el1s_mon_trap_o; + wire [`MAIA_CN:0] ic_sre_el2_mon_trap_o; + wire l2_acp_flsh_rd_cnt_active_glb_l2_dly; + wire l2_acp_flsh_wr_cnt_active_glb_l2_dly; + wire l2_acp_rd_haz_vld_l2_dly_q; + wire l2_acp_wr_haz_vld_l2_dly_q; + wire l2_actlr_disable_b2b_setway_hzd_opt_x2_ns; + wire l2_actlr_disable_setway_opt; + wire l2_actlr_ncpu_rcg_enable; + wire l2_actlr_plru_dynamic; + wire l2_actlr_plru_en; + wire [1:0] l2_actlr_plru_mode; + wire l2_actlr_writeunique_disable; + wire l2_cfg_broadcastinner; + wire l2_cfg_broadcastouter; + wire l2_cpu0_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu0_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu0_snp_active; + wire l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_wr_decerr_q; + wire l2_cpu0_wr_slverr_q; + wire l2_cpu1_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu1_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu1_snp_active; + wire l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_wr_decerr_q; + wire l2_cpu1_wr_slverr_q; + wire l2_cpu2_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu2_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu2_snp_active; + wire l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_wr_decerr_q; + wire l2_cpu2_wr_slverr_q; + wire l2_cpu3_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu3_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu3_snp_active; + wire l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_wr_decerr_q; + wire l2_cpu3_wr_slverr_q; + wire l2_ctlr_x1_wr_q; + wire [9:0] l2_ctlr_x2_ns; + wire l2_idle; + wire [`MAIA_CN:0] l2_mbist1_en_b1; + wire [16:0] l2_mbist2_tbnk0_addr_b1; + wire l2_mbist2_tbnk0_all_b1; + wire [2:0] l2_mbist2_tbnk0_array_b1; + wire [17:0] l2_mbist2_tbnk0_be_b1; + wire l2_mbist2_tbnk0_en_b1; + wire [143:0] l2_mbist2_tbnk0_indata_b1; + wire [143:0] l2_mbist2_tbnk0_outdata_b3; + wire l2_mbist2_tbnk0_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp0_outdata_b2; + wire l2_mbist2_tbnk0_snp0_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp0_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp1_outdata_b2; + wire l2_mbist2_tbnk0_snp1_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp1_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp2_outdata_b2; + wire l2_mbist2_tbnk0_snp2_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp2_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp3_outdata_b2; + wire l2_mbist2_tbnk0_snp3_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp3_sel_b1; + wire l2_mbist2_tbnk0_wr_en_b1; + wire [16:0] l2_mbist2_tbnk1_addr_b1; + wire l2_mbist2_tbnk1_all_b1; + wire [2:0] l2_mbist2_tbnk1_array_b1; + wire [17:0] l2_mbist2_tbnk1_be_b1; + wire l2_mbist2_tbnk1_en_b1; + wire [143:0] l2_mbist2_tbnk1_indata_b1; + wire [143:0] l2_mbist2_tbnk1_outdata_b3; + wire l2_mbist2_tbnk1_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp0_outdata_b2; + wire l2_mbist2_tbnk1_snp0_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp0_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp1_outdata_b2; + wire l2_mbist2_tbnk1_snp1_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp1_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp2_outdata_b2; + wire l2_mbist2_tbnk1_snp2_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp2_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp3_outdata_b2; + wire l2_mbist2_tbnk1_snp3_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp3_sel_b1; + wire l2_mbist2_tbnk1_wr_en_b1; + wire l2_no_ram_acc_nxt_cycle; + wire [13:0] l2_p_addr; + wire [1:0] l2_p_cpu; + wire l2_p_nsecure; + wire [2:0] l2_p_sel; + wire [31:0] l2_p_wdata; + wire l2_p_write; + wire l2_reset3; + wire l2_rstdisable_x1_q; + wire l2_tbnk0_addr44_l3_q; + wire [44:0] l2_tbnk0_addr_l1; + wire [5:2] l2_tbnk0_addr_l6; + wire l2_tbnk0_all_tag_incl_active_l3; + wire l2_tbnk0_asq_cmp_evict_l3_q; + wire l2_tbnk0_asq_full_flsh; + wire l2_tbnk0_asq_nc_so_dev_limit; + wire [2:0] l2_tbnk0_cache_attr_l1; + wire l2_tbnk0_cfg_ecc_en; + wire l2_tbnk0_cmo_setway_l2_inv_incl_l4; + wire l2_tbnk0_cpu0_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu0_hit_l4; + wire l2_tbnk0_cpu0_l2_inv_l4_dly2; + wire l2_tbnk0_cpu0_l2hit_e_l4; + wire l2_tbnk0_cpu0_l2hit_s_l4; + wire l2_tbnk0_cpu0_peq_full_q; + wire l2_tbnk0_cpu0_peq_hit_q; + wire l2_tbnk0_cpu0_peq_self_evict_l3_q; + wire l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu0_rd_access_l4_dly; + wire l2_tbnk0_cpu0_self_evict_l4_dly_q; + wire l2_tbnk0_cpu0_single_ecc_err_l7_q; + wire l2_tbnk0_cpu0_snp_hit_e_l3; + wire l2_tbnk0_cpu0_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu0_snp_setway_addr_l3; + wire l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu0_vld_nxt_l5; + wire l2_tbnk0_cpu0_wr_access_l4_dly; + wire l2_tbnk0_cpu1_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu1_hit_l4; + wire l2_tbnk0_cpu1_l2_inv_l4_dly2; + wire l2_tbnk0_cpu1_l2hit_e_l4; + wire l2_tbnk0_cpu1_l2hit_s_l4; + wire l2_tbnk0_cpu1_peq_full_q; + wire l2_tbnk0_cpu1_peq_hit_q; + wire l2_tbnk0_cpu1_peq_self_evict_l3_q; + wire l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu1_rd_access_l4_dly; + wire l2_tbnk0_cpu1_self_evict_l4_dly_q; + wire l2_tbnk0_cpu1_single_ecc_err_l7_q; + wire l2_tbnk0_cpu1_snp_hit_e_l3; + wire l2_tbnk0_cpu1_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu1_snp_setway_addr_l3; + wire l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu1_vld_nxt_l5; + wire l2_tbnk0_cpu1_wr_access_l4_dly; + wire l2_tbnk0_cpu2_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu2_hit_l4; + wire l2_tbnk0_cpu2_l2_inv_l4_dly2; + wire l2_tbnk0_cpu2_l2hit_e_l4; + wire l2_tbnk0_cpu2_l2hit_s_l4; + wire l2_tbnk0_cpu2_peq_full_q; + wire l2_tbnk0_cpu2_peq_hit_q; + wire l2_tbnk0_cpu2_peq_self_evict_l3_q; + wire l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu2_rd_access_l4_dly; + wire l2_tbnk0_cpu2_self_evict_l4_dly_q; + wire l2_tbnk0_cpu2_single_ecc_err_l7_q; + wire l2_tbnk0_cpu2_snp_hit_e_l3; + wire l2_tbnk0_cpu2_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu2_snp_setway_addr_l3; + wire l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu2_vld_nxt_l5; + wire l2_tbnk0_cpu2_wr_access_l4_dly; + wire l2_tbnk0_cpu3_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu3_hit_l4; + wire l2_tbnk0_cpu3_l2_inv_l4_dly2; + wire l2_tbnk0_cpu3_l2hit_e_l4; + wire l2_tbnk0_cpu3_l2hit_s_l4; + wire l2_tbnk0_cpu3_peq_full_q; + wire l2_tbnk0_cpu3_peq_hit_q; + wire l2_tbnk0_cpu3_peq_self_evict_l3_q; + wire l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu3_rd_access_l4_dly; + wire l2_tbnk0_cpu3_self_evict_l4_dly_q; + wire l2_tbnk0_cpu3_single_ecc_err_l7_q; + wire l2_tbnk0_cpu3_snp_hit_e_l3; + wire l2_tbnk0_cpu3_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu3_snp_setway_addr_l3; + wire l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu3_vld_nxt_l5; + wire l2_tbnk0_cpu3_wr_access_l4_dly; + wire [3:0] l2_tbnk0_cpu_rvalid_init_nxt_l5; + wire [3:0] l2_tbnk0_cpu_rvalid_nxt_l5; + wire [3:0] l2_tbnk0_cpu_snp_hit_e_l4_q; + wire l2_tbnk0_crit_qw_nxt_l5; + wire [143:0] l2_tbnk0_data_corrected_l7_q; + wire [127:0] l2_tbnk0_data_l6; + wire l2_tbnk0_dbg_ram_acc_l5a; + wire [2:0] l2_tbnk0_dbg_ram_acc_unit_nxt; + wire [7:0] l2_tbnk0_dbg_ram_id_nxt_l5; + wire l2_tbnk0_dirty_l1; + wire l2_tbnk0_dirty_l3_q; + wire l2_tbnk0_dis_ns_dbg_arr_acc_x2; + wire l2_tbnk0_double_ecc_err_l7_q; + wire l2_tbnk0_early_rvalid_l4_q; + wire l2_tbnk0_ecc_fixup_blk_arb; + wire l2_tbnk0_ecc_fixup_inprog_dly_q; + wire l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q; + wire [31:0] l2_tbnk0_ecc_syndrome_reg_q; + wire l2_tbnk0_evict_special_hazard_l3_q; + wire l2_tbnk0_evict_special_hazard_rwvic_l3_q; + wire l2_tbnk0_excl_l1; + wire l2_tbnk0_excl_l4_q; + wire [44:6] l2_tbnk0_feq_addr_upd; + wire l2_tbnk0_feq_alloc_failed_l4; + wire l2_tbnk0_feq_axi_wr_vld_not_popped; + wire l2_tbnk0_feq_clr_l4; + wire [15:0] l2_tbnk0_feq_frc_incl_l3a; + wire l2_tbnk0_feq_kill_l3; + wire [4:0] l2_tbnk0_feq_last_id_q; + wire l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3; + wire l2_tbnk0_feq_tbnk_id_update_or_l3; + wire l2_tbnk0_full_miss_l4_q; + wire l2_tbnk0_hit_l4; + wire l2_tbnk0_hit_l7_q; + wire [3:0] l2_tbnk0_hit_way_l4_q; + wire [9:0] l2_tbnk0_id_l1; + wire [9:0] l2_tbnk0_id_l6_q; + wire [9:0] l2_tbnk0_id_nxt_l5; + wire l2_tbnk0_idle; + wire l2_tbnk0_init_req_l1; + wire l2_tbnk0_kill_l2; + wire l2_tbnk0_l2bb_fake_wr_l1; + wire l2_tbnk0_l2bb_wr_l1; + wire l2_tbnk0_l2hit_e_l4; + wire l2_tbnk0_l2hit_s_l4; + wire l2_tbnk0_l2v_s_q; + wire l2_tbnk0_l2v_vld_q; + wire l2_tbnk0_last_qw_l1; + wire l2_tbnk0_last_qw_l6_q; + wire l2_tbnk0_last_qw_nxt_l5; + wire [2:0] l2_tbnk0_lock_l1; + wire [2:0] l2_tbnk0_lock_l4; + wire [32:0] l2_tbnk0_merrsr_data; + wire [9:0] l2_tbnk0_page_attr_l1; + wire l2_tbnk0_partial_dw_wr_l1; + wire l2_tbnk0_pf_cnt_dec_l4_dly; + wire l2_tbnk0_pf_hazard_l3; + wire l2_tbnk0_pf_req_sel_for_fwd_l4; + wire l2_tbnk0_prfm_l1; + wire l2_tbnk0_prfm_nxt_l5; + wire [3:0] l2_tbnk0_prot_l1; + wire [3:0] l2_tbnk0_prot_l4_q; + wire [1:0] l2_tbnk0_qw_cnt_l1; + wire [1:0] l2_tbnk0_qw_cnt_l3_q; + wire l2_tbnk0_raw_hit_l4_q; + wire [2:0] l2_tbnk0_rbufid_nxt_l5; + wire l2_tbnk0_rd_en_nxt_l5; + wire l2_tbnk0_rd_fail_hazchk_feq_l3; + wire l2_tbnk0_rwvic_axi_read_err_l1; + wire l2_tbnk0_rwvic_axi_read_err_l3_q; + wire l2_tbnk0_rwvic_ccb_dirty_l6_q; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l1; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l3_q; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l6_q; + wire [3:0] l2_tbnk0_rwvic_ccb_way_l1; + wire l2_tbnk0_rwvic_cmo_clean_l1; + wire l2_tbnk0_rwvic_cmo_inv_l1; + wire l2_tbnk0_rwvic_cmo_inv_l7_q; + wire l2_tbnk0_rwvic_cmo_l7_q; + wire l2_tbnk0_rwvic_cmo_pou_l1; + wire l2_tbnk0_rwvic_cmo_pou_l6_q; + wire l2_tbnk0_rwvic_cmo_setway_l1; + wire l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1; + wire l2_tbnk0_rwvic_cmo_setway_ls_l6_q; + wire [2:0] l2_tbnk0_rwvic_cpu_fb_id_l1; + wire [3:0] l2_tbnk0_rwvic_cpu_id_dcd_l1; + wire l2_tbnk0_rwvic_ddi_l6_q; + wire l2_tbnk0_rwvic_feq_cmp_l3_q; + wire l2_tbnk0_rwvic_frc_l2hit_fwd_l1; + wire l2_tbnk0_rwvic_l2hit_e_l1; + wire l2_tbnk0_rwvic_l2hit_e_l3_q; + wire l2_tbnk0_rwvic_l2hit_e_l7_q; + wire l2_tbnk0_rwvic_l2v_dirty_l7_q; + wire [3:0] l2_tbnk0_rwvic_l2v_page_attr_l7_q; + wire l2_tbnk0_rwvic_l2v_vld_l6_q; + wire l2_tbnk0_rwvic_mesi_sh_l1; + wire l2_tbnk0_rwvic_non_snp_fail_hazchk_l3; + wire [2:0] l2_tbnk0_rwvic_owner_l1; + wire [2:0] l2_tbnk0_rwvic_owner_l7_q; + wire l2_tbnk0_rwvic_rd_type_l6_q; + wire l2_tbnk0_rwvic_snp_clr_dirty_l1; + wire l2_tbnk0_rwvic_snp_inv_l1; + wire l2_tbnk0_rwvic_snp_l1; + wire l2_tbnk0_rwvic_snp_l3_q; + wire l2_tbnk0_rwvic_snp_l6_q; + wire l2_tbnk0_rwvic_tag_wr_l0; + wire [3:0] l2_tbnk0_rwvic_type_l1; + wire l2_tbnk0_rwvic_wa_l1; + wire l2_tbnk0_rwvic_wa_l6_q; + wire [13:0] l2_tbnk0_sel_l1; + wire [2:0] l2_tbnk0_size_l1; + wire [2:0] l2_tbnk0_size_l4_q; + wire l2_tbnk0_snp_byp_peq_haz_pending_q; + wire l2_tbnk0_snp_dvm_cmpl_l1; + wire l2_tbnk0_snp_hit_e_l4_q; + wire l2_tbnk0_snp_hit_feq_evict_l4_dly; + wire l2_tbnk0_snp_hit_s_l4_q; + wire [4:0] l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q; + wire [7:0] l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q; + wire [7:0] l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q; + wire [44:7] l2_tbnk0_snp_tag_wr_l2_hit_addr_l1; + wire [1:0] l2_tbnk0_snp_tag_wr_l2_hit_state_l1; + wire l2_tbnk0_snp_tag_wr_l2_hit_way_l1; + wire l2_tbnk0_special_evict_hazard_l3; + wire l2_tbnk0_special_hazard_l3_q; + wire l2_tbnk0_sync_l1; + wire l2_tbnk0_tag_ecc_dbl_rmw_wr_l1; + wire l2_tbnk0_tag_ecc_err_cpu0_l4; + wire l2_tbnk0_tag_ecc_err_cpu1_l4; + wire l2_tbnk0_tag_ecc_err_cpu2_l4; + wire l2_tbnk0_tag_ecc_err_cpu3_l4; + wire l2_tbnk0_tag_ecc_err_l4; + wire [6:0] l2_tbnk0_type_l1; + wire [1:0] l2_tbnk0_ulen_l1; + wire [1:0] l2_tbnk0_ulen_l4_q; + wire l2_tbnk0_vld_init_l6_q; + wire l2_tbnk0_vld_l6_q; + wire l2_tbnk0_way_l1; + wire l2_tbnk0_way_l4_q; + wire l2_tbnk0_way_nxt_l3a; + wire [143:0] l2_tbnk0_wr_data_l3; + wire [127:0] l2_tbnk0_wr_data_l3a_q; + wire l2_tbnk0_wr_data_l4_en; + wire l2_tbnk0_wr_err_l1; + wire l2_tbnk0_wr_fail_feq_full_l3; + wire l2_tbnk0_wr_fail_hazchk_feq_l3; + wire [11:0] l2_tbnk0_wr_non_crit_id_l1; + wire [11:0] l2_tbnk0_wr_non_crit_id_l4_q; + wire [15:0] l2_tbnk0_wr_strb_mask_l3a_q; + wire l2_tbnk1_addr44_l3_q; + wire [44:0] l2_tbnk1_addr_l1; + wire [5:2] l2_tbnk1_addr_l6; + wire l2_tbnk1_all_tag_incl_active_l3; + wire l2_tbnk1_asq_cmp_evict_l3_q; + wire l2_tbnk1_asq_full_flsh; + wire l2_tbnk1_asq_nc_so_dev_limit; + wire [2:0] l2_tbnk1_cache_attr_l1; + wire l2_tbnk1_cfg_ecc_en; + wire l2_tbnk1_cmo_setway_l2_inv_incl_l4; + wire l2_tbnk1_cpu0_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu0_hit_l4; + wire l2_tbnk1_cpu0_l2_inv_l4_dly2; + wire l2_tbnk1_cpu0_l2hit_e_l4; + wire l2_tbnk1_cpu0_l2hit_s_l4; + wire l2_tbnk1_cpu0_peq_full_q; + wire l2_tbnk1_cpu0_peq_hit_q; + wire l2_tbnk1_cpu0_peq_self_evict_l3_q; + wire l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu0_rd_access_l4_dly; + wire l2_tbnk1_cpu0_self_evict_l4_dly_q; + wire l2_tbnk1_cpu0_single_ecc_err_l7_q; + wire l2_tbnk1_cpu0_snp_hit_e_l3; + wire l2_tbnk1_cpu0_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu0_snp_setway_addr_l3; + wire l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu0_vld_nxt_l5; + wire l2_tbnk1_cpu0_wr_access_l4_dly; + wire l2_tbnk1_cpu1_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu1_hit_l4; + wire l2_tbnk1_cpu1_l2_inv_l4_dly2; + wire l2_tbnk1_cpu1_l2hit_e_l4; + wire l2_tbnk1_cpu1_l2hit_s_l4; + wire l2_tbnk1_cpu1_peq_full_q; + wire l2_tbnk1_cpu1_peq_hit_q; + wire l2_tbnk1_cpu1_peq_self_evict_l3_q; + wire l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu1_rd_access_l4_dly; + wire l2_tbnk1_cpu1_self_evict_l4_dly_q; + wire l2_tbnk1_cpu1_single_ecc_err_l7_q; + wire l2_tbnk1_cpu1_snp_hit_e_l3; + wire l2_tbnk1_cpu1_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu1_snp_setway_addr_l3; + wire l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu1_vld_nxt_l5; + wire l2_tbnk1_cpu1_wr_access_l4_dly; + wire l2_tbnk1_cpu2_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu2_hit_l4; + wire l2_tbnk1_cpu2_l2_inv_l4_dly2; + wire l2_tbnk1_cpu2_l2hit_e_l4; + wire l2_tbnk1_cpu2_l2hit_s_l4; + wire l2_tbnk1_cpu2_peq_full_q; + wire l2_tbnk1_cpu2_peq_hit_q; + wire l2_tbnk1_cpu2_peq_self_evict_l3_q; + wire l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu2_rd_access_l4_dly; + wire l2_tbnk1_cpu2_self_evict_l4_dly_q; + wire l2_tbnk1_cpu2_single_ecc_err_l7_q; + wire l2_tbnk1_cpu2_snp_hit_e_l3; + wire l2_tbnk1_cpu2_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu2_snp_setway_addr_l3; + wire l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu2_vld_nxt_l5; + wire l2_tbnk1_cpu2_wr_access_l4_dly; + wire l2_tbnk1_cpu3_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu3_hit_l4; + wire l2_tbnk1_cpu3_l2_inv_l4_dly2; + wire l2_tbnk1_cpu3_l2hit_e_l4; + wire l2_tbnk1_cpu3_l2hit_s_l4; + wire l2_tbnk1_cpu3_peq_full_q; + wire l2_tbnk1_cpu3_peq_hit_q; + wire l2_tbnk1_cpu3_peq_self_evict_l3_q; + wire l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu3_rd_access_l4_dly; + wire l2_tbnk1_cpu3_self_evict_l4_dly_q; + wire l2_tbnk1_cpu3_single_ecc_err_l7_q; + wire l2_tbnk1_cpu3_snp_hit_e_l3; + wire l2_tbnk1_cpu3_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu3_snp_setway_addr_l3; + wire l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu3_vld_nxt_l5; + wire l2_tbnk1_cpu3_wr_access_l4_dly; + wire [3:0] l2_tbnk1_cpu_rvalid_init_nxt_l5; + wire [3:0] l2_tbnk1_cpu_rvalid_nxt_l5; + wire [3:0] l2_tbnk1_cpu_snp_hit_e_l4_q; + wire l2_tbnk1_crit_qw_nxt_l5; + wire [143:0] l2_tbnk1_data_corrected_l7_q; + wire [127:0] l2_tbnk1_data_l6; + wire l2_tbnk1_dbg_ram_acc_l5a; + wire [2:0] l2_tbnk1_dbg_ram_acc_unit_nxt; + wire [7:0] l2_tbnk1_dbg_ram_id_nxt_l5; + wire l2_tbnk1_dirty_l1; + wire l2_tbnk1_dirty_l3_q; + wire l2_tbnk1_dis_ns_dbg_arr_acc_x2; + wire l2_tbnk1_double_ecc_err_l7_q; + wire l2_tbnk1_early_rvalid_l4_q; + wire l2_tbnk1_ecc_fixup_blk_arb; + wire l2_tbnk1_ecc_fixup_inprog_dly_q; + wire l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q; + wire [31:0] l2_tbnk1_ecc_syndrome_reg_q; + wire l2_tbnk1_evict_special_hazard_l3_q; + wire l2_tbnk1_evict_special_hazard_rwvic_l3_q; + wire l2_tbnk1_excl_l1; + wire l2_tbnk1_excl_l4_q; + wire [44:6] l2_tbnk1_feq_addr_upd; + wire l2_tbnk1_feq_alloc_failed_l4; + wire l2_tbnk1_feq_axi_wr_vld_not_popped; + wire l2_tbnk1_feq_clr_l4; + wire [15:0] l2_tbnk1_feq_frc_incl_l3a; + wire l2_tbnk1_feq_kill_l3; + wire [4:0] l2_tbnk1_feq_last_id_q; + wire l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3; + wire l2_tbnk1_feq_tbnk_id_update_or_l3; + wire l2_tbnk1_full_miss_l4_q; + wire l2_tbnk1_hit_l4; + wire l2_tbnk1_hit_l7_q; + wire [3:0] l2_tbnk1_hit_way_l4_q; + wire [9:0] l2_tbnk1_id_l1; + wire [9:0] l2_tbnk1_id_l6_q; + wire [9:0] l2_tbnk1_id_nxt_l5; + wire l2_tbnk1_idle; + wire l2_tbnk1_init_req_l1; + wire l2_tbnk1_kill_l2; + wire l2_tbnk1_l2bb_fake_wr_l1; + wire l2_tbnk1_l2bb_wr_l1; + wire l2_tbnk1_l2hit_e_l4; + wire l2_tbnk1_l2hit_s_l4; + wire l2_tbnk1_l2v_s_q; + wire l2_tbnk1_l2v_vld_q; + wire l2_tbnk1_last_qw_l1; + wire l2_tbnk1_last_qw_l6_q; + wire l2_tbnk1_last_qw_nxt_l5; + wire [2:0] l2_tbnk1_lock_l1; + wire [2:0] l2_tbnk1_lock_l4; + wire [32:0] l2_tbnk1_merrsr_data; + wire [9:0] l2_tbnk1_page_attr_l1; + wire l2_tbnk1_partial_dw_wr_l1; + wire l2_tbnk1_pf_cnt_dec_l4_dly; + wire l2_tbnk1_pf_hazard_l3; + wire l2_tbnk1_pf_req_sel_for_fwd_l4; + wire l2_tbnk1_prfm_l1; + wire l2_tbnk1_prfm_nxt_l5; + wire [3:0] l2_tbnk1_prot_l1; + wire [3:0] l2_tbnk1_prot_l4_q; + wire [1:0] l2_tbnk1_qw_cnt_l1; + wire [1:0] l2_tbnk1_qw_cnt_l3_q; + wire l2_tbnk1_raw_hit_l4_q; + wire [2:0] l2_tbnk1_rbufid_nxt_l5; + wire l2_tbnk1_rd_en_nxt_l5; + wire l2_tbnk1_rd_fail_hazchk_feq_l3; + wire l2_tbnk1_rwvic_axi_read_err_l1; + wire l2_tbnk1_rwvic_axi_read_err_l3_q; + wire l2_tbnk1_rwvic_ccb_dirty_l6_q; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l1; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l3_q; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l6_q; + wire [3:0] l2_tbnk1_rwvic_ccb_way_l1; + wire l2_tbnk1_rwvic_cmo_clean_l1; + wire l2_tbnk1_rwvic_cmo_inv_l1; + wire l2_tbnk1_rwvic_cmo_inv_l7_q; + wire l2_tbnk1_rwvic_cmo_l7_q; + wire l2_tbnk1_rwvic_cmo_pou_l1; + wire l2_tbnk1_rwvic_cmo_pou_l6_q; + wire l2_tbnk1_rwvic_cmo_setway_l1; + wire l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1; + wire l2_tbnk1_rwvic_cmo_setway_ls_l6_q; + wire [2:0] l2_tbnk1_rwvic_cpu_fb_id_l1; + wire [3:0] l2_tbnk1_rwvic_cpu_id_dcd_l1; + wire l2_tbnk1_rwvic_ddi_l6_q; + wire l2_tbnk1_rwvic_feq_cmp_l3_q; + wire l2_tbnk1_rwvic_frc_l2hit_fwd_l1; + wire l2_tbnk1_rwvic_l2hit_e_l1; + wire l2_tbnk1_rwvic_l2hit_e_l3_q; + wire l2_tbnk1_rwvic_l2hit_e_l7_q; + wire l2_tbnk1_rwvic_l2v_dirty_l7_q; + wire [3:0] l2_tbnk1_rwvic_l2v_page_attr_l7_q; + wire l2_tbnk1_rwvic_l2v_vld_l6_q; + wire l2_tbnk1_rwvic_mesi_sh_l1; + wire l2_tbnk1_rwvic_non_snp_fail_hazchk_l3; + wire [2:0] l2_tbnk1_rwvic_owner_l1; + wire [2:0] l2_tbnk1_rwvic_owner_l7_q; + wire l2_tbnk1_rwvic_rd_type_l6_q; + wire l2_tbnk1_rwvic_snp_clr_dirty_l1; + wire l2_tbnk1_rwvic_snp_inv_l1; + wire l2_tbnk1_rwvic_snp_l1; + wire l2_tbnk1_rwvic_snp_l3_q; + wire l2_tbnk1_rwvic_snp_l6_q; + wire l2_tbnk1_rwvic_tag_wr_l0; + wire [3:0] l2_tbnk1_rwvic_type_l1; + wire l2_tbnk1_rwvic_wa_l1; + wire l2_tbnk1_rwvic_wa_l6_q; + wire [13:0] l2_tbnk1_sel_l1; + wire [2:0] l2_tbnk1_size_l1; + wire [2:0] l2_tbnk1_size_l4_q; + wire l2_tbnk1_snp_byp_peq_haz_pending_q; + wire l2_tbnk1_snp_dvm_cmpl_l1; + wire l2_tbnk1_snp_hit_e_l4_q; + wire l2_tbnk1_snp_hit_feq_evict_l4_dly; + wire l2_tbnk1_snp_hit_s_l4_q; + wire [4:0] l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q; + wire [7:0] l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q; + wire [7:0] l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q; + wire [44:7] l2_tbnk1_snp_tag_wr_l2_hit_addr_l1; + wire [1:0] l2_tbnk1_snp_tag_wr_l2_hit_state_l1; + wire l2_tbnk1_snp_tag_wr_l2_hit_way_l1; + wire l2_tbnk1_special_evict_hazard_l3; + wire l2_tbnk1_special_hazard_l3_q; + wire l2_tbnk1_sync_l1; + wire l2_tbnk1_tag_ecc_dbl_rmw_wr_l1; + wire l2_tbnk1_tag_ecc_err_cpu0_l4; + wire l2_tbnk1_tag_ecc_err_cpu1_l4; + wire l2_tbnk1_tag_ecc_err_cpu2_l4; + wire l2_tbnk1_tag_ecc_err_cpu3_l4; + wire l2_tbnk1_tag_ecc_err_l4; + wire [6:0] l2_tbnk1_type_l1; + wire [1:0] l2_tbnk1_ulen_l1; + wire [1:0] l2_tbnk1_ulen_l4_q; + wire l2_tbnk1_vld_init_l6_q; + wire l2_tbnk1_vld_l6_q; + wire l2_tbnk1_way_l1; + wire l2_tbnk1_way_l4_q; + wire l2_tbnk1_way_nxt_l3a; + wire [143:0] l2_tbnk1_wr_data_l3; + wire [127:0] l2_tbnk1_wr_data_l3a_q; + wire l2_tbnk1_wr_data_l4_en; + wire l2_tbnk1_wr_err_l1; + wire l2_tbnk1_wr_fail_feq_full_l3; + wire l2_tbnk1_wr_fail_hazchk_feq_l3; + wire [11:0] l2_tbnk1_wr_non_crit_id_l1; + wire [11:0] l2_tbnk1_wr_non_crit_id_l4_q; + wire [15:0] l2_tbnk1_wr_strb_mask_l3a_q; + wire l2_tbnk_hwrst_done_x2; + wire [13:0] l2_tbnk_hwrst_idx_x1_q; + wire [8:0] tm_cntpct_q; + wire tm_cpu0_event_sev; + wire [63:0] tm_cpu0_spr_rd_data; + wire tm_cpu1_event_sev; + wire [63:0] tm_cpu1_spr_rd_data; + wire tm_cpu2_event_sev; + wire [63:0] tm_cpu2_spr_rd_data; + wire tm_cpu3_event_sev; + wire [63:0] tm_cpu3_spr_rd_data; + wire [63:0] tm_tval_cpu0_spr_rd_data; + wire [63:0] tm_tval_cpu1_spr_rd_data; + wire [63:0] tm_tval_cpu2_spr_rd_data; + wire [63:0] tm_tval_cpu3_spr_rd_data; + + maia_timer utm( // outputs + .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), + .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), + .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), + .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tm_cpu0_event_sev (tm_cpu0_event_sev), + .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), + .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tm_cpu1_event_sev (tm_cpu1_event_sev), + .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), + .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tm_cpu2_event_sev (tm_cpu2_event_sev), + .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), + .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tm_cpu3_event_sev (tm_cpu3_event_sev), + .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), + .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), + .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), + .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), + .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]), + + // inputs + .CNTCLKEN (CNTCLKEN), + .CNTVALUEB (CNTVALUEB[63:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .ck_areset_l2 (ck_areset_l2), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .eventi_sev (eventi_sev), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable) + ); // utm + + maia_l2_logic_feq20 ul2_logic( // outputs + .ACREADYM (ACREADYM), + .ARADDRM (ARADDRM[43:0]), + .ARBARM (ARBARM[1:0]), + .ARBURSTM (ARBURSTM[1:0]), + .ARCACHEM (ARCACHEM[3:0]), + .ARDOMAINM (ARDOMAINM[1:0]), + .ARIDM (ARIDM[6:0]), + .ARLENM (ARLENM[7:0]), + .ARLOCKM (ARLOCKM), + .ARPROTM (ARPROTM[2:0]), + .ARREADYS (ARREADYS), + .ARSIZEM (ARSIZEM[2:0]), + .ARSNOOPM (ARSNOOPM[3:0]), + .ARVALIDM (ARVALIDM), + .AWADDRM (AWADDRM[43:0]), + .AWBARM (AWBARM[1:0]), + .AWBURSTM (AWBURSTM[1:0]), + .AWCACHEM (AWCACHEM[3:0]), + .AWDOMAINM (AWDOMAINM[1:0]), + .AWIDM (AWIDM[6:0]), + .AWLENM (AWLENM[7:0]), + .AWLOCKM (AWLOCKM), + .AWPROTM (AWPROTM[2:0]), + .AWREADYS (AWREADYS), + .AWSIZEM (AWSIZEM[2:0]), + .AWSNOOPM (AWSNOOPM[2:0]), + .AWUNIQUEM (AWUNIQUEM), + .AWVALIDM (AWVALIDM), + .BIDS (BIDS[4:0]), + .BREADYM (BREADYM), + .BRESPS (BRESPS[1:0]), + .BVALIDS (BVALIDS), + .CDDATAM (CDDATAM[127:0]), + .CDLASTM (CDLASTM), + .CDVALIDM (CDVALIDM), + .CRRESPM (CRRESPM[4:0]), + .CRVALIDM (CRVALIDM), + .L2FLUSHDONE (L2FLUSHDONE), + .L2QACCEPTn (L2QACCEPTn), + .L2QACTIVE (L2QACTIVE), + .L2QDENY (L2QDENY), + .RACKM (RACKM), + .RDATAS (RDATAS[127:0]), + .RDMEMATTR (RDMEMATTR[7:0]), + .RIDS (RIDS[4:0]), + .RLASTS (RLASTS), + .RREADYM (RREADYM), + .RRESPS (RRESPS[1:0]), + .RVALIDS (RVALIDS), + .WACKM (WACKM), + .WDATAM (WDATAM[127:0]), + .WIDM (WIDM[6:0]), + .WLASTM (WLASTM), + .WREADYS (WREADYS), + .WRMEMATTR (WRMEMATTR[7:0]), + .WSTRBM (WSTRBM[15:0]), + .WVALIDM (WVALIDM), + .ck_areset_l2 (ck_areset_l2), + .ck_l2_logic_clk_en (ck_l2_logic_clk_en), + .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), + .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu0_barrier_done (l2_cpu0_barrier_done), + .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddbl_ecc_err_r3), + .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idbl_ecc_err_r3), + .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu0_rd_arb (l2_cpu0_rd_arb), + .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu0_rexfail (l2_cpu0_rexfail), + .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu0_rvalid (l2_cpu0_rvalid), + .l2_cpu0_snp_active (l2_cpu0_snp_active), + .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu0_spec_valid (l2_cpu0_spec_valid), + .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu0_wr_arb (l2_cpu0_wr_arb), + .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu0_wr_decerr_q (l2_cpu0_wr_decerr_q), + .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu0_wr_slverr_q (l2_cpu0_wr_slverr_q), + .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu1_barrier_done (l2_cpu1_barrier_done), + .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddbl_ecc_err_r3), + .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idbl_ecc_err_r3), + .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu1_rd_arb (l2_cpu1_rd_arb), + .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu1_rexfail (l2_cpu1_rexfail), + .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu1_rvalid (l2_cpu1_rvalid), + .l2_cpu1_snp_active (l2_cpu1_snp_active), + .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu1_spec_valid (l2_cpu1_spec_valid), + .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu1_wr_arb (l2_cpu1_wr_arb), + .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu1_wr_decerr_q (l2_cpu1_wr_decerr_q), + .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu1_wr_slverr_q (l2_cpu1_wr_slverr_q), + .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu2_barrier_done (l2_cpu2_barrier_done), + .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddbl_ecc_err_r3), + .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idbl_ecc_err_r3), + .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu2_rd_arb (l2_cpu2_rd_arb), + .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu2_rexfail (l2_cpu2_rexfail), + .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu2_rvalid (l2_cpu2_rvalid), + .l2_cpu2_snp_active (l2_cpu2_snp_active), + .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu2_spec_valid (l2_cpu2_spec_valid), + .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu2_wr_arb (l2_cpu2_wr_arb), + .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu2_wr_decerr_q (l2_cpu2_wr_decerr_q), + .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu2_wr_slverr_q (l2_cpu2_wr_slverr_q), + .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu3_barrier_done (l2_cpu3_barrier_done), + .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddbl_ecc_err_r3), + .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idbl_ecc_err_r3), + .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu3_rd_arb (l2_cpu3_rd_arb), + .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu3_rexfail (l2_cpu3_rexfail), + .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu3_rvalid (l2_cpu3_rvalid), + .l2_cpu3_snp_active (l2_cpu3_snp_active), + .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu3_spec_valid (l2_cpu3_spec_valid), + .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu3_wr_arb (l2_cpu3_wr_arb), + .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu3_wr_decerr_q (l2_cpu3_wr_decerr_q), + .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu3_wr_slverr_q (l2_cpu3_wr_slverr_q), + .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_idle (l2_idle), + .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), + .l2_mbist2_tbnk0_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), + .l2_mbist2_tbnk0_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), + .l2_mbist2_tbnk0_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), + .l2_mbist2_tbnk0_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), + .l2_mbist2_tbnk1_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), + .l2_mbist2_tbnk1_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), + .l2_mbist2_tbnk1_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), + .l2_mbist2_tbnk1_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_p_addr (l2_p_addr[13:0]), + .l2_p_cpu (l2_p_cpu[1:0]), + .l2_p_nsecure (l2_p_nsecure), + .l2_p_sel (l2_p_sel[2:0]), + .l2_p_wdata (l2_p_wdata[31:0]), + .l2_p_write (l2_p_write), + .l2_reset3 (l2_reset3), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_tbnk0_addr_l1 (l2_tbnk0_addr_l1[44:0]), + .l2_tbnk0_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), + .l2_tbnk0_asq_full_flsh (l2_tbnk0_asq_full_flsh), + .l2_tbnk0_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), + .l2_tbnk0_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), + .l2_tbnk0_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), + .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), + .l2_tbnk0_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), + .l2_tbnk0_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), + .l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), + .l2_tbnk0_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), + .l2_tbnk0_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), + .l2_tbnk0_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), + .l2_tbnk0_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), + .l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), + .l2_tbnk0_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), + .l2_tbnk0_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), + .l2_tbnk0_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), + .l2_tbnk0_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), + .l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), + .l2_tbnk0_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), + .l2_tbnk0_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), + .l2_tbnk0_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), + .l2_tbnk0_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), + .l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), + .l2_tbnk0_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), + .l2_tbnk0_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_dirty_l1 (l2_tbnk0_dirty_l1), + .l2_tbnk0_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), + .l2_tbnk0_excl_l1 (l2_tbnk0_excl_l1), + .l2_tbnk0_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), + .l2_tbnk0_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), + .l2_tbnk0_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), + .l2_tbnk0_feq_kill_l3 (l2_tbnk0_feq_kill_l3), + .l2_tbnk0_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), + .l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk0_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), + .l2_tbnk0_id_l1 (l2_tbnk0_id_l1[9:0]), + .l2_tbnk0_init_req_l1 (l2_tbnk0_init_req_l1), + .l2_tbnk0_kill_l2 (l2_tbnk0_kill_l2), + .l2_tbnk0_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), + .l2_tbnk0_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), + .l2_tbnk0_last_qw_l1 (l2_tbnk0_last_qw_l1), + .l2_tbnk0_lock_l1 (l2_tbnk0_lock_l1[2:0]), + .l2_tbnk0_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), + .l2_tbnk0_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), + .l2_tbnk0_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), + .l2_tbnk0_prfm_l1 (l2_tbnk0_prfm_l1), + .l2_tbnk0_prot_l1 (l2_tbnk0_prot_l1[3:0]), + .l2_tbnk0_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), + .l2_tbnk0_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), + .l2_tbnk0_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), + .l2_tbnk0_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), + .l2_tbnk0_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), + .l2_tbnk0_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), + .l2_tbnk0_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), + .l2_tbnk0_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), + .l2_tbnk0_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), + .l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk0_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk0_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk0_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), + .l2_tbnk0_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk0_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), + .l2_tbnk0_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), + .l2_tbnk0_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), + .l2_tbnk0_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), + .l2_tbnk0_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), + .l2_tbnk0_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), + .l2_tbnk0_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), + .l2_tbnk0_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), + .l2_tbnk0_sel_l1 (l2_tbnk0_sel_l1[13:0]), + .l2_tbnk0_size_l1 (l2_tbnk0_size_l1[2:0]), + .l2_tbnk0_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), + .l2_tbnk0_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), + .l2_tbnk0_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), + .l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk0_sync_l1 (l2_tbnk0_sync_l1), + .l2_tbnk0_type_l1 (l2_tbnk0_type_l1[6:0]), + .l2_tbnk0_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), + .l2_tbnk0_way_l1 (l2_tbnk0_way_l1), + .l2_tbnk0_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), + .l2_tbnk0_wr_err_l1 (l2_tbnk0_wr_err_l1), + .l2_tbnk0_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), + .l2_tbnk0_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), + .l2_tbnk0_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), + .l2_tbnk0_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]), + .l2_tbnk1_addr_l1 (l2_tbnk1_addr_l1[44:0]), + .l2_tbnk1_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), + .l2_tbnk1_asq_full_flsh (l2_tbnk1_asq_full_flsh), + .l2_tbnk1_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), + .l2_tbnk1_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), + .l2_tbnk1_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), + .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), + .l2_tbnk1_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), + .l2_tbnk1_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), + .l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), + .l2_tbnk1_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), + .l2_tbnk1_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), + .l2_tbnk1_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), + .l2_tbnk1_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), + .l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), + .l2_tbnk1_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), + .l2_tbnk1_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), + .l2_tbnk1_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), + .l2_tbnk1_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), + .l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), + .l2_tbnk1_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), + .l2_tbnk1_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), + .l2_tbnk1_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), + .l2_tbnk1_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), + .l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), + .l2_tbnk1_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), + .l2_tbnk1_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_dirty_l1 (l2_tbnk1_dirty_l1), + .l2_tbnk1_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), + .l2_tbnk1_excl_l1 (l2_tbnk1_excl_l1), + .l2_tbnk1_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), + .l2_tbnk1_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), + .l2_tbnk1_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), + .l2_tbnk1_feq_kill_l3 (l2_tbnk1_feq_kill_l3), + .l2_tbnk1_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), + .l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk1_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), + .l2_tbnk1_id_l1 (l2_tbnk1_id_l1[9:0]), + .l2_tbnk1_init_req_l1 (l2_tbnk1_init_req_l1), + .l2_tbnk1_kill_l2 (l2_tbnk1_kill_l2), + .l2_tbnk1_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), + .l2_tbnk1_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), + .l2_tbnk1_last_qw_l1 (l2_tbnk1_last_qw_l1), + .l2_tbnk1_lock_l1 (l2_tbnk1_lock_l1[2:0]), + .l2_tbnk1_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), + .l2_tbnk1_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), + .l2_tbnk1_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), + .l2_tbnk1_prfm_l1 (l2_tbnk1_prfm_l1), + .l2_tbnk1_prot_l1 (l2_tbnk1_prot_l1[3:0]), + .l2_tbnk1_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), + .l2_tbnk1_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), + .l2_tbnk1_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), + .l2_tbnk1_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), + .l2_tbnk1_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), + .l2_tbnk1_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), + .l2_tbnk1_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), + .l2_tbnk1_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), + .l2_tbnk1_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), + .l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk1_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk1_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk1_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), + .l2_tbnk1_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk1_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), + .l2_tbnk1_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), + .l2_tbnk1_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), + .l2_tbnk1_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), + .l2_tbnk1_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), + .l2_tbnk1_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), + .l2_tbnk1_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), + .l2_tbnk1_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), + .l2_tbnk1_sel_l1 (l2_tbnk1_sel_l1[13:0]), + .l2_tbnk1_size_l1 (l2_tbnk1_size_l1[2:0]), + .l2_tbnk1_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), + .l2_tbnk1_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), + .l2_tbnk1_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), + .l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk1_sync_l1 (l2_tbnk1_sync_l1), + .l2_tbnk1_type_l1 (l2_tbnk1_type_l1[6:0]), + .l2_tbnk1_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), + .l2_tbnk1_way_l1 (l2_tbnk1_way_l1), + .l2_tbnk1_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), + .l2_tbnk1_wr_err_l1 (l2_tbnk1_wr_err_l1), + .l2_tbnk1_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), + .l2_tbnk1_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), + .l2_tbnk1_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), + .l2_tbnk1_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .nEXTERRIRQ (nEXTERRIRQ), + .nINTERRIRQ (nINTERRIRQ), + + // inputs + .ACADDRM (ACADDRM[43:0]), + .ACLKENM (ACLKENM), + .ACLKENS (ACLKENS), + .ACPROTM (ACPROTM[2:0]), + .ACSNOOPM (ACSNOOPM[3:0]), + .ACVALIDM (ACVALIDM), + .ARADDRS (ARADDRS[43:0]), + .ARCACHES (ARCACHES[3:0]), + .ARIDS (ARIDS[4:0]), + .ARLENS (ARLENS[7:0]), + .ARPROTS (ARPROTS[2:0]), + .ARREADYM (ARREADYM), + .ARUSERS (ARUSERS[1:0]), + .ARVALIDS (ARVALIDS), + .AWADDRS (AWADDRS[43:0]), + .AWCACHES (AWCACHES[3:0]), + .AWIDS (AWIDS[4:0]), + .AWLENS (AWLENS[7:0]), + .AWPROTS (AWPROTS[2:0]), + .AWREADYM (AWREADYM), + .AWUSERS (AWUSERS[1:0]), + .AWVALIDS (AWVALIDS), + .BIDM (BIDM[6:0]), + .BREADYS (BREADYS), + .BRESPM (BRESPM[1:0]), + .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), + .BROADCASTINNER (BROADCASTINNER), + .BROADCASTOUTER (BROADCASTOUTER), + .BVALIDM (BVALIDM), + .CDREADYM (CDREADYM), + .CRREADYM (CRREADYM), + .DBGL1RSTDISABLE (DBGL1RSTDISABLE), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .L2FLUSHREQ (L2FLUSHREQ), + .L2QREQn (L2QREQn), + .L2RSTDISABLE (L2RSTDISABLE), + .MBISTREQ (MBISTREQ), + .PERIPHBASE (PERIPHBASE[43:18]), + .RDATAM (RDATAM[127:0]), + .RIDM (RIDM[6:0]), + .RLASTM (RLASTM), + .RREADYS (RREADYS), + .RRESPM (RRESPM[3:0]), + .RVALIDM (RVALIDM), + .STANDBYWFIL2 (STANDBYWFIL2), + .SYSBARDISABLE (SYSBARDISABLE), + .WDATAS (WDATAS[127:0]), + .WLASTS (WLASTS), + .WREADYM (WREADYM), + .WSTRBS (WSTRBS[15:0]), + .WVALIDS (WVALIDS), + .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), + .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), + .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), + .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), + .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), + .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), + .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), + .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), + .ck_gclkfr (ck_gclkfr), + .ck_gclkl2 (ck_gclkl2), + .ck_l2_ace_inactive (ck_l2_ace_inactive), + .ck_l2_acp_inactive (ck_l2_acp_inactive), + .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), + .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), + .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), + .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), + .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), + .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), + .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), + .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), + .ic_p_rdata (ic_p_rdata[31:0]), + .ic_p_rdata_valid (ic_p_rdata_valid), + .ic_p_ready (ic_p_ready), + .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .l2_mbist2_tbnk0_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), + .l2_mbist2_tbnk0_all_b1 (l2_mbist2_tbnk0_all_b1), + .l2_mbist2_tbnk0_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), + .l2_mbist2_tbnk0_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), + .l2_mbist2_tbnk0_en_b1 (l2_mbist2_tbnk0_en_b1), + .l2_mbist2_tbnk0_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), + .l2_mbist2_tbnk0_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), + .l2_mbist2_tbnk0_sel_b1 (l2_mbist2_tbnk0_sel_b1), + .l2_mbist2_tbnk0_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), + .l2_mbist2_tbnk0_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), + .l2_mbist2_tbnk0_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), + .l2_mbist2_tbnk0_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), + .l2_mbist2_tbnk0_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), + .l2_mbist2_tbnk1_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), + .l2_mbist2_tbnk1_all_b1 (l2_mbist2_tbnk1_all_b1), + .l2_mbist2_tbnk1_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), + .l2_mbist2_tbnk1_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), + .l2_mbist2_tbnk1_en_b1 (l2_mbist2_tbnk1_en_b1), + .l2_mbist2_tbnk1_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), + .l2_mbist2_tbnk1_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), + .l2_mbist2_tbnk1_sel_b1 (l2_mbist2_tbnk1_sel_b1), + .l2_mbist2_tbnk1_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), + .l2_mbist2_tbnk1_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), + .l2_mbist2_tbnk1_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), + .l2_mbist2_tbnk1_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), + .l2_mbist2_tbnk1_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), + .l2_tbnk0_addr44_l3_q (l2_tbnk0_addr44_l3_q), + .l2_tbnk0_addr_l6 (l2_tbnk0_addr_l6[5:2]), + .l2_tbnk0_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), + .l2_tbnk0_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), + .l2_tbnk0_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), + .l2_tbnk0_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), + .l2_tbnk0_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), + .l2_tbnk0_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), + .l2_tbnk0_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), + .l2_tbnk0_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), + .l2_tbnk0_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), + .l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), + .l2_tbnk0_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), + .l2_tbnk0_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), + .l2_tbnk0_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), + .l2_tbnk0_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), + .l2_tbnk0_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), + .l2_tbnk0_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), + .l2_tbnk0_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), + .l2_tbnk0_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), + .l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), + .l2_tbnk0_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), + .l2_tbnk0_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), + .l2_tbnk0_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), + .l2_tbnk0_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), + .l2_tbnk0_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), + .l2_tbnk0_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), + .l2_tbnk0_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), + .l2_tbnk0_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), + .l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), + .l2_tbnk0_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), + .l2_tbnk0_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), + .l2_tbnk0_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), + .l2_tbnk0_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), + .l2_tbnk0_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), + .l2_tbnk0_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), + .l2_tbnk0_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), + .l2_tbnk0_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), + .l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), + .l2_tbnk0_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), + .l2_tbnk0_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk0_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk0_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk0_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), + .l2_tbnk0_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), + .l2_tbnk0_data_l6 (l2_tbnk0_data_l6[127:0]), + .l2_tbnk0_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), + .l2_tbnk0_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk0_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk0_dirty_l3_q (l2_tbnk0_dirty_l3_q), + .l2_tbnk0_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), + .l2_tbnk0_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), + .l2_tbnk0_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), + .l2_tbnk0_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), + .l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk0_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), + .l2_tbnk0_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), + .l2_tbnk0_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), + .l2_tbnk0_excl_l4_q (l2_tbnk0_excl_l4_q), + .l2_tbnk0_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), + .l2_tbnk0_feq_clr_l4 (l2_tbnk0_feq_clr_l4), + .l2_tbnk0_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), + .l2_tbnk0_hit_l4 (l2_tbnk0_hit_l4), + .l2_tbnk0_hit_l7_q (l2_tbnk0_hit_l7_q), + .l2_tbnk0_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), + .l2_tbnk0_id_l6_q (l2_tbnk0_id_l6_q[9:0]), + .l2_tbnk0_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), + .l2_tbnk0_idle (l2_tbnk0_idle), + .l2_tbnk0_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), + .l2_tbnk0_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), + .l2_tbnk0_l2v_s_q (l2_tbnk0_l2v_s_q), + .l2_tbnk0_l2v_vld_q (l2_tbnk0_l2v_vld_q), + .l2_tbnk0_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), + .l2_tbnk0_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), + .l2_tbnk0_lock_l4 (l2_tbnk0_lock_l4[2:0]), + .l2_tbnk0_merrsr_data (l2_tbnk0_merrsr_data[32:0]), + .l2_tbnk0_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), + .l2_tbnk0_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), + .l2_tbnk0_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), + .l2_tbnk0_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), + .l2_tbnk0_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), + .l2_tbnk0_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), + .l2_tbnk0_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), + .l2_tbnk0_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), + .l2_tbnk0_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), + .l2_tbnk0_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), + .l2_tbnk0_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk0_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk0_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), + .l2_tbnk0_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), + .l2_tbnk0_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), + .l2_tbnk0_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk0_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), + .l2_tbnk0_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), + .l2_tbnk0_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), + .l2_tbnk0_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), + .l2_tbnk0_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk0_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), + .l2_tbnk0_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk0_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), + .l2_tbnk0_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), + .l2_tbnk0_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), + .l2_tbnk0_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), + .l2_tbnk0_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), + .l2_tbnk0_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), + .l2_tbnk0_size_l4_q (l2_tbnk0_size_l4_q[2:0]), + .l2_tbnk0_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), + .l2_tbnk0_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), + .l2_tbnk0_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk0_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk0_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk0_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), + .l2_tbnk0_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), + .l2_tbnk0_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk0_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), + .l2_tbnk0_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), + .l2_tbnk0_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), + .l2_tbnk0_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), + .l2_tbnk0_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), + .l2_tbnk0_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), + .l2_tbnk0_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), + .l2_tbnk0_vld_l6_q (l2_tbnk0_vld_l6_q), + .l2_tbnk0_way_l4_q (l2_tbnk0_way_l4_q), + .l2_tbnk0_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), + .l2_tbnk0_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), + .l2_tbnk0_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), + .l2_tbnk0_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), + .l2_tbnk1_addr44_l3_q (l2_tbnk1_addr44_l3_q), + .l2_tbnk1_addr_l6 (l2_tbnk1_addr_l6[5:2]), + .l2_tbnk1_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), + .l2_tbnk1_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), + .l2_tbnk1_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), + .l2_tbnk1_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), + .l2_tbnk1_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), + .l2_tbnk1_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), + .l2_tbnk1_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), + .l2_tbnk1_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), + .l2_tbnk1_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), + .l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), + .l2_tbnk1_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), + .l2_tbnk1_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), + .l2_tbnk1_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), + .l2_tbnk1_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), + .l2_tbnk1_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), + .l2_tbnk1_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), + .l2_tbnk1_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), + .l2_tbnk1_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), + .l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), + .l2_tbnk1_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), + .l2_tbnk1_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), + .l2_tbnk1_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), + .l2_tbnk1_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), + .l2_tbnk1_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), + .l2_tbnk1_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), + .l2_tbnk1_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), + .l2_tbnk1_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), + .l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), + .l2_tbnk1_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), + .l2_tbnk1_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), + .l2_tbnk1_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), + .l2_tbnk1_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), + .l2_tbnk1_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), + .l2_tbnk1_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), + .l2_tbnk1_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), + .l2_tbnk1_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), + .l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), + .l2_tbnk1_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), + .l2_tbnk1_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk1_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk1_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk1_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), + .l2_tbnk1_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), + .l2_tbnk1_data_l6 (l2_tbnk1_data_l6[127:0]), + .l2_tbnk1_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), + .l2_tbnk1_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk1_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk1_dirty_l3_q (l2_tbnk1_dirty_l3_q), + .l2_tbnk1_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), + .l2_tbnk1_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), + .l2_tbnk1_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), + .l2_tbnk1_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), + .l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk1_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), + .l2_tbnk1_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), + .l2_tbnk1_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), + .l2_tbnk1_excl_l4_q (l2_tbnk1_excl_l4_q), + .l2_tbnk1_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), + .l2_tbnk1_feq_clr_l4 (l2_tbnk1_feq_clr_l4), + .l2_tbnk1_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), + .l2_tbnk1_hit_l4 (l2_tbnk1_hit_l4), + .l2_tbnk1_hit_l7_q (l2_tbnk1_hit_l7_q), + .l2_tbnk1_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), + .l2_tbnk1_id_l6_q (l2_tbnk1_id_l6_q[9:0]), + .l2_tbnk1_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), + .l2_tbnk1_idle (l2_tbnk1_idle), + .l2_tbnk1_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), + .l2_tbnk1_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), + .l2_tbnk1_l2v_s_q (l2_tbnk1_l2v_s_q), + .l2_tbnk1_l2v_vld_q (l2_tbnk1_l2v_vld_q), + .l2_tbnk1_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), + .l2_tbnk1_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), + .l2_tbnk1_lock_l4 (l2_tbnk1_lock_l4[2:0]), + .l2_tbnk1_merrsr_data (l2_tbnk1_merrsr_data[32:0]), + .l2_tbnk1_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), + .l2_tbnk1_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), + .l2_tbnk1_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), + .l2_tbnk1_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), + .l2_tbnk1_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), + .l2_tbnk1_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), + .l2_tbnk1_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), + .l2_tbnk1_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), + .l2_tbnk1_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), + .l2_tbnk1_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), + .l2_tbnk1_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk1_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk1_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), + .l2_tbnk1_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), + .l2_tbnk1_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), + .l2_tbnk1_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk1_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), + .l2_tbnk1_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), + .l2_tbnk1_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), + .l2_tbnk1_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), + .l2_tbnk1_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk1_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), + .l2_tbnk1_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk1_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), + .l2_tbnk1_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), + .l2_tbnk1_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), + .l2_tbnk1_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), + .l2_tbnk1_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), + .l2_tbnk1_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), + .l2_tbnk1_size_l4_q (l2_tbnk1_size_l4_q[2:0]), + .l2_tbnk1_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), + .l2_tbnk1_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), + .l2_tbnk1_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk1_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk1_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk1_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), + .l2_tbnk1_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), + .l2_tbnk1_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk1_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), + .l2_tbnk1_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), + .l2_tbnk1_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), + .l2_tbnk1_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), + .l2_tbnk1_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), + .l2_tbnk1_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), + .l2_tbnk1_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), + .l2_tbnk1_vld_l6_q (l2_tbnk1_vld_l6_q), + .l2_tbnk1_way_l4_q (l2_tbnk1_way_l4_q), + .l2_tbnk1_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), + .l2_tbnk1_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), + .l2_tbnk1_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), + .l2_tbnk1_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), + .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), + .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), + .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), + .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), + .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), + .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), + .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]) + ); // ul2_logic + + maia_l2_tbnk ul2_tbnk0( // outputs + .l2_mbist2_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), + .l2_mbist2_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), + .l2_mbist2_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), + .l2_mbist2_en_b1 (l2_mbist2_tbnk0_en_b1), + .l2_mbist2_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), + .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk0_all_b1), + .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), + .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk0_sel_b1), + .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), + .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), + .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), + .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), + .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), + .l2_tbnk_addr44_l3_q (l2_tbnk0_addr44_l3_q), + .l2_tbnk_addr_l6 (l2_tbnk0_addr_l6[5:2]), + .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), + .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), + .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), + .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), + .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), + .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), + .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), + .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), + .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), + .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), + .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), + .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), + .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), + .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), + .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), + .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), + .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), + .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), + .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), + .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), + .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), + .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), + .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), + .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), + .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), + .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), + .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), + .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), + .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), + .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), + .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), + .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), + .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), + .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), + .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), + .l2_tbnk_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), + .l2_tbnk_data_l6 (l2_tbnk0_data_l6[127:0]), + .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), + .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk_dirty_l3_q (l2_tbnk0_dirty_l3_q), + .l2_tbnk_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), + .l2_tbnk_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), + .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), + .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), + .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), + .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), + .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), + .l2_tbnk_excl_l4_q (l2_tbnk0_excl_l4_q), + .l2_tbnk_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), + .l2_tbnk_feq_clr_l4 (l2_tbnk0_feq_clr_l4), + .l2_tbnk_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), + .l2_tbnk_hit_l4 (l2_tbnk0_hit_l4), + .l2_tbnk_hit_l7_q (l2_tbnk0_hit_l7_q), + .l2_tbnk_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), + .l2_tbnk_id_l6_q (l2_tbnk0_id_l6_q[9:0]), + .l2_tbnk_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), + .l2_tbnk_idle (l2_tbnk0_idle), + .l2_tbnk_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), + .l2_tbnk_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), + .l2_tbnk_l2v_s_q (l2_tbnk0_l2v_s_q), + .l2_tbnk_l2v_vld_q (l2_tbnk0_l2v_vld_q), + .l2_tbnk_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), + .l2_tbnk_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), + .l2_tbnk_lock_l4 (l2_tbnk0_lock_l4[2:0]), + .l2_tbnk_merrsr_data (l2_tbnk0_merrsr_data[32:0]), + .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), + .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), + .l2_tbnk_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), + .l2_tbnk_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), + .l2_tbnk_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), + .l2_tbnk_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), + .l2_tbnk_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), + .l2_tbnk_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), + .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), + .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), + .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), + .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), + .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), + .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), + .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), + .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), + .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), + .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), + .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), + .l2_tbnk_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), + .l2_tbnk_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), + .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), + .l2_tbnk_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), + .l2_tbnk_size_l4_q (l2_tbnk0_size_l4_q[2:0]), + .l2_tbnk_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), + .l2_tbnk_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), + .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), + .l2_tbnk_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), + .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), + .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), + .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), + .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), + .l2_tbnk_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), + .l2_tbnk_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), + .l2_tbnk_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), + .l2_tbnk_vld_l6_q (l2_tbnk0_vld_l6_q), + .l2_tbnk_way_l4_q (l2_tbnk0_way_l4_q), + .l2_tbnk_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), + .l2_tbnk_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), + .l2_tbnk_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), + .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), + + // inputs + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ), + .ck_areset_l2 (ck_areset_l2), + .ck_gclkl2 (ck_gclkb0), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), + .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), + .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), + .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), + .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), + .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), + .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), + .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_skyros_intf (1'b0), + .l2_tbnk_addr_l1 (l2_tbnk0_addr_l1[44:0]), + .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), + .l2_tbnk_asq_full_flsh (l2_tbnk0_asq_full_flsh), + .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), + .l2_tbnk_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), + .l2_tbnk_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), + .l2_tbnk_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), + .l2_tbnk_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), + .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), + .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), + .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), + .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), + .l2_tbnk_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), + .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), + .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), + .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), + .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), + .l2_tbnk_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), + .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), + .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), + .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), + .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), + .l2_tbnk_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), + .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), + .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), + .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), + .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_dirty_l1 (l2_tbnk0_dirty_l1), + .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), + .l2_tbnk_excl_l1 (l2_tbnk0_excl_l1), + .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), + .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), + .l2_tbnk_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), + .l2_tbnk_feq_kill_l3 (l2_tbnk0_feq_kill_l3), + .l2_tbnk_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), + .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .l2_tbnk_id_l1 (l2_tbnk0_id_l1[9:0]), + .l2_tbnk_init_req_l1 (l2_tbnk0_init_req_l1), + .l2_tbnk_kill_l2 (l2_tbnk0_kill_l2), + .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), + .l2_tbnk_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), + .l2_tbnk_last_qw_l1 (l2_tbnk0_last_qw_l1), + .l2_tbnk_lock_l1 (l2_tbnk0_lock_l1[2:0]), + .l2_tbnk_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), + .l2_tbnk_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), + .l2_tbnk_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), + .l2_tbnk_prfm_l1 (l2_tbnk0_prfm_l1), + .l2_tbnk_prot_l1 (l2_tbnk0_prot_l1[3:0]), + .l2_tbnk_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), + .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), + .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), + .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), + .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), + .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), + .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), + .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), + .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), + .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), + .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), + .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), + .l2_tbnk_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), + .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), + .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), + .l2_tbnk_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), + .l2_tbnk_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), + .l2_tbnk_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), + .l2_tbnk_sel_l1 (l2_tbnk0_sel_l1[13:0]), + .l2_tbnk_size_l1 (l2_tbnk0_size_l1[2:0]), + .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), + .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), + .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), + .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_sync_l1 (l2_tbnk0_sync_l1), + .l2_tbnk_type_l1 (l2_tbnk0_type_l1[6:0]), + .l2_tbnk_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), + .l2_tbnk_way_l1 (l2_tbnk0_way_l1), + .l2_tbnk_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), + .l2_tbnk_wr_err_l1 (l2_tbnk0_wr_err_l1), + .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), + .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), + .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), + .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]) + ); // ul2_tbnk0 + + maia_l2_tbnk ul2_tbnk1( // outputs + .l2_mbist2_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), + .l2_mbist2_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), + .l2_mbist2_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), + .l2_mbist2_en_b1 (l2_mbist2_tbnk1_en_b1), + .l2_mbist2_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), + .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk1_all_b1), + .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), + .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk1_sel_b1), + .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), + .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), + .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), + .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), + .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), + .l2_tbnk_addr44_l3_q (l2_tbnk1_addr44_l3_q), + .l2_tbnk_addr_l6 (l2_tbnk1_addr_l6[5:2]), + .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), + .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), + .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), + .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), + .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), + .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), + .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), + .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), + .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), + .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), + .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), + .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), + .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), + .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), + .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), + .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), + .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), + .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), + .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), + .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), + .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), + .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), + .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), + .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), + .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), + .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), + .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), + .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), + .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), + .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), + .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), + .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), + .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), + .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), + .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), + .l2_tbnk_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), + .l2_tbnk_data_l6 (l2_tbnk1_data_l6[127:0]), + .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), + .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk_dirty_l3_q (l2_tbnk1_dirty_l3_q), + .l2_tbnk_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), + .l2_tbnk_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), + .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), + .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), + .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), + .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), + .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), + .l2_tbnk_excl_l4_q (l2_tbnk1_excl_l4_q), + .l2_tbnk_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), + .l2_tbnk_feq_clr_l4 (l2_tbnk1_feq_clr_l4), + .l2_tbnk_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), + .l2_tbnk_hit_l4 (l2_tbnk1_hit_l4), + .l2_tbnk_hit_l7_q (l2_tbnk1_hit_l7_q), + .l2_tbnk_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), + .l2_tbnk_id_l6_q (l2_tbnk1_id_l6_q[9:0]), + .l2_tbnk_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), + .l2_tbnk_idle (l2_tbnk1_idle), + .l2_tbnk_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), + .l2_tbnk_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), + .l2_tbnk_l2v_s_q (l2_tbnk1_l2v_s_q), + .l2_tbnk_l2v_vld_q (l2_tbnk1_l2v_vld_q), + .l2_tbnk_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), + .l2_tbnk_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), + .l2_tbnk_lock_l4 (l2_tbnk1_lock_l4[2:0]), + .l2_tbnk_merrsr_data (l2_tbnk1_merrsr_data[32:0]), + .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), + .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), + .l2_tbnk_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), + .l2_tbnk_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), + .l2_tbnk_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), + .l2_tbnk_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), + .l2_tbnk_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), + .l2_tbnk_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), + .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), + .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), + .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), + .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), + .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), + .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), + .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), + .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), + .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), + .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), + .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), + .l2_tbnk_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), + .l2_tbnk_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), + .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), + .l2_tbnk_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), + .l2_tbnk_size_l4_q (l2_tbnk1_size_l4_q[2:0]), + .l2_tbnk_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), + .l2_tbnk_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), + .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), + .l2_tbnk_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), + .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), + .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), + .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), + .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), + .l2_tbnk_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), + .l2_tbnk_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), + .l2_tbnk_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), + .l2_tbnk_vld_l6_q (l2_tbnk1_vld_l6_q), + .l2_tbnk_way_l4_q (l2_tbnk1_way_l4_q), + .l2_tbnk_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), + .l2_tbnk_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), + .l2_tbnk_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), + .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), + + // inputs + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ), + .ck_areset_l2 (ck_areset_l2), + .ck_gclkl2 (ck_gclkb1), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), + .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), + .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), + .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), + .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), + .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), + .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), + .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_skyros_intf (1'b0), + .l2_tbnk_addr_l1 (l2_tbnk1_addr_l1[44:0]), + .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), + .l2_tbnk_asq_full_flsh (l2_tbnk1_asq_full_flsh), + .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), + .l2_tbnk_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), + .l2_tbnk_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), + .l2_tbnk_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), + .l2_tbnk_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), + .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), + .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), + .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), + .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), + .l2_tbnk_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), + .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), + .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), + .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), + .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), + .l2_tbnk_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), + .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), + .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), + .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), + .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), + .l2_tbnk_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), + .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), + .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), + .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), + .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_dirty_l1 (l2_tbnk1_dirty_l1), + .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), + .l2_tbnk_excl_l1 (l2_tbnk1_excl_l1), + .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), + .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), + .l2_tbnk_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), + .l2_tbnk_feq_kill_l3 (l2_tbnk1_feq_kill_l3), + .l2_tbnk_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), + .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .l2_tbnk_id_l1 (l2_tbnk1_id_l1[9:0]), + .l2_tbnk_init_req_l1 (l2_tbnk1_init_req_l1), + .l2_tbnk_kill_l2 (l2_tbnk1_kill_l2), + .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), + .l2_tbnk_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), + .l2_tbnk_last_qw_l1 (l2_tbnk1_last_qw_l1), + .l2_tbnk_lock_l1 (l2_tbnk1_lock_l1[2:0]), + .l2_tbnk_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), + .l2_tbnk_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), + .l2_tbnk_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), + .l2_tbnk_prfm_l1 (l2_tbnk1_prfm_l1), + .l2_tbnk_prot_l1 (l2_tbnk1_prot_l1[3:0]), + .l2_tbnk_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), + .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), + .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), + .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), + .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), + .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), + .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), + .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), + .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), + .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), + .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), + .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), + .l2_tbnk_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), + .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), + .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), + .l2_tbnk_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), + .l2_tbnk_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), + .l2_tbnk_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), + .l2_tbnk_sel_l1 (l2_tbnk1_sel_l1[13:0]), + .l2_tbnk_size_l1 (l2_tbnk1_size_l1[2:0]), + .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), + .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), + .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), + .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_sync_l1 (l2_tbnk1_sync_l1), + .l2_tbnk_type_l1 (l2_tbnk1_type_l1[6:0]), + .l2_tbnk_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), + .l2_tbnk_way_l1 (l2_tbnk1_way_l1), + .l2_tbnk_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), + .l2_tbnk_wr_err_l1 (l2_tbnk1_wr_err_l1), + .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), + .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), + .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), + .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]) + ); // ul2_tbnk1 + + maia_dt_pclk udt_pclk( // outputs + .CTICHINACK (CTICHINACK[3:0]), + .CTICHOUT (CTICHOUT[3:0]), + .CTIIRQ (CTIIRQ[`MAIA_CN:0]), + .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), + .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), + .PRDATADBG (PRDATADBG[31:0]), + .PREADYDBG (PREADYDBG), + .PSLVERRDBG (PSLVERRDBG), + .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), + .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), + .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), + .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), + .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), + .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), + .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), + .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), + .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + + // inputs + .CIHSBYPASS (CIHSBYPASS[3:0]), + .CISBYPASS (CISBYPASS), + .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), + .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), + .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), + .CTICHIN (CTICHIN[3:0]), + .CTICHOUTACK (CTICHOUTACK[3:0]), + .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), + .DBGEN (DBGEN[`MAIA_CN:0]), + .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .EDBGRQ (EDBGRQ[`MAIA_CN:0]), + .GICCDISABLE (GICCDISABLE), + .NIDEN (NIDEN[`MAIA_CN:0]), + .PADDRDBG (PADDRDBG[21:2]), + .PADDRDBG31 (PADDRDBG31), + .PCLKDBG (PCLKDBG), + .PCLKENDBG (PCLKENDBG), + .PENABLEDBG (PENABLEDBG), + .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), + .PSELDBG (PSELDBG), + .PWDATADBG (PWDATADBG[31:0]), + .PWRITEDBG (PWRITEDBG), + .SPIDEN (SPIDEN[`MAIA_CN:0]), + .SPNIDEN (SPNIDEN[`MAIA_CN:0]), + .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), + .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), + .ck_cpu0_poreset_status (ck_cpu0_poreset_status), + .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), + .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), + .ck_cpu1_poreset_status (ck_cpu1_poreset_status), + .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), + .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), + .ck_cpu2_poreset_status (ck_cpu2_poreset_status), + .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), + .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), + .ck_cpu3_poreset_status (ck_cpu3_poreset_status), + .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), + .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), + .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), + .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), + .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), + .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), + .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), + .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), + .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), + .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), + .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), + .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), + .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), + .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), + .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), + .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), + .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), + .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), + .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), + .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), + .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), + .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), + .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), + .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), + .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .nPRESETDBG (nPRESETDBG) + ); // udt_pclk + + maia_intctrl uic( // outputs + .ICCTDATA (ICCTDATA[15:0]), + .ICCTID (ICCTID[1:0]), + .ICCTLAST (ICCTLAST), + .ICCTVALID (ICCTVALID), + .ICDTREADY (ICDTREADY), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), + .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), + .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), + .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), + .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), + .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), + .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), + .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), + .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), + .ic_el_change_complete_o (ic_el_change_complete_o[`MAIA_CN:0]), + .ic_hcr_change_complete_o (ic_hcr_change_complete_o[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .ic_p_rdata (ic_p_rdata[31:0]), + .ic_p_rdata_valid (ic_p_rdata_valid), + .ic_p_ready (ic_p_ready), + .ic_p_valid (ic_p_valid[`MAIA_CN:0]), + .ic_sample_spr_o (ic_sample_spr_o[`MAIA_CN:0]), + .ic_scr_change_complete_o (ic_scr_change_complete_o[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]), + .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), + + // inputs + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .GICCDISABLE (GICCDISABLE), + .ICCTREADY (ICCTREADY), + .ICDTDATA (ICDTDATA[15:0]), + .ICDTDEST (ICDTDEST[1:0]), + .ICDTLAST (ICDTLAST), + .ICDTVALID (ICDTVALID), + .ck_areset_l2 (ck_areset_l2), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_aa64naa32_i (ds_cpu0_ic_aa64naa32_i), + .ds_cpu0_cpsr_mode_i (ds_cpu0_ic_cpsr_mode_i[4:0]), + .ds_cpu0_hcr_change_i (ds_cpu0_ic_hcr_change_i), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu0_sample_spr_i (ds_cpu0_ic_sample_spr_i), + .ds_cpu0_scr_change_i (ds_cpu0_ic_scr_change_i), + .ds_cpu1_aa64naa32_i (ds_cpu1_ic_aa64naa32_i), + .ds_cpu1_cpsr_mode_i (ds_cpu1_ic_cpsr_mode_i[4:0]), + .ds_cpu1_hcr_change_i (ds_cpu1_ic_hcr_change_i), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu1_sample_spr_i (ds_cpu1_ic_sample_spr_i), + .ds_cpu1_scr_change_i (ds_cpu1_ic_scr_change_i), + .ds_cpu2_aa64naa32_i (ds_cpu2_ic_aa64naa32_i), + .ds_cpu2_cpsr_mode_i (ds_cpu2_ic_cpsr_mode_i[4:0]), + .ds_cpu2_hcr_change_i (ds_cpu2_ic_hcr_change_i), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu2_sample_spr_i (ds_cpu2_ic_sample_spr_i), + .ds_cpu2_scr_change_i (ds_cpu2_ic_scr_change_i), + .ds_cpu3_aa64naa32_i (ds_cpu3_ic_aa64naa32_i), + .ds_cpu3_cpsr_mode_i (ds_cpu3_ic_cpsr_mode_i[4:0]), + .ds_cpu3_hcr_change_i (ds_cpu3_ic_hcr_change_i), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_cpu3_sample_spr_i (ds_cpu3_ic_sample_spr_i), + .ds_cpu3_scr_change_i (ds_cpu3_ic_scr_change_i), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_cpu0_wr_decerr_i (l2_cpu0_wr_decerr_q), + .l2_cpu0_wr_slverr_i (l2_cpu0_wr_slverr_q), + .l2_cpu1_wr_decerr_i (l2_cpu1_wr_decerr_q), + .l2_cpu1_wr_slverr_i (l2_cpu1_wr_slverr_q), + .l2_cpu2_wr_decerr_i (l2_cpu2_wr_decerr_q), + .l2_cpu2_wr_slverr_i (l2_cpu2_wr_slverr_q), + .l2_cpu3_wr_decerr_i (l2_cpu3_wr_decerr_q), + .l2_cpu3_wr_slverr_i (l2_cpu3_wr_slverr_q), + .l2_p_addr (l2_p_addr[13:0]), + .l2_p_cpu (l2_p_cpu[1:0]), + .l2_p_nsecure (l2_p_nsecure), + .l2_p_sel (l2_p_sel[2:0]), + .l2_p_wdata (l2_p_wdata[31:0]), + .l2_p_write (l2_p_write), + .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), + .nFIQ (nFIQ[`MAIA_CN:0]), + .nIRQ (nIRQ[`MAIA_CN:0]), + .nREI (nREI[`MAIA_CN:0]), + .nSEI (nSEI[`MAIA_CN:0]), + .nVFIQ (nVFIQ[`MAIA_CN:0]), + .nVIRQ (nVIRQ[`MAIA_CN:0]), + .nVSEI (nVSEI[`MAIA_CN:0]) + ); // uic + + maia_ck_l2 uck_l2( // outputs + .ck_gclkb0 (ck_gclkb0), + .ck_gclkb1 (ck_gclkb1), + .ck_gclkfr (ck_gclkfr), + .ck_gclkl2 (ck_gclkl2), + + // inputs + .DFTL2CLKDISABLE (DFTL2CLKDISABLE), + .DFTSE (DFTSE), + .ck_gclktl2 (ck_gclktl2), + .ck_l2_logic_clk_en (ck_l2_logic_clk_en), + .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), + .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), + .l2_reset3 (l2_reset3) + ); // uck_l2 + + maia_ck_top uck_top( // outputs + .ck_gclkt (ck_gclkt[`MAIA_CN:0]), + .ck_gclktl2 (ck_gclktl2), + + // inputs + .CLK (CLK), + .CLKEN (CLKEN), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ) + ); // uck_top + + maia_ck_logic uck_logic( // outputs + .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), + .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), + .CPUQDENY (CPUQDENY[`MAIA_CN:0]), + .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), + .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), + .STANDBYWFIL2 (STANDBYWFIL2), + .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), + .ck_cpu0_commrx (ck_cpu0_commrx), + .ck_cpu0_commtx (ck_cpu0_commtx), + .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), + .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), + .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), + .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), + .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), + .ck_cpu0_event_reg (ck_cpu0_event_reg), + .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), + .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), + .ck_cpu0_ncommirq (ck_cpu0_ncommirq), + .ck_cpu0_npmuirq (ck_cpu0_npmuirq), + .ck_cpu0_poreset_status (ck_cpu0_poreset_status), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), + .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), + .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), + .ck_cpu1_commrx (ck_cpu1_commrx), + .ck_cpu1_commtx (ck_cpu1_commtx), + .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), + .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), + .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), + .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), + .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), + .ck_cpu1_event_reg (ck_cpu1_event_reg), + .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), + .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), + .ck_cpu1_ncommirq (ck_cpu1_ncommirq), + .ck_cpu1_npmuirq (ck_cpu1_npmuirq), + .ck_cpu1_poreset_status (ck_cpu1_poreset_status), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), + .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), + .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), + .ck_cpu2_commrx (ck_cpu2_commrx), + .ck_cpu2_commtx (ck_cpu2_commtx), + .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), + .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), + .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), + .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), + .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), + .ck_cpu2_event_reg (ck_cpu2_event_reg), + .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), + .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), + .ck_cpu2_ncommirq (ck_cpu2_ncommirq), + .ck_cpu2_npmuirq (ck_cpu2_npmuirq), + .ck_cpu2_poreset_status (ck_cpu2_poreset_status), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), + .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), + .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), + .ck_cpu3_commrx (ck_cpu3_commrx), + .ck_cpu3_commtx (ck_cpu3_commtx), + .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), + .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), + .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), + .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), + .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), + .ck_cpu3_event_reg (ck_cpu3_event_reg), + .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), + .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), + .ck_cpu3_ncommirq (ck_cpu3_ncommirq), + .ck_cpu3_npmuirq (ck_cpu3_npmuirq), + .ck_cpu3_poreset_status (ck_cpu3_poreset_status), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), + .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), + .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), + .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), + .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), + .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), + .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), + .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), + .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), + .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), + .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), + .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), + .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), + .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), + .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), + .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), + .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), + .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), + .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), + .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), + .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), + .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), + .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), + .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), + .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), + .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), + .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), + .ck_l2_ace_inactive (ck_l2_ace_inactive), + .ck_l2_acp_inactive (ck_l2_acp_inactive), + .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), + + // inputs + .ACINACTM (ACINACTM), + .AINACTS (AINACTS), + .CPUQREQn (CPUQREQn[`MAIA_CN:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .ck_gclkfr (ck_gclkfr), + .clrexmon_c1 (clrexmon_c1), + .commrx_cpu0_i (commrx_cpu0_i), + .commrx_cpu1_i (commrx_cpu1_i), + .commrx_cpu2_i (commrx_cpu2_i), + .commrx_cpu3_i (commrx_cpu3_i), + .commtx_cpu0_i (commtx_cpu0_i), + .commtx_cpu1_i (commtx_cpu1_i), + .commtx_cpu2_i (commtx_cpu2_i), + .commtx_cpu3_i (commtx_cpu3_i), + .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), + .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), + .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), + .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), + .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), + .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), + .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), + .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_cpu0_flush (ds_cpu0_flush), + .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), + .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), + .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_cpu0_reset_req (ds_cpu0_reset_req), + .ds_cpu0_sevl_req (ds_cpu0_sevl_req), + .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_cpu0_wfe_req (ds_cpu0_wfe_req), + .ds_cpu0_wfi_req (ds_cpu0_wfi_req), + .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_cpu1_flush (ds_cpu1_flush), + .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), + .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), + .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_cpu1_reset_req (ds_cpu1_reset_req), + .ds_cpu1_sevl_req (ds_cpu1_sevl_req), + .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_cpu1_wfe_req (ds_cpu1_wfe_req), + .ds_cpu1_wfi_req (ds_cpu1_wfi_req), + .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_cpu2_flush (ds_cpu2_flush), + .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), + .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), + .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_cpu2_reset_req (ds_cpu2_reset_req), + .ds_cpu2_sevl_req (ds_cpu2_sevl_req), + .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_cpu2_wfe_req (ds_cpu2_wfe_req), + .ds_cpu2_wfi_req (ds_cpu2_wfi_req), + .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_cpu3_flush (ds_cpu3_flush), + .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), + .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), + .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_cpu3_reset_req (ds_cpu3_reset_req), + .ds_cpu3_sevl_req (ds_cpu3_sevl_req), + .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_cpu3_wfe_req (ds_cpu3_wfe_req), + .ds_cpu3_wfi_req (ds_cpu3_wfi_req), + .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), + .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), + .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), + .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), + .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), + .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), + .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), + .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), + .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_cpu0_snp_active (l2_cpu0_snp_active), + .l2_cpu1_snp_active (l2_cpu1_snp_active), + .l2_cpu2_snp_active (l2_cpu2_snp_active), + .l2_cpu3_snp_active (l2_cpu3_snp_active), + .l2_idle (l2_idle), + .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), + .l2_reset3 (l2_reset3), + .l2_sky_link_stopped (1'b1), + .ls_cpu0_clrexmon (ls_cpu0_clrexmon), + .ls_cpu1_clrexmon (ls_cpu1_clrexmon), + .ls_cpu2_clrexmon (ls_cpu2_clrexmon), + .ls_cpu3_clrexmon (ls_cpu3_clrexmon), + .nCORERESET (nCORERESET[`MAIA_CN:0]), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .ncommirq_cpu0_i (ncommirq_cpu0_i), + .ncommirq_cpu1_i (ncommirq_cpu1_i), + .ncommirq_cpu2_i (ncommirq_cpu2_i), + .ncommirq_cpu3_i (ncommirq_cpu3_i), + .npmuirq_cpu0_i (npmuirq_cpu0_i), + .npmuirq_cpu1_i (npmuirq_cpu1_i), + .npmuirq_cpu2_i (npmuirq_cpu2_i), + .npmuirq_cpu3_i (npmuirq_cpu3_i), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_event_sev (tm_cpu0_event_sev), + .tm_cpu1_event_sev (tm_cpu1_event_sev), + .tm_cpu2_event_sev (tm_cpu2_event_sev), + .tm_cpu3_event_sev (tm_cpu3_event_sev) + ); // uck_logic + + maia_cpu_io ucpu_io( // outputs + .aa64naa32_cpu0_o (aa64naa32_cpu0_o), + .aa64naa32_cpu1_o (aa64naa32_cpu1_o), + .aa64naa32_cpu2_o (aa64naa32_cpu2_o), + .aa64naa32_cpu3_o (aa64naa32_cpu3_o), + .cfgend_cpu0_o (cfgend_cpu0_o), + .cfgend_cpu1_o (cfgend_cpu1_o), + .cfgend_cpu2_o (cfgend_cpu2_o), + .cfgend_cpu3_o (cfgend_cpu3_o), + .cfgte_cpu0_o (cfgte_cpu0_o), + .cfgte_cpu1_o (cfgte_cpu1_o), + .cfgte_cpu2_o (cfgte_cpu2_o), + .cfgte_cpu3_o (cfgte_cpu3_o), + .clrexmon_c1 (clrexmon_c1), + .clrexmonack_o (CLREXMONACK), + .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), + .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), + .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), + .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), + .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), + .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), + .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), + .commrx_o (COMMRX[`MAIA_CN:0]), + .commtx_o (COMMTX[`MAIA_CN:0]), + .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), + .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), + .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), + .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), + .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), + .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), + .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), + .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu0_o (cryptodisable_cpu0_o), + .cryptodisable_cpu1_o (cryptodisable_cpu1_o), + .cryptodisable_cpu2_o (cryptodisable_cpu2_o), + .cryptodisable_cpu3_o (cryptodisable_cpu3_o), + .dbgack_o (DBGACK[`MAIA_CN:0]), + .dbgen_cpu0_o (dbgen_cpu0_o), + .dbgen_cpu1_o (dbgen_cpu1_o), + .dbgen_cpu2_o (dbgen_cpu2_o), + .dbgen_cpu3_o (dbgen_cpu3_o), + .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), + .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), + .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), + .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), + .dbgnopwrdwn_o (DBGNOPWRDWN[`MAIA_CN:0]), + .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), + .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), + .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), + .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), + .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), + .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), + .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), + .dbgrstreq_o (DBGRSTREQ[`MAIA_CN:0]), + .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), + .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), + .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), + .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), + .dftramhold_cpu0_o (dftramhold_cpu0_o), + .dftramhold_cpu1_o (dftramhold_cpu1_o), + .dftramhold_cpu2_o (dftramhold_cpu2_o), + .dftramhold_cpu3_o (dftramhold_cpu3_o), + .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), + .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), + .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), + .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), + .dftse_cpu0_o (dftse_cpu0_o), + .dftse_cpu1_o (dftse_cpu1_o), + .dftse_cpu2_o (dftse_cpu2_o), + .dftse_cpu3_o (dftse_cpu3_o), + .eventi_sev (eventi_sev), + .evento_o (EVENTO), + .giccdisable_cpu0_o (giccdisable_cpu0_o), + .giccdisable_cpu1_o (giccdisable_cpu1_o), + .giccdisable_cpu2_o (giccdisable_cpu2_o), + .giccdisable_cpu3_o (giccdisable_cpu3_o), + .ncommirq_o (nCOMMIRQ[`MAIA_CN:0]), + .ncorereset_cpu0_o (ncorereset_cpu0_o), + .ncorereset_cpu1_o (ncorereset_cpu1_o), + .ncorereset_cpu2_o (ncorereset_cpu2_o), + .ncorereset_cpu3_o (ncorereset_cpu3_o), + .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), + .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), + .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), + .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), + .niden_cpu0_o (niden_cpu0_o), + .niden_cpu1_o (niden_cpu1_o), + .niden_cpu2_o (niden_cpu2_o), + .niden_cpu3_o (niden_cpu3_o), + .nmbistreset_cpu0_o (nmbistreset_cpu0_o), + .nmbistreset_cpu1_o (nmbistreset_cpu1_o), + .nmbistreset_cpu2_o (nmbistreset_cpu2_o), + .nmbistreset_cpu3_o (nmbistreset_cpu3_o), + .npmuirq_o (nPMUIRQ[`MAIA_CN:0]), + .pmuevent0_o (PMUEVENT0[24:0]), + .pmuevent1_o (PMUEVENT1[24:0]), + .pmuevent2_o (PMUEVENT2[24:0]), + .pmuevent3_o (PMUEVENT3[24:0]), + .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), + .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), + .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), + .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), + .smpen_o (SMPEN[`MAIA_CN:0]), + .spiden_cpu0_o (spiden_cpu0_o), + .spiden_cpu1_o (spiden_cpu1_o), + .spiden_cpu2_o (spiden_cpu2_o), + .spiden_cpu3_o (spiden_cpu3_o), + .spniden_cpu0_o (spniden_cpu0_o), + .spniden_cpu1_o (spniden_cpu1_o), + .spniden_cpu2_o (spniden_cpu2_o), + .spniden_cpu3_o (spniden_cpu3_o), + .vinithi_cpu0_o (vinithi_cpu0_o), + .vinithi_cpu1_o (vinithi_cpu1_o), + .vinithi_cpu2_o (vinithi_cpu2_o), + .vinithi_cpu3_o (vinithi_cpu3_o), + + // inputs + .aa64naa32_i (AA64nAA32[`MAIA_CN:0]), + .cfgend_i (CFGEND[`MAIA_CN:0]), + .cfgte_i (CFGTE[`MAIA_CN:0]), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), + .ck_cpu0_commrx (ck_cpu0_commrx), + .ck_cpu0_commtx (ck_cpu0_commtx), + .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), + .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), + .ck_cpu0_ncommirq (ck_cpu0_ncommirq), + .ck_cpu0_npmuirq (ck_cpu0_npmuirq), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), + .ck_cpu1_commrx (ck_cpu1_commrx), + .ck_cpu1_commtx (ck_cpu1_commtx), + .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), + .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), + .ck_cpu1_ncommirq (ck_cpu1_ncommirq), + .ck_cpu1_npmuirq (ck_cpu1_npmuirq), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), + .ck_cpu2_commrx (ck_cpu2_commrx), + .ck_cpu2_commtx (ck_cpu2_commtx), + .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), + .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), + .ck_cpu2_ncommirq (ck_cpu2_ncommirq), + .ck_cpu2_npmuirq (ck_cpu2_npmuirq), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), + .ck_cpu3_commrx (ck_cpu3_commrx), + .ck_cpu3_commtx (ck_cpu3_commtx), + .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), + .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), + .ck_cpu3_ncommirq (ck_cpu3_ncommirq), + .ck_cpu3_npmuirq (ck_cpu3_npmuirq), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), + .ck_gclkfr (ck_gclkfr), + .clrexmonreq_i (CLREXMONREQ), + .clusteridaff1_i (CLUSTERIDAFF1[7:0]), + .clusteridaff2_i (CLUSTERIDAFF2[7:0]), + .cp15sdisable_i (CP15SDISABLE[`MAIA_CN:0]), + .cryptodisable_i (CRYPTODISABLE[`MAIA_CN:0]), + .dbgack_cpu0_i (dbgack_cpu0_i), + .dbgack_cpu1_i (dbgack_cpu1_i), + .dbgack_cpu2_i (dbgack_cpu2_i), + .dbgack_cpu3_i (dbgack_cpu3_i), + .dbgen_i (DBGEN[`MAIA_CN:0]), + .dbgl1rstdisable_i (DBGL1RSTDISABLE), + .dbgromaddr_i (DBGROMADDR[43:12]), + .dbgromaddrv_i (DBGROMADDRV), + .dftcrclkdisable_i (DFTCRCLKDISABLE[`MAIA_CN:0]), + .dftramhold_i (DFTRAMHOLD), + .dftrstdisable_i (DFTRSTDISABLE), + .dftse_i (DFTSE), + .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_cpu0_sev_req (ds_cpu0_sev_req), + .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_cpu1_sev_req (ds_cpu1_sev_req), + .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_cpu2_sev_req (ds_cpu2_sev_req), + .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_cpu3_sev_req (ds_cpu3_sev_req), + .eventi_i (EVENTI), + .giccdisable_i (GICCDISABLE), + .l2_reset3 (l2_reset3), + .ncorereset_i (nCORERESET[`MAIA_CN:0]), + .ncpuporeset_i (nCPUPORESET[`MAIA_CN:0]), + .niden_i (NIDEN[`MAIA_CN:0]), + .nmbistreset_i (nMBISTRESET), + .pm_export_cpu0_i (pm_export_cpu0_i), + .pm_export_cpu1_i (pm_export_cpu1_i), + .pm_export_cpu2_i (pm_export_cpu2_i), + .pm_export_cpu3_i (pm_export_cpu3_i), + .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), + .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), + .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), + .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]), + .rvbaraddr0_i (RVBARADDR0[43:2]), + .rvbaraddr1_i (RVBARADDR1[43:2]), + .rvbaraddr2_i (RVBARADDR2[43:2]), + .rvbaraddr3_i (RVBARADDR3[43:2]), + .spiden_i (SPIDEN[`MAIA_CN:0]), + .spniden_i (SPNIDEN[`MAIA_CN:0]), + .vinithi_i (VINITHI[`MAIA_CN:0]) + ); // ucpu_io + + maia_dt_sb udt_sb( // outputs + .afreadym0_o (AFREADYM0), + .afreadym1_o (AFREADYM1), + .afreadym2_o (AFREADYM2), + .afreadym3_o (AFREADYM3), + .afvalidm_cpu0_o (afvalidm_cpu0_o), + .afvalidm_cpu1_o (afvalidm_cpu1_o), + .afvalidm_cpu2_o (afvalidm_cpu2_o), + .afvalidm_cpu3_o (afvalidm_cpu3_o), + .atbytesm0_o (ATBYTESM0[1:0]), + .atbytesm1_o (ATBYTESM1[1:0]), + .atbytesm2_o (ATBYTESM2[1:0]), + .atbytesm3_o (ATBYTESM3[1:0]), + .atclken_cpu0_o (atclken_cpu0_o), + .atclken_cpu1_o (atclken_cpu1_o), + .atclken_cpu2_o (atclken_cpu2_o), + .atclken_cpu3_o (atclken_cpu3_o), + .atdatam0_o (ATDATAM0[31:0]), + .atdatam1_o (ATDATAM1[31:0]), + .atdatam2_o (ATDATAM2[31:0]), + .atdatam3_o (ATDATAM3[31:0]), + .atidm0_o (ATIDM0[6:0]), + .atidm1_o (ATIDM1[6:0]), + .atidm2_o (ATIDM2[6:0]), + .atidm3_o (ATIDM3[6:0]), + .atreadym_cpu0_o (atreadym_cpu0_o), + .atreadym_cpu1_o (atreadym_cpu1_o), + .atreadym_cpu2_o (atreadym_cpu2_o), + .atreadym_cpu3_o (atreadym_cpu3_o), + .atvalidm0_o (ATVALIDM0), + .atvalidm1_o (ATVALIDM1), + .atvalidm2_o (ATVALIDM2), + .atvalidm3_o (ATVALIDM3), + .syncreqm_cpu0_o (syncreqm_cpu0_o), + .syncreqm_cpu1_o (syncreqm_cpu1_o), + .syncreqm_cpu2_o (syncreqm_cpu2_o), + .syncreqm_cpu3_o (syncreqm_cpu3_o), + .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), + .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), + .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), + .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), + + // inputs + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .TSVALUEB (TSVALUEB[63:0]), + .afreadym_cpu0_i (afreadym_cpu0_i), + .afreadym_cpu1_i (afreadym_cpu1_i), + .afreadym_cpu2_i (afreadym_cpu2_i), + .afreadym_cpu3_i (afreadym_cpu3_i), + .afvalidm0_i (AFVALIDM0), + .afvalidm1_i (AFVALIDM1), + .afvalidm2_i (AFVALIDM2), + .afvalidm3_i (AFVALIDM3), + .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), + .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), + .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), + .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), + .atclken_i (ATCLKEN), + .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), + .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), + .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), + .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), + .atidm_cpu0_i (atidm_cpu0_i[6:0]), + .atidm_cpu1_i (atidm_cpu1_i[6:0]), + .atidm_cpu2_i (atidm_cpu2_i[6:0]), + .atidm_cpu3_i (atidm_cpu3_i[6:0]), + .atreadym0_i (ATREADYM0), + .atreadym1_i (ATREADYM1), + .atreadym2_i (ATREADYM2), + .atreadym3_i (ATREADYM3), + .atvalidm_cpu0_i (atvalidm_cpu0_i), + .atvalidm_cpu1_i (atvalidm_cpu1_i), + .atvalidm_cpu2_i (atvalidm_cpu2_i), + .atvalidm_cpu3_i (atvalidm_cpu3_i), + .ck_gclkfr (ck_gclkfr), + .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), + .etclken_cpu0_i (etclken_cpu0_i), + .etclken_cpu1_i (etclken_cpu1_i), + .etclken_cpu2_i (etclken_cpu2_i), + .etclken_cpu3_i (etclken_cpu3_i), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nMBISTRESET (nMBISTRESET), + .syncreqm0_i (SYNCREQM0), + .syncreqm1_i (SYNCREQM1), + .syncreqm2_i (SYNCREQM2), + .syncreqm3_i (SYNCREQM3) + ); // udt_sb + + maia_ncpu_reg_rep uncpu_reg_rep( // outputs + .ds_cpu0_ic_aa64naa32_reg_o (ds_cpu0_ic_aa64naa32_i), + .ds_cpu0_ic_cpsr_mode_reg_o (ds_cpu0_ic_cpsr_mode_i[4:0]), + .ds_cpu0_ic_hcr_change_reg_o (ds_cpu0_ic_hcr_change_i), + .ds_cpu0_ic_sample_spr_reg_o (ds_cpu0_ic_sample_spr_i), + .ds_cpu0_ic_scr_change_reg_o (ds_cpu0_ic_scr_change_i), + .ds_cpu1_ic_aa64naa32_reg_o (ds_cpu1_ic_aa64naa32_i), + .ds_cpu1_ic_cpsr_mode_reg_o (ds_cpu1_ic_cpsr_mode_i[4:0]), + .ds_cpu1_ic_hcr_change_reg_o (ds_cpu1_ic_hcr_change_i), + .ds_cpu1_ic_sample_spr_reg_o (ds_cpu1_ic_sample_spr_i), + .ds_cpu1_ic_scr_change_reg_o (ds_cpu1_ic_scr_change_i), + .ds_cpu2_ic_aa64naa32_reg_o (ds_cpu2_ic_aa64naa32_i), + .ds_cpu2_ic_cpsr_mode_reg_o (ds_cpu2_ic_cpsr_mode_i[4:0]), + .ds_cpu2_ic_hcr_change_reg_o (ds_cpu2_ic_hcr_change_i), + .ds_cpu2_ic_sample_spr_reg_o (ds_cpu2_ic_sample_spr_i), + .ds_cpu2_ic_scr_change_reg_o (ds_cpu2_ic_scr_change_i), + .ds_cpu3_ic_aa64naa32_reg_o (ds_cpu3_ic_aa64naa32_i), + .ds_cpu3_ic_cpsr_mode_reg_o (ds_cpu3_ic_cpsr_mode_i[4:0]), + .ds_cpu3_ic_hcr_change_reg_o (ds_cpu3_ic_hcr_change_i), + .ds_cpu3_ic_sample_spr_reg_o (ds_cpu3_ic_sample_spr_i), + .ds_cpu3_ic_scr_change_reg_o (ds_cpu3_ic_scr_change_i), + .ic_block_eoi_sgi_wr_reg_o (ic_block_eoi_sgi_wr[`MAIA_CN:0]), + .ic_el_change_complete_reg_o (ic_el_change_complete[`MAIA_CN:0]), + .ic_hcr_change_complete_reg_o (ic_hcr_change_complete[`MAIA_CN:0]), + .ic_ich_el2_tall0_reg_o (ic_ich_el2_tall0[`MAIA_CN:0]), + .ic_ich_el2_tall1_reg_o (ic_ich_el2_tall1[`MAIA_CN:0]), + .ic_ich_el2_tc_reg_o (ic_ich_el2_tc[`MAIA_CN:0]), + .ic_nfiq_reg_o (ic_nfiq[`MAIA_CN:0]), + .ic_nirq_reg_o (ic_nirq[`MAIA_CN:0]), + .ic_nsei_reg_o (ic_nsei[`MAIA_CN:0]), + .ic_nvfiq_reg_o (ic_nvfiq[`MAIA_CN:0]), + .ic_nvirq_reg_o (ic_nvirq[`MAIA_CN:0]), + .ic_nvsei_reg_o (ic_nvsei[`MAIA_CN:0]), + .ic_sample_spr_reg_o (ic_sample_spr[`MAIA_CN:0]), + .ic_scr_change_complete_reg_o (ic_scr_change_complete[`MAIA_CN:0]), + .ic_sra_el1ns_en_reg_o (ic_sra_el1ns_en[`MAIA_CN:0]), + .ic_sra_el1s_en_reg_o (ic_sra_el1s_en[`MAIA_CN:0]), + .ic_sra_el2_en_reg_o (ic_sra_el2_en[`MAIA_CN:0]), + .ic_sra_el3_en_reg_o (ic_sra_el3_en[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap_reg_o (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap_reg_o (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap_reg_o (ic_sre_el1s_mon_trap[`MAIA_CN:0]), + .ic_sre_el2_mon_trap_reg_o (ic_sre_el2_mon_trap[`MAIA_CN:0]), + + // inputs + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), + .ic_el_change_complete (ic_el_change_complete_o[`MAIA_CN:0]), + .ic_hcr_change_complete (ic_hcr_change_complete_o[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .ic_sample_spr (ic_sample_spr_o[`MAIA_CN:0]), + .ic_scr_change_complete (ic_scr_change_complete_o[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]) + ); // uncpu_reg_rep + +//----------------------------------------------------------------------------- +// OVL Assertions +//----------------------------------------------------------------------------- +`ifdef ARM_ASSERT_ON + `include "maia_noncpu_feq20_val.v" +`endif + +endmodule // maia_noncpu_feq20 + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20_s.v b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20_s.v new file mode 100644 index 0000000000..d5b5463db9 --- /dev/null +++ b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq20_s.v @@ -0,0 +1,7951 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: maia_noncpu_feq20_s.v $ +// Checked In : $Date: 2015-05-06 10:47:09 -0500 (Wed, 06 May 2015) $ +// Revision : $Revision: 73443 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// +// This is top-level interconnect layer for the non-CPU blocks at the Maia top-level. +// + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +`define MAIA_CN 3 + +module maia_noncpu_feq20_s ( + CLK, + CLKEN, + nCPUPORESET, + nCORERESET, + nL2RESET, + L2RSTDISABLE, + WARMRSTREQ, + CFGEND, + VINITHI, + CFGTE, + CP15SDISABLE, + CLUSTERIDAFF1, + CLUSTERIDAFF2, + AA64nAA32, + RVBARADDR0, +// BEGIN INCLUDE FOR CPU1 + RVBARADDR1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + RVBARADDR2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + RVBARADDR3, +// END INCLUDE FOR CPU3 + CRYPTODISABLE, + nFIQ, + nIRQ, + nSEI, + nREI, + nVFIQ, + nVIRQ, + nVSEI, +// BEGIN NO-GIC pins + nVCPUMNTIRQ, +// END NO-GIC pins + PERIPHBASE, +// BEGIN NO-GIC pins + GICCDISABLE, + ICDTVALID, + ICDTREADY, + ICDTDATA, + ICDTLAST, + ICDTDEST, + ICCTVALID, + ICCTREADY, + ICCTDATA, + ICCTLAST, + ICCTID, +// END NO-GIC pins + CNTVALUEB, + CNTCLKEN, + nCNTPNSIRQ, + nCNTPSIRQ, + nCNTVIRQ, + nCNTHPIRQ, + CLREXMONREQ, + CLREXMONACK, + EVENTI, + EVENTO, + STANDBYWFI, + STANDBYWFE, + STANDBYWFIL2, + SMPEN, + CPUQACTIVE, + CPUQREQn, + CPUQACCEPTn, + CPUQDENY, + L2QACTIVE, + L2QREQn, + L2QACCEPTn, + L2QDENY, + L2FLUSHREQ, + L2FLUSHDONE, + nINTERRIRQ, + nEXTERRIRQ, + SYSBARDISABLE, + BROADCASTINNER, + BROADCASTOUTER, + BROADCASTCACHEMAINT, + SCLKEN, + SINACT, + NODEID, + TXSACTIVE, + RXSACTIVE, + TXLINKACTIVEREQ, + TXLINKACTIVEACK, + RXLINKACTIVEREQ, + RXLINKACTIVEACK, + TXREQFLITPEND, + TXREQFLITV, + TXREQFLIT, + REQMEMATTR, + TXREQLCRDV, + TXRSPFLITPEND, + TXRSPFLITV, + TXRSPFLIT, + TXRSPLCRDV, + TXDATFLITPEND, + TXDATFLITV, + TXDATFLIT, + TXDATLCRDV, + RXSNPFLITPEND, + RXSNPFLITV, + RXSNPFLIT, + RXSNPLCRDV, + RXRSPFLITPEND, + RXRSPFLITV, + RXRSPFLIT, + RXRSPLCRDV, + RXDATFLITPEND, + RXDATFLITV, + RXDATFLIT, + RXDATLCRDV, + SAMMNBASE, + SAMADDRMAP0, + SAMADDRMAP1, + SAMADDRMAP2, + SAMADDRMAP3, + SAMADDRMAP4, + SAMADDRMAP5, + SAMADDRMAP6, + SAMADDRMAP7, + SAMADDRMAP8, + SAMADDRMAP9, + SAMADDRMAP10, + SAMADDRMAP11, + SAMADDRMAP12, + SAMADDRMAP13, + SAMADDRMAP14, + SAMADDRMAP15, + SAMADDRMAP16, + SAMADDRMAP17, + SAMADDRMAP18, + SAMADDRMAP19, + SAMMNNODEID, + SAMHNI0NODEID, + SAMHNI1NODEID, + SAMHNF0NODEID, + SAMHNF1NODEID, + SAMHNF2NODEID, + SAMHNF3NODEID, + SAMHNF4NODEID, + SAMHNF5NODEID, + SAMHNF6NODEID, + SAMHNF7NODEID, + SAMHNFMODE, + ACLKENS, + AINACTS, +// BEGIN NO-ACP pins + AWREADYS, + AWVALIDS, + AWIDS, + AWADDRS, + AWLENS, + AWCACHES, + AWUSERS, + AWPROTS, + WREADYS, + WVALIDS, + WDATAS, + WSTRBS, + WLASTS, + BREADYS, + BVALIDS, + BIDS, + BRESPS, + ARREADYS, + ARVALIDS, + ARIDS, + ARADDRS, + ARLENS, + ARCACHES, + ARUSERS, + ARPROTS, + RREADYS, + RVALIDS, + RIDS, + RDATAS, + RRESPS, + RLASTS, +// END NO-ACP pins + DBGROMADDR, + DBGROMADDRV, + DBGACK, + nCOMMIRQ, + COMMRX, + COMMTX, + DBGRSTREQ, + DBGNOPWRDWN, + DBGL1RSTDISABLE, + nPMUIRQ, + PMUEVENT0, +// BEGIN INCLUDE FOR CPU1 + PMUEVENT1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + PMUEVENT2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + PMUEVENT3, +// END INCLUDE FOR CPU3 + ATCLKEN, + TSVALUEB, + ATREADYM0, + AFVALIDM0, + ATDATAM0, + ATVALIDM0, + ATBYTESM0, + AFREADYM0, + ATIDM0, + SYNCREQM0, +// BEGIN INCLUDE FOR CPU1 + ATREADYM1, + AFVALIDM1, + ATDATAM1, + ATVALIDM1, + ATBYTESM1, + AFREADYM1, + ATIDM1, + SYNCREQM1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ATREADYM2, + AFVALIDM2, + ATDATAM2, + ATVALIDM2, + ATBYTESM2, + AFREADYM2, + ATIDM2, + SYNCREQM2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ATREADYM3, + AFVALIDM3, + ATDATAM3, + ATVALIDM3, + ATBYTESM3, + AFREADYM3, + ATIDM3, + SYNCREQM3, +// END INCLUDE FOR CPU3 + PCLKDBG, + PCLKENDBG, + nPRESETDBG, + PSELDBG, + PADDRDBG, + PADDRDBG31, + PENABLEDBG, + PWRITEDBG, + PWDATADBG, + PRDATADBG, + PREADYDBG, + PSLVERRDBG, + EDBGRQ, + PMUSNAPSHOTREQ, + PMUSNAPSHOTACK, + DBGPWRDUP, + DBGPWRUPREQ, + CTICHIN, + CTICHOUTACK, + CTICHOUT, + CTICHINACK, + CISBYPASS, + CIHSBYPASS, + CTIIRQ, + CTIIRQACK, + DBGEN, + NIDEN, + SPIDEN, + SPNIDEN, + DFTSE, + DFTRSTDISABLE, + DFTCRCLKDISABLE, + DFTL2CLKDISABLE, + DFTRAMHOLD, + DFTCLKBYPASS, + DFTMCPHOLD, + nMBISTRESET, + MBISTREQ, + +//----------------------------------------------------------------------------- +// Signals from maia -> maia_cpu_io -> maia_cpu +//----------------------------------------------------------------------------- +// Outputs to maia_cpu + ncpuporeset_cpu0_o, + ncorereset_cpu0_o, + + cfgend_cpu0_o, + cfgte_cpu0_o, + cp15sdisable_cpu0_o, + vinithi_cpu0_o, + clusteridaff1_cpu0_o, + clusteridaff2_cpu0_o, + cpuid_cpu0_o, + aa64naa32_cpu0_o, + rvbaraddr_cpu0_o, + cryptodisable_cpu0_o, + giccdisable_cpu0_o, + + dbgromaddr_cpu0_o, + dbgromaddrv_cpu0_o, + dbgl1rstdisable_cpu0_o, + + dbgen_cpu0_o, + niden_cpu0_o, + spiden_cpu0_o, + spniden_cpu0_o, + + tsvalueb_cpu0_o, + + atclken_cpu0_o, + afvalidm_cpu0_o, + atreadym_cpu0_o, + syncreqm_cpu0_o, + + dftse_cpu0_o, + dftrstdisable_cpu0_o, + dftcrclkdisable_cpu0_o, + dftramhold_cpu0_o, + + nmbistreset_cpu0_o, + +// BEGIN INCLUDE FOR CPU1 + ncpuporeset_cpu1_o, + ncorereset_cpu1_o, + + cfgend_cpu1_o, + cfgte_cpu1_o, + cp15sdisable_cpu1_o, + vinithi_cpu1_o, + clusteridaff1_cpu1_o, + clusteridaff2_cpu1_o, + cpuid_cpu1_o, + aa64naa32_cpu1_o, + rvbaraddr_cpu1_o, + cryptodisable_cpu1_o, + giccdisable_cpu1_o, + + dbgromaddr_cpu1_o, + dbgromaddrv_cpu1_o, + dbgl1rstdisable_cpu1_o, + + dbgen_cpu1_o, + niden_cpu1_o, + spiden_cpu1_o, + spniden_cpu1_o, + + tsvalueb_cpu1_o, + + atclken_cpu1_o, + afvalidm_cpu1_o, + atreadym_cpu1_o, + syncreqm_cpu1_o, + + dftse_cpu1_o, + dftrstdisable_cpu1_o, + dftcrclkdisable_cpu1_o, + dftramhold_cpu1_o, + + nmbistreset_cpu1_o, +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + ncpuporeset_cpu2_o, + ncorereset_cpu2_o, + + cfgend_cpu2_o, + cfgte_cpu2_o, + cp15sdisable_cpu2_o, + vinithi_cpu2_o, + clusteridaff1_cpu2_o, + clusteridaff2_cpu2_o, + cpuid_cpu2_o, + aa64naa32_cpu2_o, + rvbaraddr_cpu2_o, + cryptodisable_cpu2_o, + giccdisable_cpu2_o, + + dbgromaddr_cpu2_o, + dbgromaddrv_cpu2_o, + dbgl1rstdisable_cpu2_o, + + dbgen_cpu2_o, + niden_cpu2_o, + spiden_cpu2_o, + spniden_cpu2_o, + + tsvalueb_cpu2_o, + + atclken_cpu2_o, + afvalidm_cpu2_o, + atreadym_cpu2_o, + syncreqm_cpu2_o, + + dftse_cpu2_o, + dftrstdisable_cpu2_o, + dftcrclkdisable_cpu2_o, + dftramhold_cpu2_o, + + nmbistreset_cpu2_o, +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + ncpuporeset_cpu3_o, + ncorereset_cpu3_o, + + cfgend_cpu3_o, + cfgte_cpu3_o, + cp15sdisable_cpu3_o, + vinithi_cpu3_o, + clusteridaff1_cpu3_o, + clusteridaff2_cpu3_o, + cpuid_cpu3_o, + aa64naa32_cpu3_o, + rvbaraddr_cpu3_o, + cryptodisable_cpu3_o, + giccdisable_cpu3_o, + + dbgromaddr_cpu3_o, + dbgromaddrv_cpu3_o, + dbgl1rstdisable_cpu3_o, + + dbgen_cpu3_o, + niden_cpu3_o, + spiden_cpu3_o, + spniden_cpu3_o, + + tsvalueb_cpu3_o, + + atclken_cpu3_o, + afvalidm_cpu3_o, + atreadym_cpu3_o, + syncreqm_cpu3_o, + + dftse_cpu3_o, + dftrstdisable_cpu3_o, + dftcrclkdisable_cpu3_o, + dftramhold_cpu3_o, + + nmbistreset_cpu3_o, +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Signals from maia_cpu -> maia_cpu_io -> maia +//----------------------------------------------------------------------------- +// Inputs from maia_cpu + ds_cpu0_sev_req, + ds_cpu0_sevl_req, + ds_cpu0_cpuectlr_smp, + + ncommirq_cpu0_i, + commrx_cpu0_i, + commtx_cpu0_i, + dbgack_cpu0_i, + dbgrstreq_cpu0_i, + dbgnopwrdwn_cpu0_i, + + npmuirq_cpu0_i, + pmuevent_cpu0_i, + pm_export_cpu0_i, + + etclken_cpu0_i, + afreadym_cpu0_i, + atbytesm_cpu0_i, + atdatam_cpu0_i, + atidm_cpu0_i, + atvalidm_cpu0_i, + +// BEGIN INCLUDE FOR CPU1 + ds_cpu1_sev_req, + ds_cpu1_sevl_req, + ds_cpu1_cpuectlr_smp, + + ncommirq_cpu1_i, + commrx_cpu1_i, + commtx_cpu1_i, + dbgack_cpu1_i, + dbgrstreq_cpu1_i, + dbgnopwrdwn_cpu1_i, + + npmuirq_cpu1_i, + pmuevent_cpu1_i, + pm_export_cpu1_i, + + etclken_cpu1_i, + afreadym_cpu1_i, + atbytesm_cpu1_i, + atdatam_cpu1_i, + atidm_cpu1_i, + atvalidm_cpu1_i, +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + ds_cpu2_sev_req, + ds_cpu2_sevl_req, + ds_cpu2_cpuectlr_smp, + + ncommirq_cpu2_i, + commrx_cpu2_i, + commtx_cpu2_i, + dbgack_cpu2_i, + dbgrstreq_cpu2_i, + dbgnopwrdwn_cpu2_i, + + npmuirq_cpu2_i, + pmuevent_cpu2_i, + pm_export_cpu2_i, + + etclken_cpu2_i, + afreadym_cpu2_i, + atbytesm_cpu2_i, + atdatam_cpu2_i, + atidm_cpu2_i, + atvalidm_cpu2_i, +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + ds_cpu3_sev_req, + ds_cpu3_sevl_req, + ds_cpu3_cpuectlr_smp, + + ncommirq_cpu3_i, + commrx_cpu3_i, + commtx_cpu3_i, + dbgack_cpu3_i, + dbgrstreq_cpu3_i, + dbgnopwrdwn_cpu3_i, + + npmuirq_cpu3_i, + pmuevent_cpu3_i, + pm_export_cpu3_i, + + etclken_cpu3_i, + afreadym_cpu3_i, + atbytesm_cpu3_i, + atdatam_cpu3_i, + atidm_cpu3_i, + atvalidm_cpu3_i, +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// L2 interface +//----------------------------------------------------------------------------- + l2_cpu0_mbist1_addr_b1, + l2_cpu0_mbist1_array_b1, + l2_cpu0_mbist1_be_b1, + l2_cpu0_mbist1_en_b1, + l2_cpu0_mbist1_rd_en_b1, + l2_cpu0_mbist1_wr_en_b1, + l2_cpu0_mbist1_all_b1, +// BEGIN INCLUDE FOR CPU1 + l2_cpu1_mbist1_addr_b1, + l2_cpu1_mbist1_array_b1, + l2_cpu1_mbist1_be_b1, + l2_cpu1_mbist1_en_b1, + l2_cpu1_mbist1_rd_en_b1, + l2_cpu1_mbist1_wr_en_b1, + l2_cpu1_mbist1_all_b1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + l2_cpu2_mbist1_addr_b1, + l2_cpu2_mbist1_array_b1, + l2_cpu2_mbist1_be_b1, + l2_cpu2_mbist1_en_b1, + l2_cpu2_mbist1_rd_en_b1, + l2_cpu2_mbist1_wr_en_b1, + l2_cpu2_mbist1_all_b1, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + l2_cpu3_mbist1_addr_b1, + l2_cpu3_mbist1_array_b1, + l2_cpu3_mbist1_be_b1, + l2_cpu3_mbist1_en_b1, + l2_cpu3_mbist1_rd_en_b1, + l2_cpu3_mbist1_wr_en_b1, + l2_cpu3_mbist1_all_b1, +// END INCLUDE FOR CPU3 + +// BEGIN L2-CPU interface + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + l2_cpu0_cfg_ecc_en, + l2_cpu0_arb_thrshld_timeout_en, + l2_cpu0_disable_clean_evict_opt, + l2_cpu0_dext_err_r2, + l2_cpu0_dext_err_type_r2, + l2_cpu0_dsngl_ecc_err_r3, + l2_cpu0_ddbl_ecc_err_r3, + l2_cpu0_ddata_r2, + l2_cpu0_barrier_done, + l2_cpu0_spec_valid, + l2_cpu0_spec_bufid, + l2_cpu0_rvalid, + l2_cpu0_rstate, + l2_cpu0_rexfail, + l2_cpu0_rbufid, + l2_cpu0_dvalid_r1, + l2_cpu0_dlast_r1, + l2_cpu0_dbufid_r1, + l2_cpu0_iext_err_r2, + l2_cpu0_iext_err_type_r2, + l2_cpu0_isngl_ecc_err_r3, + l2_cpu0_idbl_ecc_err_r3, + l2_cpu0_idata_r2, + l2_cpu0_ivalid_r1, + l2_cpu0_ibufid_r1, + l2_cpu0_ls_sync_req, + l2_cpu0_ccb_req_addr_c3, + l2_cpu0_ccb_dbg_req_c3, + l2_cpu0_ls_ccb_clken_c3, + l2_cpu0_ls_ccb_req_c3, + l2_cpu0_ccb_req_id_c3, + l2_cpu0_ccb_req_type_c3, + l2_cpu0_ccb_req_info_c3, + l2_cpu0_if_ccb_clken_c3, + l2_cpu0_if_ccb_req_c3, + l2_cpu0_if_sync_req, + l2_cpu0_tlb_ccb_clken_c3, + l2_cpu0_tlb_ccb_req_c3, + l2_cpu0_tlb_sync_req, + l2_cpu0_tlb_sync_complete, + l2_cpu0_tbw_desc_vld, + l2_cpu0_tbw_ext_err, + l2_cpu0_tbw_ext_err_type, + l2_cpu0_tbw_dbl_ecc_err, + l2_cpu0_tbw_desc_data, + l2_cpu0_spr_rd_data, + l2_cpu0_l2_cache_size, + l2_cpu0_pf_throttle_q, + + l2_cpu0_wr_ex_resp, + l2_cpu0_wr_ex_fail, + + l2_cpu0_ic_base, + l2_cpu0_no_intctrl, + + + l2_cpu0_pmu_events, + + ds_cpu0_l2_spr_en, + ds_cpu0_l2_spr_rd, + ds_cpu0_l2_spr_wr, + ds_cpu0_l2_spr_addr, + ds_cpu0_l2_spr_dw, + ds_cpu0_l2_spr_wr_data, + + l2_cpu0_wr_data_vld_x1_q, + l2_cpu0_wr_evict_x1_q, + l2_cpu0_wr_data, + l2_cpu0_ls_rd_haz_vld_arb_q, + l2_cpu0_ls_wr_haz_vld_arb_q, + l2_cpu0_dt_pmu_evt_en, + + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + l2_cpu1_cfg_ecc_en, + l2_cpu1_arb_thrshld_timeout_en, + l2_cpu1_disable_clean_evict_opt, + l2_cpu1_dext_err_r2, + l2_cpu1_dext_err_type_r2, + l2_cpu1_dsngl_ecc_err_r3, + l2_cpu1_ddbl_ecc_err_r3, + l2_cpu1_ddata_r2, + l2_cpu1_barrier_done, + l2_cpu1_spec_valid, + l2_cpu1_spec_bufid, + l2_cpu1_rvalid, + l2_cpu1_rstate, + l2_cpu1_rexfail, + l2_cpu1_rbufid, + l2_cpu1_dvalid_r1, + l2_cpu1_dlast_r1, + l2_cpu1_dbufid_r1, + l2_cpu1_iext_err_r2, + l2_cpu1_iext_err_type_r2, + l2_cpu1_isngl_ecc_err_r3, + l2_cpu1_idbl_ecc_err_r3, + l2_cpu1_idata_r2, + l2_cpu1_ivalid_r1, + l2_cpu1_ibufid_r1, + l2_cpu1_ls_sync_req, + l2_cpu1_ccb_req_addr_c3, + l2_cpu1_ccb_dbg_req_c3, + l2_cpu1_ls_ccb_clken_c3, + l2_cpu1_ls_ccb_req_c3, + l2_cpu1_ccb_req_id_c3, + l2_cpu1_ccb_req_type_c3, + l2_cpu1_ccb_req_info_c3, + l2_cpu1_if_ccb_clken_c3, + l2_cpu1_if_ccb_req_c3, + l2_cpu1_if_sync_req, + l2_cpu1_tlb_ccb_clken_c3, + l2_cpu1_tlb_ccb_req_c3, + l2_cpu1_tlb_sync_req, + l2_cpu1_tlb_sync_complete, + l2_cpu1_tbw_desc_vld, + l2_cpu1_tbw_ext_err, + l2_cpu1_tbw_ext_err_type, + l2_cpu1_tbw_dbl_ecc_err, + l2_cpu1_tbw_desc_data, + l2_cpu1_spr_rd_data, + l2_cpu1_l2_cache_size, + l2_cpu1_pf_throttle_q, + + l2_cpu1_wr_ex_resp, + l2_cpu1_wr_ex_fail, + + l2_cpu1_ic_base, + l2_cpu1_no_intctrl, + + l2_cpu1_pmu_events, + + ds_cpu1_l2_spr_en, + ds_cpu1_l2_spr_rd, + ds_cpu1_l2_spr_wr, + ds_cpu1_l2_spr_addr, + ds_cpu1_l2_spr_dw, + ds_cpu1_l2_spr_wr_data, + + l2_cpu1_wr_data_vld_x1_q, + l2_cpu1_wr_evict_x1_q, + l2_cpu1_wr_data, + l2_cpu1_ls_rd_haz_vld_arb_q, + l2_cpu1_ls_wr_haz_vld_arb_q, + l2_cpu1_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + l2_cpu2_cfg_ecc_en, + l2_cpu2_arb_thrshld_timeout_en, + l2_cpu2_disable_clean_evict_opt, + l2_cpu2_dext_err_r2, + l2_cpu2_dext_err_type_r2, + l2_cpu2_dsngl_ecc_err_r3, + l2_cpu2_ddbl_ecc_err_r3, + l2_cpu2_ddata_r2, + l2_cpu2_barrier_done, + l2_cpu2_spec_valid, + l2_cpu2_spec_bufid, + l2_cpu2_rvalid, + l2_cpu2_rstate, + l2_cpu2_rexfail, + l2_cpu2_rbufid, + l2_cpu2_dvalid_r1, + l2_cpu2_dlast_r1, + l2_cpu2_dbufid_r1, + l2_cpu2_iext_err_r2, + l2_cpu2_iext_err_type_r2, + l2_cpu2_isngl_ecc_err_r3, + l2_cpu2_idbl_ecc_err_r3, + l2_cpu2_idata_r2, + l2_cpu2_ivalid_r1, + l2_cpu2_ibufid_r1, + l2_cpu2_ls_sync_req, + l2_cpu2_ccb_req_addr_c3, + l2_cpu2_ccb_dbg_req_c3, + l2_cpu2_ls_ccb_clken_c3, + l2_cpu2_ls_ccb_req_c3, + l2_cpu2_ccb_req_id_c3, + l2_cpu2_ccb_req_type_c3, + l2_cpu2_ccb_req_info_c3, + l2_cpu2_if_ccb_clken_c3, + l2_cpu2_if_ccb_req_c3, + l2_cpu2_if_sync_req, + l2_cpu2_tlb_ccb_clken_c3, + l2_cpu2_tlb_ccb_req_c3, + l2_cpu2_tlb_sync_req, + l2_cpu2_tlb_sync_complete, + l2_cpu2_tbw_desc_vld, + l2_cpu2_tbw_ext_err, + l2_cpu2_tbw_ext_err_type, + l2_cpu2_tbw_dbl_ecc_err, + l2_cpu2_tbw_desc_data, + l2_cpu2_spr_rd_data, + l2_cpu2_l2_cache_size, + l2_cpu2_pf_throttle_q, + + l2_cpu2_wr_ex_resp, + l2_cpu2_wr_ex_fail, + + l2_cpu2_ic_base, + l2_cpu2_no_intctrl, + + l2_cpu2_pmu_events, + + ds_cpu2_l2_spr_en, + ds_cpu2_l2_spr_rd, + ds_cpu2_l2_spr_wr, + ds_cpu2_l2_spr_addr, + ds_cpu2_l2_spr_dw, + ds_cpu2_l2_spr_wr_data, + + l2_cpu2_wr_data_vld_x1_q, + l2_cpu2_wr_evict_x1_q, + l2_cpu2_wr_data, + l2_cpu2_ls_rd_haz_vld_arb_q, + l2_cpu2_ls_wr_haz_vld_arb_q, + l2_cpu2_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + l2_cpu3_cfg_ecc_en, + l2_cpu3_arb_thrshld_timeout_en, + l2_cpu3_disable_clean_evict_opt, + l2_cpu3_dext_err_r2, + l2_cpu3_dext_err_type_r2, + l2_cpu3_dsngl_ecc_err_r3, + l2_cpu3_ddbl_ecc_err_r3, + l2_cpu3_ddata_r2, + l2_cpu3_barrier_done, + l2_cpu3_spec_valid, + l2_cpu3_spec_bufid, + l2_cpu3_rvalid, + l2_cpu3_rstate, + l2_cpu3_rexfail, + l2_cpu3_rbufid, + l2_cpu3_dvalid_r1, + l2_cpu3_dlast_r1, + l2_cpu3_dbufid_r1, + l2_cpu3_iext_err_r2, + l2_cpu3_iext_err_type_r2, + l2_cpu3_isngl_ecc_err_r3, + l2_cpu3_idbl_ecc_err_r3, + l2_cpu3_idata_r2, + l2_cpu3_ivalid_r1, + l2_cpu3_ibufid_r1, + l2_cpu3_ls_sync_req, + l2_cpu3_ccb_req_addr_c3, + l2_cpu3_ccb_dbg_req_c3, + l2_cpu3_ls_ccb_clken_c3, + l2_cpu3_ls_ccb_req_c3, + l2_cpu3_ccb_req_id_c3, + l2_cpu3_ccb_req_type_c3, + l2_cpu3_ccb_req_info_c3, + l2_cpu3_if_ccb_clken_c3, + l2_cpu3_if_ccb_req_c3, + l2_cpu3_if_sync_req, + l2_cpu3_tlb_ccb_clken_c3, + l2_cpu3_tlb_ccb_req_c3, + l2_cpu3_tlb_sync_req, + l2_cpu3_tlb_sync_complete, + l2_cpu3_tbw_desc_vld, + l2_cpu3_tbw_ext_err, + l2_cpu3_tbw_ext_err_type, + l2_cpu3_tbw_dbl_ecc_err, + l2_cpu3_tbw_desc_data, + l2_cpu3_spr_rd_data, + l2_cpu3_l2_cache_size, + l2_cpu3_pf_throttle_q, + + l2_cpu3_wr_ex_resp, + l2_cpu3_wr_ex_fail, + + l2_cpu3_ic_base, + l2_cpu3_no_intctrl, + + l2_cpu3_pmu_events, + + ds_cpu3_l2_spr_en, + ds_cpu3_l2_spr_rd, + ds_cpu3_l2_spr_wr, + ds_cpu3_l2_spr_addr, + ds_cpu3_l2_spr_dw, + ds_cpu3_l2_spr_wr_data, + + l2_cpu3_wr_data_vld_x1_q, + l2_cpu3_wr_evict_x1_q, + l2_cpu3_wr_data, + l2_cpu3_ls_rd_haz_vld_arb_q, + l2_cpu3_ls_wr_haz_vld_arb_q, + l2_cpu3_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// tag_pipe / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_flsh_ls_rd_l2_dly, + l2_cpu0_flsh_ls_wr_l2_dly, + + l2_cpu0_wr_data_stall, + + l2_cpu1_flsh_ls_rd_l2_dly, + l2_cpu1_flsh_ls_wr_l2_dly, + + l2_cpu1_wr_data_stall, + + l2_cpu2_flsh_ls_rd_l2_dly, + l2_cpu2_flsh_ls_wr_l2_dly, + + l2_cpu2_wr_data_stall, + + l2_cpu3_flsh_ls_rd_l2_dly, + l2_cpu3_flsh_ls_wr_l2_dly, + + l2_cpu3_wr_data_stall, + + l2_cpu0_flsh_ls_rd_id_l2_dly, + l2_cpu0_flsh_ls_wr_id_l2_dly, + + l2_cpu1_flsh_ls_rd_id_l2_dly, + l2_cpu1_flsh_ls_wr_id_l2_dly, + + l2_cpu2_flsh_ls_rd_id_l2_dly, + l2_cpu2_flsh_ls_wr_id_l2_dly, + + l2_cpu3_flsh_ls_rd_id_l2_dly, + l2_cpu3_flsh_ls_wr_id_l2_dly, + + l2_cpu0_flsh_ls_rd_l4_dly, + l2_cpu0_flsh_if_rd_l4_dly, + l2_cpu0_flsh_tw_rd_l4_dly, + l2_cpu0_flsh_ls_wr_l4_dly, + + l2_cpu1_flsh_ls_rd_l4_dly, + l2_cpu1_flsh_if_rd_l4_dly, + l2_cpu1_flsh_tw_rd_l4_dly, + l2_cpu1_flsh_ls_wr_l4_dly, + + l2_cpu2_flsh_ls_rd_l4_dly, + l2_cpu2_flsh_if_rd_l4_dly, + l2_cpu2_flsh_tw_rd_l4_dly, + l2_cpu2_flsh_ls_wr_l4_dly, + + l2_cpu3_flsh_ls_rd_l4_dly, + l2_cpu3_flsh_if_rd_l4_dly, + l2_cpu3_flsh_tw_rd_l4_dly, + l2_cpu3_flsh_ls_wr_l4_dly, + + l2_cpu0_flsh_ls_rd_id_l4_dly, + l2_cpu0_flsh_if_rd_id_l4_dly, + l2_cpu0_flsh_ls_wr_id_l4_dly, + l2_cpu0_flsh_ls_wr_evict_l4_dly, + + l2_cpu1_flsh_ls_rd_id_l4_dly, + l2_cpu1_flsh_if_rd_id_l4_dly, + l2_cpu1_flsh_ls_wr_id_l4_dly, + l2_cpu1_flsh_ls_wr_evict_l4_dly, + + l2_cpu2_flsh_ls_rd_id_l4_dly, + l2_cpu2_flsh_if_rd_id_l4_dly, + l2_cpu2_flsh_ls_wr_id_l4_dly, + l2_cpu2_flsh_ls_wr_evict_l4_dly, + + l2_cpu3_flsh_ls_rd_id_l4_dly, + l2_cpu3_flsh_if_rd_id_l4_dly, + l2_cpu3_flsh_ls_wr_id_l4_dly, + l2_cpu3_flsh_ls_wr_evict_l4_dly, + + l2_cpu0_lrq_haz_pending, + l2_cpu1_lrq_haz_pending, + l2_cpu2_lrq_haz_pending, + l2_cpu3_lrq_haz_pending, + + l2_cpu0_ifq_haz_pending, + l2_cpu1_ifq_haz_pending, + l2_cpu2_ifq_haz_pending, + l2_cpu3_ifq_haz_pending, + + l2_cpu0_trq_haz_pending, + l2_cpu1_trq_haz_pending, + l2_cpu2_trq_haz_pending, + l2_cpu3_trq_haz_pending, + + l2_cpu0_wrq_haz_pending, + l2_cpu1_wrq_haz_pending, + l2_cpu2_wrq_haz_pending, + l2_cpu3_wrq_haz_pending, + + l2_cpu0_idle_block_reqs_q, + l2_cpu1_idle_block_reqs_q, + l2_cpu2_idle_block_reqs_q, + l2_cpu3_idle_block_reqs_q, + + l2_cpu0_ls_peq_coll_l4_dly, + l2_cpu1_ls_peq_coll_l4_dly, + l2_cpu2_ls_peq_coll_l4_dly, + l2_cpu3_ls_peq_coll_l4_dly, + +//----------------------------------------------------------------------------- +// tag_pipe +//----------------------------------------------------------------------------- + l2_tbnk0_cpu0_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu1_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu2_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu3_lrq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu1_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu2_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu3_lrq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu1_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu2_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu3_ifq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu1_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu2_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu3_ifq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_trq_clr_l4_dly2_q, + l2_tbnk0_cpu1_trq_clr_l4_dly2_q, + l2_tbnk0_cpu2_trq_clr_l4_dly2_q, + l2_tbnk0_cpu3_trq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_trq_clr_l4_dly2_q, + l2_tbnk1_cpu1_trq_clr_l4_dly2_q, + l2_tbnk1_cpu2_trq_clr_l4_dly2_q, + l2_tbnk1_cpu3_trq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu1_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu2_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu3_wrq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu1_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu2_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu3_wrq_clr_l4_dly2_q, + + +//----------------------------------------------------------------------------- +// cpu_logic / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly, + + +//----------------------------------------------------------------------------- +// feq / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_dsq_rd_data_q, + l2_cpu0_dsq_rd_byte_strb_q, + l2_cpu1_dsq_rd_data_q, + l2_cpu1_dsq_rd_byte_strb_q, + l2_cpu2_dsq_rd_data_q, + l2_cpu2_dsq_rd_byte_strb_q, + l2_cpu3_dsq_rd_data_q, + l2_cpu3_dsq_rd_byte_strb_q, + + l2_cpu0_dsq_clr_vld_q, + l2_cpu0_dsq_clr_id_q, + l2_cpu0_dsq_rd_en, + l2_cpu0_dsq_rd_en_x2, + l2_cpu0_dsq_rd_buf_id, + l2_cpu1_dsq_clr_vld_q, + l2_cpu1_dsq_clr_id_q, + l2_cpu1_dsq_rd_en, + l2_cpu1_dsq_rd_en_x2, + l2_cpu1_dsq_rd_buf_id, + l2_cpu2_dsq_clr_vld_q, + l2_cpu2_dsq_clr_id_q, + l2_cpu2_dsq_rd_en, + l2_cpu2_dsq_rd_en_x2, + l2_cpu2_dsq_rd_buf_id, + l2_cpu3_dsq_clr_vld_q, + l2_cpu3_dsq_rd_en, + l2_cpu3_dsq_rd_en_x2, + l2_cpu3_dsq_clr_id_q, + l2_cpu3_dsq_rd_buf_id, + +//----------------------------------------------------------------------------- +// arbitration +//----------------------------------------------------------------------------- + l2_cpu0_rd_vld_skid, + l2_cpu1_rd_vld_skid, + l2_cpu2_rd_vld_skid, + l2_cpu3_rd_vld_skid, + + l2_cpu0_pf_rd_vld_skid_popped, + l2_cpu1_pf_rd_vld_skid_popped, + l2_cpu2_pf_rd_vld_skid_popped, + l2_cpu3_pf_rd_vld_skid_popped, + + l2_cpu0_rd_arb, + l2_cpu1_rd_arb, + l2_cpu2_rd_arb, + l2_cpu3_rd_arb, + + l2_cpu0_wr_vld_skid, + l2_cpu1_wr_vld_skid, + l2_cpu2_wr_vld_skid, + l2_cpu3_wr_vld_skid, + + l2_cpu0_wr_arb, + l2_cpu1_wr_arb, + l2_cpu2_wr_arb, + l2_cpu3_wr_arb, + + l2_cpu0_ic_vld_skid, + l2_cpu1_ic_vld_skid, + l2_cpu2_ic_vld_skid, + l2_cpu3_ic_vld_skid, + + l2_cpu0_ic_barrier_stall_q, + l2_cpu1_ic_barrier_stall_q, + l2_cpu2_ic_barrier_stall_q, + l2_cpu3_ic_barrier_stall_q, + + l2_cpu0_blk_non_evict_wr, + l2_cpu1_blk_non_evict_wr, + l2_cpu2_blk_non_evict_wr, + l2_cpu3_blk_non_evict_wr, + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + l2_cpu0_idle_wakeup_q, + l2_cpu0_rd_arb_fast, + l2_cpu0_rd_id_arb_set, + l2_cpu0_rd_lrq_id_arb_set, + l2_cpu0_rd_type_arb_set, + l2_cpu0_rd_cache_attr_arb_set, + l2_cpu0_rd_page_attr_arb_set, + l2_cpu0_rd_elem_size_arb_set, + l2_cpu0_rd_way_arb_set, + l2_cpu0_rd_replayed_arb_set, + l2_cpu0_rd_excl_arb_set, + l2_cpu0_rd_priv_arb_set, + l2_cpu0_rd_shared_arb_set, + l2_cpu0_rd_va48_arb_set, + l2_cpu0_rd_aarch64_arb_set, + l2_cpu0_rd_asid_arb_set, + l2_cpu0_rd_prfm_arb_set, + l2_cpu0_rd_addr_arb_set, + l2_cpu0_rd_bypass_arb_set, + l2_cpu0_rd_bypass_req_can_e5, + l2_cpu0_early_rd_reqe4_e5_q, + l2_cpu0_rd_bypass_way_e5, + l2_cpu0_rd_bypass_bufid_e5, + l2_cpu0_rd_bypass_lrq_id_e5, + + l2_cpu0_wr_arb_fast, + l2_cpu0_wr_id_arb_set, + l2_cpu0_wr_partial_dw_arb_set, + l2_cpu0_wr_cache_attr_arb_set, + l2_cpu0_wr_page_attr_arb_set, + l2_cpu0_wr_elem_size_arb_set, + l2_cpu0_wr_type_arb_set, + l2_cpu0_wr_cl_id_arb_set, + l2_cpu0_wr_priv_arb_set, + l2_cpu0_wr_shared_arb_set, + l2_cpu0_wr_last_arb_set, + l2_cpu0_wr_clean_evict_arb_set, + l2_cpu0_wr_err_arb_set, + l2_cpu0_wr_way_arb_set, + l2_cpu0_wr_dirty_arb_set, + l2_cpu0_wr_1st_replayed_arb_set, + l2_cpu0_wr_addr_arb_set, + l2_cpu0_ic_arb_fast, + l2_cpu0_ic_id_arb_set, + l2_cpu0_ic_write_arb_set, + l2_cpu0_ic_excl_arb_set, + l2_cpu0_ic_elem_size_arb_set, + l2_cpu0_ic_ns_arb_set, + l2_cpu0_ic_addr_arb_set, + l2_cpu0_ic_data_arb_set, + + l2_cpu0_wrq_almost_full, + + l2_cpu0_ls_wr_req_w2a, + l2_cpu0_ls_wr_last_w2a, + l2_cpu0_ls_wr_dirty_w2a, + l2_cpu0_ls_wr_err_w2a, + l2_cpu0_ls_wr_type_w2a, + l2_cpu0_ls_wr_ccb_id_w2a, + l2_cpu0_ls_wr_data_w2a, + + l2_cpu0_ls_ccb_resp, + l2_cpu0_ls_ccb_resp_id, + l2_cpu0_ls_ccb_data_wr, + + l2_cpu0_if_ccb_resp, + l2_cpu0_if_ccb_resp_id, + + l2_cpu0_tw_ccb_resp, + l2_cpu0_tw_ccb_resp_id, + + l2_cpu0_if_sync_done_q, + l2_cpu0_tlb_sync_done_q, + + l2_cpu0_lrq_haz_clr_id_dcd_q, + l2_cpu0_wrq_haz_clr_id_dcd_q, + l2_cpu0_ls_rd_haz_id_arb_q, + l2_cpu0_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + l2_cpu1_idle_wakeup_q, + l2_cpu1_rd_arb_fast, + l2_cpu1_rd_id_arb_set, + l2_cpu1_rd_lrq_id_arb_set, + l2_cpu1_rd_type_arb_set, + l2_cpu1_rd_cache_attr_arb_set, + l2_cpu1_rd_page_attr_arb_set, + l2_cpu1_rd_elem_size_arb_set, + l2_cpu1_rd_way_arb_set, + l2_cpu1_rd_replayed_arb_set, + l2_cpu1_rd_excl_arb_set, + l2_cpu1_rd_priv_arb_set, + l2_cpu1_rd_shared_arb_set, + l2_cpu1_rd_va48_arb_set, + l2_cpu1_rd_aarch64_arb_set, + l2_cpu1_rd_asid_arb_set, + l2_cpu1_rd_prfm_arb_set, + l2_cpu1_rd_addr_arb_set, + l2_cpu1_rd_bypass_arb_set, + l2_cpu1_rd_bypass_req_can_e5, + l2_cpu1_early_rd_reqe4_e5_q, + l2_cpu1_rd_bypass_way_e5, + l2_cpu1_rd_bypass_bufid_e5, + l2_cpu1_rd_bypass_lrq_id_e5, + + l2_cpu1_wr_arb_fast, + l2_cpu1_wr_id_arb_set, + l2_cpu1_wr_partial_dw_arb_set, + l2_cpu1_wr_cache_attr_arb_set, + l2_cpu1_wr_page_attr_arb_set, + l2_cpu1_wr_elem_size_arb_set, + l2_cpu1_wr_type_arb_set, + l2_cpu1_wr_cl_id_arb_set, + l2_cpu1_wr_priv_arb_set, + l2_cpu1_wr_shared_arb_set, + l2_cpu1_wr_last_arb_set, + l2_cpu1_wr_clean_evict_arb_set, + l2_cpu1_wr_err_arb_set, + l2_cpu1_wr_way_arb_set, + l2_cpu1_wr_dirty_arb_set, + l2_cpu1_wr_1st_replayed_arb_set, + l2_cpu1_wr_addr_arb_set, + l2_cpu1_ic_arb_fast, + l2_cpu1_ic_id_arb_set, + l2_cpu1_ic_write_arb_set, + l2_cpu1_ic_excl_arb_set, + l2_cpu1_ic_elem_size_arb_set, + l2_cpu1_ic_ns_arb_set, + l2_cpu1_ic_addr_arb_set, + l2_cpu1_ic_data_arb_set, + + l2_cpu1_wrq_almost_full, + + l2_cpu1_ls_wr_req_w2a, + l2_cpu1_ls_wr_last_w2a, + l2_cpu1_ls_wr_dirty_w2a, + l2_cpu1_ls_wr_err_w2a, + l2_cpu1_ls_wr_type_w2a, + l2_cpu1_ls_wr_ccb_id_w2a, + l2_cpu1_ls_wr_data_w2a, + + l2_cpu1_ls_ccb_resp, + l2_cpu1_ls_ccb_resp_id, + l2_cpu1_ls_ccb_data_wr, + + l2_cpu1_if_ccb_resp, + l2_cpu1_if_ccb_resp_id, + + l2_cpu1_tw_ccb_resp, + l2_cpu1_tw_ccb_resp_id, + + l2_cpu1_if_sync_done_q, + l2_cpu1_tlb_sync_done_q, + + l2_cpu1_lrq_haz_clr_id_dcd_q, + l2_cpu1_wrq_haz_clr_id_dcd_q, + l2_cpu1_ls_rd_haz_id_arb_q, + l2_cpu1_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + l2_cpu2_idle_wakeup_q, + l2_cpu2_rd_arb_fast, + l2_cpu2_rd_id_arb_set, + l2_cpu2_rd_lrq_id_arb_set, + l2_cpu2_rd_type_arb_set, + l2_cpu2_rd_cache_attr_arb_set, + l2_cpu2_rd_page_attr_arb_set, + l2_cpu2_rd_elem_size_arb_set, + l2_cpu2_rd_way_arb_set, + l2_cpu2_rd_replayed_arb_set, + l2_cpu2_rd_excl_arb_set, + l2_cpu2_rd_priv_arb_set, + l2_cpu2_rd_shared_arb_set, + l2_cpu2_rd_va48_arb_set, + l2_cpu2_rd_aarch64_arb_set, + l2_cpu2_rd_asid_arb_set, + l2_cpu2_rd_prfm_arb_set, + l2_cpu2_rd_addr_arb_set, + l2_cpu2_rd_bypass_arb_set, + l2_cpu2_rd_bypass_req_can_e5, + l2_cpu2_early_rd_reqe4_e5_q, + l2_cpu2_rd_bypass_way_e5, + l2_cpu2_rd_bypass_bufid_e5, + l2_cpu2_rd_bypass_lrq_id_e5, + + l2_cpu2_wr_arb_fast, + l2_cpu2_wr_id_arb_set, + l2_cpu2_wr_partial_dw_arb_set, + l2_cpu2_wr_cache_attr_arb_set, + l2_cpu2_wr_page_attr_arb_set, + l2_cpu2_wr_elem_size_arb_set, + l2_cpu2_wr_type_arb_set, + l2_cpu2_wr_cl_id_arb_set, + l2_cpu2_wr_priv_arb_set, + l2_cpu2_wr_shared_arb_set, + l2_cpu2_wr_last_arb_set, + l2_cpu2_wr_clean_evict_arb_set, + l2_cpu2_wr_err_arb_set, + l2_cpu2_wr_way_arb_set, + l2_cpu2_wr_dirty_arb_set, + l2_cpu2_wr_1st_replayed_arb_set, + l2_cpu2_wr_addr_arb_set, + l2_cpu2_ic_arb_fast, + l2_cpu2_ic_id_arb_set, + l2_cpu2_ic_write_arb_set, + l2_cpu2_ic_excl_arb_set, + l2_cpu2_ic_elem_size_arb_set, + l2_cpu2_ic_ns_arb_set, + l2_cpu2_ic_addr_arb_set, + l2_cpu2_ic_data_arb_set, + + l2_cpu2_wrq_almost_full, + + l2_cpu2_ls_wr_req_w2a, + l2_cpu2_ls_wr_last_w2a, + l2_cpu2_ls_wr_dirty_w2a, + l2_cpu2_ls_wr_err_w2a, + l2_cpu2_ls_wr_type_w2a, + l2_cpu2_ls_wr_ccb_id_w2a, + l2_cpu2_ls_wr_data_w2a, + + l2_cpu2_ls_ccb_resp, + l2_cpu2_ls_ccb_resp_id, + l2_cpu2_ls_ccb_data_wr, + + l2_cpu2_if_ccb_resp, + l2_cpu2_if_ccb_resp_id, + + l2_cpu2_tw_ccb_resp, + l2_cpu2_tw_ccb_resp_id, + + l2_cpu2_if_sync_done_q, + l2_cpu2_tlb_sync_done_q, + + l2_cpu2_lrq_haz_clr_id_dcd_q, + l2_cpu2_wrq_haz_clr_id_dcd_q, + l2_cpu2_ls_rd_haz_id_arb_q, + l2_cpu2_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + l2_cpu3_idle_wakeup_q, + l2_cpu3_rd_arb_fast, + l2_cpu3_rd_id_arb_set, + l2_cpu3_rd_lrq_id_arb_set, + l2_cpu3_rd_type_arb_set, + l2_cpu3_rd_cache_attr_arb_set, + l2_cpu3_rd_page_attr_arb_set, + l2_cpu3_rd_elem_size_arb_set, + l2_cpu3_rd_way_arb_set, + l2_cpu3_rd_replayed_arb_set, + l2_cpu3_rd_excl_arb_set, + l2_cpu3_rd_priv_arb_set, + l2_cpu3_rd_shared_arb_set, + l2_cpu3_rd_va48_arb_set, + l2_cpu3_rd_aarch64_arb_set, + l2_cpu3_rd_asid_arb_set, + l2_cpu3_rd_prfm_arb_set, + l2_cpu3_rd_addr_arb_set, + l2_cpu3_rd_bypass_arb_set, + l2_cpu3_rd_bypass_req_can_e5, + l2_cpu3_early_rd_reqe4_e5_q, + l2_cpu3_rd_bypass_way_e5, + l2_cpu3_rd_bypass_bufid_e5, + l2_cpu3_rd_bypass_lrq_id_e5, + + l2_cpu3_wr_arb_fast, + l2_cpu3_wr_id_arb_set, + l2_cpu3_wr_partial_dw_arb_set, + l2_cpu3_wr_cache_attr_arb_set, + l2_cpu3_wr_page_attr_arb_set, + l2_cpu3_wr_elem_size_arb_set, + l2_cpu3_wr_type_arb_set, + l2_cpu3_wr_cl_id_arb_set, + l2_cpu3_wr_priv_arb_set, + l2_cpu3_wr_shared_arb_set, + l2_cpu3_wr_last_arb_set, + l2_cpu3_wr_clean_evict_arb_set, + l2_cpu3_wr_err_arb_set, + l2_cpu3_wr_way_arb_set, + l2_cpu3_wr_dirty_arb_set, + l2_cpu3_wr_1st_replayed_arb_set, + l2_cpu3_wr_addr_arb_set, + l2_cpu3_ic_arb_fast, + l2_cpu3_ic_id_arb_set, + l2_cpu3_ic_write_arb_set, + l2_cpu3_ic_excl_arb_set, + l2_cpu3_ic_elem_size_arb_set, + l2_cpu3_ic_ns_arb_set, + l2_cpu3_ic_addr_arb_set, + l2_cpu3_ic_data_arb_set, + + l2_cpu3_wrq_almost_full, + + l2_cpu3_ls_wr_req_w2a, + l2_cpu3_ls_wr_last_w2a, + l2_cpu3_ls_wr_dirty_w2a, + l2_cpu3_ls_wr_err_w2a, + l2_cpu3_ls_wr_type_w2a, + l2_cpu3_ls_wr_ccb_id_w2a, + l2_cpu3_ls_wr_data_w2a, + + l2_cpu3_ls_ccb_resp, + l2_cpu3_ls_ccb_resp_id, + l2_cpu3_ls_ccb_data_wr, + + l2_cpu3_if_ccb_resp, + l2_cpu3_if_ccb_resp_id, + + l2_cpu3_tw_ccb_resp, + l2_cpu3_tw_ccb_resp_id, + + l2_cpu3_if_sync_done_q, + l2_cpu3_tlb_sync_done_q, + + l2_cpu3_lrq_haz_clr_id_dcd_q, + l2_cpu3_wrq_haz_clr_id_dcd_q, + l2_cpu3_ls_rd_haz_id_arb_q, + l2_cpu3_ls_wr_haz_id_arb_q, + +// END L2-CPU interface + +//------------------------------------------------------------------- +// TM interface +//------------------------------------------------------------------- +// BEGIN TIMER-CPU interface + tm_cpu0_cntkctl_usr, + tm_cpu0_cnthctl_kernel, + + tm_cpu1_cntkctl_usr, + tm_cpu1_cnthctl_kernel, + + tm_cpu2_cntkctl_usr, + tm_cpu2_cnthctl_kernel, + + tm_cpu3_cntkctl_usr, + tm_cpu3_cnthctl_kernel, +// END TIMER-CPU interface + +//----------------------------------------------------------------------------- +// IC interface +//----------------------------------------------------------------------------- + ls_cpu0_imp_abort_slv, + ls_cpu0_imp_abort_ecc, + ls_cpu0_imp_abort_dec, + ls_cpu0_imp_abort_containable, + ls_cpu0_raw_eae_nonsec, + ls_cpu0_raw_eae_secure, + + ds_cpu0_ic_cpsr_mode, + ds_cpu0_ic_sample_spr, + ds_cpu0_ic_aa64naa32, + ds_cpu0_ic_hcr_change, + ds_cpu0_ic_scr_change, +// BEGIN INCLUDE FOR CPU1 + ds_cpu1_ic_cpsr_mode, + ds_cpu1_ic_sample_spr, + ds_cpu1_ic_aa64naa32, + ds_cpu1_ic_hcr_change, + ds_cpu1_ic_scr_change, + ls_cpu1_imp_abort_slv, + ls_cpu1_imp_abort_ecc, + ls_cpu1_imp_abort_dec, + ls_cpu1_imp_abort_containable, + ls_cpu1_raw_eae_nonsec, + ls_cpu1_raw_eae_secure, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ds_cpu2_ic_cpsr_mode, + ds_cpu2_ic_sample_spr, + ds_cpu2_ic_aa64naa32, + ds_cpu2_ic_hcr_change, + ds_cpu2_ic_scr_change, + ls_cpu2_imp_abort_slv, + ls_cpu2_imp_abort_ecc, + ls_cpu2_imp_abort_dec, + ls_cpu2_imp_abort_containable, + ls_cpu2_raw_eae_nonsec, + ls_cpu2_raw_eae_secure, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ds_cpu3_ic_cpsr_mode, + ds_cpu3_ic_sample_spr, + ds_cpu3_ic_aa64naa32, + ds_cpu3_ic_hcr_change, + ds_cpu3_ic_scr_change, + ls_cpu3_imp_abort_slv, + ls_cpu3_imp_abort_ecc, + ls_cpu3_imp_abort_dec, + ls_cpu3_imp_abort_containable, + ls_cpu3_raw_eae_nonsec, + ls_cpu3_raw_eae_secure, +// END INCLUDE FOR CPU3 + + ic_nfiq, + ic_nirq, + ic_nsei, + ic_nvfiq, + ic_nvirq, + ic_nvsei, + ic_p_valid, + + ic_sample_spr, + ic_hcr_change_complete, + ic_scr_change_complete, + ic_el_change_complete, + ic_ich_el2_tc, + ic_ich_el2_tall0, + ic_ich_el2_tall1, + ic_sra_el3_en, + ic_sra_el1s_en, + ic_sra_el2_en, + ic_sra_el1ns_en, + ic_sre_el1ns_hyp_trap, + ic_sre_el1ns_mon_trap, + ic_sre_el1s_mon_trap, + ic_sre_el2_mon_trap, + ic_block_eoi_sgi_wr, + +//----------------------------------------------------------------------------- +// DT interface +//----------------------------------------------------------------------------- +// BEGIN DT-CPU interface +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + dt_cpu0_et_oslock_gclk, + dt_cpu0_os_double_lock_gclk, + dt_cpu0_halt_ack_gclk, + dt_cpu0_coredbg_in_reset_gclk, + dt_cpu0_wfx_dbg_req_gclk, + dt_cpu0_hlt_dbgevt_ok_gclk, + dt_cpu0_dbif_ack_gclk, + dt_cpu0_dbif_err_gclk, + dt_cpu0_dbif_rddata_gclk, + + dt_cpu0_dbif_addr_pclk, + dt_cpu0_dbif_locked_pclk, + dt_cpu0_dbif_req_pclk, + dt_cpu0_dbif_wrdata_pclk, + dt_cpu0_dbif_write_pclk, + dt_cpu0_edecr_osuce_pclk, + dt_cpu0_edecr_rce_pclk, + dt_cpu0_edecr_ss_pclk, + dt_cpu0_edbgrq_pclk, + dt_cpu0_edacr_frc_idleack_pclk, + dt_cpu0_edprcr_corepurq_pclk, + + dt_cpu0_pmusnapshot_ack_gclk, + dt_cpu0_pmusnapshot_req_pclk, + + dt_cpu0_cti_trigin_7to4_gclk, + dt_cpu0_cti_trigin_1to0_gclk, + dt_cpu0_cti_trigoutack_7to4_gclk, + dt_cpu0_cti_trigoutack_bit1_gclk, + + dt_cpu0_cti_trigout_7to4_pclk, + dt_cpu0_cti_trigout_1to0_pclk, + dt_cpu0_cti_triginack_7to4_pclk, + dt_cpu0_cti_triginack_1to0_pclk, + + dt_cpu0_wfx_wakeup_pclk, + dt_cpu0_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + dt_cpu1_et_oslock_gclk, + dt_cpu1_os_double_lock_gclk, + dt_cpu1_halt_ack_gclk, + dt_cpu1_coredbg_in_reset_gclk, + dt_cpu1_wfx_dbg_req_gclk, + dt_cpu1_hlt_dbgevt_ok_gclk, + dt_cpu1_dbif_ack_gclk, + dt_cpu1_dbif_err_gclk, + dt_cpu1_dbif_rddata_gclk, + + dt_cpu1_dbif_addr_pclk, + dt_cpu1_dbif_locked_pclk, + dt_cpu1_dbif_req_pclk, + dt_cpu1_dbif_wrdata_pclk, + dt_cpu1_dbif_write_pclk, + dt_cpu1_edecr_osuce_pclk, + dt_cpu1_edecr_rce_pclk, + dt_cpu1_edecr_ss_pclk, + dt_cpu1_edbgrq_pclk, + dt_cpu1_edacr_frc_idleack_pclk, + dt_cpu1_edprcr_corepurq_pclk, + + dt_cpu1_pmusnapshot_ack_gclk, + dt_cpu1_pmusnapshot_req_pclk, + + dt_cpu1_cti_trigin_7to4_gclk, + dt_cpu1_cti_trigin_1to0_gclk, + dt_cpu1_cti_trigoutack_7to4_gclk, + dt_cpu1_cti_trigoutack_bit1_gclk, + + dt_cpu1_cti_trigout_7to4_pclk, + dt_cpu1_cti_trigout_1to0_pclk, + dt_cpu1_cti_triginack_7to4_pclk, + dt_cpu1_cti_triginack_1to0_pclk, + + dt_cpu1_wfx_wakeup_pclk, + dt_cpu1_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + dt_cpu2_et_oslock_gclk, + dt_cpu2_os_double_lock_gclk, + dt_cpu2_halt_ack_gclk, + dt_cpu2_coredbg_in_reset_gclk, + dt_cpu2_wfx_dbg_req_gclk, + dt_cpu2_hlt_dbgevt_ok_gclk, + dt_cpu2_dbif_ack_gclk, + dt_cpu2_dbif_err_gclk, + dt_cpu2_dbif_rddata_gclk, + + dt_cpu2_dbif_addr_pclk, + dt_cpu2_dbif_locked_pclk, + dt_cpu2_dbif_req_pclk, + dt_cpu2_dbif_wrdata_pclk, + dt_cpu2_dbif_write_pclk, + dt_cpu2_edecr_osuce_pclk, + dt_cpu2_edecr_rce_pclk, + dt_cpu2_edecr_ss_pclk, + dt_cpu2_edbgrq_pclk, + dt_cpu2_edacr_frc_idleack_pclk, + dt_cpu2_edprcr_corepurq_pclk, + + dt_cpu2_pmusnapshot_ack_gclk, + dt_cpu2_pmusnapshot_req_pclk, + + dt_cpu2_cti_trigin_7to4_gclk, + dt_cpu2_cti_trigin_1to0_gclk, + dt_cpu2_cti_trigoutack_7to4_gclk, + dt_cpu2_cti_trigoutack_bit1_gclk, + + dt_cpu2_cti_trigout_7to4_pclk, + dt_cpu2_cti_trigout_1to0_pclk, + dt_cpu2_cti_triginack_7to4_pclk, + dt_cpu2_cti_triginack_1to0_pclk, + + dt_cpu2_wfx_wakeup_pclk, + dt_cpu2_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + dt_cpu3_et_oslock_gclk, + dt_cpu3_os_double_lock_gclk, + dt_cpu3_halt_ack_gclk, + dt_cpu3_coredbg_in_reset_gclk, + dt_cpu3_wfx_dbg_req_gclk, + dt_cpu3_hlt_dbgevt_ok_gclk, + dt_cpu3_dbif_ack_gclk, + dt_cpu3_dbif_err_gclk, + dt_cpu3_dbif_rddata_gclk, + + dt_cpu3_dbif_addr_pclk, + dt_cpu3_dbif_locked_pclk, + dt_cpu3_dbif_req_pclk, + dt_cpu3_dbif_wrdata_pclk, + dt_cpu3_dbif_write_pclk, + dt_cpu3_edecr_osuce_pclk, + dt_cpu3_edecr_rce_pclk, + dt_cpu3_edecr_ss_pclk, + dt_cpu3_edbgrq_pclk, + dt_cpu3_edacr_frc_idleack_pclk, + dt_cpu3_edprcr_corepurq_pclk, + + dt_cpu3_pmusnapshot_ack_gclk, + dt_cpu3_pmusnapshot_req_pclk, + + dt_cpu3_cti_trigin_7to4_gclk, + dt_cpu3_cti_trigin_1to0_gclk, + dt_cpu3_cti_trigoutack_7to4_gclk, + dt_cpu3_cti_trigoutack_bit1_gclk, + + dt_cpu3_cti_trigout_7to4_pclk, + dt_cpu3_cti_trigout_1to0_pclk, + dt_cpu3_cti_triginack_7to4_pclk, + dt_cpu3_cti_triginack_1to0_pclk, + + dt_cpu3_wfx_wakeup_pclk, + dt_cpu3_noclkstop_pclk, +// END DT-CPU interface + +//----------------------------------------------------------------------------- +// CK interface +//----------------------------------------------------------------------------- +// BEGIN CK-CPU interface + ds_cpu0_reset_req, + ds_cpu0_wfi_req, + ds_cpu0_wfe_req, + ds_cpu0_flush, + ds_cpu0_flush_type, + ds_cpu0_imp_abrt_wfi_qual, + ds_cpu0_irq_wfi_qual, + ds_cpu0_fiq_wfi_qual, + ds_cpu0_vimp_abrt_wfi_qual, + ds_cpu0_virq_wfi_qual, + ds_cpu0_vfiq_wfi_qual, + ds_cpu0_imp_abrt_wfe_qual, + ds_cpu0_irq_wfe_qual, + ds_cpu0_fiq_wfe_qual, + ds_cpu0_vimp_abrt_wfe_qual, + ds_cpu0_virq_wfe_qual, + ds_cpu0_vfiq_wfe_qual, + ds_cpu0_hcr_va, + ds_cpu0_hcr_vi, + ds_cpu0_hcr_vf, + ds_cpu0_cpuectlr_ret, + ck_cpu0_event_reg, + ck_cpu0_wfi_ack, + ck_cpu0_wfe_ack, + ck_cpu0_crcx_clk_en_n, + + ds_cpu1_reset_req, + ds_cpu1_wfi_req, + ds_cpu1_wfe_req, + ds_cpu1_flush, + ds_cpu1_flush_type, + ds_cpu1_imp_abrt_wfi_qual, + ds_cpu1_irq_wfi_qual, + ds_cpu1_fiq_wfi_qual, + ds_cpu1_vimp_abrt_wfi_qual, + ds_cpu1_virq_wfi_qual, + ds_cpu1_vfiq_wfi_qual, + ds_cpu1_imp_abrt_wfe_qual, + ds_cpu1_irq_wfe_qual, + ds_cpu1_fiq_wfe_qual, + ds_cpu1_vimp_abrt_wfe_qual, + ds_cpu1_virq_wfe_qual, + ds_cpu1_vfiq_wfe_qual, + ds_cpu1_hcr_va, + ds_cpu1_hcr_vi, + ds_cpu1_hcr_vf, + ds_cpu1_cpuectlr_ret, + ck_cpu1_event_reg, + ck_cpu1_wfi_ack, + ck_cpu1_wfe_ack, + ck_cpu1_crcx_clk_en_n, + + ds_cpu2_reset_req, + ds_cpu2_wfi_req, + ds_cpu2_wfe_req, + ds_cpu2_flush, + ds_cpu2_flush_type, + ds_cpu2_imp_abrt_wfi_qual, + ds_cpu2_irq_wfi_qual, + ds_cpu2_fiq_wfi_qual, + ds_cpu2_vimp_abrt_wfi_qual, + ds_cpu2_virq_wfi_qual, + ds_cpu2_vfiq_wfi_qual, + ds_cpu2_imp_abrt_wfe_qual, + ds_cpu2_irq_wfe_qual, + ds_cpu2_fiq_wfe_qual, + ds_cpu2_vimp_abrt_wfe_qual, + ds_cpu2_virq_wfe_qual, + ds_cpu2_vfiq_wfe_qual, + ds_cpu2_hcr_va, + ds_cpu2_hcr_vi, + ds_cpu2_hcr_vf, + ds_cpu2_cpuectlr_ret, + ck_cpu2_event_reg, + ck_cpu2_wfi_ack, + ck_cpu2_wfe_ack, + ck_cpu2_crcx_clk_en_n, + + ds_cpu3_reset_req, + ds_cpu3_wfi_req, + ds_cpu3_wfe_req, + ds_cpu3_flush, + ds_cpu3_flush_type, + ds_cpu3_imp_abrt_wfi_qual, + ds_cpu3_irq_wfi_qual, + ds_cpu3_fiq_wfi_qual, + ds_cpu3_vimp_abrt_wfi_qual, + ds_cpu3_virq_wfi_qual, + ds_cpu3_vfiq_wfi_qual, + ds_cpu3_imp_abrt_wfe_qual, + ds_cpu3_irq_wfe_qual, + ds_cpu3_fiq_wfe_qual, + ds_cpu3_vimp_abrt_wfe_qual, + ds_cpu3_virq_wfe_qual, + ds_cpu3_vfiq_wfe_qual, + ds_cpu3_hcr_va, + ds_cpu3_hcr_vi, + ds_cpu3_hcr_vf, + ds_cpu3_cpuectlr_ret, + ck_cpu3_event_reg, + ck_cpu3_wfi_ack, + ck_cpu3_wfe_ack, + ck_cpu3_crcx_clk_en_n, + + ls_cpu0_clrexmon, + ls_cpu1_clrexmon, + ls_cpu2_clrexmon, + ls_cpu3_clrexmon, +// END CK-CPU interface + + ck_gclkt +); + +//# +//# Interface Signals +//# ================= +//# + +//----------------------------------------------------------------------------- +// Clock and Reset Signals +//----------------------------------------------------------------------------- + input CLK; // Fast Clock + input CLKEN; // Fast Clock Enable + + input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset + input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) + input nL2RESET; // L2 reset + input L2RSTDISABLE; // L2 RAMs hardware reset disable + output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request +//See also nPRESETDBG; // Debug APB reset (PCLK) + +//----------------------------------------------------------------------------- +// Static Configuration Signals +//----------------------------------------------------------------------------- +// Static configuration signals that should be tied off and not change dynamically. +// Many of the initial values specified by these inputs +// may be overridden in software using CP15 registers. + + input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) + input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors + input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) + input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers + + input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] + input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] + + input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) + input [43:2] RVBARADDR0; // RVBAR address +// BEGIN INCLUDE FOR CPU1 + input [43:2] RVBARADDR1; // RVBAR address +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input [43:2] RVBARADDR2; // RVBAR address +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input [43:2] RVBARADDR3; // RVBAR address +// END INCLUDE FOR CPU3 + input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension + +//----------------------------------------------------------------------------- +// Interrupt Controller Signals +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] nFIQ; // Fast Interrupt request + input [`MAIA_CN:0] nIRQ; // Interrupt request + input [`MAIA_CN:0] nSEI; // System Error Interrupt + input [`MAIA_CN:0] nREI; // RAM Error Interrupt + input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request + input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request + input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt + +// BEGIN NO-GIC pins + output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output +// END NO-GIC pins + + input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers +// BEGIN NO-GIC pins + input GICCDISABLE; // Put GIC into bypass mode + + input ICDTVALID; // Distrubuter AXI4 SP Message Valid + output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message + input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data + input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet + input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID + + output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid + input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message + output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data + output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet + output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID +// END NO-GIC pins + +//----------------------------------------------------------------------------- +// Timer Signals +//----------------------------------------------------------------------------- + input [63:0] CNTVALUEB; // Counter value in binary + input CNTCLKEN; // Counter clock enable + output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event + output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event + output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event + output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event + +//----------------------------------------------------------------------------- +// Power Management Signals +//----------------------------------------------------------------------------- + input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) + output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) + input EVENTI; // Event input for processor wake-up from WFE state + output EVENTO; // Event output, signal is active when SEV instruction is executed + output [`MAIA_CN:0] STANDBYWFI; // WFI mode + output [`MAIA_CN:0] STANDBYWFE; // WFE mode + output STANDBYWFIL2; // WFI mode for L2 + output [`MAIA_CN:0] SMPEN; // CPU SMP bit + + output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE + input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn + output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn + output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY + + output L2QACTIVE; // L2 Q-channel QACTIVE + input L2QREQn; // L2 Q-channel QREQn + output L2QACCEPTn; // L2 Q-channel QACCEPTn + output L2QDENY; // L2 Q-channel QDENY + + input L2FLUSHREQ; // L2 hardware flush request + output L2FLUSHDONE; // L2 hardware flush done + +//----------------------------------------------------------------------------- +// Asynchronous Error Signals +//----------------------------------------------------------------------------- + output nINTERRIRQ; // L2 RAM dbl-bit ECC error + output nEXTERRIRQ; // Write transaction error + +//----------------------------------------------------------------------------- +// Bus Configuration Signals +//----------------------------------------------------------------------------- + input SYSBARDISABLE; // Disable broadcast of barriers + input BROADCASTINNER; // Extend Inner Shared Domain + input BROADCASTOUTER; // Extend Outer Shared Domain + input BROADCASTCACHEMAINT; // Broadcast cache maint ops + +//----------------------------------------------------------------------------- +// Skyros RN-F Interface +//----------------------------------------------------------------------------- + input SCLKEN; // Skyros clock enable + input SINACT; // Skyros snoop inactive + + input [6:0] NODEID; // Skyros requestor NodeID + + output TXSACTIVE; // Skyros active - indicates pending activity on pins + input RXSACTIVE; // Skyros active - indicates pending activity on pins + + output TXLINKACTIVEREQ; // Skyros transmit link active request + input TXLINKACTIVEACK; // SKyros transmit link active acknowledge + + input RXLINKACTIVEREQ; // SKyros receive link active request + output RXLINKACTIVEACK; // Skyros receive link active acknowledge + +// TXREQ - outbound requests + output TXREQFLITPEND; // Skyros TXREQ FLIT pending + output TXREQFLITV; // Skyros TXREQ FLIT valid + output [99:0] TXREQFLIT; // Skyros TXREQ FLIT payload + output [7:0] REQMEMATTR; // Skyros TXREQ raw memory attributes + input TXREQLCRDV; // Skyros TXREQ link-layer credit valid + +// TXRSP - outbound response + output TXRSPFLITPEND; // Skyros TXRSP FLIT pending + output TXRSPFLITV; // Skyros TXRSP FLIT valid + output [44:0] TXRSPFLIT; // Skyros TXRSP FLIT payload + input TXRSPLCRDV; // Skyros TXRSP link-layer credit valid + +// TXDAT - outbound data + output TXDATFLITPEND; // Skyros TXDAT FLIT pending + output TXDATFLITV; // Skyros TXDAT FLIT valid + output [193:0] TXDATFLIT; // Skyros TXDAT FLIT payload + input TXDATLCRDV; // Skyros TXDAT link-layer credit valid + +// RXSNP - inbound snoops + input RXSNPFLITPEND; // Skyros RXSNP FLIT pending + input RXSNPFLITV; // Skyros RXSNP FLIT valid + input [64:0] RXSNPFLIT; // Skyros RXSNP FLIT payload + output RXSNPLCRDV; // Skyros RXSNP link-layer credit valid + +// RXRSP - inbound response + input RXRSPFLITPEND; // Skyros RXRSP FLIT pending + input RXRSPFLITV; // Skyros RXRSP FLIT valid + input [44:0] RXRSPFLIT; // Skyros RXRSP FLIT payload + output RXRSPLCRDV; // Skyros RXRSP link-layer credit valid + +// RXDAT - inbound data + input RXDATFLITPEND; // Skyros RXDAT FLIT pending + input RXDATFLITV; // Skyros RXDAT FLIT valid + input [193:0] RXDATFLIT; // Skyros RXDAT FLIT payload + output RXDATLCRDV; // Skyros RXDAT link-layer credit valid + + input [43:24] SAMMNBASE; // Skyros SAM MN base address + input [1:0] SAMADDRMAP0; // Skyros SAM address region 0 mapping + input [1:0] SAMADDRMAP1; // Skyros SAM address region 1 mapping + input [1:0] SAMADDRMAP2; // Skyros SAM address region 2 mapping + input [1:0] SAMADDRMAP3; // Skyros SAM address region 3 mapping + input [1:0] SAMADDRMAP4; // Skyros SAM address region 4 mapping + input [1:0] SAMADDRMAP5; // Skyros SAM address region 5 mapping + input [1:0] SAMADDRMAP6; // Skyros SAM address region 6 mapping + input [1:0] SAMADDRMAP7; // Skyros SAM address region 7 mapping + input [1:0] SAMADDRMAP8; // Skyros SAM address region 8 mapping + input [1:0] SAMADDRMAP9; // Skyros SAM address region 9 mapping + input [1:0] SAMADDRMAP10; // Skyros SAM address region 10 mapping + input [1:0] SAMADDRMAP11; // Skyros SAM address region 11 mapping + input [1:0] SAMADDRMAP12; // Skyros SAM address region 12 mapping + input [1:0] SAMADDRMAP13; // Skyros SAM address region 13 mapping + input [1:0] SAMADDRMAP14; // Skyros SAM address region 14 mapping + input [1:0] SAMADDRMAP15; // Skyros SAM address region 15 mapping + input [1:0] SAMADDRMAP16; // Skyros SAM address region 16 mapping + input [1:0] SAMADDRMAP17; // Skyros SAM address region 17 mapping + input [1:0] SAMADDRMAP18; // Skyros SAM address region 18 mapping + input [1:0] SAMADDRMAP19; // Skyros SAM address region 19 mapping + input [6:0] SAMMNNODEID; // Skyros SAM MN target ID + input [6:0] SAMHNI0NODEID; // Skyros SAM HNI0 target ID + input [6:0] SAMHNI1NODEID; // Skyros SAM HNI1 target ID + input [6:0] SAMHNF0NODEID; // Skyros SAM HNF0 target ID + input [6:0] SAMHNF1NODEID; // Skyros SAM HNF1 target ID + input [6:0] SAMHNF2NODEID; // Skyros SAM HNF2 target ID + input [6:0] SAMHNF3NODEID; // Skyros SAM HNF3 target ID + input [6:0] SAMHNF4NODEID; // Skyros SAM HNF4 target ID + input [6:0] SAMHNF5NODEID; // Skyros SAM HNF5 target ID + input [6:0] SAMHNF6NODEID; // Skyros SAM HNF6 target ID + input [6:0] SAMHNF7NODEID; // Skyros SAM HNF7 target ID + input [2:0] SAMHNFMODE; // Skyros SAM HNF interleaving mode + +//----------------------------------------------------------------------------- +// ACP AXI Slave +//----------------------------------------------------------------------------- + input ACLKENS; // AXI slave clock enable + input AINACTS; // AXI slave interface no longer active or accepting requests + +// Write Address channel signals + output AWREADYS; // Write Address ready (slave ready to accept write address) + input AWVALIDS; // Write Address valid + input [4:0] AWIDS; // Write Address ID + input [43:0] AWADDRS; // Write Address + input [7:0] AWLENS; // Write Burst Length + input [3:0] AWCACHES; // Write Cache type + input [1:0] AWUSERS; // Write inner & outer shareability + input [2:0] AWPROTS; // Write Protection type + +// Write Data channel signals + output WREADYS; // Write Data ready (slave ready to accept data) + input WVALIDS; // Write Data valid + input [127:0] WDATAS; // Write Data + input [15:0] WSTRBS; // Write byte-lane strobes + input WLASTS; // Write Data last transfer indicator + +// Write Response channel signals + input BREADYS; // Write Response ready (master ready to accept response) + output BVALIDS; // Write Response Valid + output [4:0] BIDS; // Write Response ID tag + output [1:0] BRESPS; // Write Response + +// Read Address channel signals + output ARREADYS; // Read Address ready (slave ready to accept read address) + input ARVALIDS; // Read Address valid + input [4:0] ARIDS; // Read Address ID + input [43:0] ARADDRS; // Read Address + input [7:0] ARLENS; // Read Burst Length + input [3:0] ARCACHES; // Read Cache type + input [1:0] ARUSERS; // Read inner & outer shareability + input [2:0] ARPROTS; // Read Protection type + +// Read Data channel signals + input RREADYS; // Read Data ready (master ready to accept data) + output RVALIDS; // Read Data valid + output [4:0] RIDS; // Read Data ID + output [127:0] RDATAS; // Read Data + output [1:0] RRESPS; // Read Data response + output RLASTS; // Read Data last transfer indicator + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (CLK) +//----------------------------------------------------------------------------- +// Debug CLK interface + input [43:12] DBGROMADDR; // Debug ROM base address + input DBGROMADDRV; // Debug ROM base address valid + + output [`MAIA_CN:0] DBGACK; // Debug acknowledge + output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt + output [`MAIA_CN:0] COMMRX; // Comms channel receive + output [`MAIA_CN:0] COMMTX; // Comms channel transmit + + output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request + output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request + + input DBGL1RSTDISABLE; // L1 DCache hardware reset disable + +// PMU CLK interface + output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request + output [24:0] PMUEVENT0; // PMU Event bus +// BEGIN INCLUDE FOR CPU1 + output [24:0] PMUEVENT1; // PMU Event bus +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + output [24:0] PMUEVENT2; // PMU Event bus +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + output [24:0] PMUEVENT3; // PMU Event bus +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (ATCLK) +//----------------------------------------------------------------------------- +// ETM ATB interface and Misc signals + input ATCLKEN; // ATB Clock Enable + input [63:0] TSVALUEB; // ATB Timestamp in binary + + input ATREADYM0; // ATDATA can be accepted + input AFVALIDM0; // ATB Fifo Flush Request + output [31:0] ATDATAM0; // ATB Data + output ATVALIDM0; // ATB Data Valid + output [1:0] ATBYTESM0; // ATB Data Size + output AFREADYM0; // ATB Fifo Flush Finished + output [6:0] ATIDM0; // ATB Trace Source ID + input SYNCREQM0; // ATB External synchronization request + +// BEGIN INCLUDE FOR CPU1 + input ATREADYM1; // ATDATA can be accepted + input AFVALIDM1; // ATB Fifo Flush Request + output [31:0] ATDATAM1; // ATB Data + output ATVALIDM1; // ATB Data Valid + output [1:0] ATBYTESM1; // ATB Data Size + output AFREADYM1; // ATB Fifo Flush Finished + output [6:0] ATIDM1; // ATB Trace Source ID + input SYNCREQM1; // ATB External synchronization request +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ATREADYM2; // ATDATA can be accepted + input AFVALIDM2; // ATB Fifo Flush Request + output [31:0] ATDATAM2; // ATB Data + output ATVALIDM2; // ATB Data Valid + output [1:0] ATBYTESM2; // ATB Data Size + output AFREADYM2; // ATB Fifo Flush Finished + output [6:0] ATIDM2; // ATB Trace Source ID + input SYNCREQM2; // ATB External synchronization request +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ATREADYM3; // ATDATA can be accepted + input AFVALIDM3; // ATB Fifo Flush Request + output [31:0] ATDATAM3; // ATB Data + output ATVALIDM3; // ATB Data Valid + output [1:0] ATBYTESM3; // ATB Data Size + output AFREADYM3; // ATB Fifo Flush Finished + output [6:0] ATIDM3; // ATB Trace Source ID + input SYNCREQM3; // ATB External synchronization request +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (PCLK) +//----------------------------------------------------------------------------- +// Debug-APBv3 port (APB) + input PCLKDBG; // APB Clock + input PCLKENDBG; // APB Clock Enable + input nPRESETDBG; // APB Reset + input PSELDBG; // Debug bus access + input [21:2] PADDRDBG; // APB address + input PADDRDBG31; // APB address bit[31] + input PENABLEDBG; // APB transfer complete flag + input PWRITEDBG; // APB read/write indicator + input [31:0] PWDATADBG; // APB write data + output [31:0] PRDATADBG; // APB read data + output PREADYDBG; // APB slave ready, used to extend a transfer + output PSLVERRDBG; // APB slave transfer error + +// Misc interface + input [`MAIA_CN:0] EDBGRQ; // External debug request + +// PMU Snapshot interface + input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request + output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge + +// Power-related interface + input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status + output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request + +// CTI interface + input [3:0] CTICHIN; // Channel In + input [3:0] CTICHOUTACK; // Channel Out acknowledge + output [3:0] CTICHOUT; // Channel Out + output [3:0] CTICHINACK; // Channel In acknowledge + input CISBYPASS; // Channel interface sync bypass + input [3:0] CIHSBYPASS; // Channel interface H/S bypass + output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt + input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge + +//----------------------------------------------------------------------------- +// Debug Authentication Interface (CLK & PCLK) +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] DBGEN; // Invasive debug enable + input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable + input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable + input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable + +//----------------------------------------------------------------------------- +// DFT Signals +//----------------------------------------------------------------------------- + input DFTSE; // Scan enable + input DFTRSTDISABLE; // Disable reset to cells during scan shift + input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr + input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 + input DFTRAMHOLD; // Holds data in RAMs + input DFTCLKBYPASS; // L2 RAM strobe clock bypass + input DFTMCPHOLD; // Disable multi-cycle RAM paths + +//----------------------------------------------------------------------------- +// MBIST Interface +//----------------------------------------------------------------------------- + input nMBISTRESET; // MBIST reset + input MBISTREQ; // MBIST mode request + +//----------------------------------------------------------------------------- +// Signals from maia -> maia_cpu_io -> maia_cpu +//----------------------------------------------------------------------------- +// Outputs to maia_cpu + output ncpuporeset_cpu0_o; + output ncorereset_cpu0_o; + + output cfgend_cpu0_o; + output cfgte_cpu0_o; + output cp15sdisable_cpu0_o; + output vinithi_cpu0_o; + output [7:0] clusteridaff1_cpu0_o; + output [7:0] clusteridaff2_cpu0_o; + output [1:0] cpuid_cpu0_o; + output aa64naa32_cpu0_o; + output [43:2] rvbaraddr_cpu0_o; + output cryptodisable_cpu0_o; + output giccdisable_cpu0_o; + + output [43:12] dbgromaddr_cpu0_o; + output dbgromaddrv_cpu0_o; + output dbgl1rstdisable_cpu0_o; + + output dbgen_cpu0_o; + output niden_cpu0_o; + output spiden_cpu0_o; + output spniden_cpu0_o; + + output [63:0] tsvalueb_cpu0_o; + + output atclken_cpu0_o; + output afvalidm_cpu0_o; + output atreadym_cpu0_o; + output syncreqm_cpu0_o; + + output dftse_cpu0_o; + output dftrstdisable_cpu0_o; + output dftcrclkdisable_cpu0_o; + output dftramhold_cpu0_o; + output nmbistreset_cpu0_o; + +// BEGIN INCLUDE FOR CPU1 + output ncpuporeset_cpu1_o; + output ncorereset_cpu1_o; + + output cfgend_cpu1_o; + output cfgte_cpu1_o; + output cp15sdisable_cpu1_o; + output vinithi_cpu1_o; + output [7:0] clusteridaff1_cpu1_o; + output [7:0] clusteridaff2_cpu1_o; + output [1:0] cpuid_cpu1_o; + output aa64naa32_cpu1_o; + output [43:2] rvbaraddr_cpu1_o; + output cryptodisable_cpu1_o; + output giccdisable_cpu1_o; + + output [43:12] dbgromaddr_cpu1_o; + output dbgromaddrv_cpu1_o; + output dbgl1rstdisable_cpu1_o; + + output dbgen_cpu1_o; + output niden_cpu1_o; + output spiden_cpu1_o; + output spniden_cpu1_o; + + output [63:0] tsvalueb_cpu1_o; + + output atclken_cpu1_o; + output afvalidm_cpu1_o; + output atreadym_cpu1_o; + output syncreqm_cpu1_o; + + output dftse_cpu1_o; + output dftrstdisable_cpu1_o; + output dftcrclkdisable_cpu1_o; + output dftramhold_cpu1_o; + output nmbistreset_cpu1_o; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + output ncpuporeset_cpu2_o; + output ncorereset_cpu2_o; + + output cfgend_cpu2_o; + output cfgte_cpu2_o; + output cp15sdisable_cpu2_o; + output vinithi_cpu2_o; + output [7:0] clusteridaff1_cpu2_o; + output [7:0] clusteridaff2_cpu2_o; + output [1:0] cpuid_cpu2_o; + output aa64naa32_cpu2_o; + output [43:2] rvbaraddr_cpu2_o; + output cryptodisable_cpu2_o; + output giccdisable_cpu2_o; + + output [43:12] dbgromaddr_cpu2_o; + output dbgromaddrv_cpu2_o; + output dbgl1rstdisable_cpu2_o; + + output dbgen_cpu2_o; + output niden_cpu2_o; + output spiden_cpu2_o; + output spniden_cpu2_o; + + output [63:0] tsvalueb_cpu2_o; + + output atclken_cpu2_o; + output afvalidm_cpu2_o; + output atreadym_cpu2_o; + output syncreqm_cpu2_o; + + output dftse_cpu2_o; + output dftrstdisable_cpu2_o; + output dftcrclkdisable_cpu2_o; + output dftramhold_cpu2_o; + output nmbistreset_cpu2_o; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + output ncpuporeset_cpu3_o; + output ncorereset_cpu3_o; + + output cfgend_cpu3_o; + output cfgte_cpu3_o; + output cp15sdisable_cpu3_o; + output vinithi_cpu3_o; + output [7:0] clusteridaff1_cpu3_o; + output [7:0] clusteridaff2_cpu3_o; + output [1:0] cpuid_cpu3_o; + output aa64naa32_cpu3_o; + output [43:2] rvbaraddr_cpu3_o; + output cryptodisable_cpu3_o; + output giccdisable_cpu3_o; + + output [43:12] dbgromaddr_cpu3_o; + output dbgromaddrv_cpu3_o; + output dbgl1rstdisable_cpu3_o; + + output dbgen_cpu3_o; + output niden_cpu3_o; + output spiden_cpu3_o; + output spniden_cpu3_o; + + output [63:0] tsvalueb_cpu3_o; + + output atclken_cpu3_o; + output afvalidm_cpu3_o; + output atreadym_cpu3_o; + output syncreqm_cpu3_o; + + output dftse_cpu3_o; + output dftrstdisable_cpu3_o; + output dftcrclkdisable_cpu3_o; + output dftramhold_cpu3_o; + output nmbistreset_cpu3_o; +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Signals from maia_cpu -> maia_cpu_io -> maia +//----------------------------------------------------------------------------- +// Inputs from maia_cpu + input ds_cpu0_sev_req; + input ds_cpu0_sevl_req; + input ds_cpu0_cpuectlr_smp; + + input ncommirq_cpu0_i; + input commrx_cpu0_i; + input commtx_cpu0_i; + input dbgack_cpu0_i; + input dbgrstreq_cpu0_i; + input dbgnopwrdwn_cpu0_i; + + input npmuirq_cpu0_i; + input [24:0] pmuevent_cpu0_i; + input pm_export_cpu0_i; + + input etclken_cpu0_i; + input afreadym_cpu0_i; + input [1:0] atbytesm_cpu0_i; + input [31:0] atdatam_cpu0_i; + input [6:0] atidm_cpu0_i; + input atvalidm_cpu0_i; + +// BEGIN INCLUDE FOR CPU1 + input ds_cpu1_sev_req; + input ds_cpu1_sevl_req; + input ds_cpu1_cpuectlr_smp; + + input ncommirq_cpu1_i; + input commrx_cpu1_i; + input commtx_cpu1_i; + input dbgack_cpu1_i; + input dbgrstreq_cpu1_i; + input dbgnopwrdwn_cpu1_i; + + input npmuirq_cpu1_i; + input [24:0] pmuevent_cpu1_i; + input pm_export_cpu1_i; + + input etclken_cpu1_i; + input afreadym_cpu1_i; + input [1:0] atbytesm_cpu1_i; + input [31:0] atdatam_cpu1_i; + input [6:0] atidm_cpu1_i; + input atvalidm_cpu1_i; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ds_cpu2_sev_req; + input ds_cpu2_sevl_req; + input ds_cpu2_cpuectlr_smp; + + input ncommirq_cpu2_i; + input commrx_cpu2_i; + input commtx_cpu2_i; + input dbgack_cpu2_i; + input dbgrstreq_cpu2_i; + input dbgnopwrdwn_cpu2_i; + + input npmuirq_cpu2_i; + input [24:0] pmuevent_cpu2_i; + input pm_export_cpu2_i; + + input etclken_cpu2_i; + input afreadym_cpu2_i; + input [1:0] atbytesm_cpu2_i; + input [31:0] atdatam_cpu2_i; + input [6:0] atidm_cpu2_i; + input atvalidm_cpu2_i; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ds_cpu3_sev_req; + input ds_cpu3_sevl_req; + input ds_cpu3_cpuectlr_smp; + + input ncommirq_cpu3_i; + input commrx_cpu3_i; + input commtx_cpu3_i; + input dbgack_cpu3_i; + input dbgrstreq_cpu3_i; + input dbgnopwrdwn_cpu3_i; + + input npmuirq_cpu3_i; + input [24:0] pmuevent_cpu3_i; + input pm_export_cpu3_i; + + input etclken_cpu3_i; + input afreadym_cpu3_i; + input [1:0] atbytesm_cpu3_i; + input [31:0] atdatam_cpu3_i; + input [6:0] atidm_cpu3_i; + input atvalidm_cpu3_i; +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// L2 interface +//----------------------------------------------------------------------------- + output [12:0] l2_cpu0_mbist1_addr_b1; + output [3:0] l2_cpu0_mbist1_array_b1; + output [7:0] l2_cpu0_mbist1_be_b1; + output l2_cpu0_mbist1_en_b1; + output l2_cpu0_mbist1_rd_en_b1; + output l2_cpu0_mbist1_wr_en_b1; + output l2_cpu0_mbist1_all_b1; + +// BEGIN INCLUDE FOR CPU1 + output [12:0] l2_cpu1_mbist1_addr_b1; + output [3:0] l2_cpu1_mbist1_array_b1; + output [7:0] l2_cpu1_mbist1_be_b1; + output l2_cpu1_mbist1_en_b1; + output l2_cpu1_mbist1_rd_en_b1; + output l2_cpu1_mbist1_wr_en_b1; + output l2_cpu1_mbist1_all_b1; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + output [12:0] l2_cpu2_mbist1_addr_b1; + output [3:0] l2_cpu2_mbist1_array_b1; + output [7:0] l2_cpu2_mbist1_be_b1; + output l2_cpu2_mbist1_en_b1; + output l2_cpu2_mbist1_rd_en_b1; + output l2_cpu2_mbist1_wr_en_b1; + output l2_cpu2_mbist1_all_b1; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + output [12:0] l2_cpu3_mbist1_addr_b1; + output [3:0] l2_cpu3_mbist1_array_b1; + output [7:0] l2_cpu3_mbist1_be_b1; + output l2_cpu3_mbist1_en_b1; + output l2_cpu3_mbist1_rd_en_b1; + output l2_cpu3_mbist1_wr_en_b1; + output l2_cpu3_mbist1_all_b1; +// END INCLUDE FOR CPU3 + +// BEGIN L2-CPU interface + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + output l2_cpu0_cfg_ecc_en; + output l2_cpu0_arb_thrshld_timeout_en; + output l2_cpu0_disable_clean_evict_opt; + output l2_cpu0_dext_err_r2; // LS external error + output l2_cpu0_dext_err_type_r2; // LS external error type + output l2_cpu0_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu0_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu0_ddata_r2; // LS read data + output l2_cpu0_barrier_done; // LS barrier complete + output l2_cpu0_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu0_spec_bufid; // LS read speculative response buffer id + output l2_cpu0_rvalid; // LS read response valid + output [1:0] l2_cpu0_rstate; // LS read response state + output l2_cpu0_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu0_rbufid; // LS read response buffer id + output l2_cpu0_dvalid_r1; // LS read data valid + output l2_cpu0_dlast_r1; // LS read last indicator + output [2:0] l2_cpu0_dbufid_r1; // LS read data fill buffer id + output l2_cpu0_iext_err_r2; // IF external error + output l2_cpu0_iext_err_type_r2; // IF external error type + output l2_cpu0_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu0_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu0_idata_r2; // IF read data + output l2_cpu0_ivalid_r1; // IF read data valid + output [1:0] l2_cpu0_ibufid_r1; // IF read data fill buffer id + output l2_cpu0_ls_sync_req; // LS sync req + output [48:0] l2_cpu0_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu0_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu0_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu0_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu0_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu0_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu0_ccb_req_info_c3; // LS ccb req info + output l2_cpu0_if_ccb_clken_c3; // IF ccb clken + output l2_cpu0_if_ccb_req_c3; // IF ccb req + output l2_cpu0_if_sync_req; // IF sync req + output l2_cpu0_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu0_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu0_tlb_sync_req; // TLB sync req + output l2_cpu0_tlb_sync_complete; // TLB sync complete + output l2_cpu0_tbw_desc_vld; // TBW descriptor valid + output l2_cpu0_tbw_ext_err; // TBW descriptor external error + output l2_cpu0_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu0_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu0_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu0_spr_rd_data; // DS spr read data + output [1:0] l2_cpu0_l2_cache_size; // DS L2 cache size + output l2_cpu0_pf_throttle_q; // PF throttling + + output l2_cpu0_wr_ex_resp; // store exclusive response + output l2_cpu0_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu0_ic_base; // PERIPHBASE + output l2_cpu0_no_intctrl; // INTCTLR not present + + + output [33:0] l2_cpu0_pmu_events; // L2 PMU events + + input ds_cpu0_l2_spr_en; // cpu0 early spr req for clk enables + input ds_cpu0_l2_spr_rd; // cpu0 spr read op + input ds_cpu0_l2_spr_wr; // cpu0 spr write op + input [8:0] ds_cpu0_l2_spr_addr; // cpu0 spr address + input ds_cpu0_l2_spr_dw; // cpu0 spr access dw + input [63:0] ds_cpu0_l2_spr_wr_data; // cpu0 spr write data + + input l2_cpu0_wr_data_vld_x1_q; // cpu0 write data vld x1 stage + input l2_cpu0_wr_evict_x1_q; // cpu0 write evict x1 stage + input [143:0] l2_cpu0_wr_data; + input l2_cpu0_ls_rd_haz_vld_arb_q; + input l2_cpu0_ls_wr_haz_vld_arb_q; + input l2_cpu0_dt_pmu_evt_en; // PMU enabled. + + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + output l2_cpu1_cfg_ecc_en; + output l2_cpu1_arb_thrshld_timeout_en; + output l2_cpu1_disable_clean_evict_opt; + output l2_cpu1_dext_err_r2; // LS external error + output l2_cpu1_dext_err_type_r2; // LS external error type + output l2_cpu1_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu1_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu1_ddata_r2; // LS read data + output l2_cpu1_barrier_done; // LS barrier complete + output l2_cpu1_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu1_spec_bufid; // LS read speculative response buffer id + output l2_cpu1_rvalid; // LS read response valid + output [1:0] l2_cpu1_rstate; // LS read response state + output l2_cpu1_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu1_rbufid; // LS read response buffer id + output l2_cpu1_dvalid_r1; // LS read data valid + output l2_cpu1_dlast_r1; // LS read last indicator + output [2:0] l2_cpu1_dbufid_r1; // LS read data fill buffer id + output l2_cpu1_iext_err_r2; // IF external error + output l2_cpu1_iext_err_type_r2; // IF external error type + output l2_cpu1_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu1_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu1_idata_r2; // IF read data + output l2_cpu1_ivalid_r1; // IF read data valid + output [1:0] l2_cpu1_ibufid_r1; // IF read data fill buffer id + output l2_cpu1_ls_sync_req; // LS sync req + output [48:0] l2_cpu1_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu1_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu1_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu1_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu1_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu1_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu1_ccb_req_info_c3; // LS ccb req info + output l2_cpu1_if_ccb_clken_c3; // IF ccb clken + output l2_cpu1_if_ccb_req_c3; // IF ccb req + output l2_cpu1_if_sync_req; // IF sync req + output l2_cpu1_tlb_ccb_clken_c3; // IF ccb clken + output l2_cpu1_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu1_tlb_sync_req; // TLB sync req + output l2_cpu1_tlb_sync_complete; // TLB sync complete + output l2_cpu1_tbw_desc_vld; // TBW descriptor valid + output l2_cpu1_tbw_ext_err; // TBW descriptor external error + output l2_cpu1_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu1_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu1_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu1_spr_rd_data; // DS spr read data + output [1:0] l2_cpu1_l2_cache_size; // DS L2 cache size + output l2_cpu1_pf_throttle_q; // PF throttling + + output l2_cpu1_wr_ex_resp; // store exclusive response + output l2_cpu1_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu1_ic_base; // PERIPHBASE + output l2_cpu1_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu1_pmu_events; // L2 PMU events + + input ds_cpu1_l2_spr_en; // cpu1 early spr req for clk enables + input ds_cpu1_l2_spr_rd; // cpu1 spr read op + input ds_cpu1_l2_spr_wr; // cpu1 spr write op + input [8:0] ds_cpu1_l2_spr_addr; // cpu1 spr address + input ds_cpu1_l2_spr_dw; // cpu1 spr access dw + input [63:0] ds_cpu1_l2_spr_wr_data; // cpu1 spr write data + + input l2_cpu1_wr_data_vld_x1_q; // cpu1 write data vld x1 stage + input l2_cpu1_wr_evict_x1_q; // cpu1 write evict x1 stage + input [143:0] l2_cpu1_wr_data; + input l2_cpu1_ls_rd_haz_vld_arb_q; + input l2_cpu1_ls_wr_haz_vld_arb_q; + input l2_cpu1_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + output l2_cpu2_cfg_ecc_en; + output l2_cpu2_arb_thrshld_timeout_en; + output l2_cpu2_disable_clean_evict_opt; + output l2_cpu2_dext_err_r2; // LS external error + output l2_cpu2_dext_err_type_r2; // LS external error type + output l2_cpu2_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu2_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu2_ddata_r2; // LS read data + output l2_cpu2_barrier_done; // LS barrier complete + output l2_cpu2_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu2_spec_bufid; // LS read speculative response buffer id + output l2_cpu2_rvalid; // LS read response valid + output [1:0] l2_cpu2_rstate; // LS read response state + output l2_cpu2_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu2_rbufid; // LS read response buffer id + output l2_cpu2_dvalid_r1; // LS read data valid + output l2_cpu2_dlast_r1; // LS read last indicator + output [2:0] l2_cpu2_dbufid_r1; // LS read data fill buffer id + output l2_cpu2_iext_err_r2; // IF external error + output l2_cpu2_iext_err_type_r2; // IF external error type + output l2_cpu2_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu2_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu2_idata_r2; // IF read data + output l2_cpu2_ivalid_r1; // IF read data valid + output [1:0] l2_cpu2_ibufid_r1; // IF read data fill buffer id + output l2_cpu2_ls_sync_req; // LS sync req + output [48:0] l2_cpu2_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu2_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu2_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu2_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu2_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu2_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu2_ccb_req_info_c3; // LS ccb req info + output l2_cpu2_if_ccb_clken_c3; // IF ccb clken + output l2_cpu2_if_ccb_req_c3; // IF ccb req + output l2_cpu2_if_sync_req; // IF sync req + output l2_cpu2_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu2_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu2_tlb_sync_req; // TLB sync req + output l2_cpu2_tlb_sync_complete; // TLB sync complete + output l2_cpu2_tbw_desc_vld; // TBW descriptor valid + output l2_cpu2_tbw_ext_err; // TBW descriptor external error + output l2_cpu2_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu2_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu2_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu2_spr_rd_data; // DS spr read data + output [1:0] l2_cpu2_l2_cache_size; // DS L2 cache size + output l2_cpu2_pf_throttle_q; // PF throttling + + output l2_cpu2_wr_ex_resp; // store exclusive response + output l2_cpu2_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu2_ic_base; // PERIPHBASE + output l2_cpu2_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu2_pmu_events; // L2 PMU events + + input ds_cpu2_l2_spr_en; // cpu2 early spr req for clk enables + input ds_cpu2_l2_spr_rd; // cpu2 spr read op + input ds_cpu2_l2_spr_wr; // cpu2 spr write op + input [8:0] ds_cpu2_l2_spr_addr; // cpu2 spr address + input ds_cpu2_l2_spr_dw; // cpu2 spr access dw + input [63:0] ds_cpu2_l2_spr_wr_data; // cpu2 spr write data + + input l2_cpu2_wr_data_vld_x1_q; // cpu2 write data vld x1 stage + input l2_cpu2_wr_evict_x1_q; // cpu2 write evict x1 stage + input [143:0] l2_cpu2_wr_data; + input l2_cpu2_ls_rd_haz_vld_arb_q; + input l2_cpu2_ls_wr_haz_vld_arb_q; + input l2_cpu2_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + output l2_cpu3_cfg_ecc_en; + output l2_cpu3_arb_thrshld_timeout_en; + output l2_cpu3_disable_clean_evict_opt; + output l2_cpu3_dext_err_r2; // LS external error + output l2_cpu3_dext_err_type_r2; // LS external error type + output l2_cpu3_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu3_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu3_ddata_r2; // LS read data + output l2_cpu3_barrier_done; // LS barrier complete + output l2_cpu3_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu3_spec_bufid; // LS read speculative response buffer id + output l2_cpu3_rvalid; // LS read response valid + output [1:0] l2_cpu3_rstate; // LS read response state + output l2_cpu3_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu3_rbufid; // LS read response buffer id + output l2_cpu3_dvalid_r1; // LS read data valid + output l2_cpu3_dlast_r1; // LS read last indicator + output [2:0] l2_cpu3_dbufid_r1; // LS read data fill buffer id + output l2_cpu3_iext_err_r2; // IF external error + output l2_cpu3_iext_err_type_r2; // IF external error type + output l2_cpu3_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu3_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu3_idata_r2; // IF read data + output l2_cpu3_ivalid_r1; // IF read data valid + output [1:0] l2_cpu3_ibufid_r1; // IF read data fill buffer id + output l2_cpu3_ls_sync_req; // LS sync req + output [48:0] l2_cpu3_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu3_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu3_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu3_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu3_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu3_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu3_ccb_req_info_c3; // LS ccb req info + output l2_cpu3_if_ccb_clken_c3; // IF ccb clken + output l2_cpu3_if_ccb_req_c3; // IF ccb req + output l2_cpu3_if_sync_req; // IF sync req + output l2_cpu3_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu3_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu3_tlb_sync_req; // TLB sync req + output l2_cpu3_tlb_sync_complete; // TLB sync complete + output l2_cpu3_tbw_desc_vld; // TBW descriptor valid + output l2_cpu3_tbw_ext_err; // TBW descriptor external error + output l2_cpu3_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu3_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu3_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu3_spr_rd_data; // DS spr read data + output [1:0] l2_cpu3_l2_cache_size; // DS L2 cache size + output l2_cpu3_pf_throttle_q; // PF throttling + + output l2_cpu3_wr_ex_resp; // store exclusive response + output l2_cpu3_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu3_ic_base; // PERIPHBASE + output l2_cpu3_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu3_pmu_events; // L2 PMU events + + input ds_cpu3_l2_spr_en; // cpu3 early spr req for clk enables + input ds_cpu3_l2_spr_rd; // cpu3 spr read op + input ds_cpu3_l2_spr_wr; // cpu3 spr write op + input [8:0] ds_cpu3_l2_spr_addr; // cpu3 spr address + input ds_cpu3_l2_spr_dw; // cpu3 spr access dw + input [63:0] ds_cpu3_l2_spr_wr_data; // cpu3 spr write data + + input l2_cpu3_wr_data_vld_x1_q; // cpu3 write data vld x1 stage + input l2_cpu3_wr_evict_x1_q; // cpu3 write evict x1 stage + input [143:0] l2_cpu3_wr_data; + input l2_cpu3_ls_rd_haz_vld_arb_q; + input l2_cpu3_ls_wr_haz_vld_arb_q; + input l2_cpu3_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// tag_pipe / cpu slave +//----------------------------------------------------------------------------- + output l2_cpu0_flsh_ls_rd_l2_dly; // cpu0 ls local hazard flush + output l2_cpu0_flsh_ls_wr_l2_dly; // cpu0 ls local hazard flush + + output l2_cpu0_wr_data_stall; // cpu0 write data stall + + output l2_cpu1_flsh_ls_rd_l2_dly; // cpu1 ls local hazard flush + output l2_cpu1_flsh_ls_wr_l2_dly; // cpu1 ls local hazard flush + + output l2_cpu1_wr_data_stall; // cpu1 write data stall + + output l2_cpu2_flsh_ls_rd_l2_dly; // cpu2 ls local hazard flush + output l2_cpu2_flsh_ls_wr_l2_dly; // cpu2 ls local hazard flush + + output l2_cpu2_wr_data_stall; // cpu2 write data stall + + output l2_cpu3_flsh_ls_rd_l2_dly; // cpu3 ls local hazard flush + output l2_cpu3_flsh_ls_wr_l2_dly; // cpu3 ls local hazard flush + + output l2_cpu3_wr_data_stall; // cpu3 write data stall + + output [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; // cpu0 ls id local hazard flush + output [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; // cpu0 ls id local hazard flush + + output [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; // cpu1 ls id local hazard flush + output [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; // cpu1 ls id local hazard flush + + output [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; // cpu2 ls id local hazard flush + output [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; // cpu2 ls id local hazard flush + + output [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; // cpu3 ls id local hazard flush + output [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; // cpu3 ls id local hazard flush + + output l2_cpu0_flsh_ls_rd_l4_dly; // cpu0 ls global hazard flush + output l2_cpu0_flsh_if_rd_l4_dly; // cpu0 if global hazard flush + output l2_cpu0_flsh_tw_rd_l4_dly; // cpu0 tw global hazard flush + output l2_cpu0_flsh_ls_wr_l4_dly; // cpu0 ls global hazard flush + + output l2_cpu1_flsh_ls_rd_l4_dly; // cpu1 ls global hazard flush + output l2_cpu1_flsh_if_rd_l4_dly; // cpu1 if global hazard flush + output l2_cpu1_flsh_tw_rd_l4_dly; // cpu1 tw global hazard flush + output l2_cpu1_flsh_ls_wr_l4_dly; // cpu1 ls global hazard flush + + output l2_cpu2_flsh_ls_rd_l4_dly; // cpu2 ls global hazard flush + output l2_cpu2_flsh_if_rd_l4_dly; // cpu2 if global hazard flush + output l2_cpu2_flsh_tw_rd_l4_dly; // cpu2 tw global hazard flush + output l2_cpu2_flsh_ls_wr_l4_dly; // cpu2 ls global hazard flush + + output l2_cpu3_flsh_ls_rd_l4_dly; // cpu3 ls global hazard flush + output l2_cpu3_flsh_if_rd_l4_dly; // cpu3 if global hazard flush + output l2_cpu3_flsh_tw_rd_l4_dly; // cpu3 tw global hazard flush + output l2_cpu3_flsh_ls_wr_l4_dly; // cpu3 ls global hazard flush + + output [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; // cpu0 ls id global hazard flush + output [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; // cpu0 if id global hazard flush + output [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; // cpu0 ls id global hazard flush + output l2_cpu0_flsh_ls_wr_evict_l4_dly; // cpu0 ls evict hazard + + output [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; // cpu1 ls id global hazard flush + output [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; // cpu1 if id global hazard flush + output [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; // cpu1 ls id global hazard flush + output l2_cpu1_flsh_ls_wr_evict_l4_dly; // cpu1 ls evict hazard + + output [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; // cpu2 ls id global hazard flush + output [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; // cpu2 if id global hazard flush + output [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; // cpu2 ls id global hazard flush + output l2_cpu2_flsh_ls_wr_evict_l4_dly; // cpu2 ls evict hazard + + output [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; // cpu3 ls id global hazard flush + output [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; // cpu3 if id global hazard flush + output [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; // cpu3 ls id global hazard flush + output l2_cpu3_flsh_ls_wr_evict_l4_dly; // cpu3 ls evict hazard + + output l2_cpu0_lrq_haz_pending; // cpu0 lrq hazard pending + output l2_cpu1_lrq_haz_pending; // cpu1 lrq hazard pending + output l2_cpu2_lrq_haz_pending; // cpu2 lrq hazard pending + output l2_cpu3_lrq_haz_pending; // cpu3 lrq hazard pending + + output l2_cpu0_ifq_haz_pending; // cpu0 ifq hazard pending + output l2_cpu1_ifq_haz_pending; // cpu1 ifq hazard pending + output l2_cpu2_ifq_haz_pending; // cpu2 ifq hazard pending + output l2_cpu3_ifq_haz_pending; // cpu3 ifq hazard pending + + output l2_cpu0_trq_haz_pending; // cpu0 trq hazard pending + output l2_cpu1_trq_haz_pending; // cpu1 trq hazard pending + output l2_cpu2_trq_haz_pending; // cpu2 trq hazard pending + output l2_cpu3_trq_haz_pending; // cpu3 trq hazard pending + + output l2_cpu0_wrq_haz_pending; // cpu0 wrq hazard pending + output l2_cpu1_wrq_haz_pending; // cpu1 wrq hazard pending + output l2_cpu2_wrq_haz_pending; // cpu2 wrq hazard pending + output l2_cpu3_wrq_haz_pending; // cpu3 wrq hazard pending + + output l2_cpu0_idle_block_reqs_q; // cpu0 idle block requests + output l2_cpu1_idle_block_reqs_q; // cpu1 idle block requests + output l2_cpu2_idle_block_reqs_q; // cpu2 idle block requests + output l2_cpu3_idle_block_reqs_q; // cpu3 idle block requests + + output l2_cpu0_ls_peq_coll_l4_dly; // cpu0 peq collision detected + output l2_cpu1_ls_peq_coll_l4_dly; // cpu1 peq collision detected + output l2_cpu2_ls_peq_coll_l4_dly; // cpu2 peq collision detected + output l2_cpu3_ls_peq_coll_l4_dly; // cpu3 peq collision detected + +//----------------------------------------------------------------------------- +// tag_pipe +//----------------------------------------------------------------------------- + output [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; // tbnk0 clear cpu0 lrq entry + output [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; // tbnk0 clear cpu1 lrq entry + output [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; // tbnk0 clear cpu2 lrq entry + output [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; // tbnk0 clear cpu3 lrq entry + + output [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; // tbnk1 clear cpu0 lrq entry + output [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; // tbnk1 clear cpu1 lrq entry + output [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; // tbnk1 clear cpu2 lrq entry + output [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; // tbnk1 clear cpu3 lrq entry + + output [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; // tbnk0 clear cpu0 ifq entry + output [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; // tbnk0 clear cpu1 ifq entry + output [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; // tbnk0 clear cpu2 ifq entry + output [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; // tbnk0 clear cpu3 ifq entry + + output [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; // tbnk1 clear cpu0 ifq entry + output [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; // tbnk1 clear cpu1 ifq entry + output [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; // tbnk1 clear cpu2 ifq entry + output [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; // tbnk1 clear cpu3 ifq entry + + output l2_tbnk0_cpu0_trq_clr_l4_dly2_q; // tbnk0 clear cpu0 trq entry + output l2_tbnk0_cpu1_trq_clr_l4_dly2_q; // tbnk0 clear cpu1 trq entry + output l2_tbnk0_cpu2_trq_clr_l4_dly2_q; // tbnk0 clear cpu2 trq entry + output l2_tbnk0_cpu3_trq_clr_l4_dly2_q; // tbnk0 clear cpu3 trq entry + + output l2_tbnk1_cpu0_trq_clr_l4_dly2_q; // tbnk1 clear cpu0 trq entry + output l2_tbnk1_cpu1_trq_clr_l4_dly2_q; // tbnk1 clear cpu1 trq entry + output l2_tbnk1_cpu2_trq_clr_l4_dly2_q; // tbnk1 clear cpu2 trq entry + output l2_tbnk1_cpu3_trq_clr_l4_dly2_q; // tbnk1 clear cpu3 trq entry + + output [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; // tbnk0 clear cpu0 wrq entry + output [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; // tbnk0 clear cpu1 wrq entry + output [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; // tbnk0 clear cpu2 wrq entry + output [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; // tbnk0 clear cpu3 wrq entry + + output [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; // tbnk1 clear cpu0 wrq entry + output [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; // tbnk1 clear cpu1 wrq entry + output [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; // tbnk1 clear cpu2 wrq entry + output [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; // tbnk1 clear cpu3 wrq entry + + +//----------------------------------------------------------------------------- +// cpu_logic / cpu slave +//----------------------------------------------------------------------------- + output l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu0 ls rd flsh l4 active + output l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu0 wr rd flsh l4 active + + output l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu1 ls rd flsh l4 active + output l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu1 wr rd flsh l4 active + + output l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu2 ls rd flsh l4 active + output l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu2 wr rd flsh l4 active + + output l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu3 ls rd flsh l4 active + output l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu3 wr rd flsh l4 active + + +//----------------------------------------------------------------------------- +// feq / cpu slave +//----------------------------------------------------------------------------- + input [129:0] l2_cpu0_dsq_rd_data_q; // cpu0 wrq/dsq data + input [15:0] l2_cpu0_dsq_rd_byte_strb_q; // cpu0 wrq/dsq byte strobes + input [129:0] l2_cpu1_dsq_rd_data_q; // cpu1 wrq/dsq data + input [15:0] l2_cpu1_dsq_rd_byte_strb_q; // cpu1 wrq/dsq byte strobes + input [129:0] l2_cpu2_dsq_rd_data_q; // cpu2 wrq/dsq data + input [15:0] l2_cpu2_dsq_rd_byte_strb_q; // cpu2 wrq/dsq byte strobes + input [129:0] l2_cpu3_dsq_rd_data_q; // cpu3 wrq/dsq data + input [15:0] l2_cpu3_dsq_rd_byte_strb_q; // cpu3 wrq/dsq byte strobes + + output l2_cpu0_dsq_clr_vld_q; // cpu0 dsq clear wrq vld entry + output [3:0] l2_cpu0_dsq_clr_id_q; // cpu0 dsq clear wrq buffer id + output l2_cpu0_dsq_rd_en; // cpu0 dsq/wrq data enable + output l2_cpu0_dsq_rd_en_x2; // cpu0 dsq/wrq data enable x2 + output [3:0] l2_cpu0_dsq_rd_buf_id; // cpu0 dsq/wrq data select + output l2_cpu1_dsq_clr_vld_q; // cpu1 dsq clear wrq vld entry + output [3:0] l2_cpu1_dsq_clr_id_q; // cpu1 dsq clear wrq buffer id + output l2_cpu1_dsq_rd_en; // cpu1 dsq/wrq data enable + output l2_cpu1_dsq_rd_en_x2; // cpu1 dsq/wrq data enable x2 + output [3:0] l2_cpu1_dsq_rd_buf_id; // cpu1 dsq/wrq data select + output l2_cpu2_dsq_clr_vld_q; // cpu2 dsq clear wrq vld entry + output [3:0] l2_cpu2_dsq_clr_id_q; // cpu2 dsq clear wrq buffer id + output l2_cpu2_dsq_rd_en; // cpu2 dsq/wrq data enable + output l2_cpu2_dsq_rd_en_x2; // cpu2 dsq/wrq data enable x2 + output [3:0] l2_cpu2_dsq_rd_buf_id; // cpu2 dsq/wrq data select + output l2_cpu3_dsq_clr_vld_q; // cpu3 dsq clear wrq vld entry + output l2_cpu3_dsq_rd_en; // cpu3 dsq/wrq data enable + output l2_cpu3_dsq_rd_en_x2; // cpu3 dsq/wrq data enable x2 + output [3:0] l2_cpu3_dsq_clr_id_q; // cpu3 dsq clear wrq buffer id + output [3:0] l2_cpu3_dsq_rd_buf_id; // cpu3 dsq/wrq data select + +//----------------------------------------------------------------------------- +// arbitration +//----------------------------------------------------------------------------- + output l2_cpu0_rd_vld_skid; // cpu0 read skid buffer valid + output l2_cpu1_rd_vld_skid; // cpu1 read skid buffer valid + output l2_cpu2_rd_vld_skid; // cpu2 read skid buffer valid + output l2_cpu3_rd_vld_skid; // cpu3 read skid buffer valid + + output l2_cpu0_pf_rd_vld_skid_popped; // cpu0 pf read skid buffer popped + output l2_cpu1_pf_rd_vld_skid_popped; // cpu1 pf read skid buffer popped + output l2_cpu2_pf_rd_vld_skid_popped; // cpu2 pf read skid buffer popped + output l2_cpu3_pf_rd_vld_skid_popped; // cpu3 pf read skid buffer popped + + output l2_cpu0_rd_arb; // + output l2_cpu1_rd_arb; // + output l2_cpu2_rd_arb; // + output l2_cpu3_rd_arb; // + + output l2_cpu0_wr_vld_skid; // cpu0 write skid buffer valid + output l2_cpu1_wr_vld_skid; // cpu1 write skid buffer valid + output l2_cpu2_wr_vld_skid; // cpu2 write skid buffer valid + output l2_cpu3_wr_vld_skid; // cpu3 write skid buffer valid + + output l2_cpu0_wr_arb; // + output l2_cpu1_wr_arb; // + output l2_cpu2_wr_arb; // + output l2_cpu3_wr_arb; // + + output l2_cpu0_ic_vld_skid; // cpu0 peripheral (ic) skid buffer valid + output l2_cpu1_ic_vld_skid; // cpu1 peripheral (ic) skid buffer valid + output l2_cpu2_ic_vld_skid; // cpu2 peripheral (ic) skid buffer valid + output l2_cpu3_ic_vld_skid; // cpu3 peripheral (ic) skid buffer valid + + output l2_cpu0_ic_barrier_stall_q; // cpu0 (ic) barrier stall + output l2_cpu1_ic_barrier_stall_q; // cpu1 (ic) barrier stall + output l2_cpu2_ic_barrier_stall_q; // cpu2 (ic) barrier stall + output l2_cpu3_ic_barrier_stall_q; // cpu3 (ic) barrier stall + + output l2_cpu0_blk_non_evict_wr; // cpu0 block non-evict writes from arbitrating + output l2_cpu1_blk_non_evict_wr; // cpu1 block non-evict writes from arbitrating + output l2_cpu2_blk_non_evict_wr; // cpu2 block non-evict writes from arbitrating + output l2_cpu3_blk_non_evict_wr; // cpu3 block non-evict writes from arbitrating + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + input l2_cpu0_idle_wakeup_q; // cpu0 idle wakeup + input l2_cpu0_rd_arb_fast; // cpu0 read arbitration fast request + input [4:0] l2_cpu0_rd_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu0_rd_lrq_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu0_rd_type_arb_set; // cpu0 read arbitration type + input [2:0] l2_cpu0_rd_cache_attr_arb_set; // cpu0 read arbitration cache attributes + input [7:0] l2_cpu0_rd_page_attr_arb_set; // cpu0 read arbitration page attributes + input [2:0] l2_cpu0_rd_elem_size_arb_set; // cpu0 read arbitration element size + input l2_cpu0_rd_way_arb_set; // cpu0 read arbitration way + input l2_cpu0_rd_replayed_arb_set; // cpu0 read arbitration replayed + input l2_cpu0_rd_excl_arb_set; // cpu0 read arbitration exclusive + input l2_cpu0_rd_priv_arb_set; // cpu0 read arbitration priv + input [1:0] l2_cpu0_rd_shared_arb_set; // cpu0 read arbitration shared + input l2_cpu0_rd_va48_arb_set; // cpu0 read arbitration va48 + input l2_cpu0_rd_aarch64_arb_set; // cpu0 read arbitration aarch64 + input [15:8] l2_cpu0_rd_asid_arb_set; // cpu0 read arbitration asid + input l2_cpu0_rd_prfm_arb_set; // cpu0 read arbitration prfm + input [44:0] l2_cpu0_rd_addr_arb_set; // cpu0 read arbitration address + input l2_cpu0_rd_bypass_arb_set; // cpu0 read arbitration bypass + input l2_cpu0_rd_bypass_req_can_e5; // cpu0 read arbitration bypass cancelled request + input l2_cpu0_early_rd_reqe4_e5_q; // cpu0 read arbitration bypass cancelled request + input l2_cpu0_rd_bypass_way_e5; // cpu0 read arbitration bypass way + input [2:0] l2_cpu0_rd_bypass_bufid_e5; // cpu0 read arbitration bypass bufid + input [2:0] l2_cpu0_rd_bypass_lrq_id_e5; // cpu0 read arbitration bypass bufid + + input l2_cpu0_wr_arb_fast; // cpu0 write arbitration fast request + input [3:0] l2_cpu0_wr_id_arb_set; // cpu0 write arbitration id for 1st qw + input [3:0] l2_cpu0_wr_partial_dw_arb_set; // cpu0 write partial qw byte strobe indicator + input [2:0] l2_cpu0_wr_cache_attr_arb_set; // cpu0 write arbitration cache attributes + input [7:0] l2_cpu0_wr_page_attr_arb_set; // cpu0 write arbitration page attributes + input [2:0] l2_cpu0_wr_elem_size_arb_set; // cpu0 write arbitration element size + input [2:0] l2_cpu0_wr_type_arb_set; // cpu0 write arbitration type + input [11:0] l2_cpu0_wr_cl_id_arb_set; // cpu0 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu0_wr_priv_arb_set; // cpu0 write arbitration priv + input [1:0] l2_cpu0_wr_shared_arb_set; // cpu0 write arbitration shared + input l2_cpu0_wr_last_arb_set; // cpu0 write arbitration last + input l2_cpu0_wr_clean_evict_arb_set; // cpu0 write arbitration clean eviction + input l2_cpu0_wr_err_arb_set; // cpu0 write arbitration error + input l2_cpu0_wr_way_arb_set; // cpu0 write arbitration way + input l2_cpu0_wr_dirty_arb_set; // cpu0 write arbitration dirty + input l2_cpu0_wr_1st_replayed_arb_set; // cpu0 write arbitration 1st replay indicator + input [44:0] l2_cpu0_wr_addr_arb_set; // cpu0 write arbitration address + input l2_cpu0_ic_arb_fast; // cpu0 peripheral (ic) arbitration fast request + input [2:0] l2_cpu0_ic_id_arb_set; // cpu0 peripheral (ic) fill buffer id + input l2_cpu0_ic_write_arb_set; // cpu0 peripheral (ic) write indicator + input l2_cpu0_ic_excl_arb_set; // cpu0 peripheral (ic) exclusive indicator + input [2:0] l2_cpu0_ic_elem_size_arb_set; // cpu0 peripheral (ic) element size + input l2_cpu0_ic_ns_arb_set; // cpu0 peripheral (ic) non-secure + input [15:0] l2_cpu0_ic_addr_arb_set; // cpu0 peripheral (ic) address + input [31:0] l2_cpu0_ic_data_arb_set; // cpu0 peripheral (ic) write data + + input l2_cpu0_wrq_almost_full; // cpu0 wrq almost full indicator + + input l2_cpu0_ls_wr_req_w2a; // cpu0 ls write request + input l2_cpu0_ls_wr_last_w2a; // cpu0 ls last indicator + input l2_cpu0_ls_wr_dirty_w2a; // cpu0 ls dirty indicator + input l2_cpu0_ls_wr_err_w2a; // cpu0 ls error indicator + input [2:0] l2_cpu0_ls_wr_type_w2a; // cpu0 ls write type + input [4:0] l2_cpu0_ls_wr_ccb_id_w2a; // cpu0 ls ccb id + input [127:0] l2_cpu0_ls_wr_data_w2a; // cpu0 ls write data + + input l2_cpu0_ls_ccb_resp; // cpu0 ls ccb resp + input [4:0] l2_cpu0_ls_ccb_resp_id; // cpu0 ls ccb id + input l2_cpu0_ls_ccb_data_wr; // cpu0 ls ccb data xfer + + input l2_cpu0_if_ccb_resp; // cpu0 if ccb resp + input [4:0] l2_cpu0_if_ccb_resp_id; // cpu0 if ccb id + + input l2_cpu0_tw_ccb_resp; // cpu0 tw ccb resp + input [4:0] l2_cpu0_tw_ccb_resp_id; // cpu0 tw ccb id + + input l2_cpu0_if_sync_done_q; // cpu0 sync response + input l2_cpu0_tlb_sync_done_q; // cpu0 tlb sync response + + input [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; // cpu0 lrq clear hazard id + input [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; // cpu0 wrq clear hazard id + input [3:0] l2_cpu0_ls_rd_haz_id_arb_q; // cpu0 ls rd wrq hazard id + input [2:0] l2_cpu0_ls_wr_haz_id_arb_q; // cpu0 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + input l2_cpu1_idle_wakeup_q; // cpu1 idle wakeup + input l2_cpu1_rd_arb_fast; // cpu1 read arbitration fast request + input [4:0] l2_cpu1_rd_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu1_rd_lrq_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu1_rd_type_arb_set; // cpu1 read arbitration type + input [2:0] l2_cpu1_rd_cache_attr_arb_set; // cpu1 read arbitration cache attributes + input [7:0] l2_cpu1_rd_page_attr_arb_set; // cpu1 read arbitration page attributes + input [2:0] l2_cpu1_rd_elem_size_arb_set; // cpu1 read arbitration element size + input l2_cpu1_rd_way_arb_set; // cpu1 read arbitration way + input l2_cpu1_rd_replayed_arb_set; // cpu1 read arbitration replayed + input l2_cpu1_rd_excl_arb_set; // cpu1 read arbitration exclusive + input l2_cpu1_rd_priv_arb_set; // cpu1 read arbitration priv + input [1:0] l2_cpu1_rd_shared_arb_set; // cpu1 read arbitration shared + input l2_cpu1_rd_va48_arb_set; // cpu1 read arbitration va48 + input l2_cpu1_rd_aarch64_arb_set; // cpu1 read arbitration aarch64 + input [15:8] l2_cpu1_rd_asid_arb_set; // cpu1 read arbitration asid + input l2_cpu1_rd_prfm_arb_set; // cpu1 read arbitration prfm + input [44:0] l2_cpu1_rd_addr_arb_set; // cpu1 read arbitration address + input l2_cpu1_rd_bypass_arb_set; // cpu1 read arbitration bypass + input l2_cpu1_rd_bypass_req_can_e5; // cpu1 read arbitration bypass cancelled request + input l2_cpu1_early_rd_reqe4_e5_q; // cpu1 read arbitration bypass cancelled request + input l2_cpu1_rd_bypass_way_e5; // cpu1 read arbitration bypass way + input [2:0] l2_cpu1_rd_bypass_bufid_e5; // cpu1 read arbitration bypass bufid + input [2:0] l2_cpu1_rd_bypass_lrq_id_e5; // cpu1 read arbitration bypass bufid + + input l2_cpu1_wr_arb_fast; // cpu1 write arbitration fast request + input [3:0] l2_cpu1_wr_id_arb_set; // cpu1 write arbitration id for 1st qw + input [3:0] l2_cpu1_wr_partial_dw_arb_set; // cpu1 write partial qw byte strobe indicator + input [2:0] l2_cpu1_wr_cache_attr_arb_set; // cpu1 write arbitration cache attributes + input [7:0] l2_cpu1_wr_page_attr_arb_set; // cpu1 write arbitration page attributes + input [2:0] l2_cpu1_wr_elem_size_arb_set; // cpu1 write arbitration element size + input [2:0] l2_cpu1_wr_type_arb_set; // cpu1 write arbitration type + input [11:0] l2_cpu1_wr_cl_id_arb_set; // cpu1 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu1_wr_priv_arb_set; // cpu1 write arbitration priv + input [1:0] l2_cpu1_wr_shared_arb_set; // cpu1 write arbitration shared + input l2_cpu1_wr_last_arb_set; // cpu1 write arbitration last + input l2_cpu1_wr_clean_evict_arb_set; // cpu1 write arbitration clean eviction + input l2_cpu1_wr_err_arb_set; // cpu1 write arbitration error + input l2_cpu1_wr_way_arb_set; // cpu1 write arbitration way + input l2_cpu1_wr_dirty_arb_set; // cpu1 write arbitration dirty + input l2_cpu1_wr_1st_replayed_arb_set; // cpu1 write arbitration 1st replay indicator + input [44:0] l2_cpu1_wr_addr_arb_set; // cpu1 write arbitration address + input l2_cpu1_ic_arb_fast; // cpu1 peripheral (ic) arbitration fast request + input [2:0] l2_cpu1_ic_id_arb_set; // cpu1 peripheral (ic) fill buffer id + input l2_cpu1_ic_write_arb_set; // cpu1 peripheral (ic) write indicator + input l2_cpu1_ic_excl_arb_set; // cpu1 peripheral (ic) exclusive indicator + input [2:0] l2_cpu1_ic_elem_size_arb_set; // cpu1 peripheral (ic) element size + input l2_cpu1_ic_ns_arb_set; // cpu1 peripheral (ic) non-secure + input [15:0] l2_cpu1_ic_addr_arb_set; // cpu1 peripheral (ic) address + input [31:0] l2_cpu1_ic_data_arb_set; // cpu1 peripheral (ic) write data + + input l2_cpu1_wrq_almost_full; // cpu1 wrq almost full indicator + + input l2_cpu1_ls_wr_req_w2a; // cpu1 ls write request + input l2_cpu1_ls_wr_last_w2a; // cpu1 ls last indicator + input l2_cpu1_ls_wr_dirty_w2a; // cpu1 ls dirty indicator + input l2_cpu1_ls_wr_err_w2a; // cpu1 ls error indicator + input [2:0] l2_cpu1_ls_wr_type_w2a; // cpu1 ls write type + input [4:0] l2_cpu1_ls_wr_ccb_id_w2a; // cpu1 ls ccb id + input [127:0] l2_cpu1_ls_wr_data_w2a; // cpu1 ls write data + + input l2_cpu1_ls_ccb_resp; // cpu1 ls ccb resp + input [4:0] l2_cpu1_ls_ccb_resp_id; // cpu1 ls ccb id + input l2_cpu1_ls_ccb_data_wr; // cpu1 ls ccb data xfer + + input l2_cpu1_if_ccb_resp; // cpu1 if ccb resp + input [4:0] l2_cpu1_if_ccb_resp_id; // cpu1 if ccb id + + input l2_cpu1_tw_ccb_resp; // cpu1 tw ccb resp + input [4:0] l2_cpu1_tw_ccb_resp_id; // cpu1 tw ccb id + + input l2_cpu1_if_sync_done_q; // cpu1 sync response + input l2_cpu1_tlb_sync_done_q; // cpu1 tlb sync response + + input [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; // cpu1 lrq clear hazard id + input [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; // cpu1 wrq clear hazard id + input [3:0] l2_cpu1_ls_rd_haz_id_arb_q; // cpu1 ls rd wrq hazard id + input [2:0] l2_cpu1_ls_wr_haz_id_arb_q; // cpu1 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + input l2_cpu2_idle_wakeup_q; // cpu2 idle wakeup + input l2_cpu2_rd_arb_fast; // cpu2 read arbitration fast request + input [4:0] l2_cpu2_rd_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu2_rd_lrq_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu2_rd_type_arb_set; // cpu2 read arbitration type + input [2:0] l2_cpu2_rd_cache_attr_arb_set; // cpu2 read arbitration cache attributes + input [7:0] l2_cpu2_rd_page_attr_arb_set; // cpu2 read arbitration page attributes + input [2:0] l2_cpu2_rd_elem_size_arb_set; // cpu2 read arbitration element size + input l2_cpu2_rd_way_arb_set; // cpu2 read arbitration way + input l2_cpu2_rd_replayed_arb_set; // cpu2 read arbitration replayed + input l2_cpu2_rd_excl_arb_set; // cpu2 read arbitration exclusive + input l2_cpu2_rd_priv_arb_set; // cpu2 read arbitration priv + input [1:0] l2_cpu2_rd_shared_arb_set; // cpu2 read arbitration shared + input l2_cpu2_rd_va48_arb_set; // cpu0 read arbitration va48 + input l2_cpu2_rd_aarch64_arb_set; // cpu2 read arbitration aarch64 + input [15:8] l2_cpu2_rd_asid_arb_set; // cpu2 read arbitration asid + input l2_cpu2_rd_prfm_arb_set; // cpu2 read arbitration prfm + input [44:0] l2_cpu2_rd_addr_arb_set; // cpu2 read arbitration address + input l2_cpu2_rd_bypass_arb_set; // cpu2 read arbitration bypass + input l2_cpu2_rd_bypass_req_can_e5; // cpu2 read arbitration bypass cancelled request + input l2_cpu2_early_rd_reqe4_e5_q; // cpu2 read arbitration bypass cancelled request + input l2_cpu2_rd_bypass_way_e5; // cpu2 read arbitration bypass way + input [2:0] l2_cpu2_rd_bypass_bufid_e5; // cpu2 read arbitration bypass bufid + input [2:0] l2_cpu2_rd_bypass_lrq_id_e5; // cpu2 read arbitration bypass bufid + + input l2_cpu2_wr_arb_fast; // cpu2 write arbitration fast request + input [3:0] l2_cpu2_wr_id_arb_set; // cpu2 write arbitration id for 1st qw + input [3:0] l2_cpu2_wr_partial_dw_arb_set; // cpu2 write partial qw byte strobe indicator + input [2:0] l2_cpu2_wr_cache_attr_arb_set; // cpu2 write arbitration cache attributes + input [7:0] l2_cpu2_wr_page_attr_arb_set; // cpu2 write arbitration page attributes + input [2:0] l2_cpu2_wr_elem_size_arb_set; // cpu2 write arbitration element size + input [2:0] l2_cpu2_wr_type_arb_set; // cpu2 write arbitration type + input [11:0] l2_cpu2_wr_cl_id_arb_set; // cpu2 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu2_wr_priv_arb_set; // cpu2 write arbitration priv + input [1:0] l2_cpu2_wr_shared_arb_set; // cpu2 write arbitration shared + input l2_cpu2_wr_last_arb_set; // cpu2 write arbitration last + input l2_cpu2_wr_clean_evict_arb_set; // cpu2 write arbitration clean eviction + input l2_cpu2_wr_err_arb_set; // cpu2 write arbitration error + input l2_cpu2_wr_way_arb_set; // cpu2 write arbitration way + input l2_cpu2_wr_dirty_arb_set; // cpu2 write arbitration dirty + input l2_cpu2_wr_1st_replayed_arb_set; // cpu2 write arbitration 1st replay indicator + input [44:0] l2_cpu2_wr_addr_arb_set; // cpu2 write arbitration address + input l2_cpu2_ic_arb_fast; // cpu2 peripheral (ic) arbitration fast request + input [2:0] l2_cpu2_ic_id_arb_set; // cpu2 peripheral (ic) fill buffer id + input l2_cpu2_ic_write_arb_set; // cpu2 peripheral (ic) write indicator + input l2_cpu2_ic_excl_arb_set; // cpu2 peripheral (ic) exclusive indicator + input [2:0] l2_cpu2_ic_elem_size_arb_set; // cpu2 peripheral (ic) element size + input l2_cpu2_ic_ns_arb_set; // cpu2 peripheral (ic) non-secure + input [15:0] l2_cpu2_ic_addr_arb_set; // cpu2 peripheral (ic) address + input [31:0] l2_cpu2_ic_data_arb_set; // cpu2 peripheral (ic) write data + + input l2_cpu2_wrq_almost_full; // cpu2 wrq almost full indicator + + input l2_cpu2_ls_wr_req_w2a; // cpu2 ls write request + input l2_cpu2_ls_wr_last_w2a; // cpu2 ls last indicator + input l2_cpu2_ls_wr_dirty_w2a; // cpu2 ls dirty indicator + input l2_cpu2_ls_wr_err_w2a; // cpu2 ls error indicator + input [2:0] l2_cpu2_ls_wr_type_w2a; // cpu2 ls write type + input [4:0] l2_cpu2_ls_wr_ccb_id_w2a; // cpu2 ls ccb id + input [127:0] l2_cpu2_ls_wr_data_w2a; // cpu2 ls write data + + input l2_cpu2_ls_ccb_resp; // cpu2 ls ccb resp + input [4:0] l2_cpu2_ls_ccb_resp_id; // cpu2 ls ccb id + input l2_cpu2_ls_ccb_data_wr; // cpu2 ls ccb data xfer + + input l2_cpu2_if_ccb_resp; // cpu2 if ccb resp + input [4:0] l2_cpu2_if_ccb_resp_id; // cpu2 if ccb id + + input l2_cpu2_tw_ccb_resp; // cpu2 tw ccb resp + input [4:0] l2_cpu2_tw_ccb_resp_id; // cpu2 tw ccb id + + input l2_cpu2_if_sync_done_q; // cpu2 sync response + input l2_cpu2_tlb_sync_done_q; // cpu2 tlb sync response + + input [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; // cpu2 lrq clear hazard id + input [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; // cpu2 wrq clear hazard id + input [3:0] l2_cpu2_ls_rd_haz_id_arb_q; // cpu2 ls rd wrq hazard id + input [2:0] l2_cpu2_ls_wr_haz_id_arb_q; // cpu2 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + input l2_cpu3_idle_wakeup_q; // cpu3 idle wakeup + input l2_cpu3_rd_arb_fast; // cpu3 read arbitration fast request + input [4:0] l2_cpu3_rd_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu3_rd_lrq_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu3_rd_type_arb_set; // cpu3 read arbitration type + input [2:0] l2_cpu3_rd_cache_attr_arb_set; // cpu3 read arbitration cache attributes + input [7:0] l2_cpu3_rd_page_attr_arb_set; // cpu3 read arbitration page attributes + input [2:0] l2_cpu3_rd_elem_size_arb_set; // cpu3 read arbitration element size + input l2_cpu3_rd_way_arb_set; // cpu3 read arbitration way + input l2_cpu3_rd_replayed_arb_set; // cpu3 read arbitration replayed + input l2_cpu3_rd_excl_arb_set; // cpu3 read arbitration exclusive + input l2_cpu3_rd_priv_arb_set; // cpu3 read arbitration priv + input [1:0] l2_cpu3_rd_shared_arb_set; // cpu3 read arbitration shared + input l2_cpu3_rd_va48_arb_set; // cpu3 read arbitration va48 + input l2_cpu3_rd_aarch64_arb_set; // cpu3 read arbitration aarch64 + input [15:8] l2_cpu3_rd_asid_arb_set; // cpu3 read arbitration asid + input l2_cpu3_rd_prfm_arb_set; // cpu3 read arbitration prfm + input [44:0] l2_cpu3_rd_addr_arb_set; // cpu3 read arbitration address + input l2_cpu3_rd_bypass_arb_set; // cpu3 read arbitration bypass + input l2_cpu3_rd_bypass_req_can_e5; // cpu3 read arbitration bypass cancelled request + input l2_cpu3_early_rd_reqe4_e5_q; // cpu3 read arbitration bypass cancelled request + input l2_cpu3_rd_bypass_way_e5; // cpu3 read arbitration bypass way + input [2:0] l2_cpu3_rd_bypass_bufid_e5; // cpu3 read arbitration bypass bufid + input [2:0] l2_cpu3_rd_bypass_lrq_id_e5; // cpu3 read arbitration bypass bufid + + input l2_cpu3_wr_arb_fast; // cpu3 write arbitration fast request + input [3:0] l2_cpu3_wr_id_arb_set; // cpu3 write arbitration id for 1st qw + input [3:0] l2_cpu3_wr_partial_dw_arb_set; // cpu3 write partial qw byte strobe indicator + input [2:0] l2_cpu3_wr_cache_attr_arb_set; // cpu3 write arbitration cache attributes + input [7:0] l2_cpu3_wr_page_attr_arb_set; // cpu3 write arbitration page attributes + input [2:0] l2_cpu3_wr_elem_size_arb_set; // cpu3 write arbitration element size + input [2:0] l2_cpu3_wr_type_arb_set; // cpu3 write arbitration type + input [11:0] l2_cpu3_wr_cl_id_arb_set; // cpu3 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu3_wr_priv_arb_set; // cpu3 write arbitration priv + input [1:0] l2_cpu3_wr_shared_arb_set; // cpu3 write arbitration shared + input l2_cpu3_wr_last_arb_set; // cpu3 write arbitration last + input l2_cpu3_wr_clean_evict_arb_set; // cpu3 write arbitration clean eviction + input l2_cpu3_wr_err_arb_set; // cpu3 write arbitration error + input l2_cpu3_wr_way_arb_set; // cpu3 write arbitration way + input l2_cpu3_wr_dirty_arb_set; // cpu3 write arbitration dirty + input l2_cpu3_wr_1st_replayed_arb_set; // cpu3 write arbitration 1st replay indicator + input [44:0] l2_cpu3_wr_addr_arb_set; // cpu3 write arbitration address + input l2_cpu3_ic_arb_fast; // cpu3 peripheral (ic) arbitration fast request + input [2:0] l2_cpu3_ic_id_arb_set; // cpu3 peripheral (ic) fill buffer id + input l2_cpu3_ic_write_arb_set; // cpu3 peripheral (ic) write indicator + input l2_cpu3_ic_excl_arb_set; // cpu3 peripheral (ic) exclusive indicator + input [2:0] l2_cpu3_ic_elem_size_arb_set; // cpu3 peripheral (ic) element size + input l2_cpu3_ic_ns_arb_set; // cpu3 peripheral (ic) non-secure + input [15:0] l2_cpu3_ic_addr_arb_set; // cpu3 peripheral (ic) address + input [31:0] l2_cpu3_ic_data_arb_set; // cpu3 peripheral (ic) write data + + input l2_cpu3_wrq_almost_full; // cpu3 wrq almost full indicator + + input l2_cpu3_ls_wr_req_w2a; // cpu3 ls write request + input l2_cpu3_ls_wr_last_w2a; // cpu3 ls last indicator + input l2_cpu3_ls_wr_dirty_w2a; // cpu3 ls dirty indicator + input l2_cpu3_ls_wr_err_w2a; // cpu3 ls error indicator + input [2:0] l2_cpu3_ls_wr_type_w2a; // cpu3 ls write type + input [4:0] l2_cpu3_ls_wr_ccb_id_w2a; // cpu3 ls ccb id + input [127:0] l2_cpu3_ls_wr_data_w2a; // cpu3 ls write data + + input l2_cpu3_ls_ccb_resp; // cpu3 ls ccb resp + input [4:0] l2_cpu3_ls_ccb_resp_id; // cpu3 ls ccb id + input l2_cpu3_ls_ccb_data_wr; // cpu3 ls ccb data xfer + + input l2_cpu3_if_ccb_resp; // cpu3 if ccb resp + input [4:0] l2_cpu3_if_ccb_resp_id; // cpu3 if ccb id + + input l2_cpu3_tw_ccb_resp; // cpu3 tw ccb resp + input [4:0] l2_cpu3_tw_ccb_resp_id; // cpu3 tw ccb id + + input l2_cpu3_if_sync_done_q; // cpu3 sync response + input l2_cpu3_tlb_sync_done_q; // cpu3 tlb sync response + + input [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; // cpu3 lrq clear hazard id + input [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; // cpu3 wrq clear hazard id + input [3:0] l2_cpu3_ls_rd_haz_id_arb_q; // cpu3 ls rd wrq hazard id + input [2:0] l2_cpu3_ls_wr_haz_id_arb_q; // cpu3 ls wr lrq hazard id + +// END L2-CPU interface + +//------------------------------------------------------------------- +// TM interface +//------------------------------------------------------------------- +// BEGIN TIMER-CPU interface + output [3:0] tm_cpu0_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu0_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu1_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu1_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu2_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu2_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu3_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu3_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> +// END TIMER-CPU interface + +//----------------------------------------------------------------------------- +// IC interface +//----------------------------------------------------------------------------- + input ls_cpu0_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu0_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu0_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu0_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu0_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu0_raw_eae_secure; // LS S LPAE to IC + + input ds_cpu0_ic_sample_spr; + input [4:0] ds_cpu0_ic_cpsr_mode; + input ds_cpu0_ic_aa64naa32; + input ds_cpu0_ic_hcr_change; + input ds_cpu0_ic_scr_change; +// BEGIN INCLUDE FOR CPU1 + input ds_cpu1_ic_sample_spr; + input [4:0] ds_cpu1_ic_cpsr_mode; + input ds_cpu1_ic_aa64naa32; + input ds_cpu1_ic_hcr_change; + input ds_cpu1_ic_scr_change; + input ls_cpu1_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu1_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu1_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu1_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu1_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu1_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input ds_cpu2_ic_sample_spr; + input [4:0] ds_cpu2_ic_cpsr_mode; + input ds_cpu2_ic_aa64naa32; + input ds_cpu2_ic_hcr_change; + input ds_cpu2_ic_scr_change; + input ls_cpu2_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu2_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu2_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu2_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu2_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu2_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input ds_cpu3_ic_sample_spr; + input [4:0] ds_cpu3_ic_cpsr_mode; + input ds_cpu3_ic_aa64naa32; + input ds_cpu3_ic_hcr_change; + input ds_cpu3_ic_scr_change; + input ls_cpu3_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu3_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu3_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu3_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu3_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu3_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU3 + + output [`MAIA_CN:0] ic_nfiq; // IC physical FIQ + output [`MAIA_CN:0] ic_nirq; // IC physical IRQ + output [`MAIA_CN:0] ic_nsei; // IC physical SEI + output [`MAIA_CN:0] ic_nvfiq; // IC virtual FIQ + output [`MAIA_CN:0] ic_nvirq; // IC virtual IRQ + output [`MAIA_CN:0] ic_nvsei; // IC virtual SEI + output [`MAIA_CN:0] ic_p_valid; // IC is present + + output [`MAIA_CN:0] ic_sample_spr; // IC sample signal for TC, TALL*, EL* signals + output [`MAIA_CN:0] ic_hcr_change_complete; + output [`MAIA_CN:0] ic_scr_change_complete; + output [`MAIA_CN:0] ic_el_change_complete; + output [`MAIA_CN:0] ic_ich_el2_tc; // IC trap common + output [`MAIA_CN:0] ic_ich_el2_tall0; // IC trap all grp0 + output [`MAIA_CN:0] ic_ich_el2_tall1; // IC trap all grp1 + output [`MAIA_CN:0] ic_sra_el3_en; // IC System Registers enabled in EL3 + output [`MAIA_CN:0] ic_sra_el1s_en; // IC System Registers enabled in EL1S + output [`MAIA_CN:0] ic_sra_el2_en; // IC System Registers enabled in EL2 + output [`MAIA_CN:0] ic_sra_el1ns_en; // IC System Registers enabled in EL1NS + output [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; // IC HYP_TRAP EL1NS accesses + output [`MAIA_CN:0] ic_sre_el1ns_mon_trap; // IC MON_TRAP EL1NS accesses + output [`MAIA_CN:0] ic_sre_el1s_mon_trap; // IC MON_TRAP EL1S accesses + output [`MAIA_CN:0] ic_sre_el2_mon_trap; // IC MON_TRAP EL2 accesses + output [`MAIA_CN:0] ic_block_eoi_sgi_wr; // IC Block all EOI and SGI write accesses + +//----------------------------------------------------------------------------- +// DT interface +//----------------------------------------------------------------------------- +// BEGIN DT-CPU interface +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + output dt_cpu0_dbif_req_pclk; // Debug Interface Req + output dt_cpu0_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu0_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu0_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu0_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu0_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu0_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu0_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu0_edbgrq_pclk; // External Debug Request + output dt_cpu0_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu0_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu0_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu0_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu0_et_oslock_gclk; // ETM OS Lock + input dt_cpu0_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu0_halt_ack_gclk; // Core Halted + input dt_cpu0_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu0_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu0_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu0_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu0_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu0_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu0_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu0_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu0_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu0_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu0_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu0_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu0_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu0_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu0_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + output dt_cpu1_dbif_req_pclk; // Debug Interface Req + output dt_cpu1_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu1_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu1_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu1_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu1_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu1_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu1_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu1_edbgrq_pclk; // External Debug Request + output dt_cpu1_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu1_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu1_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu1_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu1_et_oslock_gclk; // ETM OS Lock + input dt_cpu1_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu1_halt_ack_gclk; // Core Halted + input dt_cpu1_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu1_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu1_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu1_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu1_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu1_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu1_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu1_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu1_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu1_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu1_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu1_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu1_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu1_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu1_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + output dt_cpu2_dbif_req_pclk; // Debug Interface Req + output dt_cpu2_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu2_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu2_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu2_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu2_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu2_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu2_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu2_edbgrq_pclk; // External Debug Request + output dt_cpu2_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu2_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu2_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu2_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu2_et_oslock_gclk; // ETM OS Lock + input dt_cpu2_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu2_halt_ack_gclk; // Core Halted + input dt_cpu2_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu2_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu2_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu2_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu2_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu2_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu2_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu2_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu2_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu2_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu2_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu2_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu2_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu2_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu2_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + output dt_cpu3_dbif_req_pclk; // Debug Interface Req + output dt_cpu3_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu3_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu3_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu3_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu3_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu3_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu3_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu3_edbgrq_pclk; // External Debug Request + output dt_cpu3_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu3_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu3_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu3_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu3_et_oslock_gclk; // ETM OS Lock + input dt_cpu3_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu3_halt_ack_gclk; // Core Halted + input dt_cpu3_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu3_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu3_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu3_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu3_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu3_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu3_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu3_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu3_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu3_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu3_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu3_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu3_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu3_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu3_noclkstop_pclk; // force CPU clock on from DT-PCLK +// END DT-CPU interface + +//----------------------------------------------------------------------------- +// CK interface +//----------------------------------------------------------------------------- +// BEGIN CK-CPU interface + input ds_cpu0_reset_req; // Warm Reset request + input ds_cpu0_wfi_req; // WFI request + input ds_cpu0_wfe_req; // WFI request + input ds_cpu0_flush; // flush for exception rtn + input [5:0] ds_cpu0_flush_type; // flush type + input ds_cpu0_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu0_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu0_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu0_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu0_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu0_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu0_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu0_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu0_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu0_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu0_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu0_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu0_hcr_va; // virtual abort + input ds_cpu0_hcr_vi; // virtual IRQ + input ds_cpu0_hcr_vf; // virtual FIQ + input [2:0] ds_cpu0_cpuectlr_ret; // CPU Retention control + output ck_cpu0_event_reg; // WFE event reg + output ck_cpu0_wfi_ack; // WFI acknowledge to DS + output ck_cpu0_wfe_ack; // WFE acknowledge to DS + output ck_cpu0_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu1_reset_req; // Warm Reset request + input ds_cpu1_wfi_req; // WFI request + input ds_cpu1_wfe_req; // WFI request + input ds_cpu1_flush; // flush for exception rtn + input [5:0] ds_cpu1_flush_type; // flush type + input ds_cpu1_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu1_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu1_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu1_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu1_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu1_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu1_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu1_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu1_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu1_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu1_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu1_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu1_hcr_va; // virtual abort + input ds_cpu1_hcr_vi; // virtual IRQ + input ds_cpu1_hcr_vf; // virtual FIQ + input [2:0] ds_cpu1_cpuectlr_ret; // CPU Retention control + output ck_cpu1_event_reg; // WFE event reg + output ck_cpu1_wfi_ack; // WFI acknowledge to DS + output ck_cpu1_wfe_ack; // WFE acknowledge to DS + output ck_cpu1_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu2_reset_req; // Warm Reset request + input ds_cpu2_wfi_req; // WFI request + input ds_cpu2_wfe_req; // WFI request + input ds_cpu2_flush; // flush for exception rtn + input [5:0] ds_cpu2_flush_type; // flush type + input ds_cpu2_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu2_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu2_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu2_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu2_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu2_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu2_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu2_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu2_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu2_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu2_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu2_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu2_hcr_va; // virtual abort + input ds_cpu2_hcr_vi; // virtual IRQ + input ds_cpu2_hcr_vf; // virtual FIQ + input [2:0] ds_cpu2_cpuectlr_ret; // CPU Retention control + output ck_cpu2_event_reg; // WFE event reg + output ck_cpu2_wfi_ack; // WFI acknowledge to DS + output ck_cpu2_wfe_ack; // WFE acknowledge to DS + output ck_cpu2_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu3_reset_req; // Warm Reset request + input ds_cpu3_wfi_req; // WFI request + input ds_cpu3_wfe_req; // WFI request + input ds_cpu3_flush; // flush for exception rtn + input [5:0] ds_cpu3_flush_type; // flush type + input ds_cpu3_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu3_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu3_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu3_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu3_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu3_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu3_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu3_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu3_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu3_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu3_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu3_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu3_hcr_va; // virtual abort + input ds_cpu3_hcr_vi; // virtual IRQ + input ds_cpu3_hcr_vf; // virtual FIQ + input [2:0] ds_cpu3_cpuectlr_ret; // CPU Retention control + output ck_cpu3_event_reg; // WFE event reg + output ck_cpu3_wfi_ack; // WFI acknowledge to DS + output ck_cpu3_wfe_ack; // WFE acknowledge to DS + output ck_cpu3_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ls_cpu0_clrexmon; // LS global exclusive monitor + input ls_cpu1_clrexmon; // LS global exclusive monitor + input ls_cpu2_clrexmon; // LS global exclusive monitor + input ls_cpu3_clrexmon; // LS global exclusive monitor + +// END CK-CPU interface + + output [`MAIA_CN:0] ck_gclkt; + + + + // wires + wire ck_areset_l2; + wire ck_cpu0_areset_l2cpu; + wire ck_cpu0_areset_l2dt; + wire ck_cpu0_commrx; + wire ck_cpu0_commtx; + wire ck_cpu0_crcx_clk_en_n_ic; + wire ck_cpu0_dbgnopwrdwn; + wire ck_cpu0_dbgrstreq; + wire ck_cpu0_dt_standbywfx; + wire ck_cpu0_dt_wfx_ack; + wire ck_cpu0_l2_standbywfi; + wire ck_cpu0_l2_standbywfx; + wire ck_cpu0_ncommirq; + wire ck_cpu0_npmuirq; + wire ck_cpu0_poreset_status; + wire ck_cpu0_reset1_n_l2cpu; + wire ck_cpu0_reset1_n_l2dt; + wire ck_cpu1_areset_l2cpu; + wire ck_cpu1_areset_l2dt; + wire ck_cpu1_commrx; + wire ck_cpu1_commtx; + wire ck_cpu1_crcx_clk_en_n_ic; + wire ck_cpu1_dbgnopwrdwn; + wire ck_cpu1_dbgrstreq; + wire ck_cpu1_dt_standbywfx; + wire ck_cpu1_dt_wfx_ack; + wire ck_cpu1_l2_standbywfi; + wire ck_cpu1_l2_standbywfx; + wire ck_cpu1_ncommirq; + wire ck_cpu1_npmuirq; + wire ck_cpu1_poreset_status; + wire ck_cpu1_reset1_n_l2cpu; + wire ck_cpu1_reset1_n_l2dt; + wire ck_cpu2_areset_l2cpu; + wire ck_cpu2_areset_l2dt; + wire ck_cpu2_commrx; + wire ck_cpu2_commtx; + wire ck_cpu2_crcx_clk_en_n_ic; + wire ck_cpu2_dbgnopwrdwn; + wire ck_cpu2_dbgrstreq; + wire ck_cpu2_dt_standbywfx; + wire ck_cpu2_dt_wfx_ack; + wire ck_cpu2_l2_standbywfi; + wire ck_cpu2_l2_standbywfx; + wire ck_cpu2_ncommirq; + wire ck_cpu2_npmuirq; + wire ck_cpu2_poreset_status; + wire ck_cpu2_reset1_n_l2cpu; + wire ck_cpu2_reset1_n_l2dt; + wire ck_cpu3_areset_l2cpu; + wire ck_cpu3_areset_l2dt; + wire ck_cpu3_commrx; + wire ck_cpu3_commtx; + wire ck_cpu3_crcx_clk_en_n_ic; + wire ck_cpu3_dbgnopwrdwn; + wire ck_cpu3_dbgrstreq; + wire ck_cpu3_dt_standbywfx; + wire ck_cpu3_dt_wfx_ack; + wire ck_cpu3_l2_standbywfi; + wire ck_cpu3_l2_standbywfx; + wire ck_cpu3_ncommirq; + wire ck_cpu3_npmuirq; + wire ck_cpu3_poreset_status; + wire ck_cpu3_reset1_n_l2cpu; + wire ck_cpu3_reset1_n_l2dt; + wire ck_dt_cpu0_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu0_cti_trigin_1to0_gclk; + wire ck_dt_cpu0_et_oslock_gclk; + wire ck_dt_cpu0_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu0_os_double_lock_gclk; + wire ck_dt_cpu0_pmusnapshot_ack_gclk; + wire ck_dt_cpu0_wfx_dbg_req_gclk; + wire ck_dt_cpu1_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu1_cti_trigin_1to0_gclk; + wire ck_dt_cpu1_et_oslock_gclk; + wire ck_dt_cpu1_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu1_os_double_lock_gclk; + wire ck_dt_cpu1_pmusnapshot_ack_gclk; + wire ck_dt_cpu1_wfx_dbg_req_gclk; + wire ck_dt_cpu2_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu2_cti_trigin_1to0_gclk; + wire ck_dt_cpu2_et_oslock_gclk; + wire ck_dt_cpu2_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu2_os_double_lock_gclk; + wire ck_dt_cpu2_pmusnapshot_ack_gclk; + wire ck_dt_cpu2_wfx_dbg_req_gclk; + wire ck_dt_cpu3_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu3_cti_trigin_1to0_gclk; + wire ck_dt_cpu3_et_oslock_gclk; + wire ck_dt_cpu3_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu3_os_double_lock_gclk; + wire ck_dt_cpu3_pmusnapshot_ack_gclk; + wire ck_dt_cpu3_wfx_dbg_req_gclk; + wire ck_gclkb0; + wire ck_gclkb1; + wire ck_gclkfr; + wire ck_gclkl2; + wire ck_gclktl2; + wire ck_l2_ace_inactive; + wire ck_l2_acp_inactive; + wire ck_l2_logic_clk_en; + wire ck_l2_sky_link_deactivate; + wire ck_l2_tbnk0_clk_en; + wire ck_l2_tbnk1_clk_en; + wire ck_reset1_n_l2; + wire clrexmon_c1; + wire ds_cpu0_ic_aa64naa32_i; + wire [4:0] ds_cpu0_ic_cpsr_mode_i; + wire ds_cpu0_ic_hcr_change_i; + wire ds_cpu0_ic_sample_spr_i; + wire ds_cpu0_ic_scr_change_i; + wire ds_cpu1_ic_aa64naa32_i; + wire [4:0] ds_cpu1_ic_cpsr_mode_i; + wire ds_cpu1_ic_hcr_change_i; + wire ds_cpu1_ic_sample_spr_i; + wire ds_cpu1_ic_scr_change_i; + wire ds_cpu2_ic_aa64naa32_i; + wire [4:0] ds_cpu2_ic_cpsr_mode_i; + wire ds_cpu2_ic_hcr_change_i; + wire ds_cpu2_ic_sample_spr_i; + wire ds_cpu2_ic_scr_change_i; + wire ds_cpu3_ic_aa64naa32_i; + wire [4:0] ds_cpu3_ic_cpsr_mode_i; + wire ds_cpu3_ic_hcr_change_i; + wire ds_cpu3_ic_sample_spr_i; + wire ds_cpu3_ic_scr_change_i; + wire dt_cpu0_apb_active_pclk; + wire dt_cpu0_poreset_status_ack_pclk; + wire dt_cpu0_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu0_wfx_wakeup_pclk; + wire dt_cpu1_apb_active_pclk; + wire dt_cpu1_poreset_status_ack_pclk; + wire dt_cpu1_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu1_wfx_wakeup_pclk; + wire dt_cpu2_apb_active_pclk; + wire dt_cpu2_poreset_status_ack_pclk; + wire dt_cpu2_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu2_wfx_wakeup_pclk; + wire dt_cpu3_apb_active_pclk; + wire dt_cpu3_poreset_status_ack_pclk; + wire dt_cpu3_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu3_wfx_wakeup_pclk; + wire eventi_sev; + wire [`MAIA_CN:0] ic_block_eoi_sgi_wr_o; + wire ic_cpu0_l2_dsb_block; + wire [63:0] ic_cpu0_spr_rd_data; + wire ic_cpu1_l2_dsb_block; + wire [63:0] ic_cpu1_spr_rd_data; + wire ic_cpu2_l2_dsb_block; + wire [63:0] ic_cpu2_spr_rd_data; + wire ic_cpu3_l2_dsb_block; + wire [63:0] ic_cpu3_spr_rd_data; + wire [`MAIA_CN:0] ic_el_change_complete_o; + wire [`MAIA_CN:0] ic_hcr_change_complete_o; + wire [`MAIA_CN:0] ic_ich_el2_tall0_o; + wire [`MAIA_CN:0] ic_ich_el2_tall1_o; + wire [`MAIA_CN:0] ic_ich_el2_tc_o; + wire [`MAIA_CN:0] ic_nfiq_o; + wire [`MAIA_CN:0] ic_nirq_o; + wire [`MAIA_CN:0] ic_nsei_o; + wire [`MAIA_CN:0] ic_nvfiq_o; + wire [`MAIA_CN:0] ic_nvirq_o; + wire [`MAIA_CN:0] ic_nvsei_o; + wire [31:0] ic_p_rdata; + wire ic_p_rdata_valid; + wire ic_p_ready; + wire [`MAIA_CN:0] ic_sample_spr_o; + wire [`MAIA_CN:0] ic_scr_change_complete_o; + wire [`MAIA_CN:0] ic_sra_el1ns_en_o; + wire [`MAIA_CN:0] ic_sra_el1s_en_o; + wire [`MAIA_CN:0] ic_sra_el2_en_o; + wire [`MAIA_CN:0] ic_sra_el3_en_o; + wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap_o; + wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap_o; + wire [`MAIA_CN:0] ic_sre_el1s_mon_trap_o; + wire [`MAIA_CN:0] ic_sre_el2_mon_trap_o; + wire l2_acp_flsh_rd_cnt_active_glb_l2_dly; + wire l2_acp_flsh_wr_cnt_active_glb_l2_dly; + wire l2_acp_rd_haz_vld_l2_dly_q; + wire l2_acp_wr_haz_vld_l2_dly_q; + wire l2_actlr_disable_b2b_setway_hzd_opt_x2_ns; + wire l2_actlr_disable_setway_opt; + wire l2_actlr_ncpu_rcg_enable; + wire l2_actlr_plru_dynamic; + wire l2_actlr_plru_en; + wire [1:0] l2_actlr_plru_mode; + wire l2_actlr_writeunique_disable; + wire l2_cfg_broadcastinner; + wire l2_cfg_broadcastouter; + wire l2_cpu0_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu0_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu0_snp_active; + wire l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_wr_decerr_q; + wire l2_cpu0_wr_slverr_q; + wire l2_cpu1_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu1_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu1_snp_active; + wire l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_wr_decerr_q; + wire l2_cpu1_wr_slverr_q; + wire l2_cpu2_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu2_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu2_snp_active; + wire l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_wr_decerr_q; + wire l2_cpu2_wr_slverr_q; + wire l2_cpu3_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu3_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu3_snp_active; + wire l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_wr_decerr_q; + wire l2_cpu3_wr_slverr_q; + wire l2_ctlr_x1_wr_q; + wire [9:0] l2_ctlr_x2_ns; + wire l2_idle; + wire [`MAIA_CN:0] l2_mbist1_en_b1; + wire [16:0] l2_mbist2_tbnk0_addr_b1; + wire l2_mbist2_tbnk0_all_b1; + wire [2:0] l2_mbist2_tbnk0_array_b1; + wire [17:0] l2_mbist2_tbnk0_be_b1; + wire l2_mbist2_tbnk0_en_b1; + wire [143:0] l2_mbist2_tbnk0_indata_b1; + wire [143:0] l2_mbist2_tbnk0_outdata_b3; + wire l2_mbist2_tbnk0_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp0_outdata_b2; + wire l2_mbist2_tbnk0_snp0_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp0_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp1_outdata_b2; + wire l2_mbist2_tbnk0_snp1_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp1_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp2_outdata_b2; + wire l2_mbist2_tbnk0_snp2_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp2_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp3_outdata_b2; + wire l2_mbist2_tbnk0_snp3_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp3_sel_b1; + wire l2_mbist2_tbnk0_wr_en_b1; + wire [16:0] l2_mbist2_tbnk1_addr_b1; + wire l2_mbist2_tbnk1_all_b1; + wire [2:0] l2_mbist2_tbnk1_array_b1; + wire [17:0] l2_mbist2_tbnk1_be_b1; + wire l2_mbist2_tbnk1_en_b1; + wire [143:0] l2_mbist2_tbnk1_indata_b1; + wire [143:0] l2_mbist2_tbnk1_outdata_b3; + wire l2_mbist2_tbnk1_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp0_outdata_b2; + wire l2_mbist2_tbnk1_snp0_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp0_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp1_outdata_b2; + wire l2_mbist2_tbnk1_snp1_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp1_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp2_outdata_b2; + wire l2_mbist2_tbnk1_snp2_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp2_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp3_outdata_b2; + wire l2_mbist2_tbnk1_snp3_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp3_sel_b1; + wire l2_mbist2_tbnk1_wr_en_b1; + wire l2_no_ram_acc_nxt_cycle; + wire [13:0] l2_p_addr; + wire [1:0] l2_p_cpu; + wire l2_p_nsecure; + wire [2:0] l2_p_sel; + wire [31:0] l2_p_wdata; + wire l2_p_write; + wire l2_reset3; + wire l2_rstdisable_x1_q; + wire l2_sky_link_stopped; + wire l2_tbnk0_addr44_l3_q; + wire [44:0] l2_tbnk0_addr_l1; + wire [5:2] l2_tbnk0_addr_l6; + wire l2_tbnk0_all_tag_incl_active_l3; + wire l2_tbnk0_asq_cmp_evict_l3_q; + wire l2_tbnk0_asq_full_flsh; + wire l2_tbnk0_asq_nc_so_dev_limit; + wire [2:0] l2_tbnk0_cache_attr_l1; + wire l2_tbnk0_cfg_ecc_en; + wire l2_tbnk0_cmo_setway_l2_inv_incl_l4; + wire l2_tbnk0_cpu0_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu0_hit_l4; + wire l2_tbnk0_cpu0_l2_inv_l4_dly2; + wire l2_tbnk0_cpu0_l2hit_e_l4; + wire l2_tbnk0_cpu0_l2hit_s_l4; + wire l2_tbnk0_cpu0_peq_full_q; + wire l2_tbnk0_cpu0_peq_hit_q; + wire l2_tbnk0_cpu0_peq_self_evict_l3_q; + wire l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu0_rd_access_l4_dly; + wire l2_tbnk0_cpu0_self_evict_l4_dly_q; + wire l2_tbnk0_cpu0_single_ecc_err_l7_q; + wire l2_tbnk0_cpu0_snp_hit_e_l3; + wire l2_tbnk0_cpu0_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu0_snp_setway_addr_l3; + wire l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu0_vld_nxt_l5; + wire l2_tbnk0_cpu0_wr_access_l4_dly; + wire l2_tbnk0_cpu1_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu1_hit_l4; + wire l2_tbnk0_cpu1_l2_inv_l4_dly2; + wire l2_tbnk0_cpu1_l2hit_e_l4; + wire l2_tbnk0_cpu1_l2hit_s_l4; + wire l2_tbnk0_cpu1_peq_full_q; + wire l2_tbnk0_cpu1_peq_hit_q; + wire l2_tbnk0_cpu1_peq_self_evict_l3_q; + wire l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu1_rd_access_l4_dly; + wire l2_tbnk0_cpu1_self_evict_l4_dly_q; + wire l2_tbnk0_cpu1_single_ecc_err_l7_q; + wire l2_tbnk0_cpu1_snp_hit_e_l3; + wire l2_tbnk0_cpu1_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu1_snp_setway_addr_l3; + wire l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu1_vld_nxt_l5; + wire l2_tbnk0_cpu1_wr_access_l4_dly; + wire l2_tbnk0_cpu2_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu2_hit_l4; + wire l2_tbnk0_cpu2_l2_inv_l4_dly2; + wire l2_tbnk0_cpu2_l2hit_e_l4; + wire l2_tbnk0_cpu2_l2hit_s_l4; + wire l2_tbnk0_cpu2_peq_full_q; + wire l2_tbnk0_cpu2_peq_hit_q; + wire l2_tbnk0_cpu2_peq_self_evict_l3_q; + wire l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu2_rd_access_l4_dly; + wire l2_tbnk0_cpu2_self_evict_l4_dly_q; + wire l2_tbnk0_cpu2_single_ecc_err_l7_q; + wire l2_tbnk0_cpu2_snp_hit_e_l3; + wire l2_tbnk0_cpu2_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu2_snp_setway_addr_l3; + wire l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu2_vld_nxt_l5; + wire l2_tbnk0_cpu2_wr_access_l4_dly; + wire l2_tbnk0_cpu3_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu3_hit_l4; + wire l2_tbnk0_cpu3_l2_inv_l4_dly2; + wire l2_tbnk0_cpu3_l2hit_e_l4; + wire l2_tbnk0_cpu3_l2hit_s_l4; + wire l2_tbnk0_cpu3_peq_full_q; + wire l2_tbnk0_cpu3_peq_hit_q; + wire l2_tbnk0_cpu3_peq_self_evict_l3_q; + wire l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu3_rd_access_l4_dly; + wire l2_tbnk0_cpu3_self_evict_l4_dly_q; + wire l2_tbnk0_cpu3_single_ecc_err_l7_q; + wire l2_tbnk0_cpu3_snp_hit_e_l3; + wire l2_tbnk0_cpu3_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu3_snp_setway_addr_l3; + wire l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu3_vld_nxt_l5; + wire l2_tbnk0_cpu3_wr_access_l4_dly; + wire [3:0] l2_tbnk0_cpu_rvalid_init_nxt_l5; + wire [3:0] l2_tbnk0_cpu_rvalid_nxt_l5; + wire [3:0] l2_tbnk0_cpu_snp_hit_e_l4_q; + wire l2_tbnk0_crit_qw_nxt_l5; + wire [143:0] l2_tbnk0_data_corrected_l7_q; + wire [127:0] l2_tbnk0_data_l6; + wire l2_tbnk0_dbg_ram_acc_l5a; + wire [2:0] l2_tbnk0_dbg_ram_acc_unit_nxt; + wire [7:0] l2_tbnk0_dbg_ram_id_nxt_l5; + wire l2_tbnk0_dirty_l1; + wire l2_tbnk0_dirty_l3_q; + wire l2_tbnk0_dis_ns_dbg_arr_acc_x2; + wire l2_tbnk0_double_ecc_err_l7_q; + wire l2_tbnk0_early_rvalid_l4_q; + wire l2_tbnk0_ecc_fixup_blk_arb; + wire l2_tbnk0_ecc_fixup_inprog_dly_q; + wire l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q; + wire [31:0] l2_tbnk0_ecc_syndrome_reg_q; + wire l2_tbnk0_evict_special_hazard_l3_q; + wire l2_tbnk0_evict_special_hazard_rwvic_l3_q; + wire l2_tbnk0_excl_l1; + wire l2_tbnk0_excl_l4_q; + wire [44:6] l2_tbnk0_feq_addr_upd; + wire l2_tbnk0_feq_alloc_failed_l4; + wire l2_tbnk0_feq_axi_wr_vld_not_popped; + wire l2_tbnk0_feq_clr_l4; + wire [15:0] l2_tbnk0_feq_frc_incl_l3a; + wire l2_tbnk0_feq_kill_l3; + wire [4:0] l2_tbnk0_feq_last_id_q; + wire l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3; + wire l2_tbnk0_feq_tbnk_id_update_or_l3; + wire l2_tbnk0_full_miss_l4_q; + wire l2_tbnk0_hit_l4; + wire l2_tbnk0_hit_l7_q; + wire [3:0] l2_tbnk0_hit_way_l4_q; + wire [9:0] l2_tbnk0_id_l1; + wire [9:0] l2_tbnk0_id_l6_q; + wire [9:0] l2_tbnk0_id_nxt_l5; + wire l2_tbnk0_idle; + wire l2_tbnk0_init_req_l1; + wire l2_tbnk0_kill_l2; + wire l2_tbnk0_l2bb_fake_wr_l1; + wire l2_tbnk0_l2bb_wr_l1; + wire l2_tbnk0_l2hit_e_l4; + wire l2_tbnk0_l2hit_s_l4; + wire l2_tbnk0_l2v_s_q; + wire l2_tbnk0_l2v_vld_q; + wire l2_tbnk0_last_qw_l1; + wire l2_tbnk0_last_qw_l6_q; + wire l2_tbnk0_last_qw_nxt_l5; + wire [2:0] l2_tbnk0_lock_l1; + wire [2:0] l2_tbnk0_lock_l4; + wire [32:0] l2_tbnk0_merrsr_data; + wire [9:0] l2_tbnk0_page_attr_l1; + wire l2_tbnk0_partial_dw_wr_l1; + wire l2_tbnk0_pf_cnt_dec_l4_dly; + wire l2_tbnk0_pf_hazard_l3; + wire l2_tbnk0_pf_req_sel_for_fwd_l4; + wire l2_tbnk0_prfm_l1; + wire l2_tbnk0_prfm_nxt_l5; + wire [3:0] l2_tbnk0_prot_l1; + wire [3:0] l2_tbnk0_prot_l4_q; + wire [1:0] l2_tbnk0_qw_cnt_l1; + wire [1:0] l2_tbnk0_qw_cnt_l3_q; + wire l2_tbnk0_raw_hit_l4_q; + wire [2:0] l2_tbnk0_rbufid_nxt_l5; + wire l2_tbnk0_rd_en_nxt_l5; + wire l2_tbnk0_rd_fail_hazchk_feq_l3; + wire l2_tbnk0_rwvic_axi_read_err_l1; + wire l2_tbnk0_rwvic_axi_read_err_l3_q; + wire l2_tbnk0_rwvic_ccb_dirty_l6_q; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l1; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l3_q; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l6_q; + wire [3:0] l2_tbnk0_rwvic_ccb_way_l1; + wire l2_tbnk0_rwvic_cmo_clean_l1; + wire l2_tbnk0_rwvic_cmo_inv_l1; + wire l2_tbnk0_rwvic_cmo_inv_l7_q; + wire l2_tbnk0_rwvic_cmo_l7_q; + wire l2_tbnk0_rwvic_cmo_pou_l1; + wire l2_tbnk0_rwvic_cmo_pou_l6_q; + wire l2_tbnk0_rwvic_cmo_setway_l1; + wire l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1; + wire l2_tbnk0_rwvic_cmo_setway_ls_l6_q; + wire [2:0] l2_tbnk0_rwvic_cpu_fb_id_l1; + wire [3:0] l2_tbnk0_rwvic_cpu_id_dcd_l1; + wire l2_tbnk0_rwvic_ddi_l6_q; + wire l2_tbnk0_rwvic_feq_cmp_l3_q; + wire l2_tbnk0_rwvic_frc_l2hit_fwd_l1; + wire l2_tbnk0_rwvic_l2hit_e_l1; + wire l2_tbnk0_rwvic_l2hit_e_l3_q; + wire l2_tbnk0_rwvic_l2hit_e_l7_q; + wire l2_tbnk0_rwvic_l2v_dirty_l7_q; + wire [3:0] l2_tbnk0_rwvic_l2v_page_attr_l7_q; + wire l2_tbnk0_rwvic_l2v_vld_l6_q; + wire l2_tbnk0_rwvic_mesi_sh_l1; + wire l2_tbnk0_rwvic_non_snp_fail_hazchk_l3; + wire [2:0] l2_tbnk0_rwvic_owner_l1; + wire [2:0] l2_tbnk0_rwvic_owner_l7_q; + wire l2_tbnk0_rwvic_rd_type_l6_q; + wire l2_tbnk0_rwvic_snp_clr_dirty_l1; + wire l2_tbnk0_rwvic_snp_inv_l1; + wire l2_tbnk0_rwvic_snp_l1; + wire l2_tbnk0_rwvic_snp_l3_q; + wire l2_tbnk0_rwvic_snp_l6_q; + wire l2_tbnk0_rwvic_tag_wr_l0; + wire [3:0] l2_tbnk0_rwvic_type_l1; + wire l2_tbnk0_rwvic_wa_l1; + wire l2_tbnk0_rwvic_wa_l6_q; + wire [13:0] l2_tbnk0_sel_l1; + wire [2:0] l2_tbnk0_size_l1; + wire [2:0] l2_tbnk0_size_l4_q; + wire l2_tbnk0_snp_byp_peq_haz_pending_q; + wire l2_tbnk0_snp_dvm_cmpl_l1; + wire l2_tbnk0_snp_hit_e_l4_q; + wire l2_tbnk0_snp_hit_feq_evict_l4_dly; + wire l2_tbnk0_snp_hit_s_l4_q; + wire [4:0] l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q; + wire [7:0] l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q; + wire [7:0] l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q; + wire [44:7] l2_tbnk0_snp_tag_wr_l2_hit_addr_l1; + wire [1:0] l2_tbnk0_snp_tag_wr_l2_hit_state_l1; + wire l2_tbnk0_snp_tag_wr_l2_hit_way_l1; + wire l2_tbnk0_special_evict_hazard_l3; + wire l2_tbnk0_special_hazard_l3_q; + wire l2_tbnk0_sync_l1; + wire l2_tbnk0_tag_ecc_dbl_rmw_wr_l1; + wire l2_tbnk0_tag_ecc_err_cpu0_l4; + wire l2_tbnk0_tag_ecc_err_cpu1_l4; + wire l2_tbnk0_tag_ecc_err_cpu2_l4; + wire l2_tbnk0_tag_ecc_err_cpu3_l4; + wire l2_tbnk0_tag_ecc_err_l4; + wire [6:0] l2_tbnk0_type_l1; + wire [1:0] l2_tbnk0_ulen_l1; + wire [1:0] l2_tbnk0_ulen_l4_q; + wire l2_tbnk0_vld_init_l6_q; + wire l2_tbnk0_vld_l6_q; + wire l2_tbnk0_way_l1; + wire l2_tbnk0_way_l4_q; + wire l2_tbnk0_way_nxt_l3a; + wire [143:0] l2_tbnk0_wr_data_l3; + wire [127:0] l2_tbnk0_wr_data_l3a_q; + wire l2_tbnk0_wr_data_l4_en; + wire l2_tbnk0_wr_err_l1; + wire l2_tbnk0_wr_fail_feq_full_l3; + wire l2_tbnk0_wr_fail_hazchk_feq_l3; + wire [11:0] l2_tbnk0_wr_non_crit_id_l1; + wire [11:0] l2_tbnk0_wr_non_crit_id_l4_q; + wire [15:0] l2_tbnk0_wr_strb_mask_l3a_q; + wire l2_tbnk1_addr44_l3_q; + wire [44:0] l2_tbnk1_addr_l1; + wire [5:2] l2_tbnk1_addr_l6; + wire l2_tbnk1_all_tag_incl_active_l3; + wire l2_tbnk1_asq_cmp_evict_l3_q; + wire l2_tbnk1_asq_full_flsh; + wire l2_tbnk1_asq_nc_so_dev_limit; + wire [2:0] l2_tbnk1_cache_attr_l1; + wire l2_tbnk1_cfg_ecc_en; + wire l2_tbnk1_cmo_setway_l2_inv_incl_l4; + wire l2_tbnk1_cpu0_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu0_hit_l4; + wire l2_tbnk1_cpu0_l2_inv_l4_dly2; + wire l2_tbnk1_cpu0_l2hit_e_l4; + wire l2_tbnk1_cpu0_l2hit_s_l4; + wire l2_tbnk1_cpu0_peq_full_q; + wire l2_tbnk1_cpu0_peq_hit_q; + wire l2_tbnk1_cpu0_peq_self_evict_l3_q; + wire l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu0_rd_access_l4_dly; + wire l2_tbnk1_cpu0_self_evict_l4_dly_q; + wire l2_tbnk1_cpu0_single_ecc_err_l7_q; + wire l2_tbnk1_cpu0_snp_hit_e_l3; + wire l2_tbnk1_cpu0_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu0_snp_setway_addr_l3; + wire l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu0_vld_nxt_l5; + wire l2_tbnk1_cpu0_wr_access_l4_dly; + wire l2_tbnk1_cpu1_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu1_hit_l4; + wire l2_tbnk1_cpu1_l2_inv_l4_dly2; + wire l2_tbnk1_cpu1_l2hit_e_l4; + wire l2_tbnk1_cpu1_l2hit_s_l4; + wire l2_tbnk1_cpu1_peq_full_q; + wire l2_tbnk1_cpu1_peq_hit_q; + wire l2_tbnk1_cpu1_peq_self_evict_l3_q; + wire l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu1_rd_access_l4_dly; + wire l2_tbnk1_cpu1_self_evict_l4_dly_q; + wire l2_tbnk1_cpu1_single_ecc_err_l7_q; + wire l2_tbnk1_cpu1_snp_hit_e_l3; + wire l2_tbnk1_cpu1_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu1_snp_setway_addr_l3; + wire l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu1_vld_nxt_l5; + wire l2_tbnk1_cpu1_wr_access_l4_dly; + wire l2_tbnk1_cpu2_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu2_hit_l4; + wire l2_tbnk1_cpu2_l2_inv_l4_dly2; + wire l2_tbnk1_cpu2_l2hit_e_l4; + wire l2_tbnk1_cpu2_l2hit_s_l4; + wire l2_tbnk1_cpu2_peq_full_q; + wire l2_tbnk1_cpu2_peq_hit_q; + wire l2_tbnk1_cpu2_peq_self_evict_l3_q; + wire l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu2_rd_access_l4_dly; + wire l2_tbnk1_cpu2_self_evict_l4_dly_q; + wire l2_tbnk1_cpu2_single_ecc_err_l7_q; + wire l2_tbnk1_cpu2_snp_hit_e_l3; + wire l2_tbnk1_cpu2_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu2_snp_setway_addr_l3; + wire l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu2_vld_nxt_l5; + wire l2_tbnk1_cpu2_wr_access_l4_dly; + wire l2_tbnk1_cpu3_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu3_hit_l4; + wire l2_tbnk1_cpu3_l2_inv_l4_dly2; + wire l2_tbnk1_cpu3_l2hit_e_l4; + wire l2_tbnk1_cpu3_l2hit_s_l4; + wire l2_tbnk1_cpu3_peq_full_q; + wire l2_tbnk1_cpu3_peq_hit_q; + wire l2_tbnk1_cpu3_peq_self_evict_l3_q; + wire l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu3_rd_access_l4_dly; + wire l2_tbnk1_cpu3_self_evict_l4_dly_q; + wire l2_tbnk1_cpu3_single_ecc_err_l7_q; + wire l2_tbnk1_cpu3_snp_hit_e_l3; + wire l2_tbnk1_cpu3_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu3_snp_setway_addr_l3; + wire l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu3_vld_nxt_l5; + wire l2_tbnk1_cpu3_wr_access_l4_dly; + wire [3:0] l2_tbnk1_cpu_rvalid_init_nxt_l5; + wire [3:0] l2_tbnk1_cpu_rvalid_nxt_l5; + wire [3:0] l2_tbnk1_cpu_snp_hit_e_l4_q; + wire l2_tbnk1_crit_qw_nxt_l5; + wire [143:0] l2_tbnk1_data_corrected_l7_q; + wire [127:0] l2_tbnk1_data_l6; + wire l2_tbnk1_dbg_ram_acc_l5a; + wire [2:0] l2_tbnk1_dbg_ram_acc_unit_nxt; + wire [7:0] l2_tbnk1_dbg_ram_id_nxt_l5; + wire l2_tbnk1_dirty_l1; + wire l2_tbnk1_dirty_l3_q; + wire l2_tbnk1_dis_ns_dbg_arr_acc_x2; + wire l2_tbnk1_double_ecc_err_l7_q; + wire l2_tbnk1_early_rvalid_l4_q; + wire l2_tbnk1_ecc_fixup_blk_arb; + wire l2_tbnk1_ecc_fixup_inprog_dly_q; + wire l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q; + wire [31:0] l2_tbnk1_ecc_syndrome_reg_q; + wire l2_tbnk1_evict_special_hazard_l3_q; + wire l2_tbnk1_evict_special_hazard_rwvic_l3_q; + wire l2_tbnk1_excl_l1; + wire l2_tbnk1_excl_l4_q; + wire [44:6] l2_tbnk1_feq_addr_upd; + wire l2_tbnk1_feq_alloc_failed_l4; + wire l2_tbnk1_feq_axi_wr_vld_not_popped; + wire l2_tbnk1_feq_clr_l4; + wire [15:0] l2_tbnk1_feq_frc_incl_l3a; + wire l2_tbnk1_feq_kill_l3; + wire [4:0] l2_tbnk1_feq_last_id_q; + wire l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3; + wire l2_tbnk1_feq_tbnk_id_update_or_l3; + wire l2_tbnk1_full_miss_l4_q; + wire l2_tbnk1_hit_l4; + wire l2_tbnk1_hit_l7_q; + wire [3:0] l2_tbnk1_hit_way_l4_q; + wire [9:0] l2_tbnk1_id_l1; + wire [9:0] l2_tbnk1_id_l6_q; + wire [9:0] l2_tbnk1_id_nxt_l5; + wire l2_tbnk1_idle; + wire l2_tbnk1_init_req_l1; + wire l2_tbnk1_kill_l2; + wire l2_tbnk1_l2bb_fake_wr_l1; + wire l2_tbnk1_l2bb_wr_l1; + wire l2_tbnk1_l2hit_e_l4; + wire l2_tbnk1_l2hit_s_l4; + wire l2_tbnk1_l2v_s_q; + wire l2_tbnk1_l2v_vld_q; + wire l2_tbnk1_last_qw_l1; + wire l2_tbnk1_last_qw_l6_q; + wire l2_tbnk1_last_qw_nxt_l5; + wire [2:0] l2_tbnk1_lock_l1; + wire [2:0] l2_tbnk1_lock_l4; + wire [32:0] l2_tbnk1_merrsr_data; + wire [9:0] l2_tbnk1_page_attr_l1; + wire l2_tbnk1_partial_dw_wr_l1; + wire l2_tbnk1_pf_cnt_dec_l4_dly; + wire l2_tbnk1_pf_hazard_l3; + wire l2_tbnk1_pf_req_sel_for_fwd_l4; + wire l2_tbnk1_prfm_l1; + wire l2_tbnk1_prfm_nxt_l5; + wire [3:0] l2_tbnk1_prot_l1; + wire [3:0] l2_tbnk1_prot_l4_q; + wire [1:0] l2_tbnk1_qw_cnt_l1; + wire [1:0] l2_tbnk1_qw_cnt_l3_q; + wire l2_tbnk1_raw_hit_l4_q; + wire [2:0] l2_tbnk1_rbufid_nxt_l5; + wire l2_tbnk1_rd_en_nxt_l5; + wire l2_tbnk1_rd_fail_hazchk_feq_l3; + wire l2_tbnk1_rwvic_axi_read_err_l1; + wire l2_tbnk1_rwvic_axi_read_err_l3_q; + wire l2_tbnk1_rwvic_ccb_dirty_l6_q; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l1; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l3_q; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l6_q; + wire [3:0] l2_tbnk1_rwvic_ccb_way_l1; + wire l2_tbnk1_rwvic_cmo_clean_l1; + wire l2_tbnk1_rwvic_cmo_inv_l1; + wire l2_tbnk1_rwvic_cmo_inv_l7_q; + wire l2_tbnk1_rwvic_cmo_l7_q; + wire l2_tbnk1_rwvic_cmo_pou_l1; + wire l2_tbnk1_rwvic_cmo_pou_l6_q; + wire l2_tbnk1_rwvic_cmo_setway_l1; + wire l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1; + wire l2_tbnk1_rwvic_cmo_setway_ls_l6_q; + wire [2:0] l2_tbnk1_rwvic_cpu_fb_id_l1; + wire [3:0] l2_tbnk1_rwvic_cpu_id_dcd_l1; + wire l2_tbnk1_rwvic_ddi_l6_q; + wire l2_tbnk1_rwvic_feq_cmp_l3_q; + wire l2_tbnk1_rwvic_frc_l2hit_fwd_l1; + wire l2_tbnk1_rwvic_l2hit_e_l1; + wire l2_tbnk1_rwvic_l2hit_e_l3_q; + wire l2_tbnk1_rwvic_l2hit_e_l7_q; + wire l2_tbnk1_rwvic_l2v_dirty_l7_q; + wire [3:0] l2_tbnk1_rwvic_l2v_page_attr_l7_q; + wire l2_tbnk1_rwvic_l2v_vld_l6_q; + wire l2_tbnk1_rwvic_mesi_sh_l1; + wire l2_tbnk1_rwvic_non_snp_fail_hazchk_l3; + wire [2:0] l2_tbnk1_rwvic_owner_l1; + wire [2:0] l2_tbnk1_rwvic_owner_l7_q; + wire l2_tbnk1_rwvic_rd_type_l6_q; + wire l2_tbnk1_rwvic_snp_clr_dirty_l1; + wire l2_tbnk1_rwvic_snp_inv_l1; + wire l2_tbnk1_rwvic_snp_l1; + wire l2_tbnk1_rwvic_snp_l3_q; + wire l2_tbnk1_rwvic_snp_l6_q; + wire l2_tbnk1_rwvic_tag_wr_l0; + wire [3:0] l2_tbnk1_rwvic_type_l1; + wire l2_tbnk1_rwvic_wa_l1; + wire l2_tbnk1_rwvic_wa_l6_q; + wire [13:0] l2_tbnk1_sel_l1; + wire [2:0] l2_tbnk1_size_l1; + wire [2:0] l2_tbnk1_size_l4_q; + wire l2_tbnk1_snp_byp_peq_haz_pending_q; + wire l2_tbnk1_snp_dvm_cmpl_l1; + wire l2_tbnk1_snp_hit_e_l4_q; + wire l2_tbnk1_snp_hit_feq_evict_l4_dly; + wire l2_tbnk1_snp_hit_s_l4_q; + wire [4:0] l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q; + wire [7:0] l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q; + wire [7:0] l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q; + wire [44:7] l2_tbnk1_snp_tag_wr_l2_hit_addr_l1; + wire [1:0] l2_tbnk1_snp_tag_wr_l2_hit_state_l1; + wire l2_tbnk1_snp_tag_wr_l2_hit_way_l1; + wire l2_tbnk1_special_evict_hazard_l3; + wire l2_tbnk1_special_hazard_l3_q; + wire l2_tbnk1_sync_l1; + wire l2_tbnk1_tag_ecc_dbl_rmw_wr_l1; + wire l2_tbnk1_tag_ecc_err_cpu0_l4; + wire l2_tbnk1_tag_ecc_err_cpu1_l4; + wire l2_tbnk1_tag_ecc_err_cpu2_l4; + wire l2_tbnk1_tag_ecc_err_cpu3_l4; + wire l2_tbnk1_tag_ecc_err_l4; + wire [6:0] l2_tbnk1_type_l1; + wire [1:0] l2_tbnk1_ulen_l1; + wire [1:0] l2_tbnk1_ulen_l4_q; + wire l2_tbnk1_vld_init_l6_q; + wire l2_tbnk1_vld_l6_q; + wire l2_tbnk1_way_l1; + wire l2_tbnk1_way_l4_q; + wire l2_tbnk1_way_nxt_l3a; + wire [143:0] l2_tbnk1_wr_data_l3; + wire [127:0] l2_tbnk1_wr_data_l3a_q; + wire l2_tbnk1_wr_data_l4_en; + wire l2_tbnk1_wr_err_l1; + wire l2_tbnk1_wr_fail_feq_full_l3; + wire l2_tbnk1_wr_fail_hazchk_feq_l3; + wire [11:0] l2_tbnk1_wr_non_crit_id_l1; + wire [11:0] l2_tbnk1_wr_non_crit_id_l4_q; + wire [15:0] l2_tbnk1_wr_strb_mask_l3a_q; + wire l2_tbnk_hwrst_done_x2; + wire [13:0] l2_tbnk_hwrst_idx_x1_q; + wire [8:0] tm_cntpct_q; + wire tm_cpu0_event_sev; + wire [63:0] tm_cpu0_spr_rd_data; + wire tm_cpu1_event_sev; + wire [63:0] tm_cpu1_spr_rd_data; + wire tm_cpu2_event_sev; + wire [63:0] tm_cpu2_spr_rd_data; + wire tm_cpu3_event_sev; + wire [63:0] tm_cpu3_spr_rd_data; + wire [63:0] tm_tval_cpu0_spr_rd_data; + wire [63:0] tm_tval_cpu1_spr_rd_data; + wire [63:0] tm_tval_cpu2_spr_rd_data; + wire [63:0] tm_tval_cpu3_spr_rd_data; + + maia_timer utm( // outputs + .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), + .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), + .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), + .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tm_cpu0_event_sev (tm_cpu0_event_sev), + .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), + .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tm_cpu1_event_sev (tm_cpu1_event_sev), + .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), + .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tm_cpu2_event_sev (tm_cpu2_event_sev), + .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), + .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tm_cpu3_event_sev (tm_cpu3_event_sev), + .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), + .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), + .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), + .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), + .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]), + + // inputs + .CNTCLKEN (CNTCLKEN), + .CNTVALUEB (CNTVALUEB[63:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .ck_areset_l2 (ck_areset_l2), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .eventi_sev (eventi_sev), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable) + ); // utm + + maia_l2_logic_feq20_s ul2_logic( // outputs + .ARREADYS (ARREADYS), + .AWREADYS (AWREADYS), + .BIDS (BIDS[4:0]), + .BRESPS (BRESPS[1:0]), + .BVALIDS (BVALIDS), + .L2FLUSHDONE (L2FLUSHDONE), + .L2QACCEPTn (L2QACCEPTn), + .L2QACTIVE (L2QACTIVE), + .L2QDENY (L2QDENY), + .RDATAS (RDATAS[127:0]), + .REQMEMATTR (REQMEMATTR[7:0]), + .RIDS (RIDS[4:0]), + .RLASTS (RLASTS), + .RRESPS (RRESPS[1:0]), + .RVALIDS (RVALIDS), + .RXDATLCRDV (RXDATLCRDV), + .RXLINKACTIVEACK (RXLINKACTIVEACK), + .RXRSPLCRDV (RXRSPLCRDV), + .RXSNPLCRDV (RXSNPLCRDV), + .TXDATFLIT (TXDATFLIT[193:0]), + .TXDATFLITPEND (TXDATFLITPEND), + .TXDATFLITV (TXDATFLITV), + .TXLINKACTIVEREQ (TXLINKACTIVEREQ), + .TXREQFLIT (TXREQFLIT[99:0]), + .TXREQFLITPEND (TXREQFLITPEND), + .TXREQFLITV (TXREQFLITV), + .TXRSPFLIT (TXRSPFLIT[44:0]), + .TXRSPFLITPEND (TXRSPFLITPEND), + .TXRSPFLITV (TXRSPFLITV), + .TXSACTIVE (TXSACTIVE), + .WREADYS (WREADYS), + .ck_areset_l2 (ck_areset_l2), + .ck_l2_logic_clk_en (ck_l2_logic_clk_en), + .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), + .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu0_barrier_done (l2_cpu0_barrier_done), + .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddbl_ecc_err_r3), + .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idbl_ecc_err_r3), + .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu0_rd_arb (l2_cpu0_rd_arb), + .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu0_rexfail (l2_cpu0_rexfail), + .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu0_rvalid (l2_cpu0_rvalid), + .l2_cpu0_snp_active (l2_cpu0_snp_active), + .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu0_spec_valid (l2_cpu0_spec_valid), + .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu0_wr_arb (l2_cpu0_wr_arb), + .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu0_wr_decerr_q (l2_cpu0_wr_decerr_q), + .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu0_wr_slverr_q (l2_cpu0_wr_slverr_q), + .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu1_barrier_done (l2_cpu1_barrier_done), + .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddbl_ecc_err_r3), + .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idbl_ecc_err_r3), + .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu1_rd_arb (l2_cpu1_rd_arb), + .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu1_rexfail (l2_cpu1_rexfail), + .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu1_rvalid (l2_cpu1_rvalid), + .l2_cpu1_snp_active (l2_cpu1_snp_active), + .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu1_spec_valid (l2_cpu1_spec_valid), + .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu1_wr_arb (l2_cpu1_wr_arb), + .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu1_wr_decerr_q (l2_cpu1_wr_decerr_q), + .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu1_wr_slverr_q (l2_cpu1_wr_slverr_q), + .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu2_barrier_done (l2_cpu2_barrier_done), + .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddbl_ecc_err_r3), + .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idbl_ecc_err_r3), + .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu2_rd_arb (l2_cpu2_rd_arb), + .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu2_rexfail (l2_cpu2_rexfail), + .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu2_rvalid (l2_cpu2_rvalid), + .l2_cpu2_snp_active (l2_cpu2_snp_active), + .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu2_spec_valid (l2_cpu2_spec_valid), + .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu2_wr_arb (l2_cpu2_wr_arb), + .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu2_wr_decerr_q (l2_cpu2_wr_decerr_q), + .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu2_wr_slverr_q (l2_cpu2_wr_slverr_q), + .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu3_barrier_done (l2_cpu3_barrier_done), + .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddbl_ecc_err_r3), + .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idbl_ecc_err_r3), + .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu3_rd_arb (l2_cpu3_rd_arb), + .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu3_rexfail (l2_cpu3_rexfail), + .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu3_rvalid (l2_cpu3_rvalid), + .l2_cpu3_snp_active (l2_cpu3_snp_active), + .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu3_spec_valid (l2_cpu3_spec_valid), + .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu3_wr_arb (l2_cpu3_wr_arb), + .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu3_wr_decerr_q (l2_cpu3_wr_decerr_q), + .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu3_wr_slverr_q (l2_cpu3_wr_slverr_q), + .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_idle (l2_idle), + .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), + .l2_mbist2_tbnk0_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), + .l2_mbist2_tbnk0_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), + .l2_mbist2_tbnk0_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), + .l2_mbist2_tbnk0_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), + .l2_mbist2_tbnk1_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), + .l2_mbist2_tbnk1_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), + .l2_mbist2_tbnk1_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), + .l2_mbist2_tbnk1_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_p_addr (l2_p_addr[13:0]), + .l2_p_cpu (l2_p_cpu[1:0]), + .l2_p_nsecure (l2_p_nsecure), + .l2_p_sel (l2_p_sel[2:0]), + .l2_p_wdata (l2_p_wdata[31:0]), + .l2_p_write (l2_p_write), + .l2_reset3 (l2_reset3), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_sky_link_stopped (l2_sky_link_stopped), + .l2_tbnk0_addr_l1 (l2_tbnk0_addr_l1[44:0]), + .l2_tbnk0_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), + .l2_tbnk0_asq_full_flsh (l2_tbnk0_asq_full_flsh), + .l2_tbnk0_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), + .l2_tbnk0_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), + .l2_tbnk0_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), + .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), + .l2_tbnk0_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), + .l2_tbnk0_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), + .l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), + .l2_tbnk0_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), + .l2_tbnk0_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), + .l2_tbnk0_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), + .l2_tbnk0_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), + .l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), + .l2_tbnk0_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), + .l2_tbnk0_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), + .l2_tbnk0_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), + .l2_tbnk0_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), + .l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), + .l2_tbnk0_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), + .l2_tbnk0_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), + .l2_tbnk0_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), + .l2_tbnk0_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), + .l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), + .l2_tbnk0_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), + .l2_tbnk0_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_dirty_l1 (l2_tbnk0_dirty_l1), + .l2_tbnk0_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), + .l2_tbnk0_excl_l1 (l2_tbnk0_excl_l1), + .l2_tbnk0_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), + .l2_tbnk0_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), + .l2_tbnk0_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), + .l2_tbnk0_feq_kill_l3 (l2_tbnk0_feq_kill_l3), + .l2_tbnk0_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), + .l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk0_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), + .l2_tbnk0_id_l1 (l2_tbnk0_id_l1[9:0]), + .l2_tbnk0_init_req_l1 (l2_tbnk0_init_req_l1), + .l2_tbnk0_kill_l2 (l2_tbnk0_kill_l2), + .l2_tbnk0_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), + .l2_tbnk0_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), + .l2_tbnk0_last_qw_l1 (l2_tbnk0_last_qw_l1), + .l2_tbnk0_lock_l1 (l2_tbnk0_lock_l1[2:0]), + .l2_tbnk0_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), + .l2_tbnk0_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), + .l2_tbnk0_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), + .l2_tbnk0_prfm_l1 (l2_tbnk0_prfm_l1), + .l2_tbnk0_prot_l1 (l2_tbnk0_prot_l1[3:0]), + .l2_tbnk0_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), + .l2_tbnk0_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), + .l2_tbnk0_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), + .l2_tbnk0_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), + .l2_tbnk0_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), + .l2_tbnk0_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), + .l2_tbnk0_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), + .l2_tbnk0_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), + .l2_tbnk0_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), + .l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk0_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk0_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk0_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), + .l2_tbnk0_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk0_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), + .l2_tbnk0_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), + .l2_tbnk0_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), + .l2_tbnk0_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), + .l2_tbnk0_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), + .l2_tbnk0_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), + .l2_tbnk0_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), + .l2_tbnk0_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), + .l2_tbnk0_sel_l1 (l2_tbnk0_sel_l1[13:0]), + .l2_tbnk0_size_l1 (l2_tbnk0_size_l1[2:0]), + .l2_tbnk0_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), + .l2_tbnk0_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), + .l2_tbnk0_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), + .l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk0_sync_l1 (l2_tbnk0_sync_l1), + .l2_tbnk0_type_l1 (l2_tbnk0_type_l1[6:0]), + .l2_tbnk0_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), + .l2_tbnk0_way_l1 (l2_tbnk0_way_l1), + .l2_tbnk0_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), + .l2_tbnk0_wr_err_l1 (l2_tbnk0_wr_err_l1), + .l2_tbnk0_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), + .l2_tbnk0_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), + .l2_tbnk0_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), + .l2_tbnk0_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]), + .l2_tbnk1_addr_l1 (l2_tbnk1_addr_l1[44:0]), + .l2_tbnk1_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), + .l2_tbnk1_asq_full_flsh (l2_tbnk1_asq_full_flsh), + .l2_tbnk1_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), + .l2_tbnk1_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), + .l2_tbnk1_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), + .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), + .l2_tbnk1_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), + .l2_tbnk1_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), + .l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), + .l2_tbnk1_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), + .l2_tbnk1_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), + .l2_tbnk1_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), + .l2_tbnk1_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), + .l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), + .l2_tbnk1_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), + .l2_tbnk1_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), + .l2_tbnk1_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), + .l2_tbnk1_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), + .l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), + .l2_tbnk1_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), + .l2_tbnk1_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), + .l2_tbnk1_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), + .l2_tbnk1_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), + .l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), + .l2_tbnk1_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), + .l2_tbnk1_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_dirty_l1 (l2_tbnk1_dirty_l1), + .l2_tbnk1_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), + .l2_tbnk1_excl_l1 (l2_tbnk1_excl_l1), + .l2_tbnk1_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), + .l2_tbnk1_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), + .l2_tbnk1_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), + .l2_tbnk1_feq_kill_l3 (l2_tbnk1_feq_kill_l3), + .l2_tbnk1_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), + .l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk1_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), + .l2_tbnk1_id_l1 (l2_tbnk1_id_l1[9:0]), + .l2_tbnk1_init_req_l1 (l2_tbnk1_init_req_l1), + .l2_tbnk1_kill_l2 (l2_tbnk1_kill_l2), + .l2_tbnk1_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), + .l2_tbnk1_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), + .l2_tbnk1_last_qw_l1 (l2_tbnk1_last_qw_l1), + .l2_tbnk1_lock_l1 (l2_tbnk1_lock_l1[2:0]), + .l2_tbnk1_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), + .l2_tbnk1_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), + .l2_tbnk1_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), + .l2_tbnk1_prfm_l1 (l2_tbnk1_prfm_l1), + .l2_tbnk1_prot_l1 (l2_tbnk1_prot_l1[3:0]), + .l2_tbnk1_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), + .l2_tbnk1_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), + .l2_tbnk1_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), + .l2_tbnk1_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), + .l2_tbnk1_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), + .l2_tbnk1_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), + .l2_tbnk1_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), + .l2_tbnk1_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), + .l2_tbnk1_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), + .l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk1_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk1_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk1_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), + .l2_tbnk1_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk1_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), + .l2_tbnk1_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), + .l2_tbnk1_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), + .l2_tbnk1_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), + .l2_tbnk1_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), + .l2_tbnk1_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), + .l2_tbnk1_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), + .l2_tbnk1_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), + .l2_tbnk1_sel_l1 (l2_tbnk1_sel_l1[13:0]), + .l2_tbnk1_size_l1 (l2_tbnk1_size_l1[2:0]), + .l2_tbnk1_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), + .l2_tbnk1_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), + .l2_tbnk1_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), + .l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk1_sync_l1 (l2_tbnk1_sync_l1), + .l2_tbnk1_type_l1 (l2_tbnk1_type_l1[6:0]), + .l2_tbnk1_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), + .l2_tbnk1_way_l1 (l2_tbnk1_way_l1), + .l2_tbnk1_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), + .l2_tbnk1_wr_err_l1 (l2_tbnk1_wr_err_l1), + .l2_tbnk1_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), + .l2_tbnk1_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), + .l2_tbnk1_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), + .l2_tbnk1_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .nEXTERRIRQ (nEXTERRIRQ), + .nINTERRIRQ (nINTERRIRQ), + + // inputs + .ACLKENS (ACLKENS), + .ARADDRS (ARADDRS[43:0]), + .ARCACHES (ARCACHES[3:0]), + .ARIDS (ARIDS[4:0]), + .ARLENS (ARLENS[7:0]), + .ARPROTS (ARPROTS[2:0]), + .ARUSERS (ARUSERS[1:0]), + .ARVALIDS (ARVALIDS), + .AWADDRS (AWADDRS[43:0]), + .AWCACHES (AWCACHES[3:0]), + .AWIDS (AWIDS[4:0]), + .AWLENS (AWLENS[7:0]), + .AWPROTS (AWPROTS[2:0]), + .AWUSERS (AWUSERS[1:0]), + .AWVALIDS (AWVALIDS), + .BREADYS (BREADYS), + .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), + .BROADCASTINNER (BROADCASTINNER), + .BROADCASTOUTER (BROADCASTOUTER), + .DBGL1RSTDISABLE (DBGL1RSTDISABLE), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .L2FLUSHREQ (L2FLUSHREQ), + .L2QREQn (L2QREQn), + .L2RSTDISABLE (L2RSTDISABLE), + .MBISTREQ (MBISTREQ), + .NODEID (NODEID[6:0]), + .PERIPHBASE (PERIPHBASE[43:18]), + .RREADYS (RREADYS), + .RXDATFLIT (RXDATFLIT[193:0]), + .RXDATFLITPEND (RXDATFLITPEND), + .RXDATFLITV (RXDATFLITV), + .RXLINKACTIVEREQ (RXLINKACTIVEREQ), + .RXRSPFLIT (RXRSPFLIT[44:0]), + .RXRSPFLITPEND (RXRSPFLITPEND), + .RXRSPFLITV (RXRSPFLITV), + .RXSACTIVE (RXSACTIVE), + .RXSNPFLIT (RXSNPFLIT[64:0]), + .RXSNPFLITPEND (RXSNPFLITPEND), + .RXSNPFLITV (RXSNPFLITV), + .SAMADDRMAP0 (SAMADDRMAP0[1:0]), + .SAMADDRMAP1 (SAMADDRMAP1[1:0]), + .SAMADDRMAP10 (SAMADDRMAP10[1:0]), + .SAMADDRMAP11 (SAMADDRMAP11[1:0]), + .SAMADDRMAP12 (SAMADDRMAP12[1:0]), + .SAMADDRMAP13 (SAMADDRMAP13[1:0]), + .SAMADDRMAP14 (SAMADDRMAP14[1:0]), + .SAMADDRMAP15 (SAMADDRMAP15[1:0]), + .SAMADDRMAP16 (SAMADDRMAP16[1:0]), + .SAMADDRMAP17 (SAMADDRMAP17[1:0]), + .SAMADDRMAP18 (SAMADDRMAP18[1:0]), + .SAMADDRMAP19 (SAMADDRMAP19[1:0]), + .SAMADDRMAP2 (SAMADDRMAP2[1:0]), + .SAMADDRMAP3 (SAMADDRMAP3[1:0]), + .SAMADDRMAP4 (SAMADDRMAP4[1:0]), + .SAMADDRMAP5 (SAMADDRMAP5[1:0]), + .SAMADDRMAP6 (SAMADDRMAP6[1:0]), + .SAMADDRMAP7 (SAMADDRMAP7[1:0]), + .SAMADDRMAP8 (SAMADDRMAP8[1:0]), + .SAMADDRMAP9 (SAMADDRMAP9[1:0]), + .SAMHNF0NODEID (SAMHNF0NODEID[6:0]), + .SAMHNF1NODEID (SAMHNF1NODEID[6:0]), + .SAMHNF2NODEID (SAMHNF2NODEID[6:0]), + .SAMHNF3NODEID (SAMHNF3NODEID[6:0]), + .SAMHNF4NODEID (SAMHNF4NODEID[6:0]), + .SAMHNF5NODEID (SAMHNF5NODEID[6:0]), + .SAMHNF6NODEID (SAMHNF6NODEID[6:0]), + .SAMHNF7NODEID (SAMHNF7NODEID[6:0]), + .SAMHNFMODE (SAMHNFMODE[2:0]), + .SAMHNI0NODEID (SAMHNI0NODEID[6:0]), + .SAMHNI1NODEID (SAMHNI1NODEID[6:0]), + .SAMMNBASE (SAMMNBASE[43:24]), + .SAMMNNODEID (SAMMNNODEID[6:0]), + .SCLKEN (SCLKEN), + .SYSBARDISABLE (SYSBARDISABLE), + .TXDATLCRDV (TXDATLCRDV), + .TXLINKACTIVEACK (TXLINKACTIVEACK), + .TXREQLCRDV (TXREQLCRDV), + .TXRSPLCRDV (TXRSPLCRDV), + .WDATAS (WDATAS[127:0]), + .WLASTS (WLASTS), + .WSTRBS (WSTRBS[15:0]), + .WVALIDS (WVALIDS), + .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), + .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), + .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), + .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), + .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), + .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), + .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), + .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), + .ck_gclkfr (ck_gclkfr), + .ck_gclkl2 (ck_gclkl2), + .ck_l2_ace_inactive (ck_l2_ace_inactive), + .ck_l2_acp_inactive (ck_l2_acp_inactive), + .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), + .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), + .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), + .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), + .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), + .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), + .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), + .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), + .ic_p_rdata (ic_p_rdata[31:0]), + .ic_p_rdata_valid (ic_p_rdata_valid), + .ic_p_ready (ic_p_ready), + .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .l2_mbist2_tbnk0_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), + .l2_mbist2_tbnk0_all_b1 (l2_mbist2_tbnk0_all_b1), + .l2_mbist2_tbnk0_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), + .l2_mbist2_tbnk0_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), + .l2_mbist2_tbnk0_en_b1 (l2_mbist2_tbnk0_en_b1), + .l2_mbist2_tbnk0_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), + .l2_mbist2_tbnk0_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), + .l2_mbist2_tbnk0_sel_b1 (l2_mbist2_tbnk0_sel_b1), + .l2_mbist2_tbnk0_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), + .l2_mbist2_tbnk0_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), + .l2_mbist2_tbnk0_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), + .l2_mbist2_tbnk0_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), + .l2_mbist2_tbnk0_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), + .l2_mbist2_tbnk1_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), + .l2_mbist2_tbnk1_all_b1 (l2_mbist2_tbnk1_all_b1), + .l2_mbist2_tbnk1_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), + .l2_mbist2_tbnk1_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), + .l2_mbist2_tbnk1_en_b1 (l2_mbist2_tbnk1_en_b1), + .l2_mbist2_tbnk1_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), + .l2_mbist2_tbnk1_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), + .l2_mbist2_tbnk1_sel_b1 (l2_mbist2_tbnk1_sel_b1), + .l2_mbist2_tbnk1_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), + .l2_mbist2_tbnk1_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), + .l2_mbist2_tbnk1_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), + .l2_mbist2_tbnk1_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), + .l2_mbist2_tbnk1_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), + .l2_tbnk0_addr44_l3_q (l2_tbnk0_addr44_l3_q), + .l2_tbnk0_addr_l6 (l2_tbnk0_addr_l6[5:2]), + .l2_tbnk0_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), + .l2_tbnk0_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), + .l2_tbnk0_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), + .l2_tbnk0_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), + .l2_tbnk0_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), + .l2_tbnk0_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), + .l2_tbnk0_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), + .l2_tbnk0_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), + .l2_tbnk0_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), + .l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), + .l2_tbnk0_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), + .l2_tbnk0_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), + .l2_tbnk0_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), + .l2_tbnk0_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), + .l2_tbnk0_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), + .l2_tbnk0_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), + .l2_tbnk0_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), + .l2_tbnk0_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), + .l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), + .l2_tbnk0_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), + .l2_tbnk0_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), + .l2_tbnk0_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), + .l2_tbnk0_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), + .l2_tbnk0_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), + .l2_tbnk0_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), + .l2_tbnk0_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), + .l2_tbnk0_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), + .l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), + .l2_tbnk0_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), + .l2_tbnk0_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), + .l2_tbnk0_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), + .l2_tbnk0_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), + .l2_tbnk0_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), + .l2_tbnk0_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), + .l2_tbnk0_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), + .l2_tbnk0_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), + .l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), + .l2_tbnk0_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), + .l2_tbnk0_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk0_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk0_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk0_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), + .l2_tbnk0_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), + .l2_tbnk0_data_l6 (l2_tbnk0_data_l6[127:0]), + .l2_tbnk0_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), + .l2_tbnk0_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk0_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk0_dirty_l3_q (l2_tbnk0_dirty_l3_q), + .l2_tbnk0_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), + .l2_tbnk0_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), + .l2_tbnk0_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), + .l2_tbnk0_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), + .l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk0_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), + .l2_tbnk0_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), + .l2_tbnk0_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), + .l2_tbnk0_excl_l4_q (l2_tbnk0_excl_l4_q), + .l2_tbnk0_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), + .l2_tbnk0_feq_clr_l4 (l2_tbnk0_feq_clr_l4), + .l2_tbnk0_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), + .l2_tbnk0_hit_l4 (l2_tbnk0_hit_l4), + .l2_tbnk0_hit_l7_q (l2_tbnk0_hit_l7_q), + .l2_tbnk0_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), + .l2_tbnk0_id_l6_q (l2_tbnk0_id_l6_q[9:0]), + .l2_tbnk0_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), + .l2_tbnk0_idle (l2_tbnk0_idle), + .l2_tbnk0_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), + .l2_tbnk0_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), + .l2_tbnk0_l2v_s_q (l2_tbnk0_l2v_s_q), + .l2_tbnk0_l2v_vld_q (l2_tbnk0_l2v_vld_q), + .l2_tbnk0_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), + .l2_tbnk0_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), + .l2_tbnk0_lock_l4 (l2_tbnk0_lock_l4[2:0]), + .l2_tbnk0_merrsr_data (l2_tbnk0_merrsr_data[32:0]), + .l2_tbnk0_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), + .l2_tbnk0_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), + .l2_tbnk0_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), + .l2_tbnk0_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), + .l2_tbnk0_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), + .l2_tbnk0_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), + .l2_tbnk0_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), + .l2_tbnk0_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), + .l2_tbnk0_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), + .l2_tbnk0_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), + .l2_tbnk0_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk0_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk0_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), + .l2_tbnk0_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), + .l2_tbnk0_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), + .l2_tbnk0_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk0_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), + .l2_tbnk0_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), + .l2_tbnk0_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), + .l2_tbnk0_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), + .l2_tbnk0_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk0_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), + .l2_tbnk0_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk0_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), + .l2_tbnk0_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), + .l2_tbnk0_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), + .l2_tbnk0_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), + .l2_tbnk0_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), + .l2_tbnk0_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), + .l2_tbnk0_size_l4_q (l2_tbnk0_size_l4_q[2:0]), + .l2_tbnk0_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), + .l2_tbnk0_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), + .l2_tbnk0_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk0_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk0_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk0_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), + .l2_tbnk0_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), + .l2_tbnk0_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk0_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), + .l2_tbnk0_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), + .l2_tbnk0_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), + .l2_tbnk0_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), + .l2_tbnk0_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), + .l2_tbnk0_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), + .l2_tbnk0_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), + .l2_tbnk0_vld_l6_q (l2_tbnk0_vld_l6_q), + .l2_tbnk0_way_l4_q (l2_tbnk0_way_l4_q), + .l2_tbnk0_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), + .l2_tbnk0_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), + .l2_tbnk0_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), + .l2_tbnk0_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), + .l2_tbnk1_addr44_l3_q (l2_tbnk1_addr44_l3_q), + .l2_tbnk1_addr_l6 (l2_tbnk1_addr_l6[5:2]), + .l2_tbnk1_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), + .l2_tbnk1_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), + .l2_tbnk1_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), + .l2_tbnk1_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), + .l2_tbnk1_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), + .l2_tbnk1_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), + .l2_tbnk1_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), + .l2_tbnk1_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), + .l2_tbnk1_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), + .l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), + .l2_tbnk1_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), + .l2_tbnk1_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), + .l2_tbnk1_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), + .l2_tbnk1_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), + .l2_tbnk1_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), + .l2_tbnk1_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), + .l2_tbnk1_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), + .l2_tbnk1_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), + .l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), + .l2_tbnk1_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), + .l2_tbnk1_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), + .l2_tbnk1_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), + .l2_tbnk1_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), + .l2_tbnk1_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), + .l2_tbnk1_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), + .l2_tbnk1_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), + .l2_tbnk1_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), + .l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), + .l2_tbnk1_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), + .l2_tbnk1_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), + .l2_tbnk1_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), + .l2_tbnk1_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), + .l2_tbnk1_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), + .l2_tbnk1_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), + .l2_tbnk1_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), + .l2_tbnk1_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), + .l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), + .l2_tbnk1_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), + .l2_tbnk1_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk1_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk1_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk1_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), + .l2_tbnk1_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), + .l2_tbnk1_data_l6 (l2_tbnk1_data_l6[127:0]), + .l2_tbnk1_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), + .l2_tbnk1_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk1_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk1_dirty_l3_q (l2_tbnk1_dirty_l3_q), + .l2_tbnk1_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), + .l2_tbnk1_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), + .l2_tbnk1_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), + .l2_tbnk1_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), + .l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk1_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), + .l2_tbnk1_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), + .l2_tbnk1_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), + .l2_tbnk1_excl_l4_q (l2_tbnk1_excl_l4_q), + .l2_tbnk1_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), + .l2_tbnk1_feq_clr_l4 (l2_tbnk1_feq_clr_l4), + .l2_tbnk1_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), + .l2_tbnk1_hit_l4 (l2_tbnk1_hit_l4), + .l2_tbnk1_hit_l7_q (l2_tbnk1_hit_l7_q), + .l2_tbnk1_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), + .l2_tbnk1_id_l6_q (l2_tbnk1_id_l6_q[9:0]), + .l2_tbnk1_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), + .l2_tbnk1_idle (l2_tbnk1_idle), + .l2_tbnk1_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), + .l2_tbnk1_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), + .l2_tbnk1_l2v_s_q (l2_tbnk1_l2v_s_q), + .l2_tbnk1_l2v_vld_q (l2_tbnk1_l2v_vld_q), + .l2_tbnk1_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), + .l2_tbnk1_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), + .l2_tbnk1_lock_l4 (l2_tbnk1_lock_l4[2:0]), + .l2_tbnk1_merrsr_data (l2_tbnk1_merrsr_data[32:0]), + .l2_tbnk1_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), + .l2_tbnk1_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), + .l2_tbnk1_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), + .l2_tbnk1_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), + .l2_tbnk1_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), + .l2_tbnk1_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), + .l2_tbnk1_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), + .l2_tbnk1_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), + .l2_tbnk1_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), + .l2_tbnk1_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), + .l2_tbnk1_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk1_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk1_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), + .l2_tbnk1_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), + .l2_tbnk1_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), + .l2_tbnk1_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk1_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), + .l2_tbnk1_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), + .l2_tbnk1_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), + .l2_tbnk1_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), + .l2_tbnk1_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk1_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), + .l2_tbnk1_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk1_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), + .l2_tbnk1_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), + .l2_tbnk1_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), + .l2_tbnk1_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), + .l2_tbnk1_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), + .l2_tbnk1_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), + .l2_tbnk1_size_l4_q (l2_tbnk1_size_l4_q[2:0]), + .l2_tbnk1_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), + .l2_tbnk1_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), + .l2_tbnk1_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk1_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk1_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk1_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), + .l2_tbnk1_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), + .l2_tbnk1_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk1_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), + .l2_tbnk1_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), + .l2_tbnk1_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), + .l2_tbnk1_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), + .l2_tbnk1_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), + .l2_tbnk1_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), + .l2_tbnk1_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), + .l2_tbnk1_vld_l6_q (l2_tbnk1_vld_l6_q), + .l2_tbnk1_way_l4_q (l2_tbnk1_way_l4_q), + .l2_tbnk1_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), + .l2_tbnk1_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), + .l2_tbnk1_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), + .l2_tbnk1_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), + .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), + .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), + .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), + .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), + .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), + .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), + .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]) + ); // ul2_logic + + maia_l2_tbnk ul2_tbnk0( // outputs + .l2_mbist2_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), + .l2_mbist2_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), + .l2_mbist2_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), + .l2_mbist2_en_b1 (l2_mbist2_tbnk0_en_b1), + .l2_mbist2_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), + .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk0_all_b1), + .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), + .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk0_sel_b1), + .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), + .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), + .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), + .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), + .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), + .l2_tbnk_addr44_l3_q (l2_tbnk0_addr44_l3_q), + .l2_tbnk_addr_l6 (l2_tbnk0_addr_l6[5:2]), + .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), + .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), + .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), + .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), + .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), + .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), + .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), + .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), + .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), + .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), + .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), + .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), + .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), + .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), + .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), + .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), + .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), + .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), + .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), + .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), + .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), + .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), + .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), + .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), + .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), + .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), + .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), + .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), + .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), + .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), + .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), + .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), + .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), + .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), + .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), + .l2_tbnk_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), + .l2_tbnk_data_l6 (l2_tbnk0_data_l6[127:0]), + .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), + .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk_dirty_l3_q (l2_tbnk0_dirty_l3_q), + .l2_tbnk_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), + .l2_tbnk_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), + .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), + .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), + .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), + .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), + .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), + .l2_tbnk_excl_l4_q (l2_tbnk0_excl_l4_q), + .l2_tbnk_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), + .l2_tbnk_feq_clr_l4 (l2_tbnk0_feq_clr_l4), + .l2_tbnk_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), + .l2_tbnk_hit_l4 (l2_tbnk0_hit_l4), + .l2_tbnk_hit_l7_q (l2_tbnk0_hit_l7_q), + .l2_tbnk_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), + .l2_tbnk_id_l6_q (l2_tbnk0_id_l6_q[9:0]), + .l2_tbnk_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), + .l2_tbnk_idle (l2_tbnk0_idle), + .l2_tbnk_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), + .l2_tbnk_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), + .l2_tbnk_l2v_s_q (l2_tbnk0_l2v_s_q), + .l2_tbnk_l2v_vld_q (l2_tbnk0_l2v_vld_q), + .l2_tbnk_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), + .l2_tbnk_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), + .l2_tbnk_lock_l4 (l2_tbnk0_lock_l4[2:0]), + .l2_tbnk_merrsr_data (l2_tbnk0_merrsr_data[32:0]), + .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), + .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), + .l2_tbnk_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), + .l2_tbnk_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), + .l2_tbnk_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), + .l2_tbnk_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), + .l2_tbnk_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), + .l2_tbnk_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), + .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), + .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), + .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), + .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), + .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), + .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), + .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), + .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), + .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), + .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), + .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), + .l2_tbnk_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), + .l2_tbnk_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), + .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), + .l2_tbnk_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), + .l2_tbnk_size_l4_q (l2_tbnk0_size_l4_q[2:0]), + .l2_tbnk_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), + .l2_tbnk_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), + .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), + .l2_tbnk_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), + .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), + .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), + .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), + .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), + .l2_tbnk_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), + .l2_tbnk_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), + .l2_tbnk_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), + .l2_tbnk_vld_l6_q (l2_tbnk0_vld_l6_q), + .l2_tbnk_way_l4_q (l2_tbnk0_way_l4_q), + .l2_tbnk_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), + .l2_tbnk_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), + .l2_tbnk_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), + .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), + + // inputs + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ), + .ck_areset_l2 (ck_areset_l2), + .ck_gclkl2 (ck_gclkb0), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), + .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), + .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), + .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), + .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), + .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), + .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), + .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_skyros_intf (1'b1), + .l2_tbnk_addr_l1 (l2_tbnk0_addr_l1[44:0]), + .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), + .l2_tbnk_asq_full_flsh (l2_tbnk0_asq_full_flsh), + .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), + .l2_tbnk_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), + .l2_tbnk_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), + .l2_tbnk_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), + .l2_tbnk_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), + .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), + .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), + .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), + .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), + .l2_tbnk_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), + .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), + .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), + .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), + .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), + .l2_tbnk_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), + .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), + .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), + .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), + .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), + .l2_tbnk_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), + .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), + .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), + .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), + .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_dirty_l1 (l2_tbnk0_dirty_l1), + .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), + .l2_tbnk_excl_l1 (l2_tbnk0_excl_l1), + .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), + .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), + .l2_tbnk_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), + .l2_tbnk_feq_kill_l3 (l2_tbnk0_feq_kill_l3), + .l2_tbnk_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), + .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .l2_tbnk_id_l1 (l2_tbnk0_id_l1[9:0]), + .l2_tbnk_init_req_l1 (l2_tbnk0_init_req_l1), + .l2_tbnk_kill_l2 (l2_tbnk0_kill_l2), + .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), + .l2_tbnk_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), + .l2_tbnk_last_qw_l1 (l2_tbnk0_last_qw_l1), + .l2_tbnk_lock_l1 (l2_tbnk0_lock_l1[2:0]), + .l2_tbnk_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), + .l2_tbnk_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), + .l2_tbnk_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), + .l2_tbnk_prfm_l1 (l2_tbnk0_prfm_l1), + .l2_tbnk_prot_l1 (l2_tbnk0_prot_l1[3:0]), + .l2_tbnk_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), + .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), + .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), + .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), + .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), + .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), + .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), + .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), + .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), + .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), + .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), + .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), + .l2_tbnk_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), + .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), + .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), + .l2_tbnk_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), + .l2_tbnk_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), + .l2_tbnk_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), + .l2_tbnk_sel_l1 (l2_tbnk0_sel_l1[13:0]), + .l2_tbnk_size_l1 (l2_tbnk0_size_l1[2:0]), + .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), + .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), + .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), + .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_sync_l1 (l2_tbnk0_sync_l1), + .l2_tbnk_type_l1 (l2_tbnk0_type_l1[6:0]), + .l2_tbnk_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), + .l2_tbnk_way_l1 (l2_tbnk0_way_l1), + .l2_tbnk_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), + .l2_tbnk_wr_err_l1 (l2_tbnk0_wr_err_l1), + .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), + .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), + .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), + .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]) + ); // ul2_tbnk0 + + maia_l2_tbnk ul2_tbnk1( // outputs + .l2_mbist2_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), + .l2_mbist2_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), + .l2_mbist2_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), + .l2_mbist2_en_b1 (l2_mbist2_tbnk1_en_b1), + .l2_mbist2_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), + .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk1_all_b1), + .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), + .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk1_sel_b1), + .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), + .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), + .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), + .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), + .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), + .l2_tbnk_addr44_l3_q (l2_tbnk1_addr44_l3_q), + .l2_tbnk_addr_l6 (l2_tbnk1_addr_l6[5:2]), + .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), + .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), + .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), + .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), + .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), + .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), + .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), + .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), + .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), + .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), + .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), + .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), + .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), + .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), + .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), + .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), + .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), + .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), + .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), + .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), + .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), + .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), + .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), + .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), + .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), + .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), + .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), + .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), + .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), + .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), + .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), + .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), + .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), + .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), + .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), + .l2_tbnk_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), + .l2_tbnk_data_l6 (l2_tbnk1_data_l6[127:0]), + .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), + .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk_dirty_l3_q (l2_tbnk1_dirty_l3_q), + .l2_tbnk_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), + .l2_tbnk_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), + .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), + .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), + .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), + .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), + .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), + .l2_tbnk_excl_l4_q (l2_tbnk1_excl_l4_q), + .l2_tbnk_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), + .l2_tbnk_feq_clr_l4 (l2_tbnk1_feq_clr_l4), + .l2_tbnk_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), + .l2_tbnk_hit_l4 (l2_tbnk1_hit_l4), + .l2_tbnk_hit_l7_q (l2_tbnk1_hit_l7_q), + .l2_tbnk_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), + .l2_tbnk_id_l6_q (l2_tbnk1_id_l6_q[9:0]), + .l2_tbnk_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), + .l2_tbnk_idle (l2_tbnk1_idle), + .l2_tbnk_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), + .l2_tbnk_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), + .l2_tbnk_l2v_s_q (l2_tbnk1_l2v_s_q), + .l2_tbnk_l2v_vld_q (l2_tbnk1_l2v_vld_q), + .l2_tbnk_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), + .l2_tbnk_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), + .l2_tbnk_lock_l4 (l2_tbnk1_lock_l4[2:0]), + .l2_tbnk_merrsr_data (l2_tbnk1_merrsr_data[32:0]), + .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), + .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), + .l2_tbnk_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), + .l2_tbnk_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), + .l2_tbnk_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), + .l2_tbnk_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), + .l2_tbnk_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), + .l2_tbnk_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), + .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), + .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), + .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), + .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), + .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), + .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), + .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), + .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), + .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), + .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), + .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), + .l2_tbnk_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), + .l2_tbnk_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), + .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), + .l2_tbnk_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), + .l2_tbnk_size_l4_q (l2_tbnk1_size_l4_q[2:0]), + .l2_tbnk_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), + .l2_tbnk_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), + .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), + .l2_tbnk_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), + .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), + .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), + .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), + .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), + .l2_tbnk_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), + .l2_tbnk_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), + .l2_tbnk_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), + .l2_tbnk_vld_l6_q (l2_tbnk1_vld_l6_q), + .l2_tbnk_way_l4_q (l2_tbnk1_way_l4_q), + .l2_tbnk_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), + .l2_tbnk_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), + .l2_tbnk_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), + .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), + + // inputs + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ), + .ck_areset_l2 (ck_areset_l2), + .ck_gclkl2 (ck_gclkb1), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), + .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), + .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), + .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), + .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), + .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), + .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), + .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_skyros_intf (1'b1), + .l2_tbnk_addr_l1 (l2_tbnk1_addr_l1[44:0]), + .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), + .l2_tbnk_asq_full_flsh (l2_tbnk1_asq_full_flsh), + .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), + .l2_tbnk_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), + .l2_tbnk_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), + .l2_tbnk_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), + .l2_tbnk_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), + .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), + .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), + .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), + .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), + .l2_tbnk_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), + .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), + .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), + .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), + .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), + .l2_tbnk_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), + .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), + .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), + .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), + .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), + .l2_tbnk_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), + .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), + .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), + .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), + .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_dirty_l1 (l2_tbnk1_dirty_l1), + .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), + .l2_tbnk_excl_l1 (l2_tbnk1_excl_l1), + .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), + .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), + .l2_tbnk_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), + .l2_tbnk_feq_kill_l3 (l2_tbnk1_feq_kill_l3), + .l2_tbnk_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), + .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .l2_tbnk_id_l1 (l2_tbnk1_id_l1[9:0]), + .l2_tbnk_init_req_l1 (l2_tbnk1_init_req_l1), + .l2_tbnk_kill_l2 (l2_tbnk1_kill_l2), + .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), + .l2_tbnk_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), + .l2_tbnk_last_qw_l1 (l2_tbnk1_last_qw_l1), + .l2_tbnk_lock_l1 (l2_tbnk1_lock_l1[2:0]), + .l2_tbnk_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), + .l2_tbnk_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), + .l2_tbnk_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), + .l2_tbnk_prfm_l1 (l2_tbnk1_prfm_l1), + .l2_tbnk_prot_l1 (l2_tbnk1_prot_l1[3:0]), + .l2_tbnk_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), + .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), + .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), + .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), + .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), + .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), + .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), + .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), + .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), + .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), + .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), + .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), + .l2_tbnk_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), + .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), + .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), + .l2_tbnk_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), + .l2_tbnk_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), + .l2_tbnk_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), + .l2_tbnk_sel_l1 (l2_tbnk1_sel_l1[13:0]), + .l2_tbnk_size_l1 (l2_tbnk1_size_l1[2:0]), + .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), + .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), + .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), + .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_sync_l1 (l2_tbnk1_sync_l1), + .l2_tbnk_type_l1 (l2_tbnk1_type_l1[6:0]), + .l2_tbnk_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), + .l2_tbnk_way_l1 (l2_tbnk1_way_l1), + .l2_tbnk_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), + .l2_tbnk_wr_err_l1 (l2_tbnk1_wr_err_l1), + .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), + .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), + .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), + .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]) + ); // ul2_tbnk1 + + maia_dt_pclk udt_pclk( // outputs + .CTICHINACK (CTICHINACK[3:0]), + .CTICHOUT (CTICHOUT[3:0]), + .CTIIRQ (CTIIRQ[`MAIA_CN:0]), + .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), + .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), + .PRDATADBG (PRDATADBG[31:0]), + .PREADYDBG (PREADYDBG), + .PSLVERRDBG (PSLVERRDBG), + .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), + .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), + .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), + .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), + .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), + .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), + .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), + .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), + .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + + // inputs + .CIHSBYPASS (CIHSBYPASS[3:0]), + .CISBYPASS (CISBYPASS), + .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), + .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), + .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), + .CTICHIN (CTICHIN[3:0]), + .CTICHOUTACK (CTICHOUTACK[3:0]), + .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), + .DBGEN (DBGEN[`MAIA_CN:0]), + .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .EDBGRQ (EDBGRQ[`MAIA_CN:0]), + .GICCDISABLE (GICCDISABLE), + .NIDEN (NIDEN[`MAIA_CN:0]), + .PADDRDBG (PADDRDBG[21:2]), + .PADDRDBG31 (PADDRDBG31), + .PCLKDBG (PCLKDBG), + .PCLKENDBG (PCLKENDBG), + .PENABLEDBG (PENABLEDBG), + .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), + .PSELDBG (PSELDBG), + .PWDATADBG (PWDATADBG[31:0]), + .PWRITEDBG (PWRITEDBG), + .SPIDEN (SPIDEN[`MAIA_CN:0]), + .SPNIDEN (SPNIDEN[`MAIA_CN:0]), + .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), + .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), + .ck_cpu0_poreset_status (ck_cpu0_poreset_status), + .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), + .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), + .ck_cpu1_poreset_status (ck_cpu1_poreset_status), + .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), + .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), + .ck_cpu2_poreset_status (ck_cpu2_poreset_status), + .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), + .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), + .ck_cpu3_poreset_status (ck_cpu3_poreset_status), + .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), + .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), + .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), + .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), + .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), + .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), + .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), + .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), + .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), + .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), + .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), + .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), + .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), + .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), + .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), + .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), + .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), + .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), + .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), + .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), + .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), + .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), + .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), + .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), + .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .nPRESETDBG (nPRESETDBG) + ); // udt_pclk + + maia_intctrl uic( // outputs + .ICCTDATA (ICCTDATA[15:0]), + .ICCTID (ICCTID[1:0]), + .ICCTLAST (ICCTLAST), + .ICCTVALID (ICCTVALID), + .ICDTREADY (ICDTREADY), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), + .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), + .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), + .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), + .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), + .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), + .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), + .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), + .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), + .ic_el_change_complete_o (ic_el_change_complete_o[`MAIA_CN:0]), + .ic_hcr_change_complete_o (ic_hcr_change_complete_o[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .ic_p_rdata (ic_p_rdata[31:0]), + .ic_p_rdata_valid (ic_p_rdata_valid), + .ic_p_ready (ic_p_ready), + .ic_p_valid (ic_p_valid[`MAIA_CN:0]), + .ic_sample_spr_o (ic_sample_spr_o[`MAIA_CN:0]), + .ic_scr_change_complete_o (ic_scr_change_complete_o[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]), + .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), + + // inputs + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .GICCDISABLE (GICCDISABLE), + .ICCTREADY (ICCTREADY), + .ICDTDATA (ICDTDATA[15:0]), + .ICDTDEST (ICDTDEST[1:0]), + .ICDTLAST (ICDTLAST), + .ICDTVALID (ICDTVALID), + .ck_areset_l2 (ck_areset_l2), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_aa64naa32_i (ds_cpu0_ic_aa64naa32_i), + .ds_cpu0_cpsr_mode_i (ds_cpu0_ic_cpsr_mode_i[4:0]), + .ds_cpu0_hcr_change_i (ds_cpu0_ic_hcr_change_i), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu0_sample_spr_i (ds_cpu0_ic_sample_spr_i), + .ds_cpu0_scr_change_i (ds_cpu0_ic_scr_change_i), + .ds_cpu1_aa64naa32_i (ds_cpu1_ic_aa64naa32_i), + .ds_cpu1_cpsr_mode_i (ds_cpu1_ic_cpsr_mode_i[4:0]), + .ds_cpu1_hcr_change_i (ds_cpu1_ic_hcr_change_i), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu1_sample_spr_i (ds_cpu1_ic_sample_spr_i), + .ds_cpu1_scr_change_i (ds_cpu1_ic_scr_change_i), + .ds_cpu2_aa64naa32_i (ds_cpu2_ic_aa64naa32_i), + .ds_cpu2_cpsr_mode_i (ds_cpu2_ic_cpsr_mode_i[4:0]), + .ds_cpu2_hcr_change_i (ds_cpu2_ic_hcr_change_i), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu2_sample_spr_i (ds_cpu2_ic_sample_spr_i), + .ds_cpu2_scr_change_i (ds_cpu2_ic_scr_change_i), + .ds_cpu3_aa64naa32_i (ds_cpu3_ic_aa64naa32_i), + .ds_cpu3_cpsr_mode_i (ds_cpu3_ic_cpsr_mode_i[4:0]), + .ds_cpu3_hcr_change_i (ds_cpu3_ic_hcr_change_i), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_cpu3_sample_spr_i (ds_cpu3_ic_sample_spr_i), + .ds_cpu3_scr_change_i (ds_cpu3_ic_scr_change_i), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_cpu0_wr_decerr_i (l2_cpu0_wr_decerr_q), + .l2_cpu0_wr_slverr_i (l2_cpu0_wr_slverr_q), + .l2_cpu1_wr_decerr_i (l2_cpu1_wr_decerr_q), + .l2_cpu1_wr_slverr_i (l2_cpu1_wr_slverr_q), + .l2_cpu2_wr_decerr_i (l2_cpu2_wr_decerr_q), + .l2_cpu2_wr_slverr_i (l2_cpu2_wr_slverr_q), + .l2_cpu3_wr_decerr_i (l2_cpu3_wr_decerr_q), + .l2_cpu3_wr_slverr_i (l2_cpu3_wr_slverr_q), + .l2_p_addr (l2_p_addr[13:0]), + .l2_p_cpu (l2_p_cpu[1:0]), + .l2_p_nsecure (l2_p_nsecure), + .l2_p_sel (l2_p_sel[2:0]), + .l2_p_wdata (l2_p_wdata[31:0]), + .l2_p_write (l2_p_write), + .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), + .nFIQ (nFIQ[`MAIA_CN:0]), + .nIRQ (nIRQ[`MAIA_CN:0]), + .nREI (nREI[`MAIA_CN:0]), + .nSEI (nSEI[`MAIA_CN:0]), + .nVFIQ (nVFIQ[`MAIA_CN:0]), + .nVIRQ (nVIRQ[`MAIA_CN:0]), + .nVSEI (nVSEI[`MAIA_CN:0]) + ); // uic + + maia_ck_l2 uck_l2( // outputs + .ck_gclkb0 (ck_gclkb0), + .ck_gclkb1 (ck_gclkb1), + .ck_gclkfr (ck_gclkfr), + .ck_gclkl2 (ck_gclkl2), + + // inputs + .DFTL2CLKDISABLE (DFTL2CLKDISABLE), + .DFTSE (DFTSE), + .ck_gclktl2 (ck_gclktl2), + .ck_l2_logic_clk_en (ck_l2_logic_clk_en), + .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), + .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), + .l2_reset3 (l2_reset3) + ); // uck_l2 + + maia_ck_top uck_top( // outputs + .ck_gclkt (ck_gclkt[`MAIA_CN:0]), + .ck_gclktl2 (ck_gclktl2), + + // inputs + .CLK (CLK), + .CLKEN (CLKEN), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ) + ); // uck_top + + maia_ck_logic uck_logic( // outputs + .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), + .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), + .CPUQDENY (CPUQDENY[`MAIA_CN:0]), + .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), + .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), + .STANDBYWFIL2 (STANDBYWFIL2), + .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), + .ck_cpu0_commrx (ck_cpu0_commrx), + .ck_cpu0_commtx (ck_cpu0_commtx), + .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), + .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), + .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), + .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), + .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), + .ck_cpu0_event_reg (ck_cpu0_event_reg), + .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), + .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), + .ck_cpu0_ncommirq (ck_cpu0_ncommirq), + .ck_cpu0_npmuirq (ck_cpu0_npmuirq), + .ck_cpu0_poreset_status (ck_cpu0_poreset_status), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), + .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), + .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), + .ck_cpu1_commrx (ck_cpu1_commrx), + .ck_cpu1_commtx (ck_cpu1_commtx), + .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), + .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), + .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), + .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), + .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), + .ck_cpu1_event_reg (ck_cpu1_event_reg), + .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), + .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), + .ck_cpu1_ncommirq (ck_cpu1_ncommirq), + .ck_cpu1_npmuirq (ck_cpu1_npmuirq), + .ck_cpu1_poreset_status (ck_cpu1_poreset_status), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), + .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), + .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), + .ck_cpu2_commrx (ck_cpu2_commrx), + .ck_cpu2_commtx (ck_cpu2_commtx), + .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), + .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), + .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), + .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), + .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), + .ck_cpu2_event_reg (ck_cpu2_event_reg), + .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), + .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), + .ck_cpu2_ncommirq (ck_cpu2_ncommirq), + .ck_cpu2_npmuirq (ck_cpu2_npmuirq), + .ck_cpu2_poreset_status (ck_cpu2_poreset_status), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), + .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), + .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), + .ck_cpu3_commrx (ck_cpu3_commrx), + .ck_cpu3_commtx (ck_cpu3_commtx), + .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), + .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), + .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), + .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), + .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), + .ck_cpu3_event_reg (ck_cpu3_event_reg), + .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), + .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), + .ck_cpu3_ncommirq (ck_cpu3_ncommirq), + .ck_cpu3_npmuirq (ck_cpu3_npmuirq), + .ck_cpu3_poreset_status (ck_cpu3_poreset_status), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), + .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), + .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), + .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), + .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), + .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), + .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), + .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), + .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), + .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), + .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), + .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), + .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), + .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), + .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), + .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), + .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), + .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), + .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), + .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), + .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), + .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), + .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), + .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), + .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), + .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), + .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), + .ck_l2_ace_inactive (ck_l2_ace_inactive), + .ck_l2_acp_inactive (ck_l2_acp_inactive), + .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), + + // inputs + .ACINACTM (SINACT), + .AINACTS (AINACTS), + .CPUQREQn (CPUQREQn[`MAIA_CN:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .ck_gclkfr (ck_gclkfr), + .clrexmon_c1 (clrexmon_c1), + .commrx_cpu0_i (commrx_cpu0_i), + .commrx_cpu1_i (commrx_cpu1_i), + .commrx_cpu2_i (commrx_cpu2_i), + .commrx_cpu3_i (commrx_cpu3_i), + .commtx_cpu0_i (commtx_cpu0_i), + .commtx_cpu1_i (commtx_cpu1_i), + .commtx_cpu2_i (commtx_cpu2_i), + .commtx_cpu3_i (commtx_cpu3_i), + .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), + .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), + .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), + .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), + .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), + .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), + .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), + .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_cpu0_flush (ds_cpu0_flush), + .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), + .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), + .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_cpu0_reset_req (ds_cpu0_reset_req), + .ds_cpu0_sevl_req (ds_cpu0_sevl_req), + .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_cpu0_wfe_req (ds_cpu0_wfe_req), + .ds_cpu0_wfi_req (ds_cpu0_wfi_req), + .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_cpu1_flush (ds_cpu1_flush), + .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), + .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), + .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_cpu1_reset_req (ds_cpu1_reset_req), + .ds_cpu1_sevl_req (ds_cpu1_sevl_req), + .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_cpu1_wfe_req (ds_cpu1_wfe_req), + .ds_cpu1_wfi_req (ds_cpu1_wfi_req), + .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_cpu2_flush (ds_cpu2_flush), + .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), + .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), + .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_cpu2_reset_req (ds_cpu2_reset_req), + .ds_cpu2_sevl_req (ds_cpu2_sevl_req), + .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_cpu2_wfe_req (ds_cpu2_wfe_req), + .ds_cpu2_wfi_req (ds_cpu2_wfi_req), + .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_cpu3_flush (ds_cpu3_flush), + .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), + .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), + .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_cpu3_reset_req (ds_cpu3_reset_req), + .ds_cpu3_sevl_req (ds_cpu3_sevl_req), + .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_cpu3_wfe_req (ds_cpu3_wfe_req), + .ds_cpu3_wfi_req (ds_cpu3_wfi_req), + .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), + .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), + .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), + .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), + .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), + .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), + .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), + .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), + .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_cpu0_snp_active (l2_cpu0_snp_active), + .l2_cpu1_snp_active (l2_cpu1_snp_active), + .l2_cpu2_snp_active (l2_cpu2_snp_active), + .l2_cpu3_snp_active (l2_cpu3_snp_active), + .l2_idle (l2_idle), + .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), + .l2_reset3 (l2_reset3), + .l2_sky_link_stopped (l2_sky_link_stopped), + .ls_cpu0_clrexmon (ls_cpu0_clrexmon), + .ls_cpu1_clrexmon (ls_cpu1_clrexmon), + .ls_cpu2_clrexmon (ls_cpu2_clrexmon), + .ls_cpu3_clrexmon (ls_cpu3_clrexmon), + .nCORERESET (nCORERESET[`MAIA_CN:0]), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .ncommirq_cpu0_i (ncommirq_cpu0_i), + .ncommirq_cpu1_i (ncommirq_cpu1_i), + .ncommirq_cpu2_i (ncommirq_cpu2_i), + .ncommirq_cpu3_i (ncommirq_cpu3_i), + .npmuirq_cpu0_i (npmuirq_cpu0_i), + .npmuirq_cpu1_i (npmuirq_cpu1_i), + .npmuirq_cpu2_i (npmuirq_cpu2_i), + .npmuirq_cpu3_i (npmuirq_cpu3_i), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_event_sev (tm_cpu0_event_sev), + .tm_cpu1_event_sev (tm_cpu1_event_sev), + .tm_cpu2_event_sev (tm_cpu2_event_sev), + .tm_cpu3_event_sev (tm_cpu3_event_sev) + ); // uck_logic + + maia_cpu_io ucpu_io( // outputs + .aa64naa32_cpu0_o (aa64naa32_cpu0_o), + .aa64naa32_cpu1_o (aa64naa32_cpu1_o), + .aa64naa32_cpu2_o (aa64naa32_cpu2_o), + .aa64naa32_cpu3_o (aa64naa32_cpu3_o), + .cfgend_cpu0_o (cfgend_cpu0_o), + .cfgend_cpu1_o (cfgend_cpu1_o), + .cfgend_cpu2_o (cfgend_cpu2_o), + .cfgend_cpu3_o (cfgend_cpu3_o), + .cfgte_cpu0_o (cfgte_cpu0_o), + .cfgte_cpu1_o (cfgte_cpu1_o), + .cfgte_cpu2_o (cfgte_cpu2_o), + .cfgte_cpu3_o (cfgte_cpu3_o), + .clrexmon_c1 (clrexmon_c1), + .clrexmonack_o (CLREXMONACK), + .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), + .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), + .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), + .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), + .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), + .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), + .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), + .commrx_o (COMMRX[`MAIA_CN:0]), + .commtx_o (COMMTX[`MAIA_CN:0]), + .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), + .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), + .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), + .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), + .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), + .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), + .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), + .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu0_o (cryptodisable_cpu0_o), + .cryptodisable_cpu1_o (cryptodisable_cpu1_o), + .cryptodisable_cpu2_o (cryptodisable_cpu2_o), + .cryptodisable_cpu3_o (cryptodisable_cpu3_o), + .dbgack_o (DBGACK[`MAIA_CN:0]), + .dbgen_cpu0_o (dbgen_cpu0_o), + .dbgen_cpu1_o (dbgen_cpu1_o), + .dbgen_cpu2_o (dbgen_cpu2_o), + .dbgen_cpu3_o (dbgen_cpu3_o), + .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), + .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), + .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), + .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), + .dbgnopwrdwn_o (DBGNOPWRDWN[`MAIA_CN:0]), + .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), + .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), + .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), + .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), + .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), + .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), + .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), + .dbgrstreq_o (DBGRSTREQ[`MAIA_CN:0]), + .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), + .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), + .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), + .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), + .dftramhold_cpu0_o (dftramhold_cpu0_o), + .dftramhold_cpu1_o (dftramhold_cpu1_o), + .dftramhold_cpu2_o (dftramhold_cpu2_o), + .dftramhold_cpu3_o (dftramhold_cpu3_o), + .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), + .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), + .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), + .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), + .dftse_cpu0_o (dftse_cpu0_o), + .dftse_cpu1_o (dftse_cpu1_o), + .dftse_cpu2_o (dftse_cpu2_o), + .dftse_cpu3_o (dftse_cpu3_o), + .eventi_sev (eventi_sev), + .evento_o (EVENTO), + .giccdisable_cpu0_o (giccdisable_cpu0_o), + .giccdisable_cpu1_o (giccdisable_cpu1_o), + .giccdisable_cpu2_o (giccdisable_cpu2_o), + .giccdisable_cpu3_o (giccdisable_cpu3_o), + .ncommirq_o (nCOMMIRQ[`MAIA_CN:0]), + .ncorereset_cpu0_o (ncorereset_cpu0_o), + .ncorereset_cpu1_o (ncorereset_cpu1_o), + .ncorereset_cpu2_o (ncorereset_cpu2_o), + .ncorereset_cpu3_o (ncorereset_cpu3_o), + .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), + .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), + .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), + .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), + .niden_cpu0_o (niden_cpu0_o), + .niden_cpu1_o (niden_cpu1_o), + .niden_cpu2_o (niden_cpu2_o), + .niden_cpu3_o (niden_cpu3_o), + .nmbistreset_cpu0_o (nmbistreset_cpu0_o), + .nmbistreset_cpu1_o (nmbistreset_cpu1_o), + .nmbistreset_cpu2_o (nmbistreset_cpu2_o), + .nmbistreset_cpu3_o (nmbistreset_cpu3_o), + .npmuirq_o (nPMUIRQ[`MAIA_CN:0]), + .pmuevent0_o (PMUEVENT0[24:0]), + .pmuevent1_o (PMUEVENT1[24:0]), + .pmuevent2_o (PMUEVENT2[24:0]), + .pmuevent3_o (PMUEVENT3[24:0]), + .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), + .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), + .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), + .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), + .smpen_o (SMPEN[`MAIA_CN:0]), + .spiden_cpu0_o (spiden_cpu0_o), + .spiden_cpu1_o (spiden_cpu1_o), + .spiden_cpu2_o (spiden_cpu2_o), + .spiden_cpu3_o (spiden_cpu3_o), + .spniden_cpu0_o (spniden_cpu0_o), + .spniden_cpu1_o (spniden_cpu1_o), + .spniden_cpu2_o (spniden_cpu2_o), + .spniden_cpu3_o (spniden_cpu3_o), + .vinithi_cpu0_o (vinithi_cpu0_o), + .vinithi_cpu1_o (vinithi_cpu1_o), + .vinithi_cpu2_o (vinithi_cpu2_o), + .vinithi_cpu3_o (vinithi_cpu3_o), + + // inputs + .aa64naa32_i (AA64nAA32[`MAIA_CN:0]), + .cfgend_i (CFGEND[`MAIA_CN:0]), + .cfgte_i (CFGTE[`MAIA_CN:0]), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), + .ck_cpu0_commrx (ck_cpu0_commrx), + .ck_cpu0_commtx (ck_cpu0_commtx), + .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), + .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), + .ck_cpu0_ncommirq (ck_cpu0_ncommirq), + .ck_cpu0_npmuirq (ck_cpu0_npmuirq), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), + .ck_cpu1_commrx (ck_cpu1_commrx), + .ck_cpu1_commtx (ck_cpu1_commtx), + .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), + .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), + .ck_cpu1_ncommirq (ck_cpu1_ncommirq), + .ck_cpu1_npmuirq (ck_cpu1_npmuirq), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), + .ck_cpu2_commrx (ck_cpu2_commrx), + .ck_cpu2_commtx (ck_cpu2_commtx), + .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), + .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), + .ck_cpu2_ncommirq (ck_cpu2_ncommirq), + .ck_cpu2_npmuirq (ck_cpu2_npmuirq), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), + .ck_cpu3_commrx (ck_cpu3_commrx), + .ck_cpu3_commtx (ck_cpu3_commtx), + .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), + .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), + .ck_cpu3_ncommirq (ck_cpu3_ncommirq), + .ck_cpu3_npmuirq (ck_cpu3_npmuirq), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), + .ck_gclkfr (ck_gclkfr), + .clrexmonreq_i (CLREXMONREQ), + .clusteridaff1_i (CLUSTERIDAFF1[7:0]), + .clusteridaff2_i (CLUSTERIDAFF2[7:0]), + .cp15sdisable_i (CP15SDISABLE[`MAIA_CN:0]), + .cryptodisable_i (CRYPTODISABLE[`MAIA_CN:0]), + .dbgack_cpu0_i (dbgack_cpu0_i), + .dbgack_cpu1_i (dbgack_cpu1_i), + .dbgack_cpu2_i (dbgack_cpu2_i), + .dbgack_cpu3_i (dbgack_cpu3_i), + .dbgen_i (DBGEN[`MAIA_CN:0]), + .dbgl1rstdisable_i (DBGL1RSTDISABLE), + .dbgromaddr_i (DBGROMADDR[43:12]), + .dbgromaddrv_i (DBGROMADDRV), + .dftcrclkdisable_i (DFTCRCLKDISABLE[`MAIA_CN:0]), + .dftramhold_i (DFTRAMHOLD), + .dftrstdisable_i (DFTRSTDISABLE), + .dftse_i (DFTSE), + .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_cpu0_sev_req (ds_cpu0_sev_req), + .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_cpu1_sev_req (ds_cpu1_sev_req), + .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_cpu2_sev_req (ds_cpu2_sev_req), + .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_cpu3_sev_req (ds_cpu3_sev_req), + .eventi_i (EVENTI), + .giccdisable_i (GICCDISABLE), + .l2_reset3 (l2_reset3), + .ncorereset_i (nCORERESET[`MAIA_CN:0]), + .ncpuporeset_i (nCPUPORESET[`MAIA_CN:0]), + .niden_i (NIDEN[`MAIA_CN:0]), + .nmbistreset_i (nMBISTRESET), + .pm_export_cpu0_i (pm_export_cpu0_i), + .pm_export_cpu1_i (pm_export_cpu1_i), + .pm_export_cpu2_i (pm_export_cpu2_i), + .pm_export_cpu3_i (pm_export_cpu3_i), + .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), + .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), + .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), + .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]), + .rvbaraddr0_i (RVBARADDR0[43:2]), + .rvbaraddr1_i (RVBARADDR1[43:2]), + .rvbaraddr2_i (RVBARADDR2[43:2]), + .rvbaraddr3_i (RVBARADDR3[43:2]), + .spiden_i (SPIDEN[`MAIA_CN:0]), + .spniden_i (SPNIDEN[`MAIA_CN:0]), + .vinithi_i (VINITHI[`MAIA_CN:0]) + ); // ucpu_io + + maia_dt_sb udt_sb( // outputs + .afreadym0_o (AFREADYM0), + .afreadym1_o (AFREADYM1), + .afreadym2_o (AFREADYM2), + .afreadym3_o (AFREADYM3), + .afvalidm_cpu0_o (afvalidm_cpu0_o), + .afvalidm_cpu1_o (afvalidm_cpu1_o), + .afvalidm_cpu2_o (afvalidm_cpu2_o), + .afvalidm_cpu3_o (afvalidm_cpu3_o), + .atbytesm0_o (ATBYTESM0[1:0]), + .atbytesm1_o (ATBYTESM1[1:0]), + .atbytesm2_o (ATBYTESM2[1:0]), + .atbytesm3_o (ATBYTESM3[1:0]), + .atclken_cpu0_o (atclken_cpu0_o), + .atclken_cpu1_o (atclken_cpu1_o), + .atclken_cpu2_o (atclken_cpu2_o), + .atclken_cpu3_o (atclken_cpu3_o), + .atdatam0_o (ATDATAM0[31:0]), + .atdatam1_o (ATDATAM1[31:0]), + .atdatam2_o (ATDATAM2[31:0]), + .atdatam3_o (ATDATAM3[31:0]), + .atidm0_o (ATIDM0[6:0]), + .atidm1_o (ATIDM1[6:0]), + .atidm2_o (ATIDM2[6:0]), + .atidm3_o (ATIDM3[6:0]), + .atreadym_cpu0_o (atreadym_cpu0_o), + .atreadym_cpu1_o (atreadym_cpu1_o), + .atreadym_cpu2_o (atreadym_cpu2_o), + .atreadym_cpu3_o (atreadym_cpu3_o), + .atvalidm0_o (ATVALIDM0), + .atvalidm1_o (ATVALIDM1), + .atvalidm2_o (ATVALIDM2), + .atvalidm3_o (ATVALIDM3), + .syncreqm_cpu0_o (syncreqm_cpu0_o), + .syncreqm_cpu1_o (syncreqm_cpu1_o), + .syncreqm_cpu2_o (syncreqm_cpu2_o), + .syncreqm_cpu3_o (syncreqm_cpu3_o), + .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), + .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), + .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), + .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), + + // inputs + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .TSVALUEB (TSVALUEB[63:0]), + .afreadym_cpu0_i (afreadym_cpu0_i), + .afreadym_cpu1_i (afreadym_cpu1_i), + .afreadym_cpu2_i (afreadym_cpu2_i), + .afreadym_cpu3_i (afreadym_cpu3_i), + .afvalidm0_i (AFVALIDM0), + .afvalidm1_i (AFVALIDM1), + .afvalidm2_i (AFVALIDM2), + .afvalidm3_i (AFVALIDM3), + .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), + .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), + .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), + .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), + .atclken_i (ATCLKEN), + .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), + .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), + .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), + .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), + .atidm_cpu0_i (atidm_cpu0_i[6:0]), + .atidm_cpu1_i (atidm_cpu1_i[6:0]), + .atidm_cpu2_i (atidm_cpu2_i[6:0]), + .atidm_cpu3_i (atidm_cpu3_i[6:0]), + .atreadym0_i (ATREADYM0), + .atreadym1_i (ATREADYM1), + .atreadym2_i (ATREADYM2), + .atreadym3_i (ATREADYM3), + .atvalidm_cpu0_i (atvalidm_cpu0_i), + .atvalidm_cpu1_i (atvalidm_cpu1_i), + .atvalidm_cpu2_i (atvalidm_cpu2_i), + .atvalidm_cpu3_i (atvalidm_cpu3_i), + .ck_gclkfr (ck_gclkfr), + .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), + .etclken_cpu0_i (etclken_cpu0_i), + .etclken_cpu1_i (etclken_cpu1_i), + .etclken_cpu2_i (etclken_cpu2_i), + .etclken_cpu3_i (etclken_cpu3_i), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nMBISTRESET (nMBISTRESET), + .syncreqm0_i (SYNCREQM0), + .syncreqm1_i (SYNCREQM1), + .syncreqm2_i (SYNCREQM2), + .syncreqm3_i (SYNCREQM3) + ); // udt_sb + + maia_ncpu_reg_rep uncpu_reg_rep( // outputs + .ds_cpu0_ic_aa64naa32_reg_o (ds_cpu0_ic_aa64naa32_i), + .ds_cpu0_ic_cpsr_mode_reg_o (ds_cpu0_ic_cpsr_mode_i[4:0]), + .ds_cpu0_ic_hcr_change_reg_o (ds_cpu0_ic_hcr_change_i), + .ds_cpu0_ic_sample_spr_reg_o (ds_cpu0_ic_sample_spr_i), + .ds_cpu0_ic_scr_change_reg_o (ds_cpu0_ic_scr_change_i), + .ds_cpu1_ic_aa64naa32_reg_o (ds_cpu1_ic_aa64naa32_i), + .ds_cpu1_ic_cpsr_mode_reg_o (ds_cpu1_ic_cpsr_mode_i[4:0]), + .ds_cpu1_ic_hcr_change_reg_o (ds_cpu1_ic_hcr_change_i), + .ds_cpu1_ic_sample_spr_reg_o (ds_cpu1_ic_sample_spr_i), + .ds_cpu1_ic_scr_change_reg_o (ds_cpu1_ic_scr_change_i), + .ds_cpu2_ic_aa64naa32_reg_o (ds_cpu2_ic_aa64naa32_i), + .ds_cpu2_ic_cpsr_mode_reg_o (ds_cpu2_ic_cpsr_mode_i[4:0]), + .ds_cpu2_ic_hcr_change_reg_o (ds_cpu2_ic_hcr_change_i), + .ds_cpu2_ic_sample_spr_reg_o (ds_cpu2_ic_sample_spr_i), + .ds_cpu2_ic_scr_change_reg_o (ds_cpu2_ic_scr_change_i), + .ds_cpu3_ic_aa64naa32_reg_o (ds_cpu3_ic_aa64naa32_i), + .ds_cpu3_ic_cpsr_mode_reg_o (ds_cpu3_ic_cpsr_mode_i[4:0]), + .ds_cpu3_ic_hcr_change_reg_o (ds_cpu3_ic_hcr_change_i), + .ds_cpu3_ic_sample_spr_reg_o (ds_cpu3_ic_sample_spr_i), + .ds_cpu3_ic_scr_change_reg_o (ds_cpu3_ic_scr_change_i), + .ic_block_eoi_sgi_wr_reg_o (ic_block_eoi_sgi_wr[`MAIA_CN:0]), + .ic_el_change_complete_reg_o (ic_el_change_complete[`MAIA_CN:0]), + .ic_hcr_change_complete_reg_o (ic_hcr_change_complete[`MAIA_CN:0]), + .ic_ich_el2_tall0_reg_o (ic_ich_el2_tall0[`MAIA_CN:0]), + .ic_ich_el2_tall1_reg_o (ic_ich_el2_tall1[`MAIA_CN:0]), + .ic_ich_el2_tc_reg_o (ic_ich_el2_tc[`MAIA_CN:0]), + .ic_nfiq_reg_o (ic_nfiq[`MAIA_CN:0]), + .ic_nirq_reg_o (ic_nirq[`MAIA_CN:0]), + .ic_nsei_reg_o (ic_nsei[`MAIA_CN:0]), + .ic_nvfiq_reg_o (ic_nvfiq[`MAIA_CN:0]), + .ic_nvirq_reg_o (ic_nvirq[`MAIA_CN:0]), + .ic_nvsei_reg_o (ic_nvsei[`MAIA_CN:0]), + .ic_sample_spr_reg_o (ic_sample_spr[`MAIA_CN:0]), + .ic_scr_change_complete_reg_o (ic_scr_change_complete[`MAIA_CN:0]), + .ic_sra_el1ns_en_reg_o (ic_sra_el1ns_en[`MAIA_CN:0]), + .ic_sra_el1s_en_reg_o (ic_sra_el1s_en[`MAIA_CN:0]), + .ic_sra_el2_en_reg_o (ic_sra_el2_en[`MAIA_CN:0]), + .ic_sra_el3_en_reg_o (ic_sra_el3_en[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap_reg_o (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap_reg_o (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap_reg_o (ic_sre_el1s_mon_trap[`MAIA_CN:0]), + .ic_sre_el2_mon_trap_reg_o (ic_sre_el2_mon_trap[`MAIA_CN:0]), + + // inputs + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), + .ic_el_change_complete (ic_el_change_complete_o[`MAIA_CN:0]), + .ic_hcr_change_complete (ic_hcr_change_complete_o[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .ic_sample_spr (ic_sample_spr_o[`MAIA_CN:0]), + .ic_scr_change_complete (ic_scr_change_complete_o[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]) + ); // uncpu_reg_rep + +//----------------------------------------------------------------------------- +// OVL Assertions +//----------------------------------------------------------------------------- +`ifdef ARM_ASSERT_ON + `include "maia_noncpu_feq20_s_val.v" +`endif + +endmodule // maia_noncpu_feq20_s + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28.v b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28.v new file mode 100644 index 0000000000..cf90e92932 --- /dev/null +++ b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28.v @@ -0,0 +1,7934 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: maia_noncpu_feq28.v $ +// Checked In : $Date: 2015-05-06 10:47:09 -0500 (Wed, 06 May 2015) $ +// Revision : $Revision: 73443 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// +// This is top-level interconnect layer for the non-CPU blocks at the Maia top-level. +// + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +`define MAIA_CN 3 + +module maia_noncpu_feq28 ( + CLK, + CLKEN, + nCPUPORESET, + nCORERESET, + nL2RESET, + L2RSTDISABLE, + WARMRSTREQ, + CFGEND, + VINITHI, + CFGTE, + CP15SDISABLE, + CLUSTERIDAFF1, + CLUSTERIDAFF2, + AA64nAA32, + RVBARADDR0, +// BEGIN INCLUDE FOR CPU1 + RVBARADDR1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + RVBARADDR2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + RVBARADDR3, +// END INCLUDE FOR CPU3 + CRYPTODISABLE, + nFIQ, + nIRQ, + nSEI, + nREI, + nVFIQ, + nVIRQ, + nVSEI, +// BEGIN NO-GIC pins + nVCPUMNTIRQ, +// END NO-GIC pins + PERIPHBASE, +// BEGIN NO-GIC pins + GICCDISABLE, + ICDTVALID, + ICDTREADY, + ICDTDATA, + ICDTLAST, + ICDTDEST, + ICCTVALID, + ICCTREADY, + ICCTDATA, + ICCTLAST, + ICCTID, +// END NO-GIC pins + CNTVALUEB, + CNTCLKEN, + nCNTPNSIRQ, + nCNTPSIRQ, + nCNTVIRQ, + nCNTHPIRQ, + CLREXMONREQ, + CLREXMONACK, + EVENTI, + EVENTO, + STANDBYWFI, + STANDBYWFE, + STANDBYWFIL2, + SMPEN, + CPUQACTIVE, + CPUQREQn, + CPUQACCEPTn, + CPUQDENY, + L2QACTIVE, + L2QREQn, + L2QACCEPTn, + L2QDENY, + L2FLUSHREQ, + L2FLUSHDONE, + nINTERRIRQ, + nEXTERRIRQ, + SYSBARDISABLE, + BROADCASTINNER, + BROADCASTOUTER, + BROADCASTCACHEMAINT, + ACLKENM, + ACINACTM, + AWREADYM, + AWVALIDM, + AWIDM, + AWADDRM, + AWLENM, + AWSIZEM, + AWBURSTM, + AWBARM, + AWDOMAINM, + AWLOCKM, + AWCACHEM, + AWPROTM, + AWSNOOPM, + AWUNIQUEM, + WRMEMATTR, + WREADYM, + WVALIDM, + WDATAM, + WSTRBM, + WIDM, + WLASTM, + BREADYM, + BVALIDM, + BIDM, + BRESPM, + ARREADYM, + ARVALIDM, + ARIDM, + ARADDRM, + ARLENM, + ARSIZEM, + ARBURSTM, + ARBARM, + ARDOMAINM, + ARLOCKM, + ARCACHEM, + ARPROTM, + ARSNOOPM, + RDMEMATTR, + RREADYM, + RVALIDM, + RIDM, + RDATAM, + RRESPM, + RLASTM, + ACREADYM, + ACVALIDM, + ACADDRM, + ACPROTM, + ACSNOOPM, + CRREADYM, + CRVALIDM, + CRRESPM, + CDREADYM, + CDVALIDM, + CDDATAM, + CDLASTM, + RACKM, + WACKM, + ACLKENS, + AINACTS, +// BEGIN NO-ACP pins + AWREADYS, + AWVALIDS, + AWIDS, + AWADDRS, + AWLENS, + AWCACHES, + AWUSERS, + AWPROTS, + WREADYS, + WVALIDS, + WDATAS, + WSTRBS, + WLASTS, + BREADYS, + BVALIDS, + BIDS, + BRESPS, + ARREADYS, + ARVALIDS, + ARIDS, + ARADDRS, + ARLENS, + ARCACHES, + ARUSERS, + ARPROTS, + RREADYS, + RVALIDS, + RIDS, + RDATAS, + RRESPS, + RLASTS, +// END NO-ACP pins + DBGROMADDR, + DBGROMADDRV, + DBGACK, + nCOMMIRQ, + COMMRX, + COMMTX, + DBGRSTREQ, + DBGNOPWRDWN, + DBGL1RSTDISABLE, + nPMUIRQ, + PMUEVENT0, +// BEGIN INCLUDE FOR CPU1 + PMUEVENT1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + PMUEVENT2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + PMUEVENT3, +// END INCLUDE FOR CPU3 + ATCLKEN, + TSVALUEB, + ATREADYM0, + AFVALIDM0, + ATDATAM0, + ATVALIDM0, + ATBYTESM0, + AFREADYM0, + ATIDM0, + SYNCREQM0, +// BEGIN INCLUDE FOR CPU1 + ATREADYM1, + AFVALIDM1, + ATDATAM1, + ATVALIDM1, + ATBYTESM1, + AFREADYM1, + ATIDM1, + SYNCREQM1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ATREADYM2, + AFVALIDM2, + ATDATAM2, + ATVALIDM2, + ATBYTESM2, + AFREADYM2, + ATIDM2, + SYNCREQM2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ATREADYM3, + AFVALIDM3, + ATDATAM3, + ATVALIDM3, + ATBYTESM3, + AFREADYM3, + ATIDM3, + SYNCREQM3, +// END INCLUDE FOR CPU3 + PCLKDBG, + PCLKENDBG, + nPRESETDBG, + PSELDBG, + PADDRDBG, + PADDRDBG31, + PENABLEDBG, + PWRITEDBG, + PWDATADBG, + PRDATADBG, + PREADYDBG, + PSLVERRDBG, + EDBGRQ, + PMUSNAPSHOTREQ, + PMUSNAPSHOTACK, + DBGPWRDUP, + DBGPWRUPREQ, + CTICHIN, + CTICHOUTACK, + CTICHOUT, + CTICHINACK, + CISBYPASS, + CIHSBYPASS, + CTIIRQ, + CTIIRQACK, + DBGEN, + NIDEN, + SPIDEN, + SPNIDEN, + DFTSE, + DFTRSTDISABLE, + DFTCRCLKDISABLE, + DFTL2CLKDISABLE, + DFTRAMHOLD, + DFTCLKBYPASS, + DFTMCPHOLD, + nMBISTRESET, + MBISTREQ, + +//----------------------------------------------------------------------------- +// Signals from maia -> maia_cpu_io -> maia_cpu +//----------------------------------------------------------------------------- +// Outputs to maia_cpu + ncpuporeset_cpu0_o, + ncorereset_cpu0_o, + + cfgend_cpu0_o, + cfgte_cpu0_o, + cp15sdisable_cpu0_o, + vinithi_cpu0_o, + clusteridaff1_cpu0_o, + clusteridaff2_cpu0_o, + cpuid_cpu0_o, + aa64naa32_cpu0_o, + rvbaraddr_cpu0_o, + cryptodisable_cpu0_o, + giccdisable_cpu0_o, + + dbgromaddr_cpu0_o, + dbgromaddrv_cpu0_o, + dbgl1rstdisable_cpu0_o, + + dbgen_cpu0_o, + niden_cpu0_o, + spiden_cpu0_o, + spniden_cpu0_o, + + tsvalueb_cpu0_o, + + atclken_cpu0_o, + afvalidm_cpu0_o, + atreadym_cpu0_o, + syncreqm_cpu0_o, + + dftse_cpu0_o, + dftrstdisable_cpu0_o, + dftcrclkdisable_cpu0_o, + dftramhold_cpu0_o, + + nmbistreset_cpu0_o, + +// BEGIN INCLUDE FOR CPU1 + ncpuporeset_cpu1_o, + ncorereset_cpu1_o, + + cfgend_cpu1_o, + cfgte_cpu1_o, + cp15sdisable_cpu1_o, + vinithi_cpu1_o, + clusteridaff1_cpu1_o, + clusteridaff2_cpu1_o, + cpuid_cpu1_o, + aa64naa32_cpu1_o, + rvbaraddr_cpu1_o, + cryptodisable_cpu1_o, + giccdisable_cpu1_o, + + dbgromaddr_cpu1_o, + dbgromaddrv_cpu1_o, + dbgl1rstdisable_cpu1_o, + + dbgen_cpu1_o, + niden_cpu1_o, + spiden_cpu1_o, + spniden_cpu1_o, + + tsvalueb_cpu1_o, + + atclken_cpu1_o, + afvalidm_cpu1_o, + atreadym_cpu1_o, + syncreqm_cpu1_o, + + dftse_cpu1_o, + dftrstdisable_cpu1_o, + dftcrclkdisable_cpu1_o, + dftramhold_cpu1_o, + + nmbistreset_cpu1_o, +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + ncpuporeset_cpu2_o, + ncorereset_cpu2_o, + + cfgend_cpu2_o, + cfgte_cpu2_o, + cp15sdisable_cpu2_o, + vinithi_cpu2_o, + clusteridaff1_cpu2_o, + clusteridaff2_cpu2_o, + cpuid_cpu2_o, + aa64naa32_cpu2_o, + rvbaraddr_cpu2_o, + cryptodisable_cpu2_o, + giccdisable_cpu2_o, + + dbgromaddr_cpu2_o, + dbgromaddrv_cpu2_o, + dbgl1rstdisable_cpu2_o, + + dbgen_cpu2_o, + niden_cpu2_o, + spiden_cpu2_o, + spniden_cpu2_o, + + tsvalueb_cpu2_o, + + atclken_cpu2_o, + afvalidm_cpu2_o, + atreadym_cpu2_o, + syncreqm_cpu2_o, + + dftse_cpu2_o, + dftrstdisable_cpu2_o, + dftcrclkdisable_cpu2_o, + dftramhold_cpu2_o, + + nmbistreset_cpu2_o, +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + ncpuporeset_cpu3_o, + ncorereset_cpu3_o, + + cfgend_cpu3_o, + cfgte_cpu3_o, + cp15sdisable_cpu3_o, + vinithi_cpu3_o, + clusteridaff1_cpu3_o, + clusteridaff2_cpu3_o, + cpuid_cpu3_o, + aa64naa32_cpu3_o, + rvbaraddr_cpu3_o, + cryptodisable_cpu3_o, + giccdisable_cpu3_o, + + dbgromaddr_cpu3_o, + dbgromaddrv_cpu3_o, + dbgl1rstdisable_cpu3_o, + + dbgen_cpu3_o, + niden_cpu3_o, + spiden_cpu3_o, + spniden_cpu3_o, + + tsvalueb_cpu3_o, + + atclken_cpu3_o, + afvalidm_cpu3_o, + atreadym_cpu3_o, + syncreqm_cpu3_o, + + dftse_cpu3_o, + dftrstdisable_cpu3_o, + dftcrclkdisable_cpu3_o, + dftramhold_cpu3_o, + + nmbistreset_cpu3_o, +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Signals from maia_cpu -> maia_cpu_io -> maia +//----------------------------------------------------------------------------- +// Inputs from maia_cpu + ds_cpu0_sev_req, + ds_cpu0_sevl_req, + ds_cpu0_cpuectlr_smp, + + ncommirq_cpu0_i, + commrx_cpu0_i, + commtx_cpu0_i, + dbgack_cpu0_i, + dbgrstreq_cpu0_i, + dbgnopwrdwn_cpu0_i, + + npmuirq_cpu0_i, + pmuevent_cpu0_i, + pm_export_cpu0_i, + + etclken_cpu0_i, + afreadym_cpu0_i, + atbytesm_cpu0_i, + atdatam_cpu0_i, + atidm_cpu0_i, + atvalidm_cpu0_i, + +// BEGIN INCLUDE FOR CPU1 + ds_cpu1_sev_req, + ds_cpu1_sevl_req, + ds_cpu1_cpuectlr_smp, + + ncommirq_cpu1_i, + commrx_cpu1_i, + commtx_cpu1_i, + dbgack_cpu1_i, + dbgrstreq_cpu1_i, + dbgnopwrdwn_cpu1_i, + + npmuirq_cpu1_i, + pmuevent_cpu1_i, + pm_export_cpu1_i, + + etclken_cpu1_i, + afreadym_cpu1_i, + atbytesm_cpu1_i, + atdatam_cpu1_i, + atidm_cpu1_i, + atvalidm_cpu1_i, +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + ds_cpu2_sev_req, + ds_cpu2_sevl_req, + ds_cpu2_cpuectlr_smp, + + ncommirq_cpu2_i, + commrx_cpu2_i, + commtx_cpu2_i, + dbgack_cpu2_i, + dbgrstreq_cpu2_i, + dbgnopwrdwn_cpu2_i, + + npmuirq_cpu2_i, + pmuevent_cpu2_i, + pm_export_cpu2_i, + + etclken_cpu2_i, + afreadym_cpu2_i, + atbytesm_cpu2_i, + atdatam_cpu2_i, + atidm_cpu2_i, + atvalidm_cpu2_i, +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + ds_cpu3_sev_req, + ds_cpu3_sevl_req, + ds_cpu3_cpuectlr_smp, + + ncommirq_cpu3_i, + commrx_cpu3_i, + commtx_cpu3_i, + dbgack_cpu3_i, + dbgrstreq_cpu3_i, + dbgnopwrdwn_cpu3_i, + + npmuirq_cpu3_i, + pmuevent_cpu3_i, + pm_export_cpu3_i, + + etclken_cpu3_i, + afreadym_cpu3_i, + atbytesm_cpu3_i, + atdatam_cpu3_i, + atidm_cpu3_i, + atvalidm_cpu3_i, +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// L2 interface +//----------------------------------------------------------------------------- + l2_cpu0_mbist1_addr_b1, + l2_cpu0_mbist1_array_b1, + l2_cpu0_mbist1_be_b1, + l2_cpu0_mbist1_en_b1, + l2_cpu0_mbist1_rd_en_b1, + l2_cpu0_mbist1_wr_en_b1, + l2_cpu0_mbist1_all_b1, +// BEGIN INCLUDE FOR CPU1 + l2_cpu1_mbist1_addr_b1, + l2_cpu1_mbist1_array_b1, + l2_cpu1_mbist1_be_b1, + l2_cpu1_mbist1_en_b1, + l2_cpu1_mbist1_rd_en_b1, + l2_cpu1_mbist1_wr_en_b1, + l2_cpu1_mbist1_all_b1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + l2_cpu2_mbist1_addr_b1, + l2_cpu2_mbist1_array_b1, + l2_cpu2_mbist1_be_b1, + l2_cpu2_mbist1_en_b1, + l2_cpu2_mbist1_rd_en_b1, + l2_cpu2_mbist1_wr_en_b1, + l2_cpu2_mbist1_all_b1, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + l2_cpu3_mbist1_addr_b1, + l2_cpu3_mbist1_array_b1, + l2_cpu3_mbist1_be_b1, + l2_cpu3_mbist1_en_b1, + l2_cpu3_mbist1_rd_en_b1, + l2_cpu3_mbist1_wr_en_b1, + l2_cpu3_mbist1_all_b1, +// END INCLUDE FOR CPU3 + +// BEGIN L2-CPU interface + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + l2_cpu0_cfg_ecc_en, + l2_cpu0_arb_thrshld_timeout_en, + l2_cpu0_disable_clean_evict_opt, + l2_cpu0_dext_err_r2, + l2_cpu0_dext_err_type_r2, + l2_cpu0_dsngl_ecc_err_r3, + l2_cpu0_ddbl_ecc_err_r3, + l2_cpu0_ddata_r2, + l2_cpu0_barrier_done, + l2_cpu0_spec_valid, + l2_cpu0_spec_bufid, + l2_cpu0_rvalid, + l2_cpu0_rstate, + l2_cpu0_rexfail, + l2_cpu0_rbufid, + l2_cpu0_dvalid_r1, + l2_cpu0_dlast_r1, + l2_cpu0_dbufid_r1, + l2_cpu0_iext_err_r2, + l2_cpu0_iext_err_type_r2, + l2_cpu0_isngl_ecc_err_r3, + l2_cpu0_idbl_ecc_err_r3, + l2_cpu0_idata_r2, + l2_cpu0_ivalid_r1, + l2_cpu0_ibufid_r1, + l2_cpu0_ls_sync_req, + l2_cpu0_ccb_req_addr_c3, + l2_cpu0_ccb_dbg_req_c3, + l2_cpu0_ls_ccb_clken_c3, + l2_cpu0_ls_ccb_req_c3, + l2_cpu0_ccb_req_id_c3, + l2_cpu0_ccb_req_type_c3, + l2_cpu0_ccb_req_info_c3, + l2_cpu0_if_ccb_clken_c3, + l2_cpu0_if_ccb_req_c3, + l2_cpu0_if_sync_req, + l2_cpu0_tlb_ccb_clken_c3, + l2_cpu0_tlb_ccb_req_c3, + l2_cpu0_tlb_sync_req, + l2_cpu0_tlb_sync_complete, + l2_cpu0_tbw_desc_vld, + l2_cpu0_tbw_ext_err, + l2_cpu0_tbw_ext_err_type, + l2_cpu0_tbw_dbl_ecc_err, + l2_cpu0_tbw_desc_data, + l2_cpu0_spr_rd_data, + l2_cpu0_l2_cache_size, + l2_cpu0_pf_throttle_q, + + l2_cpu0_wr_ex_resp, + l2_cpu0_wr_ex_fail, + + l2_cpu0_ic_base, + l2_cpu0_no_intctrl, + + + l2_cpu0_pmu_events, + + ds_cpu0_l2_spr_en, + ds_cpu0_l2_spr_rd, + ds_cpu0_l2_spr_wr, + ds_cpu0_l2_spr_addr, + ds_cpu0_l2_spr_dw, + ds_cpu0_l2_spr_wr_data, + + l2_cpu0_wr_data_vld_x1_q, + l2_cpu0_wr_evict_x1_q, + l2_cpu0_wr_data, + l2_cpu0_ls_rd_haz_vld_arb_q, + l2_cpu0_ls_wr_haz_vld_arb_q, + l2_cpu0_dt_pmu_evt_en, + + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + l2_cpu1_cfg_ecc_en, + l2_cpu1_arb_thrshld_timeout_en, + l2_cpu1_disable_clean_evict_opt, + l2_cpu1_dext_err_r2, + l2_cpu1_dext_err_type_r2, + l2_cpu1_dsngl_ecc_err_r3, + l2_cpu1_ddbl_ecc_err_r3, + l2_cpu1_ddata_r2, + l2_cpu1_barrier_done, + l2_cpu1_spec_valid, + l2_cpu1_spec_bufid, + l2_cpu1_rvalid, + l2_cpu1_rstate, + l2_cpu1_rexfail, + l2_cpu1_rbufid, + l2_cpu1_dvalid_r1, + l2_cpu1_dlast_r1, + l2_cpu1_dbufid_r1, + l2_cpu1_iext_err_r2, + l2_cpu1_iext_err_type_r2, + l2_cpu1_isngl_ecc_err_r3, + l2_cpu1_idbl_ecc_err_r3, + l2_cpu1_idata_r2, + l2_cpu1_ivalid_r1, + l2_cpu1_ibufid_r1, + l2_cpu1_ls_sync_req, + l2_cpu1_ccb_req_addr_c3, + l2_cpu1_ccb_dbg_req_c3, + l2_cpu1_ls_ccb_clken_c3, + l2_cpu1_ls_ccb_req_c3, + l2_cpu1_ccb_req_id_c3, + l2_cpu1_ccb_req_type_c3, + l2_cpu1_ccb_req_info_c3, + l2_cpu1_if_ccb_clken_c3, + l2_cpu1_if_ccb_req_c3, + l2_cpu1_if_sync_req, + l2_cpu1_tlb_ccb_clken_c3, + l2_cpu1_tlb_ccb_req_c3, + l2_cpu1_tlb_sync_req, + l2_cpu1_tlb_sync_complete, + l2_cpu1_tbw_desc_vld, + l2_cpu1_tbw_ext_err, + l2_cpu1_tbw_ext_err_type, + l2_cpu1_tbw_dbl_ecc_err, + l2_cpu1_tbw_desc_data, + l2_cpu1_spr_rd_data, + l2_cpu1_l2_cache_size, + l2_cpu1_pf_throttle_q, + + l2_cpu1_wr_ex_resp, + l2_cpu1_wr_ex_fail, + + l2_cpu1_ic_base, + l2_cpu1_no_intctrl, + + l2_cpu1_pmu_events, + + ds_cpu1_l2_spr_en, + ds_cpu1_l2_spr_rd, + ds_cpu1_l2_spr_wr, + ds_cpu1_l2_spr_addr, + ds_cpu1_l2_spr_dw, + ds_cpu1_l2_spr_wr_data, + + l2_cpu1_wr_data_vld_x1_q, + l2_cpu1_wr_evict_x1_q, + l2_cpu1_wr_data, + l2_cpu1_ls_rd_haz_vld_arb_q, + l2_cpu1_ls_wr_haz_vld_arb_q, + l2_cpu1_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + l2_cpu2_cfg_ecc_en, + l2_cpu2_arb_thrshld_timeout_en, + l2_cpu2_disable_clean_evict_opt, + l2_cpu2_dext_err_r2, + l2_cpu2_dext_err_type_r2, + l2_cpu2_dsngl_ecc_err_r3, + l2_cpu2_ddbl_ecc_err_r3, + l2_cpu2_ddata_r2, + l2_cpu2_barrier_done, + l2_cpu2_spec_valid, + l2_cpu2_spec_bufid, + l2_cpu2_rvalid, + l2_cpu2_rstate, + l2_cpu2_rexfail, + l2_cpu2_rbufid, + l2_cpu2_dvalid_r1, + l2_cpu2_dlast_r1, + l2_cpu2_dbufid_r1, + l2_cpu2_iext_err_r2, + l2_cpu2_iext_err_type_r2, + l2_cpu2_isngl_ecc_err_r3, + l2_cpu2_idbl_ecc_err_r3, + l2_cpu2_idata_r2, + l2_cpu2_ivalid_r1, + l2_cpu2_ibufid_r1, + l2_cpu2_ls_sync_req, + l2_cpu2_ccb_req_addr_c3, + l2_cpu2_ccb_dbg_req_c3, + l2_cpu2_ls_ccb_clken_c3, + l2_cpu2_ls_ccb_req_c3, + l2_cpu2_ccb_req_id_c3, + l2_cpu2_ccb_req_type_c3, + l2_cpu2_ccb_req_info_c3, + l2_cpu2_if_ccb_clken_c3, + l2_cpu2_if_ccb_req_c3, + l2_cpu2_if_sync_req, + l2_cpu2_tlb_ccb_clken_c3, + l2_cpu2_tlb_ccb_req_c3, + l2_cpu2_tlb_sync_req, + l2_cpu2_tlb_sync_complete, + l2_cpu2_tbw_desc_vld, + l2_cpu2_tbw_ext_err, + l2_cpu2_tbw_ext_err_type, + l2_cpu2_tbw_dbl_ecc_err, + l2_cpu2_tbw_desc_data, + l2_cpu2_spr_rd_data, + l2_cpu2_l2_cache_size, + l2_cpu2_pf_throttle_q, + + l2_cpu2_wr_ex_resp, + l2_cpu2_wr_ex_fail, + + l2_cpu2_ic_base, + l2_cpu2_no_intctrl, + + l2_cpu2_pmu_events, + + ds_cpu2_l2_spr_en, + ds_cpu2_l2_spr_rd, + ds_cpu2_l2_spr_wr, + ds_cpu2_l2_spr_addr, + ds_cpu2_l2_spr_dw, + ds_cpu2_l2_spr_wr_data, + + l2_cpu2_wr_data_vld_x1_q, + l2_cpu2_wr_evict_x1_q, + l2_cpu2_wr_data, + l2_cpu2_ls_rd_haz_vld_arb_q, + l2_cpu2_ls_wr_haz_vld_arb_q, + l2_cpu2_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + l2_cpu3_cfg_ecc_en, + l2_cpu3_arb_thrshld_timeout_en, + l2_cpu3_disable_clean_evict_opt, + l2_cpu3_dext_err_r2, + l2_cpu3_dext_err_type_r2, + l2_cpu3_dsngl_ecc_err_r3, + l2_cpu3_ddbl_ecc_err_r3, + l2_cpu3_ddata_r2, + l2_cpu3_barrier_done, + l2_cpu3_spec_valid, + l2_cpu3_spec_bufid, + l2_cpu3_rvalid, + l2_cpu3_rstate, + l2_cpu3_rexfail, + l2_cpu3_rbufid, + l2_cpu3_dvalid_r1, + l2_cpu3_dlast_r1, + l2_cpu3_dbufid_r1, + l2_cpu3_iext_err_r2, + l2_cpu3_iext_err_type_r2, + l2_cpu3_isngl_ecc_err_r3, + l2_cpu3_idbl_ecc_err_r3, + l2_cpu3_idata_r2, + l2_cpu3_ivalid_r1, + l2_cpu3_ibufid_r1, + l2_cpu3_ls_sync_req, + l2_cpu3_ccb_req_addr_c3, + l2_cpu3_ccb_dbg_req_c3, + l2_cpu3_ls_ccb_clken_c3, + l2_cpu3_ls_ccb_req_c3, + l2_cpu3_ccb_req_id_c3, + l2_cpu3_ccb_req_type_c3, + l2_cpu3_ccb_req_info_c3, + l2_cpu3_if_ccb_clken_c3, + l2_cpu3_if_ccb_req_c3, + l2_cpu3_if_sync_req, + l2_cpu3_tlb_ccb_clken_c3, + l2_cpu3_tlb_ccb_req_c3, + l2_cpu3_tlb_sync_req, + l2_cpu3_tlb_sync_complete, + l2_cpu3_tbw_desc_vld, + l2_cpu3_tbw_ext_err, + l2_cpu3_tbw_ext_err_type, + l2_cpu3_tbw_dbl_ecc_err, + l2_cpu3_tbw_desc_data, + l2_cpu3_spr_rd_data, + l2_cpu3_l2_cache_size, + l2_cpu3_pf_throttle_q, + + l2_cpu3_wr_ex_resp, + l2_cpu3_wr_ex_fail, + + l2_cpu3_ic_base, + l2_cpu3_no_intctrl, + + l2_cpu3_pmu_events, + + ds_cpu3_l2_spr_en, + ds_cpu3_l2_spr_rd, + ds_cpu3_l2_spr_wr, + ds_cpu3_l2_spr_addr, + ds_cpu3_l2_spr_dw, + ds_cpu3_l2_spr_wr_data, + + l2_cpu3_wr_data_vld_x1_q, + l2_cpu3_wr_evict_x1_q, + l2_cpu3_wr_data, + l2_cpu3_ls_rd_haz_vld_arb_q, + l2_cpu3_ls_wr_haz_vld_arb_q, + l2_cpu3_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// tag_pipe / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_flsh_ls_rd_l2_dly, + l2_cpu0_flsh_ls_wr_l2_dly, + + l2_cpu0_wr_data_stall, + + l2_cpu1_flsh_ls_rd_l2_dly, + l2_cpu1_flsh_ls_wr_l2_dly, + + l2_cpu1_wr_data_stall, + + l2_cpu2_flsh_ls_rd_l2_dly, + l2_cpu2_flsh_ls_wr_l2_dly, + + l2_cpu2_wr_data_stall, + + l2_cpu3_flsh_ls_rd_l2_dly, + l2_cpu3_flsh_ls_wr_l2_dly, + + l2_cpu3_wr_data_stall, + + l2_cpu0_flsh_ls_rd_id_l2_dly, + l2_cpu0_flsh_ls_wr_id_l2_dly, + + l2_cpu1_flsh_ls_rd_id_l2_dly, + l2_cpu1_flsh_ls_wr_id_l2_dly, + + l2_cpu2_flsh_ls_rd_id_l2_dly, + l2_cpu2_flsh_ls_wr_id_l2_dly, + + l2_cpu3_flsh_ls_rd_id_l2_dly, + l2_cpu3_flsh_ls_wr_id_l2_dly, + + l2_cpu0_flsh_ls_rd_l4_dly, + l2_cpu0_flsh_if_rd_l4_dly, + l2_cpu0_flsh_tw_rd_l4_dly, + l2_cpu0_flsh_ls_wr_l4_dly, + + l2_cpu1_flsh_ls_rd_l4_dly, + l2_cpu1_flsh_if_rd_l4_dly, + l2_cpu1_flsh_tw_rd_l4_dly, + l2_cpu1_flsh_ls_wr_l4_dly, + + l2_cpu2_flsh_ls_rd_l4_dly, + l2_cpu2_flsh_if_rd_l4_dly, + l2_cpu2_flsh_tw_rd_l4_dly, + l2_cpu2_flsh_ls_wr_l4_dly, + + l2_cpu3_flsh_ls_rd_l4_dly, + l2_cpu3_flsh_if_rd_l4_dly, + l2_cpu3_flsh_tw_rd_l4_dly, + l2_cpu3_flsh_ls_wr_l4_dly, + + l2_cpu0_flsh_ls_rd_id_l4_dly, + l2_cpu0_flsh_if_rd_id_l4_dly, + l2_cpu0_flsh_ls_wr_id_l4_dly, + l2_cpu0_flsh_ls_wr_evict_l4_dly, + + l2_cpu1_flsh_ls_rd_id_l4_dly, + l2_cpu1_flsh_if_rd_id_l4_dly, + l2_cpu1_flsh_ls_wr_id_l4_dly, + l2_cpu1_flsh_ls_wr_evict_l4_dly, + + l2_cpu2_flsh_ls_rd_id_l4_dly, + l2_cpu2_flsh_if_rd_id_l4_dly, + l2_cpu2_flsh_ls_wr_id_l4_dly, + l2_cpu2_flsh_ls_wr_evict_l4_dly, + + l2_cpu3_flsh_ls_rd_id_l4_dly, + l2_cpu3_flsh_if_rd_id_l4_dly, + l2_cpu3_flsh_ls_wr_id_l4_dly, + l2_cpu3_flsh_ls_wr_evict_l4_dly, + + l2_cpu0_lrq_haz_pending, + l2_cpu1_lrq_haz_pending, + l2_cpu2_lrq_haz_pending, + l2_cpu3_lrq_haz_pending, + + l2_cpu0_ifq_haz_pending, + l2_cpu1_ifq_haz_pending, + l2_cpu2_ifq_haz_pending, + l2_cpu3_ifq_haz_pending, + + l2_cpu0_trq_haz_pending, + l2_cpu1_trq_haz_pending, + l2_cpu2_trq_haz_pending, + l2_cpu3_trq_haz_pending, + + l2_cpu0_wrq_haz_pending, + l2_cpu1_wrq_haz_pending, + l2_cpu2_wrq_haz_pending, + l2_cpu3_wrq_haz_pending, + + l2_cpu0_idle_block_reqs_q, + l2_cpu1_idle_block_reqs_q, + l2_cpu2_idle_block_reqs_q, + l2_cpu3_idle_block_reqs_q, + + l2_cpu0_ls_peq_coll_l4_dly, + l2_cpu1_ls_peq_coll_l4_dly, + l2_cpu2_ls_peq_coll_l4_dly, + l2_cpu3_ls_peq_coll_l4_dly, + +//----------------------------------------------------------------------------- +// tag_pipe +//----------------------------------------------------------------------------- + l2_tbnk0_cpu0_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu1_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu2_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu3_lrq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu1_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu2_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu3_lrq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu1_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu2_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu3_ifq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu1_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu2_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu3_ifq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_trq_clr_l4_dly2_q, + l2_tbnk0_cpu1_trq_clr_l4_dly2_q, + l2_tbnk0_cpu2_trq_clr_l4_dly2_q, + l2_tbnk0_cpu3_trq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_trq_clr_l4_dly2_q, + l2_tbnk1_cpu1_trq_clr_l4_dly2_q, + l2_tbnk1_cpu2_trq_clr_l4_dly2_q, + l2_tbnk1_cpu3_trq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu1_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu2_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu3_wrq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu1_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu2_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu3_wrq_clr_l4_dly2_q, + + +//----------------------------------------------------------------------------- +// cpu_logic / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly, + + +//----------------------------------------------------------------------------- +// feq / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_dsq_rd_data_q, + l2_cpu0_dsq_rd_byte_strb_q, + l2_cpu1_dsq_rd_data_q, + l2_cpu1_dsq_rd_byte_strb_q, + l2_cpu2_dsq_rd_data_q, + l2_cpu2_dsq_rd_byte_strb_q, + l2_cpu3_dsq_rd_data_q, + l2_cpu3_dsq_rd_byte_strb_q, + + l2_cpu0_dsq_clr_vld_q, + l2_cpu0_dsq_clr_id_q, + l2_cpu0_dsq_rd_en, + l2_cpu0_dsq_rd_en_x2, + l2_cpu0_dsq_rd_buf_id, + l2_cpu1_dsq_clr_vld_q, + l2_cpu1_dsq_clr_id_q, + l2_cpu1_dsq_rd_en, + l2_cpu1_dsq_rd_en_x2, + l2_cpu1_dsq_rd_buf_id, + l2_cpu2_dsq_clr_vld_q, + l2_cpu2_dsq_clr_id_q, + l2_cpu2_dsq_rd_en, + l2_cpu2_dsq_rd_en_x2, + l2_cpu2_dsq_rd_buf_id, + l2_cpu3_dsq_clr_vld_q, + l2_cpu3_dsq_rd_en, + l2_cpu3_dsq_rd_en_x2, + l2_cpu3_dsq_clr_id_q, + l2_cpu3_dsq_rd_buf_id, + +//----------------------------------------------------------------------------- +// arbitration +//----------------------------------------------------------------------------- + l2_cpu0_rd_vld_skid, + l2_cpu1_rd_vld_skid, + l2_cpu2_rd_vld_skid, + l2_cpu3_rd_vld_skid, + + l2_cpu0_pf_rd_vld_skid_popped, + l2_cpu1_pf_rd_vld_skid_popped, + l2_cpu2_pf_rd_vld_skid_popped, + l2_cpu3_pf_rd_vld_skid_popped, + + l2_cpu0_rd_arb, + l2_cpu1_rd_arb, + l2_cpu2_rd_arb, + l2_cpu3_rd_arb, + + l2_cpu0_wr_vld_skid, + l2_cpu1_wr_vld_skid, + l2_cpu2_wr_vld_skid, + l2_cpu3_wr_vld_skid, + + l2_cpu0_wr_arb, + l2_cpu1_wr_arb, + l2_cpu2_wr_arb, + l2_cpu3_wr_arb, + + l2_cpu0_ic_vld_skid, + l2_cpu1_ic_vld_skid, + l2_cpu2_ic_vld_skid, + l2_cpu3_ic_vld_skid, + + l2_cpu0_ic_barrier_stall_q, + l2_cpu1_ic_barrier_stall_q, + l2_cpu2_ic_barrier_stall_q, + l2_cpu3_ic_barrier_stall_q, + + l2_cpu0_blk_non_evict_wr, + l2_cpu1_blk_non_evict_wr, + l2_cpu2_blk_non_evict_wr, + l2_cpu3_blk_non_evict_wr, + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + l2_cpu0_idle_wakeup_q, + l2_cpu0_rd_arb_fast, + l2_cpu0_rd_id_arb_set, + l2_cpu0_rd_lrq_id_arb_set, + l2_cpu0_rd_type_arb_set, + l2_cpu0_rd_cache_attr_arb_set, + l2_cpu0_rd_page_attr_arb_set, + l2_cpu0_rd_elem_size_arb_set, + l2_cpu0_rd_way_arb_set, + l2_cpu0_rd_replayed_arb_set, + l2_cpu0_rd_excl_arb_set, + l2_cpu0_rd_priv_arb_set, + l2_cpu0_rd_shared_arb_set, + l2_cpu0_rd_va48_arb_set, + l2_cpu0_rd_aarch64_arb_set, + l2_cpu0_rd_asid_arb_set, + l2_cpu0_rd_prfm_arb_set, + l2_cpu0_rd_addr_arb_set, + l2_cpu0_rd_bypass_arb_set, + l2_cpu0_rd_bypass_req_can_e5, + l2_cpu0_early_rd_reqe4_e5_q, + l2_cpu0_rd_bypass_way_e5, + l2_cpu0_rd_bypass_bufid_e5, + l2_cpu0_rd_bypass_lrq_id_e5, + + l2_cpu0_wr_arb_fast, + l2_cpu0_wr_id_arb_set, + l2_cpu0_wr_partial_dw_arb_set, + l2_cpu0_wr_cache_attr_arb_set, + l2_cpu0_wr_page_attr_arb_set, + l2_cpu0_wr_elem_size_arb_set, + l2_cpu0_wr_type_arb_set, + l2_cpu0_wr_cl_id_arb_set, + l2_cpu0_wr_priv_arb_set, + l2_cpu0_wr_shared_arb_set, + l2_cpu0_wr_last_arb_set, + l2_cpu0_wr_clean_evict_arb_set, + l2_cpu0_wr_err_arb_set, + l2_cpu0_wr_way_arb_set, + l2_cpu0_wr_dirty_arb_set, + l2_cpu0_wr_1st_replayed_arb_set, + l2_cpu0_wr_addr_arb_set, + l2_cpu0_ic_arb_fast, + l2_cpu0_ic_id_arb_set, + l2_cpu0_ic_write_arb_set, + l2_cpu0_ic_excl_arb_set, + l2_cpu0_ic_elem_size_arb_set, + l2_cpu0_ic_ns_arb_set, + l2_cpu0_ic_addr_arb_set, + l2_cpu0_ic_data_arb_set, + + l2_cpu0_wrq_almost_full, + + l2_cpu0_ls_wr_req_w2a, + l2_cpu0_ls_wr_last_w2a, + l2_cpu0_ls_wr_dirty_w2a, + l2_cpu0_ls_wr_err_w2a, + l2_cpu0_ls_wr_type_w2a, + l2_cpu0_ls_wr_ccb_id_w2a, + l2_cpu0_ls_wr_data_w2a, + + l2_cpu0_ls_ccb_resp, + l2_cpu0_ls_ccb_resp_id, + l2_cpu0_ls_ccb_data_wr, + + l2_cpu0_if_ccb_resp, + l2_cpu0_if_ccb_resp_id, + + l2_cpu0_tw_ccb_resp, + l2_cpu0_tw_ccb_resp_id, + + l2_cpu0_if_sync_done_q, + l2_cpu0_tlb_sync_done_q, + + l2_cpu0_lrq_haz_clr_id_dcd_q, + l2_cpu0_wrq_haz_clr_id_dcd_q, + l2_cpu0_ls_rd_haz_id_arb_q, + l2_cpu0_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + l2_cpu1_idle_wakeup_q, + l2_cpu1_rd_arb_fast, + l2_cpu1_rd_id_arb_set, + l2_cpu1_rd_lrq_id_arb_set, + l2_cpu1_rd_type_arb_set, + l2_cpu1_rd_cache_attr_arb_set, + l2_cpu1_rd_page_attr_arb_set, + l2_cpu1_rd_elem_size_arb_set, + l2_cpu1_rd_way_arb_set, + l2_cpu1_rd_replayed_arb_set, + l2_cpu1_rd_excl_arb_set, + l2_cpu1_rd_priv_arb_set, + l2_cpu1_rd_shared_arb_set, + l2_cpu1_rd_va48_arb_set, + l2_cpu1_rd_aarch64_arb_set, + l2_cpu1_rd_asid_arb_set, + l2_cpu1_rd_prfm_arb_set, + l2_cpu1_rd_addr_arb_set, + l2_cpu1_rd_bypass_arb_set, + l2_cpu1_rd_bypass_req_can_e5, + l2_cpu1_early_rd_reqe4_e5_q, + l2_cpu1_rd_bypass_way_e5, + l2_cpu1_rd_bypass_bufid_e5, + l2_cpu1_rd_bypass_lrq_id_e5, + + l2_cpu1_wr_arb_fast, + l2_cpu1_wr_id_arb_set, + l2_cpu1_wr_partial_dw_arb_set, + l2_cpu1_wr_cache_attr_arb_set, + l2_cpu1_wr_page_attr_arb_set, + l2_cpu1_wr_elem_size_arb_set, + l2_cpu1_wr_type_arb_set, + l2_cpu1_wr_cl_id_arb_set, + l2_cpu1_wr_priv_arb_set, + l2_cpu1_wr_shared_arb_set, + l2_cpu1_wr_last_arb_set, + l2_cpu1_wr_clean_evict_arb_set, + l2_cpu1_wr_err_arb_set, + l2_cpu1_wr_way_arb_set, + l2_cpu1_wr_dirty_arb_set, + l2_cpu1_wr_1st_replayed_arb_set, + l2_cpu1_wr_addr_arb_set, + l2_cpu1_ic_arb_fast, + l2_cpu1_ic_id_arb_set, + l2_cpu1_ic_write_arb_set, + l2_cpu1_ic_excl_arb_set, + l2_cpu1_ic_elem_size_arb_set, + l2_cpu1_ic_ns_arb_set, + l2_cpu1_ic_addr_arb_set, + l2_cpu1_ic_data_arb_set, + + l2_cpu1_wrq_almost_full, + + l2_cpu1_ls_wr_req_w2a, + l2_cpu1_ls_wr_last_w2a, + l2_cpu1_ls_wr_dirty_w2a, + l2_cpu1_ls_wr_err_w2a, + l2_cpu1_ls_wr_type_w2a, + l2_cpu1_ls_wr_ccb_id_w2a, + l2_cpu1_ls_wr_data_w2a, + + l2_cpu1_ls_ccb_resp, + l2_cpu1_ls_ccb_resp_id, + l2_cpu1_ls_ccb_data_wr, + + l2_cpu1_if_ccb_resp, + l2_cpu1_if_ccb_resp_id, + + l2_cpu1_tw_ccb_resp, + l2_cpu1_tw_ccb_resp_id, + + l2_cpu1_if_sync_done_q, + l2_cpu1_tlb_sync_done_q, + + l2_cpu1_lrq_haz_clr_id_dcd_q, + l2_cpu1_wrq_haz_clr_id_dcd_q, + l2_cpu1_ls_rd_haz_id_arb_q, + l2_cpu1_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + l2_cpu2_idle_wakeup_q, + l2_cpu2_rd_arb_fast, + l2_cpu2_rd_id_arb_set, + l2_cpu2_rd_lrq_id_arb_set, + l2_cpu2_rd_type_arb_set, + l2_cpu2_rd_cache_attr_arb_set, + l2_cpu2_rd_page_attr_arb_set, + l2_cpu2_rd_elem_size_arb_set, + l2_cpu2_rd_way_arb_set, + l2_cpu2_rd_replayed_arb_set, + l2_cpu2_rd_excl_arb_set, + l2_cpu2_rd_priv_arb_set, + l2_cpu2_rd_shared_arb_set, + l2_cpu2_rd_va48_arb_set, + l2_cpu2_rd_aarch64_arb_set, + l2_cpu2_rd_asid_arb_set, + l2_cpu2_rd_prfm_arb_set, + l2_cpu2_rd_addr_arb_set, + l2_cpu2_rd_bypass_arb_set, + l2_cpu2_rd_bypass_req_can_e5, + l2_cpu2_early_rd_reqe4_e5_q, + l2_cpu2_rd_bypass_way_e5, + l2_cpu2_rd_bypass_bufid_e5, + l2_cpu2_rd_bypass_lrq_id_e5, + + l2_cpu2_wr_arb_fast, + l2_cpu2_wr_id_arb_set, + l2_cpu2_wr_partial_dw_arb_set, + l2_cpu2_wr_cache_attr_arb_set, + l2_cpu2_wr_page_attr_arb_set, + l2_cpu2_wr_elem_size_arb_set, + l2_cpu2_wr_type_arb_set, + l2_cpu2_wr_cl_id_arb_set, + l2_cpu2_wr_priv_arb_set, + l2_cpu2_wr_shared_arb_set, + l2_cpu2_wr_last_arb_set, + l2_cpu2_wr_clean_evict_arb_set, + l2_cpu2_wr_err_arb_set, + l2_cpu2_wr_way_arb_set, + l2_cpu2_wr_dirty_arb_set, + l2_cpu2_wr_1st_replayed_arb_set, + l2_cpu2_wr_addr_arb_set, + l2_cpu2_ic_arb_fast, + l2_cpu2_ic_id_arb_set, + l2_cpu2_ic_write_arb_set, + l2_cpu2_ic_excl_arb_set, + l2_cpu2_ic_elem_size_arb_set, + l2_cpu2_ic_ns_arb_set, + l2_cpu2_ic_addr_arb_set, + l2_cpu2_ic_data_arb_set, + + l2_cpu2_wrq_almost_full, + + l2_cpu2_ls_wr_req_w2a, + l2_cpu2_ls_wr_last_w2a, + l2_cpu2_ls_wr_dirty_w2a, + l2_cpu2_ls_wr_err_w2a, + l2_cpu2_ls_wr_type_w2a, + l2_cpu2_ls_wr_ccb_id_w2a, + l2_cpu2_ls_wr_data_w2a, + + l2_cpu2_ls_ccb_resp, + l2_cpu2_ls_ccb_resp_id, + l2_cpu2_ls_ccb_data_wr, + + l2_cpu2_if_ccb_resp, + l2_cpu2_if_ccb_resp_id, + + l2_cpu2_tw_ccb_resp, + l2_cpu2_tw_ccb_resp_id, + + l2_cpu2_if_sync_done_q, + l2_cpu2_tlb_sync_done_q, + + l2_cpu2_lrq_haz_clr_id_dcd_q, + l2_cpu2_wrq_haz_clr_id_dcd_q, + l2_cpu2_ls_rd_haz_id_arb_q, + l2_cpu2_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + l2_cpu3_idle_wakeup_q, + l2_cpu3_rd_arb_fast, + l2_cpu3_rd_id_arb_set, + l2_cpu3_rd_lrq_id_arb_set, + l2_cpu3_rd_type_arb_set, + l2_cpu3_rd_cache_attr_arb_set, + l2_cpu3_rd_page_attr_arb_set, + l2_cpu3_rd_elem_size_arb_set, + l2_cpu3_rd_way_arb_set, + l2_cpu3_rd_replayed_arb_set, + l2_cpu3_rd_excl_arb_set, + l2_cpu3_rd_priv_arb_set, + l2_cpu3_rd_shared_arb_set, + l2_cpu3_rd_va48_arb_set, + l2_cpu3_rd_aarch64_arb_set, + l2_cpu3_rd_asid_arb_set, + l2_cpu3_rd_prfm_arb_set, + l2_cpu3_rd_addr_arb_set, + l2_cpu3_rd_bypass_arb_set, + l2_cpu3_rd_bypass_req_can_e5, + l2_cpu3_early_rd_reqe4_e5_q, + l2_cpu3_rd_bypass_way_e5, + l2_cpu3_rd_bypass_bufid_e5, + l2_cpu3_rd_bypass_lrq_id_e5, + + l2_cpu3_wr_arb_fast, + l2_cpu3_wr_id_arb_set, + l2_cpu3_wr_partial_dw_arb_set, + l2_cpu3_wr_cache_attr_arb_set, + l2_cpu3_wr_page_attr_arb_set, + l2_cpu3_wr_elem_size_arb_set, + l2_cpu3_wr_type_arb_set, + l2_cpu3_wr_cl_id_arb_set, + l2_cpu3_wr_priv_arb_set, + l2_cpu3_wr_shared_arb_set, + l2_cpu3_wr_last_arb_set, + l2_cpu3_wr_clean_evict_arb_set, + l2_cpu3_wr_err_arb_set, + l2_cpu3_wr_way_arb_set, + l2_cpu3_wr_dirty_arb_set, + l2_cpu3_wr_1st_replayed_arb_set, + l2_cpu3_wr_addr_arb_set, + l2_cpu3_ic_arb_fast, + l2_cpu3_ic_id_arb_set, + l2_cpu3_ic_write_arb_set, + l2_cpu3_ic_excl_arb_set, + l2_cpu3_ic_elem_size_arb_set, + l2_cpu3_ic_ns_arb_set, + l2_cpu3_ic_addr_arb_set, + l2_cpu3_ic_data_arb_set, + + l2_cpu3_wrq_almost_full, + + l2_cpu3_ls_wr_req_w2a, + l2_cpu3_ls_wr_last_w2a, + l2_cpu3_ls_wr_dirty_w2a, + l2_cpu3_ls_wr_err_w2a, + l2_cpu3_ls_wr_type_w2a, + l2_cpu3_ls_wr_ccb_id_w2a, + l2_cpu3_ls_wr_data_w2a, + + l2_cpu3_ls_ccb_resp, + l2_cpu3_ls_ccb_resp_id, + l2_cpu3_ls_ccb_data_wr, + + l2_cpu3_if_ccb_resp, + l2_cpu3_if_ccb_resp_id, + + l2_cpu3_tw_ccb_resp, + l2_cpu3_tw_ccb_resp_id, + + l2_cpu3_if_sync_done_q, + l2_cpu3_tlb_sync_done_q, + + l2_cpu3_lrq_haz_clr_id_dcd_q, + l2_cpu3_wrq_haz_clr_id_dcd_q, + l2_cpu3_ls_rd_haz_id_arb_q, + l2_cpu3_ls_wr_haz_id_arb_q, + +// END L2-CPU interface + +//------------------------------------------------------------------- +// TM interface +//------------------------------------------------------------------- +// BEGIN TIMER-CPU interface + tm_cpu0_cntkctl_usr, + tm_cpu0_cnthctl_kernel, + + tm_cpu1_cntkctl_usr, + tm_cpu1_cnthctl_kernel, + + tm_cpu2_cntkctl_usr, + tm_cpu2_cnthctl_kernel, + + tm_cpu3_cntkctl_usr, + tm_cpu3_cnthctl_kernel, +// END TIMER-CPU interface + +//----------------------------------------------------------------------------- +// IC interface +//----------------------------------------------------------------------------- + ls_cpu0_imp_abort_slv, + ls_cpu0_imp_abort_ecc, + ls_cpu0_imp_abort_dec, + ls_cpu0_imp_abort_containable, + ls_cpu0_raw_eae_nonsec, + ls_cpu0_raw_eae_secure, + + ds_cpu0_ic_cpsr_mode, + ds_cpu0_ic_sample_spr, + ds_cpu0_ic_aa64naa32, + ds_cpu0_ic_hcr_change, + ds_cpu0_ic_scr_change, +// BEGIN INCLUDE FOR CPU1 + ds_cpu1_ic_cpsr_mode, + ds_cpu1_ic_sample_spr, + ds_cpu1_ic_aa64naa32, + ds_cpu1_ic_hcr_change, + ds_cpu1_ic_scr_change, + ls_cpu1_imp_abort_slv, + ls_cpu1_imp_abort_ecc, + ls_cpu1_imp_abort_dec, + ls_cpu1_imp_abort_containable, + ls_cpu1_raw_eae_nonsec, + ls_cpu1_raw_eae_secure, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ds_cpu2_ic_cpsr_mode, + ds_cpu2_ic_sample_spr, + ds_cpu2_ic_aa64naa32, + ds_cpu2_ic_hcr_change, + ds_cpu2_ic_scr_change, + ls_cpu2_imp_abort_slv, + ls_cpu2_imp_abort_ecc, + ls_cpu2_imp_abort_dec, + ls_cpu2_imp_abort_containable, + ls_cpu2_raw_eae_nonsec, + ls_cpu2_raw_eae_secure, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ds_cpu3_ic_cpsr_mode, + ds_cpu3_ic_sample_spr, + ds_cpu3_ic_aa64naa32, + ds_cpu3_ic_hcr_change, + ds_cpu3_ic_scr_change, + ls_cpu3_imp_abort_slv, + ls_cpu3_imp_abort_ecc, + ls_cpu3_imp_abort_dec, + ls_cpu3_imp_abort_containable, + ls_cpu3_raw_eae_nonsec, + ls_cpu3_raw_eae_secure, +// END INCLUDE FOR CPU3 + + ic_nfiq, + ic_nirq, + ic_nsei, + ic_nvfiq, + ic_nvirq, + ic_nvsei, + ic_p_valid, + + ic_sample_spr, + ic_hcr_change_complete, + ic_scr_change_complete, + ic_el_change_complete, + ic_ich_el2_tc, + ic_ich_el2_tall0, + ic_ich_el2_tall1, + ic_sra_el3_en, + ic_sra_el1s_en, + ic_sra_el2_en, + ic_sra_el1ns_en, + ic_sre_el1ns_hyp_trap, + ic_sre_el1ns_mon_trap, + ic_sre_el1s_mon_trap, + ic_sre_el2_mon_trap, + ic_block_eoi_sgi_wr, + +//----------------------------------------------------------------------------- +// DT interface +//----------------------------------------------------------------------------- +// BEGIN DT-CPU interface +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + dt_cpu0_et_oslock_gclk, + dt_cpu0_os_double_lock_gclk, + dt_cpu0_halt_ack_gclk, + dt_cpu0_coredbg_in_reset_gclk, + dt_cpu0_wfx_dbg_req_gclk, + dt_cpu0_hlt_dbgevt_ok_gclk, + dt_cpu0_dbif_ack_gclk, + dt_cpu0_dbif_err_gclk, + dt_cpu0_dbif_rddata_gclk, + + dt_cpu0_dbif_addr_pclk, + dt_cpu0_dbif_locked_pclk, + dt_cpu0_dbif_req_pclk, + dt_cpu0_dbif_wrdata_pclk, + dt_cpu0_dbif_write_pclk, + dt_cpu0_edecr_osuce_pclk, + dt_cpu0_edecr_rce_pclk, + dt_cpu0_edecr_ss_pclk, + dt_cpu0_edbgrq_pclk, + dt_cpu0_edacr_frc_idleack_pclk, + dt_cpu0_edprcr_corepurq_pclk, + + dt_cpu0_pmusnapshot_ack_gclk, + dt_cpu0_pmusnapshot_req_pclk, + + dt_cpu0_cti_trigin_7to4_gclk, + dt_cpu0_cti_trigin_1to0_gclk, + dt_cpu0_cti_trigoutack_7to4_gclk, + dt_cpu0_cti_trigoutack_bit1_gclk, + + dt_cpu0_cti_trigout_7to4_pclk, + dt_cpu0_cti_trigout_1to0_pclk, + dt_cpu0_cti_triginack_7to4_pclk, + dt_cpu0_cti_triginack_1to0_pclk, + + dt_cpu0_wfx_wakeup_pclk, + dt_cpu0_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + dt_cpu1_et_oslock_gclk, + dt_cpu1_os_double_lock_gclk, + dt_cpu1_halt_ack_gclk, + dt_cpu1_coredbg_in_reset_gclk, + dt_cpu1_wfx_dbg_req_gclk, + dt_cpu1_hlt_dbgevt_ok_gclk, + dt_cpu1_dbif_ack_gclk, + dt_cpu1_dbif_err_gclk, + dt_cpu1_dbif_rddata_gclk, + + dt_cpu1_dbif_addr_pclk, + dt_cpu1_dbif_locked_pclk, + dt_cpu1_dbif_req_pclk, + dt_cpu1_dbif_wrdata_pclk, + dt_cpu1_dbif_write_pclk, + dt_cpu1_edecr_osuce_pclk, + dt_cpu1_edecr_rce_pclk, + dt_cpu1_edecr_ss_pclk, + dt_cpu1_edbgrq_pclk, + dt_cpu1_edacr_frc_idleack_pclk, + dt_cpu1_edprcr_corepurq_pclk, + + dt_cpu1_pmusnapshot_ack_gclk, + dt_cpu1_pmusnapshot_req_pclk, + + dt_cpu1_cti_trigin_7to4_gclk, + dt_cpu1_cti_trigin_1to0_gclk, + dt_cpu1_cti_trigoutack_7to4_gclk, + dt_cpu1_cti_trigoutack_bit1_gclk, + + dt_cpu1_cti_trigout_7to4_pclk, + dt_cpu1_cti_trigout_1to0_pclk, + dt_cpu1_cti_triginack_7to4_pclk, + dt_cpu1_cti_triginack_1to0_pclk, + + dt_cpu1_wfx_wakeup_pclk, + dt_cpu1_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + dt_cpu2_et_oslock_gclk, + dt_cpu2_os_double_lock_gclk, + dt_cpu2_halt_ack_gclk, + dt_cpu2_coredbg_in_reset_gclk, + dt_cpu2_wfx_dbg_req_gclk, + dt_cpu2_hlt_dbgevt_ok_gclk, + dt_cpu2_dbif_ack_gclk, + dt_cpu2_dbif_err_gclk, + dt_cpu2_dbif_rddata_gclk, + + dt_cpu2_dbif_addr_pclk, + dt_cpu2_dbif_locked_pclk, + dt_cpu2_dbif_req_pclk, + dt_cpu2_dbif_wrdata_pclk, + dt_cpu2_dbif_write_pclk, + dt_cpu2_edecr_osuce_pclk, + dt_cpu2_edecr_rce_pclk, + dt_cpu2_edecr_ss_pclk, + dt_cpu2_edbgrq_pclk, + dt_cpu2_edacr_frc_idleack_pclk, + dt_cpu2_edprcr_corepurq_pclk, + + dt_cpu2_pmusnapshot_ack_gclk, + dt_cpu2_pmusnapshot_req_pclk, + + dt_cpu2_cti_trigin_7to4_gclk, + dt_cpu2_cti_trigin_1to0_gclk, + dt_cpu2_cti_trigoutack_7to4_gclk, + dt_cpu2_cti_trigoutack_bit1_gclk, + + dt_cpu2_cti_trigout_7to4_pclk, + dt_cpu2_cti_trigout_1to0_pclk, + dt_cpu2_cti_triginack_7to4_pclk, + dt_cpu2_cti_triginack_1to0_pclk, + + dt_cpu2_wfx_wakeup_pclk, + dt_cpu2_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + dt_cpu3_et_oslock_gclk, + dt_cpu3_os_double_lock_gclk, + dt_cpu3_halt_ack_gclk, + dt_cpu3_coredbg_in_reset_gclk, + dt_cpu3_wfx_dbg_req_gclk, + dt_cpu3_hlt_dbgevt_ok_gclk, + dt_cpu3_dbif_ack_gclk, + dt_cpu3_dbif_err_gclk, + dt_cpu3_dbif_rddata_gclk, + + dt_cpu3_dbif_addr_pclk, + dt_cpu3_dbif_locked_pclk, + dt_cpu3_dbif_req_pclk, + dt_cpu3_dbif_wrdata_pclk, + dt_cpu3_dbif_write_pclk, + dt_cpu3_edecr_osuce_pclk, + dt_cpu3_edecr_rce_pclk, + dt_cpu3_edecr_ss_pclk, + dt_cpu3_edbgrq_pclk, + dt_cpu3_edacr_frc_idleack_pclk, + dt_cpu3_edprcr_corepurq_pclk, + + dt_cpu3_pmusnapshot_ack_gclk, + dt_cpu3_pmusnapshot_req_pclk, + + dt_cpu3_cti_trigin_7to4_gclk, + dt_cpu3_cti_trigin_1to0_gclk, + dt_cpu3_cti_trigoutack_7to4_gclk, + dt_cpu3_cti_trigoutack_bit1_gclk, + + dt_cpu3_cti_trigout_7to4_pclk, + dt_cpu3_cti_trigout_1to0_pclk, + dt_cpu3_cti_triginack_7to4_pclk, + dt_cpu3_cti_triginack_1to0_pclk, + + dt_cpu3_wfx_wakeup_pclk, + dt_cpu3_noclkstop_pclk, +// END DT-CPU interface + +//----------------------------------------------------------------------------- +// CK interface +//----------------------------------------------------------------------------- +// BEGIN CK-CPU interface + ds_cpu0_reset_req, + ds_cpu0_wfi_req, + ds_cpu0_wfe_req, + ds_cpu0_flush, + ds_cpu0_flush_type, + ds_cpu0_imp_abrt_wfi_qual, + ds_cpu0_irq_wfi_qual, + ds_cpu0_fiq_wfi_qual, + ds_cpu0_vimp_abrt_wfi_qual, + ds_cpu0_virq_wfi_qual, + ds_cpu0_vfiq_wfi_qual, + ds_cpu0_imp_abrt_wfe_qual, + ds_cpu0_irq_wfe_qual, + ds_cpu0_fiq_wfe_qual, + ds_cpu0_vimp_abrt_wfe_qual, + ds_cpu0_virq_wfe_qual, + ds_cpu0_vfiq_wfe_qual, + ds_cpu0_hcr_va, + ds_cpu0_hcr_vi, + ds_cpu0_hcr_vf, + ds_cpu0_cpuectlr_ret, + ck_cpu0_event_reg, + ck_cpu0_wfi_ack, + ck_cpu0_wfe_ack, + ck_cpu0_crcx_clk_en_n, + + ds_cpu1_reset_req, + ds_cpu1_wfi_req, + ds_cpu1_wfe_req, + ds_cpu1_flush, + ds_cpu1_flush_type, + ds_cpu1_imp_abrt_wfi_qual, + ds_cpu1_irq_wfi_qual, + ds_cpu1_fiq_wfi_qual, + ds_cpu1_vimp_abrt_wfi_qual, + ds_cpu1_virq_wfi_qual, + ds_cpu1_vfiq_wfi_qual, + ds_cpu1_imp_abrt_wfe_qual, + ds_cpu1_irq_wfe_qual, + ds_cpu1_fiq_wfe_qual, + ds_cpu1_vimp_abrt_wfe_qual, + ds_cpu1_virq_wfe_qual, + ds_cpu1_vfiq_wfe_qual, + ds_cpu1_hcr_va, + ds_cpu1_hcr_vi, + ds_cpu1_hcr_vf, + ds_cpu1_cpuectlr_ret, + ck_cpu1_event_reg, + ck_cpu1_wfi_ack, + ck_cpu1_wfe_ack, + ck_cpu1_crcx_clk_en_n, + + ds_cpu2_reset_req, + ds_cpu2_wfi_req, + ds_cpu2_wfe_req, + ds_cpu2_flush, + ds_cpu2_flush_type, + ds_cpu2_imp_abrt_wfi_qual, + ds_cpu2_irq_wfi_qual, + ds_cpu2_fiq_wfi_qual, + ds_cpu2_vimp_abrt_wfi_qual, + ds_cpu2_virq_wfi_qual, + ds_cpu2_vfiq_wfi_qual, + ds_cpu2_imp_abrt_wfe_qual, + ds_cpu2_irq_wfe_qual, + ds_cpu2_fiq_wfe_qual, + ds_cpu2_vimp_abrt_wfe_qual, + ds_cpu2_virq_wfe_qual, + ds_cpu2_vfiq_wfe_qual, + ds_cpu2_hcr_va, + ds_cpu2_hcr_vi, + ds_cpu2_hcr_vf, + ds_cpu2_cpuectlr_ret, + ck_cpu2_event_reg, + ck_cpu2_wfi_ack, + ck_cpu2_wfe_ack, + ck_cpu2_crcx_clk_en_n, + + ds_cpu3_reset_req, + ds_cpu3_wfi_req, + ds_cpu3_wfe_req, + ds_cpu3_flush, + ds_cpu3_flush_type, + ds_cpu3_imp_abrt_wfi_qual, + ds_cpu3_irq_wfi_qual, + ds_cpu3_fiq_wfi_qual, + ds_cpu3_vimp_abrt_wfi_qual, + ds_cpu3_virq_wfi_qual, + ds_cpu3_vfiq_wfi_qual, + ds_cpu3_imp_abrt_wfe_qual, + ds_cpu3_irq_wfe_qual, + ds_cpu3_fiq_wfe_qual, + ds_cpu3_vimp_abrt_wfe_qual, + ds_cpu3_virq_wfe_qual, + ds_cpu3_vfiq_wfe_qual, + ds_cpu3_hcr_va, + ds_cpu3_hcr_vi, + ds_cpu3_hcr_vf, + ds_cpu3_cpuectlr_ret, + ck_cpu3_event_reg, + ck_cpu3_wfi_ack, + ck_cpu3_wfe_ack, + ck_cpu3_crcx_clk_en_n, + + ls_cpu0_clrexmon, + ls_cpu1_clrexmon, + ls_cpu2_clrexmon, + ls_cpu3_clrexmon, +// END CK-CPU interface + + ck_gclkt +); + +//# +//# Interface Signals +//# ================= +//# + +//----------------------------------------------------------------------------- +// Clock and Reset Signals +//----------------------------------------------------------------------------- + input CLK; // Fast Clock + input CLKEN; // Fast Clock Enable + + input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset + input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) + input nL2RESET; // L2 reset + input L2RSTDISABLE; // L2 RAMs hardware reset disable + output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request +//See also nPRESETDBG; // Debug APB reset (PCLK) + +//----------------------------------------------------------------------------- +// Static Configuration Signals +//----------------------------------------------------------------------------- +// Static configuration signals that should be tied off and not change dynamically. +// Many of the initial values specified by these inputs +// may be overridden in software using CP15 registers. + + input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) + input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors + input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) + input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers + + input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] + input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] + + input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) + input [43:2] RVBARADDR0; // RVBAR address +// BEGIN INCLUDE FOR CPU1 + input [43:2] RVBARADDR1; // RVBAR address +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input [43:2] RVBARADDR2; // RVBAR address +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input [43:2] RVBARADDR3; // RVBAR address +// END INCLUDE FOR CPU3 + input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension + +//----------------------------------------------------------------------------- +// Interrupt Controller Signals +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] nFIQ; // Fast Interrupt request + input [`MAIA_CN:0] nIRQ; // Interrupt request + input [`MAIA_CN:0] nSEI; // System Error Interrupt + input [`MAIA_CN:0] nREI; // RAM Error Interrupt + input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request + input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request + input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt + +// BEGIN NO-GIC pins + output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output +// END NO-GIC pins + + input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers +// BEGIN NO-GIC pins + input GICCDISABLE; // Put GIC into bypass mode + + input ICDTVALID; // Distrubuter AXI4 SP Message Valid + output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message + input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data + input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet + input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID + + output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid + input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message + output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data + output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet + output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID +// END NO-GIC pins + +//----------------------------------------------------------------------------- +// Timer Signals +//----------------------------------------------------------------------------- + input [63:0] CNTVALUEB; // Counter value in binary + input CNTCLKEN; // Counter clock enable + output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event + output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event + output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event + output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event + +//----------------------------------------------------------------------------- +// Power Management Signals +//----------------------------------------------------------------------------- + input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) + output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) + input EVENTI; // Event input for processor wake-up from WFE state + output EVENTO; // Event output, signal is active when SEV instruction is executed + output [`MAIA_CN:0] STANDBYWFI; // WFI mode + output [`MAIA_CN:0] STANDBYWFE; // WFE mode + output STANDBYWFIL2; // WFI mode for L2 + output [`MAIA_CN:0] SMPEN; // CPU SMP bit + + output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE + input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn + output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn + output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY + + output L2QACTIVE; // L2 Q-channel QACTIVE + input L2QREQn; // L2 Q-channel QREQn + output L2QACCEPTn; // L2 Q-channel QACCEPTn + output L2QDENY; // L2 Q-channel QDENY + + input L2FLUSHREQ; // L2 hardware flush request + output L2FLUSHDONE; // L2 hardware flush done + +//----------------------------------------------------------------------------- +// Asynchronous Error Signals +//----------------------------------------------------------------------------- + output nINTERRIRQ; // L2 RAM dbl-bit ECC error + output nEXTERRIRQ; // Write transaction error + +//----------------------------------------------------------------------------- +// Bus Configuration Signals +//----------------------------------------------------------------------------- + input SYSBARDISABLE; // Disable broadcast of barriers + input BROADCASTINNER; // Extend Inner Shared Domain + input BROADCASTOUTER; // Extend Outer Shared Domain + input BROADCASTCACHEMAINT; // Broadcast cache maint ops + +//----------------------------------------------------------------------------- +// AMBA4 ACE Master (AXI with Coherency extensions) +//----------------------------------------------------------------------------- + input ACLKENM; // AXI Master clock enable + input ACINACTM; // ACE Snoop interface no longer active or accepting requests + +// Write Address channel signals + input AWREADYM; // Write Address ready (slave ready to accept write address) + output AWVALIDM; // Write Address valid + output [6:0] AWIDM; // Write Address ID + output [43:0] AWADDRM; // Write Address + output [7:0] AWLENM; // Write Burst Length + output [2:0] AWSIZEM; // Write Burst Size + output [1:0] AWBURSTM; // Write Burst type + output [1:0] AWBARM; // Barrier + output [1:0] AWDOMAINM; // Domain + output AWLOCKM; // Write Lock type + output [3:0] AWCACHEM; // Write Cache type + output [2:0] AWPROTM; // Write Protection type + output [2:0] AWSNOOPM; // Write Snoop Request type + output AWUNIQUEM; // Write Unique state + output [7:0] WRMEMATTR; // Write raw memory attributes + +// Write Data channel signals + input WREADYM; // Write Data ready (slave ready to accept data) + output WVALIDM; // Write Data valid + output [127:0] WDATAM; // Write Data + output [15:0] WSTRBM; // Write byte-lane strobes + output [6:0] WIDM; // Write id + output WLASTM; // Write Data last transfer indicator + +// Write Response channel signals + output BREADYM; // Write Response ready (master ready to accept response) + input BVALIDM; // Write Response Valid + input [6:0] BIDM; // Write Response ID + input [1:0] BRESPM; // Write Response + +// Read Address channel signals + input ARREADYM; // Read Address ready (slave ready to accept read address) + output ARVALIDM; // Read Address valid + output [6:0] ARIDM; // Read Address ID + output [43:0] ARADDRM; // Read Address + output [7:0] ARLENM; // Read Burst Length + output [2:0] ARSIZEM; // Read Burst Size + output [1:0] ARBURSTM; // Read Burst type + output [1:0] ARBARM; // Barrier + output [1:0] ARDOMAINM; // Domain + output ARLOCKM; // Read Lock type + output [3:0] ARCACHEM; // Read Cache type + output [2:0] ARPROTM; // Read Protection type + output [3:0] ARSNOOPM; // Read Snoop Request type + output [7:0] RDMEMATTR; // Read raw memory attributes + +// Read Data channel signals + output RREADYM; // Read Data ready (master ready to accept data) + input RVALIDM; // Read Data valid + input [6:0] RIDM; // Read Data ID + input [127:0] RDATAM; // Read Data + input [3:0] RRESPM; // Read Data response + input RLASTM; // Read Data last transfer indicator + +// Coherency Address channel signals + output ACREADYM; // master ready to accept snoop address + input ACVALIDM; // Snoop Address valid + input [43:0] ACADDRM; // Snoop Address + input [2:0] ACPROTM; // Snoop Protection type + input [3:0] ACSNOOPM; // Snoop Request type + +// Coherency Response channel signals + input CRREADYM; // slave ready to accept snoop response + output CRVALIDM; // Snoop Response valid + output [4:0] CRRESPM; // Snoop Response + +// Coherency Data handshake channel signals + input CDREADYM; // slave ready to accept snoop data + output CDVALIDM; // Snoop Data valid + output [127:0] CDDATAM; // Snoop Data + output CDLASTM; // Snoop Data last transfer indicator + +// Read/Write Acknowledge signals + output RACKM; // Read Acknowledge + output WACKM; // Write Acknowledge + +//----------------------------------------------------------------------------- +// ACP AXI Slave +//----------------------------------------------------------------------------- + input ACLKENS; // AXI slave clock enable + input AINACTS; // AXI slave interface no longer active or accepting requests + +// Write Address channel signals + output AWREADYS; // Write Address ready (slave ready to accept write address) + input AWVALIDS; // Write Address valid + input [4:0] AWIDS; // Write Address ID + input [43:0] AWADDRS; // Write Address + input [7:0] AWLENS; // Write Burst Length + input [3:0] AWCACHES; // Write Cache type + input [1:0] AWUSERS; // Write inner & outer shareability + input [2:0] AWPROTS; // Write Protection type + +// Write Data channel signals + output WREADYS; // Write Data ready (slave ready to accept data) + input WVALIDS; // Write Data valid + input [127:0] WDATAS; // Write Data + input [15:0] WSTRBS; // Write byte-lane strobes + input WLASTS; // Write Data last transfer indicator + +// Write Response channel signals + input BREADYS; // Write Response ready (master ready to accept response) + output BVALIDS; // Write Response Valid + output [4:0] BIDS; // Write Response ID tag + output [1:0] BRESPS; // Write Response + +// Read Address channel signals + output ARREADYS; // Read Address ready (slave ready to accept read address) + input ARVALIDS; // Read Address valid + input [4:0] ARIDS; // Read Address ID + input [43:0] ARADDRS; // Read Address + input [7:0] ARLENS; // Read Burst Length + input [3:0] ARCACHES; // Read Cache type + input [1:0] ARUSERS; // Read inner & outer shareability + input [2:0] ARPROTS; // Read Protection type + +// Read Data channel signals + input RREADYS; // Read Data ready (master ready to accept data) + output RVALIDS; // Read Data valid + output [4:0] RIDS; // Read Data ID + output [127:0] RDATAS; // Read Data + output [1:0] RRESPS; // Read Data response + output RLASTS; // Read Data last transfer indicator + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (CLK) +//----------------------------------------------------------------------------- +// Debug CLK interface + input [43:12] DBGROMADDR; // Debug ROM base address + input DBGROMADDRV; // Debug ROM base address valid + + output [`MAIA_CN:0] DBGACK; // Debug acknowledge + output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt + output [`MAIA_CN:0] COMMRX; // Comms channel receive + output [`MAIA_CN:0] COMMTX; // Comms channel transmit + + output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request + output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request + + input DBGL1RSTDISABLE; // L1 DCache hardware reset disable + +// PMU CLK interface + output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request + output [24:0] PMUEVENT0; // PMU Event bus +// BEGIN INCLUDE FOR CPU1 + output [24:0] PMUEVENT1; // PMU Event bus +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + output [24:0] PMUEVENT2; // PMU Event bus +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + output [24:0] PMUEVENT3; // PMU Event bus +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (ATCLK) +//----------------------------------------------------------------------------- +// ETM ATB interface and Misc signals + input ATCLKEN; // ATB Clock Enable + input [63:0] TSVALUEB; // ATB Timestamp in binary + + input ATREADYM0; // ATDATA can be accepted + input AFVALIDM0; // ATB Fifo Flush Request + output [31:0] ATDATAM0; // ATB Data + output ATVALIDM0; // ATB Data Valid + output [1:0] ATBYTESM0; // ATB Data Size + output AFREADYM0; // ATB Fifo Flush Finished + output [6:0] ATIDM0; // ATB Trace Source ID + input SYNCREQM0; // ATB External synchronization request + +// BEGIN INCLUDE FOR CPU1 + input ATREADYM1; // ATDATA can be accepted + input AFVALIDM1; // ATB Fifo Flush Request + output [31:0] ATDATAM1; // ATB Data + output ATVALIDM1; // ATB Data Valid + output [1:0] ATBYTESM1; // ATB Data Size + output AFREADYM1; // ATB Fifo Flush Finished + output [6:0] ATIDM1; // ATB Trace Source ID + input SYNCREQM1; // ATB External synchronization request +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ATREADYM2; // ATDATA can be accepted + input AFVALIDM2; // ATB Fifo Flush Request + output [31:0] ATDATAM2; // ATB Data + output ATVALIDM2; // ATB Data Valid + output [1:0] ATBYTESM2; // ATB Data Size + output AFREADYM2; // ATB Fifo Flush Finished + output [6:0] ATIDM2; // ATB Trace Source ID + input SYNCREQM2; // ATB External synchronization request +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ATREADYM3; // ATDATA can be accepted + input AFVALIDM3; // ATB Fifo Flush Request + output [31:0] ATDATAM3; // ATB Data + output ATVALIDM3; // ATB Data Valid + output [1:0] ATBYTESM3; // ATB Data Size + output AFREADYM3; // ATB Fifo Flush Finished + output [6:0] ATIDM3; // ATB Trace Source ID + input SYNCREQM3; // ATB External synchronization request +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (PCLK) +//----------------------------------------------------------------------------- +// Debug-APBv3 port (APB) + input PCLKDBG; // APB Clock + input PCLKENDBG; // APB Clock Enable + input nPRESETDBG; // APB Reset + input PSELDBG; // Debug bus access + input [21:2] PADDRDBG; // APB address + input PADDRDBG31; // APB address bit[31] + input PENABLEDBG; // APB transfer complete flag + input PWRITEDBG; // APB read/write indicator + input [31:0] PWDATADBG; // APB write data + output [31:0] PRDATADBG; // APB read data + output PREADYDBG; // APB slave ready, used to extend a transfer + output PSLVERRDBG; // APB slave transfer error + +// Misc interface + input [`MAIA_CN:0] EDBGRQ; // External debug request + +// PMU Snapshot interface + input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request + output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge + +// Power-related interface + input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status + output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request + +// CTI interface + input [3:0] CTICHIN; // Channel In + input [3:0] CTICHOUTACK; // Channel Out acknowledge + output [3:0] CTICHOUT; // Channel Out + output [3:0] CTICHINACK; // Channel In acknowledge + input CISBYPASS; // Channel interface sync bypass + input [3:0] CIHSBYPASS; // Channel interface H/S bypass + output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt + input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge + +//----------------------------------------------------------------------------- +// Debug Authentication Interface (CLK & PCLK) +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] DBGEN; // Invasive debug enable + input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable + input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable + input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable + +//----------------------------------------------------------------------------- +// DFT Signals +//----------------------------------------------------------------------------- + input DFTSE; // Scan enable + input DFTRSTDISABLE; // Disable reset to cells during scan shift + input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr + input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 + input DFTRAMHOLD; // Holds data in RAMs + input DFTCLKBYPASS; // L2 RAM strobe clock bypass + input DFTMCPHOLD; // Disable multi-cycle RAM paths + +//----------------------------------------------------------------------------- +// MBIST Interface +//----------------------------------------------------------------------------- + input nMBISTRESET; // MBIST reset + input MBISTREQ; // MBIST mode request + +//----------------------------------------------------------------------------- +// Signals from maia -> maia_cpu_io -> maia_cpu +//----------------------------------------------------------------------------- +// Outputs to maia_cpu + output ncpuporeset_cpu0_o; + output ncorereset_cpu0_o; + + output cfgend_cpu0_o; + output cfgte_cpu0_o; + output cp15sdisable_cpu0_o; + output vinithi_cpu0_o; + output [7:0] clusteridaff1_cpu0_o; + output [7:0] clusteridaff2_cpu0_o; + output [1:0] cpuid_cpu0_o; + output aa64naa32_cpu0_o; + output [43:2] rvbaraddr_cpu0_o; + output cryptodisable_cpu0_o; + output giccdisable_cpu0_o; + + output [43:12] dbgromaddr_cpu0_o; + output dbgromaddrv_cpu0_o; + output dbgl1rstdisable_cpu0_o; + + output dbgen_cpu0_o; + output niden_cpu0_o; + output spiden_cpu0_o; + output spniden_cpu0_o; + + output [63:0] tsvalueb_cpu0_o; + + output atclken_cpu0_o; + output afvalidm_cpu0_o; + output atreadym_cpu0_o; + output syncreqm_cpu0_o; + + output dftse_cpu0_o; + output dftrstdisable_cpu0_o; + output dftcrclkdisable_cpu0_o; + output dftramhold_cpu0_o; + output nmbistreset_cpu0_o; + +// BEGIN INCLUDE FOR CPU1 + output ncpuporeset_cpu1_o; + output ncorereset_cpu1_o; + + output cfgend_cpu1_o; + output cfgte_cpu1_o; + output cp15sdisable_cpu1_o; + output vinithi_cpu1_o; + output [7:0] clusteridaff1_cpu1_o; + output [7:0] clusteridaff2_cpu1_o; + output [1:0] cpuid_cpu1_o; + output aa64naa32_cpu1_o; + output [43:2] rvbaraddr_cpu1_o; + output cryptodisable_cpu1_o; + output giccdisable_cpu1_o; + + output [43:12] dbgromaddr_cpu1_o; + output dbgromaddrv_cpu1_o; + output dbgl1rstdisable_cpu1_o; + + output dbgen_cpu1_o; + output niden_cpu1_o; + output spiden_cpu1_o; + output spniden_cpu1_o; + + output [63:0] tsvalueb_cpu1_o; + + output atclken_cpu1_o; + output afvalidm_cpu1_o; + output atreadym_cpu1_o; + output syncreqm_cpu1_o; + + output dftse_cpu1_o; + output dftrstdisable_cpu1_o; + output dftcrclkdisable_cpu1_o; + output dftramhold_cpu1_o; + output nmbistreset_cpu1_o; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + output ncpuporeset_cpu2_o; + output ncorereset_cpu2_o; + + output cfgend_cpu2_o; + output cfgte_cpu2_o; + output cp15sdisable_cpu2_o; + output vinithi_cpu2_o; + output [7:0] clusteridaff1_cpu2_o; + output [7:0] clusteridaff2_cpu2_o; + output [1:0] cpuid_cpu2_o; + output aa64naa32_cpu2_o; + output [43:2] rvbaraddr_cpu2_o; + output cryptodisable_cpu2_o; + output giccdisable_cpu2_o; + + output [43:12] dbgromaddr_cpu2_o; + output dbgromaddrv_cpu2_o; + output dbgl1rstdisable_cpu2_o; + + output dbgen_cpu2_o; + output niden_cpu2_o; + output spiden_cpu2_o; + output spniden_cpu2_o; + + output [63:0] tsvalueb_cpu2_o; + + output atclken_cpu2_o; + output afvalidm_cpu2_o; + output atreadym_cpu2_o; + output syncreqm_cpu2_o; + + output dftse_cpu2_o; + output dftrstdisable_cpu2_o; + output dftcrclkdisable_cpu2_o; + output dftramhold_cpu2_o; + output nmbistreset_cpu2_o; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + output ncpuporeset_cpu3_o; + output ncorereset_cpu3_o; + + output cfgend_cpu3_o; + output cfgte_cpu3_o; + output cp15sdisable_cpu3_o; + output vinithi_cpu3_o; + output [7:0] clusteridaff1_cpu3_o; + output [7:0] clusteridaff2_cpu3_o; + output [1:0] cpuid_cpu3_o; + output aa64naa32_cpu3_o; + output [43:2] rvbaraddr_cpu3_o; + output cryptodisable_cpu3_o; + output giccdisable_cpu3_o; + + output [43:12] dbgromaddr_cpu3_o; + output dbgromaddrv_cpu3_o; + output dbgl1rstdisable_cpu3_o; + + output dbgen_cpu3_o; + output niden_cpu3_o; + output spiden_cpu3_o; + output spniden_cpu3_o; + + output [63:0] tsvalueb_cpu3_o; + + output atclken_cpu3_o; + output afvalidm_cpu3_o; + output atreadym_cpu3_o; + output syncreqm_cpu3_o; + + output dftse_cpu3_o; + output dftrstdisable_cpu3_o; + output dftcrclkdisable_cpu3_o; + output dftramhold_cpu3_o; + output nmbistreset_cpu3_o; +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Signals from maia_cpu -> maia_cpu_io -> maia +//----------------------------------------------------------------------------- +// Inputs from maia_cpu + input ds_cpu0_sev_req; + input ds_cpu0_sevl_req; + input ds_cpu0_cpuectlr_smp; + + input ncommirq_cpu0_i; + input commrx_cpu0_i; + input commtx_cpu0_i; + input dbgack_cpu0_i; + input dbgrstreq_cpu0_i; + input dbgnopwrdwn_cpu0_i; + + input npmuirq_cpu0_i; + input [24:0] pmuevent_cpu0_i; + input pm_export_cpu0_i; + + input etclken_cpu0_i; + input afreadym_cpu0_i; + input [1:0] atbytesm_cpu0_i; + input [31:0] atdatam_cpu0_i; + input [6:0] atidm_cpu0_i; + input atvalidm_cpu0_i; + +// BEGIN INCLUDE FOR CPU1 + input ds_cpu1_sev_req; + input ds_cpu1_sevl_req; + input ds_cpu1_cpuectlr_smp; + + input ncommirq_cpu1_i; + input commrx_cpu1_i; + input commtx_cpu1_i; + input dbgack_cpu1_i; + input dbgrstreq_cpu1_i; + input dbgnopwrdwn_cpu1_i; + + input npmuirq_cpu1_i; + input [24:0] pmuevent_cpu1_i; + input pm_export_cpu1_i; + + input etclken_cpu1_i; + input afreadym_cpu1_i; + input [1:0] atbytesm_cpu1_i; + input [31:0] atdatam_cpu1_i; + input [6:0] atidm_cpu1_i; + input atvalidm_cpu1_i; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ds_cpu2_sev_req; + input ds_cpu2_sevl_req; + input ds_cpu2_cpuectlr_smp; + + input ncommirq_cpu2_i; + input commrx_cpu2_i; + input commtx_cpu2_i; + input dbgack_cpu2_i; + input dbgrstreq_cpu2_i; + input dbgnopwrdwn_cpu2_i; + + input npmuirq_cpu2_i; + input [24:0] pmuevent_cpu2_i; + input pm_export_cpu2_i; + + input etclken_cpu2_i; + input afreadym_cpu2_i; + input [1:0] atbytesm_cpu2_i; + input [31:0] atdatam_cpu2_i; + input [6:0] atidm_cpu2_i; + input atvalidm_cpu2_i; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ds_cpu3_sev_req; + input ds_cpu3_sevl_req; + input ds_cpu3_cpuectlr_smp; + + input ncommirq_cpu3_i; + input commrx_cpu3_i; + input commtx_cpu3_i; + input dbgack_cpu3_i; + input dbgrstreq_cpu3_i; + input dbgnopwrdwn_cpu3_i; + + input npmuirq_cpu3_i; + input [24:0] pmuevent_cpu3_i; + input pm_export_cpu3_i; + + input etclken_cpu3_i; + input afreadym_cpu3_i; + input [1:0] atbytesm_cpu3_i; + input [31:0] atdatam_cpu3_i; + input [6:0] atidm_cpu3_i; + input atvalidm_cpu3_i; +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// L2 interface +//----------------------------------------------------------------------------- + output [12:0] l2_cpu0_mbist1_addr_b1; + output [3:0] l2_cpu0_mbist1_array_b1; + output [7:0] l2_cpu0_mbist1_be_b1; + output l2_cpu0_mbist1_en_b1; + output l2_cpu0_mbist1_rd_en_b1; + output l2_cpu0_mbist1_wr_en_b1; + output l2_cpu0_mbist1_all_b1; + +// BEGIN INCLUDE FOR CPU1 + output [12:0] l2_cpu1_mbist1_addr_b1; + output [3:0] l2_cpu1_mbist1_array_b1; + output [7:0] l2_cpu1_mbist1_be_b1; + output l2_cpu1_mbist1_en_b1; + output l2_cpu1_mbist1_rd_en_b1; + output l2_cpu1_mbist1_wr_en_b1; + output l2_cpu1_mbist1_all_b1; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + output [12:0] l2_cpu2_mbist1_addr_b1; + output [3:0] l2_cpu2_mbist1_array_b1; + output [7:0] l2_cpu2_mbist1_be_b1; + output l2_cpu2_mbist1_en_b1; + output l2_cpu2_mbist1_rd_en_b1; + output l2_cpu2_mbist1_wr_en_b1; + output l2_cpu2_mbist1_all_b1; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + output [12:0] l2_cpu3_mbist1_addr_b1; + output [3:0] l2_cpu3_mbist1_array_b1; + output [7:0] l2_cpu3_mbist1_be_b1; + output l2_cpu3_mbist1_en_b1; + output l2_cpu3_mbist1_rd_en_b1; + output l2_cpu3_mbist1_wr_en_b1; + output l2_cpu3_mbist1_all_b1; +// END INCLUDE FOR CPU3 + +// BEGIN L2-CPU interface + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + output l2_cpu0_cfg_ecc_en; + output l2_cpu0_arb_thrshld_timeout_en; + output l2_cpu0_disable_clean_evict_opt; + output l2_cpu0_dext_err_r2; // LS external error + output l2_cpu0_dext_err_type_r2; // LS external error type + output l2_cpu0_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu0_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu0_ddata_r2; // LS read data + output l2_cpu0_barrier_done; // LS barrier complete + output l2_cpu0_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu0_spec_bufid; // LS read speculative response buffer id + output l2_cpu0_rvalid; // LS read response valid + output [1:0] l2_cpu0_rstate; // LS read response state + output l2_cpu0_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu0_rbufid; // LS read response buffer id + output l2_cpu0_dvalid_r1; // LS read data valid + output l2_cpu0_dlast_r1; // LS read last indicator + output [2:0] l2_cpu0_dbufid_r1; // LS read data fill buffer id + output l2_cpu0_iext_err_r2; // IF external error + output l2_cpu0_iext_err_type_r2; // IF external error type + output l2_cpu0_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu0_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu0_idata_r2; // IF read data + output l2_cpu0_ivalid_r1; // IF read data valid + output [1:0] l2_cpu0_ibufid_r1; // IF read data fill buffer id + output l2_cpu0_ls_sync_req; // LS sync req + output [48:0] l2_cpu0_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu0_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu0_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu0_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu0_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu0_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu0_ccb_req_info_c3; // LS ccb req info + output l2_cpu0_if_ccb_clken_c3; // IF ccb clken + output l2_cpu0_if_ccb_req_c3; // IF ccb req + output l2_cpu0_if_sync_req; // IF sync req + output l2_cpu0_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu0_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu0_tlb_sync_req; // TLB sync req + output l2_cpu0_tlb_sync_complete; // TLB sync complete + output l2_cpu0_tbw_desc_vld; // TBW descriptor valid + output l2_cpu0_tbw_ext_err; // TBW descriptor external error + output l2_cpu0_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu0_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu0_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu0_spr_rd_data; // DS spr read data + output [1:0] l2_cpu0_l2_cache_size; // DS L2 cache size + output l2_cpu0_pf_throttle_q; // PF throttling + + output l2_cpu0_wr_ex_resp; // store exclusive response + output l2_cpu0_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu0_ic_base; // PERIPHBASE + output l2_cpu0_no_intctrl; // INTCTLR not present + + + output [33:0] l2_cpu0_pmu_events; // L2 PMU events + + input ds_cpu0_l2_spr_en; // cpu0 early spr req for clk enables + input ds_cpu0_l2_spr_rd; // cpu0 spr read op + input ds_cpu0_l2_spr_wr; // cpu0 spr write op + input [8:0] ds_cpu0_l2_spr_addr; // cpu0 spr address + input ds_cpu0_l2_spr_dw; // cpu0 spr access dw + input [63:0] ds_cpu0_l2_spr_wr_data; // cpu0 spr write data + + input l2_cpu0_wr_data_vld_x1_q; // cpu0 write data vld x1 stage + input l2_cpu0_wr_evict_x1_q; // cpu0 write evict x1 stage + input [143:0] l2_cpu0_wr_data; + input l2_cpu0_ls_rd_haz_vld_arb_q; + input l2_cpu0_ls_wr_haz_vld_arb_q; + input l2_cpu0_dt_pmu_evt_en; // PMU enabled. + + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + output l2_cpu1_cfg_ecc_en; + output l2_cpu1_arb_thrshld_timeout_en; + output l2_cpu1_disable_clean_evict_opt; + output l2_cpu1_dext_err_r2; // LS external error + output l2_cpu1_dext_err_type_r2; // LS external error type + output l2_cpu1_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu1_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu1_ddata_r2; // LS read data + output l2_cpu1_barrier_done; // LS barrier complete + output l2_cpu1_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu1_spec_bufid; // LS read speculative response buffer id + output l2_cpu1_rvalid; // LS read response valid + output [1:0] l2_cpu1_rstate; // LS read response state + output l2_cpu1_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu1_rbufid; // LS read response buffer id + output l2_cpu1_dvalid_r1; // LS read data valid + output l2_cpu1_dlast_r1; // LS read last indicator + output [2:0] l2_cpu1_dbufid_r1; // LS read data fill buffer id + output l2_cpu1_iext_err_r2; // IF external error + output l2_cpu1_iext_err_type_r2; // IF external error type + output l2_cpu1_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu1_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu1_idata_r2; // IF read data + output l2_cpu1_ivalid_r1; // IF read data valid + output [1:0] l2_cpu1_ibufid_r1; // IF read data fill buffer id + output l2_cpu1_ls_sync_req; // LS sync req + output [48:0] l2_cpu1_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu1_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu1_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu1_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu1_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu1_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu1_ccb_req_info_c3; // LS ccb req info + output l2_cpu1_if_ccb_clken_c3; // IF ccb clken + output l2_cpu1_if_ccb_req_c3; // IF ccb req + output l2_cpu1_if_sync_req; // IF sync req + output l2_cpu1_tlb_ccb_clken_c3; // IF ccb clken + output l2_cpu1_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu1_tlb_sync_req; // TLB sync req + output l2_cpu1_tlb_sync_complete; // TLB sync complete + output l2_cpu1_tbw_desc_vld; // TBW descriptor valid + output l2_cpu1_tbw_ext_err; // TBW descriptor external error + output l2_cpu1_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu1_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu1_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu1_spr_rd_data; // DS spr read data + output [1:0] l2_cpu1_l2_cache_size; // DS L2 cache size + output l2_cpu1_pf_throttle_q; // PF throttling + + output l2_cpu1_wr_ex_resp; // store exclusive response + output l2_cpu1_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu1_ic_base; // PERIPHBASE + output l2_cpu1_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu1_pmu_events; // L2 PMU events + + input ds_cpu1_l2_spr_en; // cpu1 early spr req for clk enables + input ds_cpu1_l2_spr_rd; // cpu1 spr read op + input ds_cpu1_l2_spr_wr; // cpu1 spr write op + input [8:0] ds_cpu1_l2_spr_addr; // cpu1 spr address + input ds_cpu1_l2_spr_dw; // cpu1 spr access dw + input [63:0] ds_cpu1_l2_spr_wr_data; // cpu1 spr write data + + input l2_cpu1_wr_data_vld_x1_q; // cpu1 write data vld x1 stage + input l2_cpu1_wr_evict_x1_q; // cpu1 write evict x1 stage + input [143:0] l2_cpu1_wr_data; + input l2_cpu1_ls_rd_haz_vld_arb_q; + input l2_cpu1_ls_wr_haz_vld_arb_q; + input l2_cpu1_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + output l2_cpu2_cfg_ecc_en; + output l2_cpu2_arb_thrshld_timeout_en; + output l2_cpu2_disable_clean_evict_opt; + output l2_cpu2_dext_err_r2; // LS external error + output l2_cpu2_dext_err_type_r2; // LS external error type + output l2_cpu2_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu2_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu2_ddata_r2; // LS read data + output l2_cpu2_barrier_done; // LS barrier complete + output l2_cpu2_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu2_spec_bufid; // LS read speculative response buffer id + output l2_cpu2_rvalid; // LS read response valid + output [1:0] l2_cpu2_rstate; // LS read response state + output l2_cpu2_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu2_rbufid; // LS read response buffer id + output l2_cpu2_dvalid_r1; // LS read data valid + output l2_cpu2_dlast_r1; // LS read last indicator + output [2:0] l2_cpu2_dbufid_r1; // LS read data fill buffer id + output l2_cpu2_iext_err_r2; // IF external error + output l2_cpu2_iext_err_type_r2; // IF external error type + output l2_cpu2_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu2_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu2_idata_r2; // IF read data + output l2_cpu2_ivalid_r1; // IF read data valid + output [1:0] l2_cpu2_ibufid_r1; // IF read data fill buffer id + output l2_cpu2_ls_sync_req; // LS sync req + output [48:0] l2_cpu2_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu2_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu2_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu2_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu2_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu2_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu2_ccb_req_info_c3; // LS ccb req info + output l2_cpu2_if_ccb_clken_c3; // IF ccb clken + output l2_cpu2_if_ccb_req_c3; // IF ccb req + output l2_cpu2_if_sync_req; // IF sync req + output l2_cpu2_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu2_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu2_tlb_sync_req; // TLB sync req + output l2_cpu2_tlb_sync_complete; // TLB sync complete + output l2_cpu2_tbw_desc_vld; // TBW descriptor valid + output l2_cpu2_tbw_ext_err; // TBW descriptor external error + output l2_cpu2_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu2_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu2_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu2_spr_rd_data; // DS spr read data + output [1:0] l2_cpu2_l2_cache_size; // DS L2 cache size + output l2_cpu2_pf_throttle_q; // PF throttling + + output l2_cpu2_wr_ex_resp; // store exclusive response + output l2_cpu2_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu2_ic_base; // PERIPHBASE + output l2_cpu2_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu2_pmu_events; // L2 PMU events + + input ds_cpu2_l2_spr_en; // cpu2 early spr req for clk enables + input ds_cpu2_l2_spr_rd; // cpu2 spr read op + input ds_cpu2_l2_spr_wr; // cpu2 spr write op + input [8:0] ds_cpu2_l2_spr_addr; // cpu2 spr address + input ds_cpu2_l2_spr_dw; // cpu2 spr access dw + input [63:0] ds_cpu2_l2_spr_wr_data; // cpu2 spr write data + + input l2_cpu2_wr_data_vld_x1_q; // cpu2 write data vld x1 stage + input l2_cpu2_wr_evict_x1_q; // cpu2 write evict x1 stage + input [143:0] l2_cpu2_wr_data; + input l2_cpu2_ls_rd_haz_vld_arb_q; + input l2_cpu2_ls_wr_haz_vld_arb_q; + input l2_cpu2_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + output l2_cpu3_cfg_ecc_en; + output l2_cpu3_arb_thrshld_timeout_en; + output l2_cpu3_disable_clean_evict_opt; + output l2_cpu3_dext_err_r2; // LS external error + output l2_cpu3_dext_err_type_r2; // LS external error type + output l2_cpu3_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu3_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu3_ddata_r2; // LS read data + output l2_cpu3_barrier_done; // LS barrier complete + output l2_cpu3_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu3_spec_bufid; // LS read speculative response buffer id + output l2_cpu3_rvalid; // LS read response valid + output [1:0] l2_cpu3_rstate; // LS read response state + output l2_cpu3_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu3_rbufid; // LS read response buffer id + output l2_cpu3_dvalid_r1; // LS read data valid + output l2_cpu3_dlast_r1; // LS read last indicator + output [2:0] l2_cpu3_dbufid_r1; // LS read data fill buffer id + output l2_cpu3_iext_err_r2; // IF external error + output l2_cpu3_iext_err_type_r2; // IF external error type + output l2_cpu3_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu3_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu3_idata_r2; // IF read data + output l2_cpu3_ivalid_r1; // IF read data valid + output [1:0] l2_cpu3_ibufid_r1; // IF read data fill buffer id + output l2_cpu3_ls_sync_req; // LS sync req + output [48:0] l2_cpu3_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu3_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu3_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu3_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu3_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu3_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu3_ccb_req_info_c3; // LS ccb req info + output l2_cpu3_if_ccb_clken_c3; // IF ccb clken + output l2_cpu3_if_ccb_req_c3; // IF ccb req + output l2_cpu3_if_sync_req; // IF sync req + output l2_cpu3_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu3_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu3_tlb_sync_req; // TLB sync req + output l2_cpu3_tlb_sync_complete; // TLB sync complete + output l2_cpu3_tbw_desc_vld; // TBW descriptor valid + output l2_cpu3_tbw_ext_err; // TBW descriptor external error + output l2_cpu3_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu3_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu3_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu3_spr_rd_data; // DS spr read data + output [1:0] l2_cpu3_l2_cache_size; // DS L2 cache size + output l2_cpu3_pf_throttle_q; // PF throttling + + output l2_cpu3_wr_ex_resp; // store exclusive response + output l2_cpu3_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu3_ic_base; // PERIPHBASE + output l2_cpu3_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu3_pmu_events; // L2 PMU events + + input ds_cpu3_l2_spr_en; // cpu3 early spr req for clk enables + input ds_cpu3_l2_spr_rd; // cpu3 spr read op + input ds_cpu3_l2_spr_wr; // cpu3 spr write op + input [8:0] ds_cpu3_l2_spr_addr; // cpu3 spr address + input ds_cpu3_l2_spr_dw; // cpu3 spr access dw + input [63:0] ds_cpu3_l2_spr_wr_data; // cpu3 spr write data + + input l2_cpu3_wr_data_vld_x1_q; // cpu3 write data vld x1 stage + input l2_cpu3_wr_evict_x1_q; // cpu3 write evict x1 stage + input [143:0] l2_cpu3_wr_data; + input l2_cpu3_ls_rd_haz_vld_arb_q; + input l2_cpu3_ls_wr_haz_vld_arb_q; + input l2_cpu3_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// tag_pipe / cpu slave +//----------------------------------------------------------------------------- + output l2_cpu0_flsh_ls_rd_l2_dly; // cpu0 ls local hazard flush + output l2_cpu0_flsh_ls_wr_l2_dly; // cpu0 ls local hazard flush + + output l2_cpu0_wr_data_stall; // cpu0 write data stall + + output l2_cpu1_flsh_ls_rd_l2_dly; // cpu1 ls local hazard flush + output l2_cpu1_flsh_ls_wr_l2_dly; // cpu1 ls local hazard flush + + output l2_cpu1_wr_data_stall; // cpu1 write data stall + + output l2_cpu2_flsh_ls_rd_l2_dly; // cpu2 ls local hazard flush + output l2_cpu2_flsh_ls_wr_l2_dly; // cpu2 ls local hazard flush + + output l2_cpu2_wr_data_stall; // cpu2 write data stall + + output l2_cpu3_flsh_ls_rd_l2_dly; // cpu3 ls local hazard flush + output l2_cpu3_flsh_ls_wr_l2_dly; // cpu3 ls local hazard flush + + output l2_cpu3_wr_data_stall; // cpu3 write data stall + + output [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; // cpu0 ls id local hazard flush + output [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; // cpu0 ls id local hazard flush + + output [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; // cpu1 ls id local hazard flush + output [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; // cpu1 ls id local hazard flush + + output [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; // cpu2 ls id local hazard flush + output [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; // cpu2 ls id local hazard flush + + output [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; // cpu3 ls id local hazard flush + output [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; // cpu3 ls id local hazard flush + + output l2_cpu0_flsh_ls_rd_l4_dly; // cpu0 ls global hazard flush + output l2_cpu0_flsh_if_rd_l4_dly; // cpu0 if global hazard flush + output l2_cpu0_flsh_tw_rd_l4_dly; // cpu0 tw global hazard flush + output l2_cpu0_flsh_ls_wr_l4_dly; // cpu0 ls global hazard flush + + output l2_cpu1_flsh_ls_rd_l4_dly; // cpu1 ls global hazard flush + output l2_cpu1_flsh_if_rd_l4_dly; // cpu1 if global hazard flush + output l2_cpu1_flsh_tw_rd_l4_dly; // cpu1 tw global hazard flush + output l2_cpu1_flsh_ls_wr_l4_dly; // cpu1 ls global hazard flush + + output l2_cpu2_flsh_ls_rd_l4_dly; // cpu2 ls global hazard flush + output l2_cpu2_flsh_if_rd_l4_dly; // cpu2 if global hazard flush + output l2_cpu2_flsh_tw_rd_l4_dly; // cpu2 tw global hazard flush + output l2_cpu2_flsh_ls_wr_l4_dly; // cpu2 ls global hazard flush + + output l2_cpu3_flsh_ls_rd_l4_dly; // cpu3 ls global hazard flush + output l2_cpu3_flsh_if_rd_l4_dly; // cpu3 if global hazard flush + output l2_cpu3_flsh_tw_rd_l4_dly; // cpu3 tw global hazard flush + output l2_cpu3_flsh_ls_wr_l4_dly; // cpu3 ls global hazard flush + + output [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; // cpu0 ls id global hazard flush + output [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; // cpu0 if id global hazard flush + output [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; // cpu0 ls id global hazard flush + output l2_cpu0_flsh_ls_wr_evict_l4_dly; // cpu0 ls evict hazard + + output [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; // cpu1 ls id global hazard flush + output [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; // cpu1 if id global hazard flush + output [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; // cpu1 ls id global hazard flush + output l2_cpu1_flsh_ls_wr_evict_l4_dly; // cpu1 ls evict hazard + + output [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; // cpu2 ls id global hazard flush + output [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; // cpu2 if id global hazard flush + output [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; // cpu2 ls id global hazard flush + output l2_cpu2_flsh_ls_wr_evict_l4_dly; // cpu2 ls evict hazard + + output [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; // cpu3 ls id global hazard flush + output [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; // cpu3 if id global hazard flush + output [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; // cpu3 ls id global hazard flush + output l2_cpu3_flsh_ls_wr_evict_l4_dly; // cpu3 ls evict hazard + + output l2_cpu0_lrq_haz_pending; // cpu0 lrq hazard pending + output l2_cpu1_lrq_haz_pending; // cpu1 lrq hazard pending + output l2_cpu2_lrq_haz_pending; // cpu2 lrq hazard pending + output l2_cpu3_lrq_haz_pending; // cpu3 lrq hazard pending + + output l2_cpu0_ifq_haz_pending; // cpu0 ifq hazard pending + output l2_cpu1_ifq_haz_pending; // cpu1 ifq hazard pending + output l2_cpu2_ifq_haz_pending; // cpu2 ifq hazard pending + output l2_cpu3_ifq_haz_pending; // cpu3 ifq hazard pending + + output l2_cpu0_trq_haz_pending; // cpu0 trq hazard pending + output l2_cpu1_trq_haz_pending; // cpu1 trq hazard pending + output l2_cpu2_trq_haz_pending; // cpu2 trq hazard pending + output l2_cpu3_trq_haz_pending; // cpu3 trq hazard pending + + output l2_cpu0_wrq_haz_pending; // cpu0 wrq hazard pending + output l2_cpu1_wrq_haz_pending; // cpu1 wrq hazard pending + output l2_cpu2_wrq_haz_pending; // cpu2 wrq hazard pending + output l2_cpu3_wrq_haz_pending; // cpu3 wrq hazard pending + + output l2_cpu0_idle_block_reqs_q; // cpu0 idle block requests + output l2_cpu1_idle_block_reqs_q; // cpu1 idle block requests + output l2_cpu2_idle_block_reqs_q; // cpu2 idle block requests + output l2_cpu3_idle_block_reqs_q; // cpu3 idle block requests + + output l2_cpu0_ls_peq_coll_l4_dly; // cpu0 peq collision detected + output l2_cpu1_ls_peq_coll_l4_dly; // cpu1 peq collision detected + output l2_cpu2_ls_peq_coll_l4_dly; // cpu2 peq collision detected + output l2_cpu3_ls_peq_coll_l4_dly; // cpu3 peq collision detected + +//----------------------------------------------------------------------------- +// tag_pipe +//----------------------------------------------------------------------------- + output [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; // tbnk0 clear cpu0 lrq entry + output [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; // tbnk0 clear cpu1 lrq entry + output [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; // tbnk0 clear cpu2 lrq entry + output [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; // tbnk0 clear cpu3 lrq entry + + output [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; // tbnk1 clear cpu0 lrq entry + output [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; // tbnk1 clear cpu1 lrq entry + output [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; // tbnk1 clear cpu2 lrq entry + output [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; // tbnk1 clear cpu3 lrq entry + + output [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; // tbnk0 clear cpu0 ifq entry + output [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; // tbnk0 clear cpu1 ifq entry + output [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; // tbnk0 clear cpu2 ifq entry + output [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; // tbnk0 clear cpu3 ifq entry + + output [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; // tbnk1 clear cpu0 ifq entry + output [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; // tbnk1 clear cpu1 ifq entry + output [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; // tbnk1 clear cpu2 ifq entry + output [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; // tbnk1 clear cpu3 ifq entry + + output l2_tbnk0_cpu0_trq_clr_l4_dly2_q; // tbnk0 clear cpu0 trq entry + output l2_tbnk0_cpu1_trq_clr_l4_dly2_q; // tbnk0 clear cpu1 trq entry + output l2_tbnk0_cpu2_trq_clr_l4_dly2_q; // tbnk0 clear cpu2 trq entry + output l2_tbnk0_cpu3_trq_clr_l4_dly2_q; // tbnk0 clear cpu3 trq entry + + output l2_tbnk1_cpu0_trq_clr_l4_dly2_q; // tbnk1 clear cpu0 trq entry + output l2_tbnk1_cpu1_trq_clr_l4_dly2_q; // tbnk1 clear cpu1 trq entry + output l2_tbnk1_cpu2_trq_clr_l4_dly2_q; // tbnk1 clear cpu2 trq entry + output l2_tbnk1_cpu3_trq_clr_l4_dly2_q; // tbnk1 clear cpu3 trq entry + + output [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; // tbnk0 clear cpu0 wrq entry + output [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; // tbnk0 clear cpu1 wrq entry + output [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; // tbnk0 clear cpu2 wrq entry + output [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; // tbnk0 clear cpu3 wrq entry + + output [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; // tbnk1 clear cpu0 wrq entry + output [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; // tbnk1 clear cpu1 wrq entry + output [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; // tbnk1 clear cpu2 wrq entry + output [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; // tbnk1 clear cpu3 wrq entry + + +//----------------------------------------------------------------------------- +// cpu_logic / cpu slave +//----------------------------------------------------------------------------- + output l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu0 ls rd flsh l4 active + output l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu0 wr rd flsh l4 active + + output l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu1 ls rd flsh l4 active + output l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu1 wr rd flsh l4 active + + output l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu2 ls rd flsh l4 active + output l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu2 wr rd flsh l4 active + + output l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu3 ls rd flsh l4 active + output l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu3 wr rd flsh l4 active + + +//----------------------------------------------------------------------------- +// feq / cpu slave +//----------------------------------------------------------------------------- + input [129:0] l2_cpu0_dsq_rd_data_q; // cpu0 wrq/dsq data + input [15:0] l2_cpu0_dsq_rd_byte_strb_q; // cpu0 wrq/dsq byte strobes + input [129:0] l2_cpu1_dsq_rd_data_q; // cpu1 wrq/dsq data + input [15:0] l2_cpu1_dsq_rd_byte_strb_q; // cpu1 wrq/dsq byte strobes + input [129:0] l2_cpu2_dsq_rd_data_q; // cpu2 wrq/dsq data + input [15:0] l2_cpu2_dsq_rd_byte_strb_q; // cpu2 wrq/dsq byte strobes + input [129:0] l2_cpu3_dsq_rd_data_q; // cpu3 wrq/dsq data + input [15:0] l2_cpu3_dsq_rd_byte_strb_q; // cpu3 wrq/dsq byte strobes + + output l2_cpu0_dsq_clr_vld_q; // cpu0 dsq clear wrq vld entry + output [3:0] l2_cpu0_dsq_clr_id_q; // cpu0 dsq clear wrq buffer id + output l2_cpu0_dsq_rd_en; // cpu0 dsq/wrq data enable + output l2_cpu0_dsq_rd_en_x2; // cpu0 dsq/wrq data enable x2 + output [3:0] l2_cpu0_dsq_rd_buf_id; // cpu0 dsq/wrq data select + output l2_cpu1_dsq_clr_vld_q; // cpu1 dsq clear wrq vld entry + output [3:0] l2_cpu1_dsq_clr_id_q; // cpu1 dsq clear wrq buffer id + output l2_cpu1_dsq_rd_en; // cpu1 dsq/wrq data enable + output l2_cpu1_dsq_rd_en_x2; // cpu1 dsq/wrq data enable x2 + output [3:0] l2_cpu1_dsq_rd_buf_id; // cpu1 dsq/wrq data select + output l2_cpu2_dsq_clr_vld_q; // cpu2 dsq clear wrq vld entry + output [3:0] l2_cpu2_dsq_clr_id_q; // cpu2 dsq clear wrq buffer id + output l2_cpu2_dsq_rd_en; // cpu2 dsq/wrq data enable + output l2_cpu2_dsq_rd_en_x2; // cpu2 dsq/wrq data enable x2 + output [3:0] l2_cpu2_dsq_rd_buf_id; // cpu2 dsq/wrq data select + output l2_cpu3_dsq_clr_vld_q; // cpu3 dsq clear wrq vld entry + output l2_cpu3_dsq_rd_en; // cpu3 dsq/wrq data enable + output l2_cpu3_dsq_rd_en_x2; // cpu3 dsq/wrq data enable x2 + output [3:0] l2_cpu3_dsq_clr_id_q; // cpu3 dsq clear wrq buffer id + output [3:0] l2_cpu3_dsq_rd_buf_id; // cpu3 dsq/wrq data select + +//----------------------------------------------------------------------------- +// arbitration +//----------------------------------------------------------------------------- + output l2_cpu0_rd_vld_skid; // cpu0 read skid buffer valid + output l2_cpu1_rd_vld_skid; // cpu1 read skid buffer valid + output l2_cpu2_rd_vld_skid; // cpu2 read skid buffer valid + output l2_cpu3_rd_vld_skid; // cpu3 read skid buffer valid + + output l2_cpu0_pf_rd_vld_skid_popped; // cpu0 pf read skid buffer popped + output l2_cpu1_pf_rd_vld_skid_popped; // cpu1 pf read skid buffer popped + output l2_cpu2_pf_rd_vld_skid_popped; // cpu2 pf read skid buffer popped + output l2_cpu3_pf_rd_vld_skid_popped; // cpu3 pf read skid buffer popped + + output l2_cpu0_rd_arb; // + output l2_cpu1_rd_arb; // + output l2_cpu2_rd_arb; // + output l2_cpu3_rd_arb; // + + output l2_cpu0_wr_vld_skid; // cpu0 write skid buffer valid + output l2_cpu1_wr_vld_skid; // cpu1 write skid buffer valid + output l2_cpu2_wr_vld_skid; // cpu2 write skid buffer valid + output l2_cpu3_wr_vld_skid; // cpu3 write skid buffer valid + + output l2_cpu0_wr_arb; // + output l2_cpu1_wr_arb; // + output l2_cpu2_wr_arb; // + output l2_cpu3_wr_arb; // + + output l2_cpu0_ic_vld_skid; // cpu0 peripheral (ic) skid buffer valid + output l2_cpu1_ic_vld_skid; // cpu1 peripheral (ic) skid buffer valid + output l2_cpu2_ic_vld_skid; // cpu2 peripheral (ic) skid buffer valid + output l2_cpu3_ic_vld_skid; // cpu3 peripheral (ic) skid buffer valid + + output l2_cpu0_ic_barrier_stall_q; // cpu0 (ic) barrier stall + output l2_cpu1_ic_barrier_stall_q; // cpu1 (ic) barrier stall + output l2_cpu2_ic_barrier_stall_q; // cpu2 (ic) barrier stall + output l2_cpu3_ic_barrier_stall_q; // cpu3 (ic) barrier stall + + output l2_cpu0_blk_non_evict_wr; // cpu0 block non-evict writes from arbitrating + output l2_cpu1_blk_non_evict_wr; // cpu1 block non-evict writes from arbitrating + output l2_cpu2_blk_non_evict_wr; // cpu2 block non-evict writes from arbitrating + output l2_cpu3_blk_non_evict_wr; // cpu3 block non-evict writes from arbitrating + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + input l2_cpu0_idle_wakeup_q; // cpu0 idle wakeup + input l2_cpu0_rd_arb_fast; // cpu0 read arbitration fast request + input [4:0] l2_cpu0_rd_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu0_rd_lrq_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu0_rd_type_arb_set; // cpu0 read arbitration type + input [2:0] l2_cpu0_rd_cache_attr_arb_set; // cpu0 read arbitration cache attributes + input [7:0] l2_cpu0_rd_page_attr_arb_set; // cpu0 read arbitration page attributes + input [2:0] l2_cpu0_rd_elem_size_arb_set; // cpu0 read arbitration element size + input l2_cpu0_rd_way_arb_set; // cpu0 read arbitration way + input l2_cpu0_rd_replayed_arb_set; // cpu0 read arbitration replayed + input l2_cpu0_rd_excl_arb_set; // cpu0 read arbitration exclusive + input l2_cpu0_rd_priv_arb_set; // cpu0 read arbitration priv + input [1:0] l2_cpu0_rd_shared_arb_set; // cpu0 read arbitration shared + input l2_cpu0_rd_va48_arb_set; // cpu0 read arbitration va48 + input l2_cpu0_rd_aarch64_arb_set; // cpu0 read arbitration aarch64 + input [15:8] l2_cpu0_rd_asid_arb_set; // cpu0 read arbitration asid + input l2_cpu0_rd_prfm_arb_set; // cpu0 read arbitration prfm + input [44:0] l2_cpu0_rd_addr_arb_set; // cpu0 read arbitration address + input l2_cpu0_rd_bypass_arb_set; // cpu0 read arbitration bypass + input l2_cpu0_rd_bypass_req_can_e5; // cpu0 read arbitration bypass cancelled request + input l2_cpu0_early_rd_reqe4_e5_q; // cpu0 read arbitration bypass cancelled request + input l2_cpu0_rd_bypass_way_e5; // cpu0 read arbitration bypass way + input [2:0] l2_cpu0_rd_bypass_bufid_e5; // cpu0 read arbitration bypass bufid + input [2:0] l2_cpu0_rd_bypass_lrq_id_e5; // cpu0 read arbitration bypass bufid + + input l2_cpu0_wr_arb_fast; // cpu0 write arbitration fast request + input [3:0] l2_cpu0_wr_id_arb_set; // cpu0 write arbitration id for 1st qw + input [3:0] l2_cpu0_wr_partial_dw_arb_set; // cpu0 write partial qw byte strobe indicator + input [2:0] l2_cpu0_wr_cache_attr_arb_set; // cpu0 write arbitration cache attributes + input [7:0] l2_cpu0_wr_page_attr_arb_set; // cpu0 write arbitration page attributes + input [2:0] l2_cpu0_wr_elem_size_arb_set; // cpu0 write arbitration element size + input [2:0] l2_cpu0_wr_type_arb_set; // cpu0 write arbitration type + input [11:0] l2_cpu0_wr_cl_id_arb_set; // cpu0 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu0_wr_priv_arb_set; // cpu0 write arbitration priv + input [1:0] l2_cpu0_wr_shared_arb_set; // cpu0 write arbitration shared + input l2_cpu0_wr_last_arb_set; // cpu0 write arbitration last + input l2_cpu0_wr_clean_evict_arb_set; // cpu0 write arbitration clean eviction + input l2_cpu0_wr_err_arb_set; // cpu0 write arbitration error + input l2_cpu0_wr_way_arb_set; // cpu0 write arbitration way + input l2_cpu0_wr_dirty_arb_set; // cpu0 write arbitration dirty + input l2_cpu0_wr_1st_replayed_arb_set; // cpu0 write arbitration 1st replay indicator + input [44:0] l2_cpu0_wr_addr_arb_set; // cpu0 write arbitration address + input l2_cpu0_ic_arb_fast; // cpu0 peripheral (ic) arbitration fast request + input [2:0] l2_cpu0_ic_id_arb_set; // cpu0 peripheral (ic) fill buffer id + input l2_cpu0_ic_write_arb_set; // cpu0 peripheral (ic) write indicator + input l2_cpu0_ic_excl_arb_set; // cpu0 peripheral (ic) exclusive indicator + input [2:0] l2_cpu0_ic_elem_size_arb_set; // cpu0 peripheral (ic) element size + input l2_cpu0_ic_ns_arb_set; // cpu0 peripheral (ic) non-secure + input [15:0] l2_cpu0_ic_addr_arb_set; // cpu0 peripheral (ic) address + input [31:0] l2_cpu0_ic_data_arb_set; // cpu0 peripheral (ic) write data + + input l2_cpu0_wrq_almost_full; // cpu0 wrq almost full indicator + + input l2_cpu0_ls_wr_req_w2a; // cpu0 ls write request + input l2_cpu0_ls_wr_last_w2a; // cpu0 ls last indicator + input l2_cpu0_ls_wr_dirty_w2a; // cpu0 ls dirty indicator + input l2_cpu0_ls_wr_err_w2a; // cpu0 ls error indicator + input [2:0] l2_cpu0_ls_wr_type_w2a; // cpu0 ls write type + input [4:0] l2_cpu0_ls_wr_ccb_id_w2a; // cpu0 ls ccb id + input [127:0] l2_cpu0_ls_wr_data_w2a; // cpu0 ls write data + + input l2_cpu0_ls_ccb_resp; // cpu0 ls ccb resp + input [4:0] l2_cpu0_ls_ccb_resp_id; // cpu0 ls ccb id + input l2_cpu0_ls_ccb_data_wr; // cpu0 ls ccb data xfer + + input l2_cpu0_if_ccb_resp; // cpu0 if ccb resp + input [4:0] l2_cpu0_if_ccb_resp_id; // cpu0 if ccb id + + input l2_cpu0_tw_ccb_resp; // cpu0 tw ccb resp + input [4:0] l2_cpu0_tw_ccb_resp_id; // cpu0 tw ccb id + + input l2_cpu0_if_sync_done_q; // cpu0 sync response + input l2_cpu0_tlb_sync_done_q; // cpu0 tlb sync response + + input [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; // cpu0 lrq clear hazard id + input [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; // cpu0 wrq clear hazard id + input [3:0] l2_cpu0_ls_rd_haz_id_arb_q; // cpu0 ls rd wrq hazard id + input [2:0] l2_cpu0_ls_wr_haz_id_arb_q; // cpu0 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + input l2_cpu1_idle_wakeup_q; // cpu1 idle wakeup + input l2_cpu1_rd_arb_fast; // cpu1 read arbitration fast request + input [4:0] l2_cpu1_rd_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu1_rd_lrq_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu1_rd_type_arb_set; // cpu1 read arbitration type + input [2:0] l2_cpu1_rd_cache_attr_arb_set; // cpu1 read arbitration cache attributes + input [7:0] l2_cpu1_rd_page_attr_arb_set; // cpu1 read arbitration page attributes + input [2:0] l2_cpu1_rd_elem_size_arb_set; // cpu1 read arbitration element size + input l2_cpu1_rd_way_arb_set; // cpu1 read arbitration way + input l2_cpu1_rd_replayed_arb_set; // cpu1 read arbitration replayed + input l2_cpu1_rd_excl_arb_set; // cpu1 read arbitration exclusive + input l2_cpu1_rd_priv_arb_set; // cpu1 read arbitration priv + input [1:0] l2_cpu1_rd_shared_arb_set; // cpu1 read arbitration shared + input l2_cpu1_rd_va48_arb_set; // cpu1 read arbitration va48 + input l2_cpu1_rd_aarch64_arb_set; // cpu1 read arbitration aarch64 + input [15:8] l2_cpu1_rd_asid_arb_set; // cpu1 read arbitration asid + input l2_cpu1_rd_prfm_arb_set; // cpu1 read arbitration prfm + input [44:0] l2_cpu1_rd_addr_arb_set; // cpu1 read arbitration address + input l2_cpu1_rd_bypass_arb_set; // cpu1 read arbitration bypass + input l2_cpu1_rd_bypass_req_can_e5; // cpu1 read arbitration bypass cancelled request + input l2_cpu1_early_rd_reqe4_e5_q; // cpu1 read arbitration bypass cancelled request + input l2_cpu1_rd_bypass_way_e5; // cpu1 read arbitration bypass way + input [2:0] l2_cpu1_rd_bypass_bufid_e5; // cpu1 read arbitration bypass bufid + input [2:0] l2_cpu1_rd_bypass_lrq_id_e5; // cpu1 read arbitration bypass bufid + + input l2_cpu1_wr_arb_fast; // cpu1 write arbitration fast request + input [3:0] l2_cpu1_wr_id_arb_set; // cpu1 write arbitration id for 1st qw + input [3:0] l2_cpu1_wr_partial_dw_arb_set; // cpu1 write partial qw byte strobe indicator + input [2:0] l2_cpu1_wr_cache_attr_arb_set; // cpu1 write arbitration cache attributes + input [7:0] l2_cpu1_wr_page_attr_arb_set; // cpu1 write arbitration page attributes + input [2:0] l2_cpu1_wr_elem_size_arb_set; // cpu1 write arbitration element size + input [2:0] l2_cpu1_wr_type_arb_set; // cpu1 write arbitration type + input [11:0] l2_cpu1_wr_cl_id_arb_set; // cpu1 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu1_wr_priv_arb_set; // cpu1 write arbitration priv + input [1:0] l2_cpu1_wr_shared_arb_set; // cpu1 write arbitration shared + input l2_cpu1_wr_last_arb_set; // cpu1 write arbitration last + input l2_cpu1_wr_clean_evict_arb_set; // cpu1 write arbitration clean eviction + input l2_cpu1_wr_err_arb_set; // cpu1 write arbitration error + input l2_cpu1_wr_way_arb_set; // cpu1 write arbitration way + input l2_cpu1_wr_dirty_arb_set; // cpu1 write arbitration dirty + input l2_cpu1_wr_1st_replayed_arb_set; // cpu1 write arbitration 1st replay indicator + input [44:0] l2_cpu1_wr_addr_arb_set; // cpu1 write arbitration address + input l2_cpu1_ic_arb_fast; // cpu1 peripheral (ic) arbitration fast request + input [2:0] l2_cpu1_ic_id_arb_set; // cpu1 peripheral (ic) fill buffer id + input l2_cpu1_ic_write_arb_set; // cpu1 peripheral (ic) write indicator + input l2_cpu1_ic_excl_arb_set; // cpu1 peripheral (ic) exclusive indicator + input [2:0] l2_cpu1_ic_elem_size_arb_set; // cpu1 peripheral (ic) element size + input l2_cpu1_ic_ns_arb_set; // cpu1 peripheral (ic) non-secure + input [15:0] l2_cpu1_ic_addr_arb_set; // cpu1 peripheral (ic) address + input [31:0] l2_cpu1_ic_data_arb_set; // cpu1 peripheral (ic) write data + + input l2_cpu1_wrq_almost_full; // cpu1 wrq almost full indicator + + input l2_cpu1_ls_wr_req_w2a; // cpu1 ls write request + input l2_cpu1_ls_wr_last_w2a; // cpu1 ls last indicator + input l2_cpu1_ls_wr_dirty_w2a; // cpu1 ls dirty indicator + input l2_cpu1_ls_wr_err_w2a; // cpu1 ls error indicator + input [2:0] l2_cpu1_ls_wr_type_w2a; // cpu1 ls write type + input [4:0] l2_cpu1_ls_wr_ccb_id_w2a; // cpu1 ls ccb id + input [127:0] l2_cpu1_ls_wr_data_w2a; // cpu1 ls write data + + input l2_cpu1_ls_ccb_resp; // cpu1 ls ccb resp + input [4:0] l2_cpu1_ls_ccb_resp_id; // cpu1 ls ccb id + input l2_cpu1_ls_ccb_data_wr; // cpu1 ls ccb data xfer + + input l2_cpu1_if_ccb_resp; // cpu1 if ccb resp + input [4:0] l2_cpu1_if_ccb_resp_id; // cpu1 if ccb id + + input l2_cpu1_tw_ccb_resp; // cpu1 tw ccb resp + input [4:0] l2_cpu1_tw_ccb_resp_id; // cpu1 tw ccb id + + input l2_cpu1_if_sync_done_q; // cpu1 sync response + input l2_cpu1_tlb_sync_done_q; // cpu1 tlb sync response + + input [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; // cpu1 lrq clear hazard id + input [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; // cpu1 wrq clear hazard id + input [3:0] l2_cpu1_ls_rd_haz_id_arb_q; // cpu1 ls rd wrq hazard id + input [2:0] l2_cpu1_ls_wr_haz_id_arb_q; // cpu1 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + input l2_cpu2_idle_wakeup_q; // cpu2 idle wakeup + input l2_cpu2_rd_arb_fast; // cpu2 read arbitration fast request + input [4:0] l2_cpu2_rd_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu2_rd_lrq_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu2_rd_type_arb_set; // cpu2 read arbitration type + input [2:0] l2_cpu2_rd_cache_attr_arb_set; // cpu2 read arbitration cache attributes + input [7:0] l2_cpu2_rd_page_attr_arb_set; // cpu2 read arbitration page attributes + input [2:0] l2_cpu2_rd_elem_size_arb_set; // cpu2 read arbitration element size + input l2_cpu2_rd_way_arb_set; // cpu2 read arbitration way + input l2_cpu2_rd_replayed_arb_set; // cpu2 read arbitration replayed + input l2_cpu2_rd_excl_arb_set; // cpu2 read arbitration exclusive + input l2_cpu2_rd_priv_arb_set; // cpu2 read arbitration priv + input [1:0] l2_cpu2_rd_shared_arb_set; // cpu2 read arbitration shared + input l2_cpu2_rd_va48_arb_set; // cpu0 read arbitration va48 + input l2_cpu2_rd_aarch64_arb_set; // cpu2 read arbitration aarch64 + input [15:8] l2_cpu2_rd_asid_arb_set; // cpu2 read arbitration asid + input l2_cpu2_rd_prfm_arb_set; // cpu2 read arbitration prfm + input [44:0] l2_cpu2_rd_addr_arb_set; // cpu2 read arbitration address + input l2_cpu2_rd_bypass_arb_set; // cpu2 read arbitration bypass + input l2_cpu2_rd_bypass_req_can_e5; // cpu2 read arbitration bypass cancelled request + input l2_cpu2_early_rd_reqe4_e5_q; // cpu2 read arbitration bypass cancelled request + input l2_cpu2_rd_bypass_way_e5; // cpu2 read arbitration bypass way + input [2:0] l2_cpu2_rd_bypass_bufid_e5; // cpu2 read arbitration bypass bufid + input [2:0] l2_cpu2_rd_bypass_lrq_id_e5; // cpu2 read arbitration bypass bufid + + input l2_cpu2_wr_arb_fast; // cpu2 write arbitration fast request + input [3:0] l2_cpu2_wr_id_arb_set; // cpu2 write arbitration id for 1st qw + input [3:0] l2_cpu2_wr_partial_dw_arb_set; // cpu2 write partial qw byte strobe indicator + input [2:0] l2_cpu2_wr_cache_attr_arb_set; // cpu2 write arbitration cache attributes + input [7:0] l2_cpu2_wr_page_attr_arb_set; // cpu2 write arbitration page attributes + input [2:0] l2_cpu2_wr_elem_size_arb_set; // cpu2 write arbitration element size + input [2:0] l2_cpu2_wr_type_arb_set; // cpu2 write arbitration type + input [11:0] l2_cpu2_wr_cl_id_arb_set; // cpu2 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu2_wr_priv_arb_set; // cpu2 write arbitration priv + input [1:0] l2_cpu2_wr_shared_arb_set; // cpu2 write arbitration shared + input l2_cpu2_wr_last_arb_set; // cpu2 write arbitration last + input l2_cpu2_wr_clean_evict_arb_set; // cpu2 write arbitration clean eviction + input l2_cpu2_wr_err_arb_set; // cpu2 write arbitration error + input l2_cpu2_wr_way_arb_set; // cpu2 write arbitration way + input l2_cpu2_wr_dirty_arb_set; // cpu2 write arbitration dirty + input l2_cpu2_wr_1st_replayed_arb_set; // cpu2 write arbitration 1st replay indicator + input [44:0] l2_cpu2_wr_addr_arb_set; // cpu2 write arbitration address + input l2_cpu2_ic_arb_fast; // cpu2 peripheral (ic) arbitration fast request + input [2:0] l2_cpu2_ic_id_arb_set; // cpu2 peripheral (ic) fill buffer id + input l2_cpu2_ic_write_arb_set; // cpu2 peripheral (ic) write indicator + input l2_cpu2_ic_excl_arb_set; // cpu2 peripheral (ic) exclusive indicator + input [2:0] l2_cpu2_ic_elem_size_arb_set; // cpu2 peripheral (ic) element size + input l2_cpu2_ic_ns_arb_set; // cpu2 peripheral (ic) non-secure + input [15:0] l2_cpu2_ic_addr_arb_set; // cpu2 peripheral (ic) address + input [31:0] l2_cpu2_ic_data_arb_set; // cpu2 peripheral (ic) write data + + input l2_cpu2_wrq_almost_full; // cpu2 wrq almost full indicator + + input l2_cpu2_ls_wr_req_w2a; // cpu2 ls write request + input l2_cpu2_ls_wr_last_w2a; // cpu2 ls last indicator + input l2_cpu2_ls_wr_dirty_w2a; // cpu2 ls dirty indicator + input l2_cpu2_ls_wr_err_w2a; // cpu2 ls error indicator + input [2:0] l2_cpu2_ls_wr_type_w2a; // cpu2 ls write type + input [4:0] l2_cpu2_ls_wr_ccb_id_w2a; // cpu2 ls ccb id + input [127:0] l2_cpu2_ls_wr_data_w2a; // cpu2 ls write data + + input l2_cpu2_ls_ccb_resp; // cpu2 ls ccb resp + input [4:0] l2_cpu2_ls_ccb_resp_id; // cpu2 ls ccb id + input l2_cpu2_ls_ccb_data_wr; // cpu2 ls ccb data xfer + + input l2_cpu2_if_ccb_resp; // cpu2 if ccb resp + input [4:0] l2_cpu2_if_ccb_resp_id; // cpu2 if ccb id + + input l2_cpu2_tw_ccb_resp; // cpu2 tw ccb resp + input [4:0] l2_cpu2_tw_ccb_resp_id; // cpu2 tw ccb id + + input l2_cpu2_if_sync_done_q; // cpu2 sync response + input l2_cpu2_tlb_sync_done_q; // cpu2 tlb sync response + + input [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; // cpu2 lrq clear hazard id + input [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; // cpu2 wrq clear hazard id + input [3:0] l2_cpu2_ls_rd_haz_id_arb_q; // cpu2 ls rd wrq hazard id + input [2:0] l2_cpu2_ls_wr_haz_id_arb_q; // cpu2 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + input l2_cpu3_idle_wakeup_q; // cpu3 idle wakeup + input l2_cpu3_rd_arb_fast; // cpu3 read arbitration fast request + input [4:0] l2_cpu3_rd_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu3_rd_lrq_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu3_rd_type_arb_set; // cpu3 read arbitration type + input [2:0] l2_cpu3_rd_cache_attr_arb_set; // cpu3 read arbitration cache attributes + input [7:0] l2_cpu3_rd_page_attr_arb_set; // cpu3 read arbitration page attributes + input [2:0] l2_cpu3_rd_elem_size_arb_set; // cpu3 read arbitration element size + input l2_cpu3_rd_way_arb_set; // cpu3 read arbitration way + input l2_cpu3_rd_replayed_arb_set; // cpu3 read arbitration replayed + input l2_cpu3_rd_excl_arb_set; // cpu3 read arbitration exclusive + input l2_cpu3_rd_priv_arb_set; // cpu3 read arbitration priv + input [1:0] l2_cpu3_rd_shared_arb_set; // cpu3 read arbitration shared + input l2_cpu3_rd_va48_arb_set; // cpu3 read arbitration va48 + input l2_cpu3_rd_aarch64_arb_set; // cpu3 read arbitration aarch64 + input [15:8] l2_cpu3_rd_asid_arb_set; // cpu3 read arbitration asid + input l2_cpu3_rd_prfm_arb_set; // cpu3 read arbitration prfm + input [44:0] l2_cpu3_rd_addr_arb_set; // cpu3 read arbitration address + input l2_cpu3_rd_bypass_arb_set; // cpu3 read arbitration bypass + input l2_cpu3_rd_bypass_req_can_e5; // cpu3 read arbitration bypass cancelled request + input l2_cpu3_early_rd_reqe4_e5_q; // cpu3 read arbitration bypass cancelled request + input l2_cpu3_rd_bypass_way_e5; // cpu3 read arbitration bypass way + input [2:0] l2_cpu3_rd_bypass_bufid_e5; // cpu3 read arbitration bypass bufid + input [2:0] l2_cpu3_rd_bypass_lrq_id_e5; // cpu3 read arbitration bypass bufid + + input l2_cpu3_wr_arb_fast; // cpu3 write arbitration fast request + input [3:0] l2_cpu3_wr_id_arb_set; // cpu3 write arbitration id for 1st qw + input [3:0] l2_cpu3_wr_partial_dw_arb_set; // cpu3 write partial qw byte strobe indicator + input [2:0] l2_cpu3_wr_cache_attr_arb_set; // cpu3 write arbitration cache attributes + input [7:0] l2_cpu3_wr_page_attr_arb_set; // cpu3 write arbitration page attributes + input [2:0] l2_cpu3_wr_elem_size_arb_set; // cpu3 write arbitration element size + input [2:0] l2_cpu3_wr_type_arb_set; // cpu3 write arbitration type + input [11:0] l2_cpu3_wr_cl_id_arb_set; // cpu3 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu3_wr_priv_arb_set; // cpu3 write arbitration priv + input [1:0] l2_cpu3_wr_shared_arb_set; // cpu3 write arbitration shared + input l2_cpu3_wr_last_arb_set; // cpu3 write arbitration last + input l2_cpu3_wr_clean_evict_arb_set; // cpu3 write arbitration clean eviction + input l2_cpu3_wr_err_arb_set; // cpu3 write arbitration error + input l2_cpu3_wr_way_arb_set; // cpu3 write arbitration way + input l2_cpu3_wr_dirty_arb_set; // cpu3 write arbitration dirty + input l2_cpu3_wr_1st_replayed_arb_set; // cpu3 write arbitration 1st replay indicator + input [44:0] l2_cpu3_wr_addr_arb_set; // cpu3 write arbitration address + input l2_cpu3_ic_arb_fast; // cpu3 peripheral (ic) arbitration fast request + input [2:0] l2_cpu3_ic_id_arb_set; // cpu3 peripheral (ic) fill buffer id + input l2_cpu3_ic_write_arb_set; // cpu3 peripheral (ic) write indicator + input l2_cpu3_ic_excl_arb_set; // cpu3 peripheral (ic) exclusive indicator + input [2:0] l2_cpu3_ic_elem_size_arb_set; // cpu3 peripheral (ic) element size + input l2_cpu3_ic_ns_arb_set; // cpu3 peripheral (ic) non-secure + input [15:0] l2_cpu3_ic_addr_arb_set; // cpu3 peripheral (ic) address + input [31:0] l2_cpu3_ic_data_arb_set; // cpu3 peripheral (ic) write data + + input l2_cpu3_wrq_almost_full; // cpu3 wrq almost full indicator + + input l2_cpu3_ls_wr_req_w2a; // cpu3 ls write request + input l2_cpu3_ls_wr_last_w2a; // cpu3 ls last indicator + input l2_cpu3_ls_wr_dirty_w2a; // cpu3 ls dirty indicator + input l2_cpu3_ls_wr_err_w2a; // cpu3 ls error indicator + input [2:0] l2_cpu3_ls_wr_type_w2a; // cpu3 ls write type + input [4:0] l2_cpu3_ls_wr_ccb_id_w2a; // cpu3 ls ccb id + input [127:0] l2_cpu3_ls_wr_data_w2a; // cpu3 ls write data + + input l2_cpu3_ls_ccb_resp; // cpu3 ls ccb resp + input [4:0] l2_cpu3_ls_ccb_resp_id; // cpu3 ls ccb id + input l2_cpu3_ls_ccb_data_wr; // cpu3 ls ccb data xfer + + input l2_cpu3_if_ccb_resp; // cpu3 if ccb resp + input [4:0] l2_cpu3_if_ccb_resp_id; // cpu3 if ccb id + + input l2_cpu3_tw_ccb_resp; // cpu3 tw ccb resp + input [4:0] l2_cpu3_tw_ccb_resp_id; // cpu3 tw ccb id + + input l2_cpu3_if_sync_done_q; // cpu3 sync response + input l2_cpu3_tlb_sync_done_q; // cpu3 tlb sync response + + input [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; // cpu3 lrq clear hazard id + input [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; // cpu3 wrq clear hazard id + input [3:0] l2_cpu3_ls_rd_haz_id_arb_q; // cpu3 ls rd wrq hazard id + input [2:0] l2_cpu3_ls_wr_haz_id_arb_q; // cpu3 ls wr lrq hazard id + +// END L2-CPU interface + +//------------------------------------------------------------------- +// TM interface +//------------------------------------------------------------------- +// BEGIN TIMER-CPU interface + output [3:0] tm_cpu0_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu0_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu1_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu1_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu2_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu2_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu3_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu3_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> +// END TIMER-CPU interface + +//----------------------------------------------------------------------------- +// IC interface +//----------------------------------------------------------------------------- + input ls_cpu0_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu0_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu0_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu0_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu0_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu0_raw_eae_secure; // LS S LPAE to IC + + input ds_cpu0_ic_sample_spr; + input [4:0] ds_cpu0_ic_cpsr_mode; + input ds_cpu0_ic_aa64naa32; + input ds_cpu0_ic_hcr_change; + input ds_cpu0_ic_scr_change; +// BEGIN INCLUDE FOR CPU1 + input ds_cpu1_ic_sample_spr; + input [4:0] ds_cpu1_ic_cpsr_mode; + input ds_cpu1_ic_aa64naa32; + input ds_cpu1_ic_hcr_change; + input ds_cpu1_ic_scr_change; + input ls_cpu1_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu1_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu1_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu1_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu1_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu1_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input ds_cpu2_ic_sample_spr; + input [4:0] ds_cpu2_ic_cpsr_mode; + input ds_cpu2_ic_aa64naa32; + input ds_cpu2_ic_hcr_change; + input ds_cpu2_ic_scr_change; + input ls_cpu2_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu2_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu2_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu2_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu2_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu2_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input ds_cpu3_ic_sample_spr; + input [4:0] ds_cpu3_ic_cpsr_mode; + input ds_cpu3_ic_aa64naa32; + input ds_cpu3_ic_hcr_change; + input ds_cpu3_ic_scr_change; + input ls_cpu3_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu3_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu3_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu3_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu3_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu3_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU3 + + output [`MAIA_CN:0] ic_nfiq; // IC physical FIQ + output [`MAIA_CN:0] ic_nirq; // IC physical IRQ + output [`MAIA_CN:0] ic_nsei; // IC physical SEI + output [`MAIA_CN:0] ic_nvfiq; // IC virtual FIQ + output [`MAIA_CN:0] ic_nvirq; // IC virtual IRQ + output [`MAIA_CN:0] ic_nvsei; // IC virtual SEI + output [`MAIA_CN:0] ic_p_valid; // IC is present + + output [`MAIA_CN:0] ic_sample_spr; // IC sample signal for TC, TALL*, EL* signals + output [`MAIA_CN:0] ic_hcr_change_complete; + output [`MAIA_CN:0] ic_scr_change_complete; + output [`MAIA_CN:0] ic_el_change_complete; + output [`MAIA_CN:0] ic_ich_el2_tc; // IC trap common + output [`MAIA_CN:0] ic_ich_el2_tall0; // IC trap all grp0 + output [`MAIA_CN:0] ic_ich_el2_tall1; // IC trap all grp1 + output [`MAIA_CN:0] ic_sra_el3_en; // IC System Registers enabled in EL3 + output [`MAIA_CN:0] ic_sra_el1s_en; // IC System Registers enabled in EL1S + output [`MAIA_CN:0] ic_sra_el2_en; // IC System Registers enabled in EL2 + output [`MAIA_CN:0] ic_sra_el1ns_en; // IC System Registers enabled in EL1NS + output [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; // IC HYP_TRAP EL1NS accesses + output [`MAIA_CN:0] ic_sre_el1ns_mon_trap; // IC MON_TRAP EL1NS accesses + output [`MAIA_CN:0] ic_sre_el1s_mon_trap; // IC MON_TRAP EL1S accesses + output [`MAIA_CN:0] ic_sre_el2_mon_trap; // IC MON_TRAP EL2 accesses + output [`MAIA_CN:0] ic_block_eoi_sgi_wr; // IC Block all EOI and SGI write accesses + +//----------------------------------------------------------------------------- +// DT interface +//----------------------------------------------------------------------------- +// BEGIN DT-CPU interface +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + output dt_cpu0_dbif_req_pclk; // Debug Interface Req + output dt_cpu0_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu0_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu0_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu0_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu0_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu0_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu0_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu0_edbgrq_pclk; // External Debug Request + output dt_cpu0_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu0_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu0_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu0_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu0_et_oslock_gclk; // ETM OS Lock + input dt_cpu0_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu0_halt_ack_gclk; // Core Halted + input dt_cpu0_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu0_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu0_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu0_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu0_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu0_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu0_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu0_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu0_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu0_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu0_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu0_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu0_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu0_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu0_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + output dt_cpu1_dbif_req_pclk; // Debug Interface Req + output dt_cpu1_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu1_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu1_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu1_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu1_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu1_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu1_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu1_edbgrq_pclk; // External Debug Request + output dt_cpu1_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu1_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu1_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu1_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu1_et_oslock_gclk; // ETM OS Lock + input dt_cpu1_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu1_halt_ack_gclk; // Core Halted + input dt_cpu1_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu1_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu1_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu1_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu1_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu1_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu1_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu1_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu1_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu1_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu1_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu1_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu1_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu1_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu1_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + output dt_cpu2_dbif_req_pclk; // Debug Interface Req + output dt_cpu2_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu2_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu2_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu2_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu2_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu2_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu2_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu2_edbgrq_pclk; // External Debug Request + output dt_cpu2_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu2_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu2_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu2_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu2_et_oslock_gclk; // ETM OS Lock + input dt_cpu2_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu2_halt_ack_gclk; // Core Halted + input dt_cpu2_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu2_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu2_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu2_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu2_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu2_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu2_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu2_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu2_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu2_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu2_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu2_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu2_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu2_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu2_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + output dt_cpu3_dbif_req_pclk; // Debug Interface Req + output dt_cpu3_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu3_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu3_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu3_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu3_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu3_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu3_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu3_edbgrq_pclk; // External Debug Request + output dt_cpu3_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu3_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu3_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu3_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu3_et_oslock_gclk; // ETM OS Lock + input dt_cpu3_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu3_halt_ack_gclk; // Core Halted + input dt_cpu3_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu3_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu3_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu3_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu3_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu3_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu3_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu3_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu3_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu3_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu3_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu3_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu3_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu3_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu3_noclkstop_pclk; // force CPU clock on from DT-PCLK +// END DT-CPU interface + +//----------------------------------------------------------------------------- +// CK interface +//----------------------------------------------------------------------------- +// BEGIN CK-CPU interface + input ds_cpu0_reset_req; // Warm Reset request + input ds_cpu0_wfi_req; // WFI request + input ds_cpu0_wfe_req; // WFI request + input ds_cpu0_flush; // flush for exception rtn + input [5:0] ds_cpu0_flush_type; // flush type + input ds_cpu0_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu0_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu0_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu0_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu0_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu0_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu0_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu0_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu0_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu0_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu0_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu0_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu0_hcr_va; // virtual abort + input ds_cpu0_hcr_vi; // virtual IRQ + input ds_cpu0_hcr_vf; // virtual FIQ + input [2:0] ds_cpu0_cpuectlr_ret; // CPU Retention control + output ck_cpu0_event_reg; // WFE event reg + output ck_cpu0_wfi_ack; // WFI acknowledge to DS + output ck_cpu0_wfe_ack; // WFE acknowledge to DS + output ck_cpu0_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu1_reset_req; // Warm Reset request + input ds_cpu1_wfi_req; // WFI request + input ds_cpu1_wfe_req; // WFI request + input ds_cpu1_flush; // flush for exception rtn + input [5:0] ds_cpu1_flush_type; // flush type + input ds_cpu1_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu1_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu1_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu1_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu1_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu1_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu1_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu1_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu1_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu1_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu1_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu1_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu1_hcr_va; // virtual abort + input ds_cpu1_hcr_vi; // virtual IRQ + input ds_cpu1_hcr_vf; // virtual FIQ + input [2:0] ds_cpu1_cpuectlr_ret; // CPU Retention control + output ck_cpu1_event_reg; // WFE event reg + output ck_cpu1_wfi_ack; // WFI acknowledge to DS + output ck_cpu1_wfe_ack; // WFE acknowledge to DS + output ck_cpu1_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu2_reset_req; // Warm Reset request + input ds_cpu2_wfi_req; // WFI request + input ds_cpu2_wfe_req; // WFI request + input ds_cpu2_flush; // flush for exception rtn + input [5:0] ds_cpu2_flush_type; // flush type + input ds_cpu2_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu2_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu2_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu2_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu2_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu2_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu2_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu2_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu2_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu2_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu2_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu2_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu2_hcr_va; // virtual abort + input ds_cpu2_hcr_vi; // virtual IRQ + input ds_cpu2_hcr_vf; // virtual FIQ + input [2:0] ds_cpu2_cpuectlr_ret; // CPU Retention control + output ck_cpu2_event_reg; // WFE event reg + output ck_cpu2_wfi_ack; // WFI acknowledge to DS + output ck_cpu2_wfe_ack; // WFE acknowledge to DS + output ck_cpu2_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu3_reset_req; // Warm Reset request + input ds_cpu3_wfi_req; // WFI request + input ds_cpu3_wfe_req; // WFI request + input ds_cpu3_flush; // flush for exception rtn + input [5:0] ds_cpu3_flush_type; // flush type + input ds_cpu3_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu3_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu3_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu3_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu3_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu3_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu3_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu3_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu3_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu3_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu3_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu3_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu3_hcr_va; // virtual abort + input ds_cpu3_hcr_vi; // virtual IRQ + input ds_cpu3_hcr_vf; // virtual FIQ + input [2:0] ds_cpu3_cpuectlr_ret; // CPU Retention control + output ck_cpu3_event_reg; // WFE event reg + output ck_cpu3_wfi_ack; // WFI acknowledge to DS + output ck_cpu3_wfe_ack; // WFE acknowledge to DS + output ck_cpu3_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ls_cpu0_clrexmon; // LS global exclusive monitor + input ls_cpu1_clrexmon; // LS global exclusive monitor + input ls_cpu2_clrexmon; // LS global exclusive monitor + input ls_cpu3_clrexmon; // LS global exclusive monitor + +// END CK-CPU interface + + output [`MAIA_CN:0] ck_gclkt; + + + + // wires + wire STANDBYWFIL2; + wire ck_areset_l2; + wire ck_cpu0_areset_l2cpu; + wire ck_cpu0_areset_l2dt; + wire ck_cpu0_commrx; + wire ck_cpu0_commtx; + wire ck_cpu0_crcx_clk_en_n_ic; + wire ck_cpu0_dbgnopwrdwn; + wire ck_cpu0_dbgrstreq; + wire ck_cpu0_dt_standbywfx; + wire ck_cpu0_dt_wfx_ack; + wire ck_cpu0_l2_standbywfi; + wire ck_cpu0_l2_standbywfx; + wire ck_cpu0_ncommirq; + wire ck_cpu0_npmuirq; + wire ck_cpu0_poreset_status; + wire ck_cpu0_reset1_n_l2cpu; + wire ck_cpu0_reset1_n_l2dt; + wire ck_cpu1_areset_l2cpu; + wire ck_cpu1_areset_l2dt; + wire ck_cpu1_commrx; + wire ck_cpu1_commtx; + wire ck_cpu1_crcx_clk_en_n_ic; + wire ck_cpu1_dbgnopwrdwn; + wire ck_cpu1_dbgrstreq; + wire ck_cpu1_dt_standbywfx; + wire ck_cpu1_dt_wfx_ack; + wire ck_cpu1_l2_standbywfi; + wire ck_cpu1_l2_standbywfx; + wire ck_cpu1_ncommirq; + wire ck_cpu1_npmuirq; + wire ck_cpu1_poreset_status; + wire ck_cpu1_reset1_n_l2cpu; + wire ck_cpu1_reset1_n_l2dt; + wire ck_cpu2_areset_l2cpu; + wire ck_cpu2_areset_l2dt; + wire ck_cpu2_commrx; + wire ck_cpu2_commtx; + wire ck_cpu2_crcx_clk_en_n_ic; + wire ck_cpu2_dbgnopwrdwn; + wire ck_cpu2_dbgrstreq; + wire ck_cpu2_dt_standbywfx; + wire ck_cpu2_dt_wfx_ack; + wire ck_cpu2_l2_standbywfi; + wire ck_cpu2_l2_standbywfx; + wire ck_cpu2_ncommirq; + wire ck_cpu2_npmuirq; + wire ck_cpu2_poreset_status; + wire ck_cpu2_reset1_n_l2cpu; + wire ck_cpu2_reset1_n_l2dt; + wire ck_cpu3_areset_l2cpu; + wire ck_cpu3_areset_l2dt; + wire ck_cpu3_commrx; + wire ck_cpu3_commtx; + wire ck_cpu3_crcx_clk_en_n_ic; + wire ck_cpu3_dbgnopwrdwn; + wire ck_cpu3_dbgrstreq; + wire ck_cpu3_dt_standbywfx; + wire ck_cpu3_dt_wfx_ack; + wire ck_cpu3_l2_standbywfi; + wire ck_cpu3_l2_standbywfx; + wire ck_cpu3_ncommirq; + wire ck_cpu3_npmuirq; + wire ck_cpu3_poreset_status; + wire ck_cpu3_reset1_n_l2cpu; + wire ck_cpu3_reset1_n_l2dt; + wire ck_dt_cpu0_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu0_cti_trigin_1to0_gclk; + wire ck_dt_cpu0_et_oslock_gclk; + wire ck_dt_cpu0_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu0_os_double_lock_gclk; + wire ck_dt_cpu0_pmusnapshot_ack_gclk; + wire ck_dt_cpu0_wfx_dbg_req_gclk; + wire ck_dt_cpu1_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu1_cti_trigin_1to0_gclk; + wire ck_dt_cpu1_et_oslock_gclk; + wire ck_dt_cpu1_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu1_os_double_lock_gclk; + wire ck_dt_cpu1_pmusnapshot_ack_gclk; + wire ck_dt_cpu1_wfx_dbg_req_gclk; + wire ck_dt_cpu2_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu2_cti_trigin_1to0_gclk; + wire ck_dt_cpu2_et_oslock_gclk; + wire ck_dt_cpu2_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu2_os_double_lock_gclk; + wire ck_dt_cpu2_pmusnapshot_ack_gclk; + wire ck_dt_cpu2_wfx_dbg_req_gclk; + wire ck_dt_cpu3_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu3_cti_trigin_1to0_gclk; + wire ck_dt_cpu3_et_oslock_gclk; + wire ck_dt_cpu3_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu3_os_double_lock_gclk; + wire ck_dt_cpu3_pmusnapshot_ack_gclk; + wire ck_dt_cpu3_wfx_dbg_req_gclk; + wire ck_gclkb0; + wire ck_gclkb1; + wire ck_gclkfr; + wire ck_gclkl2; + wire ck_gclktl2; + wire ck_l2_ace_inactive; + wire ck_l2_acp_inactive; + wire ck_l2_logic_clk_en; + wire ck_l2_sky_link_deactivate; + wire ck_l2_tbnk0_clk_en; + wire ck_l2_tbnk1_clk_en; + wire ck_reset1_n_l2; + wire clrexmon_c1; + wire ds_cpu0_ic_aa64naa32_i; + wire [4:0] ds_cpu0_ic_cpsr_mode_i; + wire ds_cpu0_ic_hcr_change_i; + wire ds_cpu0_ic_sample_spr_i; + wire ds_cpu0_ic_scr_change_i; + wire ds_cpu1_ic_aa64naa32_i; + wire [4:0] ds_cpu1_ic_cpsr_mode_i; + wire ds_cpu1_ic_hcr_change_i; + wire ds_cpu1_ic_sample_spr_i; + wire ds_cpu1_ic_scr_change_i; + wire ds_cpu2_ic_aa64naa32_i; + wire [4:0] ds_cpu2_ic_cpsr_mode_i; + wire ds_cpu2_ic_hcr_change_i; + wire ds_cpu2_ic_sample_spr_i; + wire ds_cpu2_ic_scr_change_i; + wire ds_cpu3_ic_aa64naa32_i; + wire [4:0] ds_cpu3_ic_cpsr_mode_i; + wire ds_cpu3_ic_hcr_change_i; + wire ds_cpu3_ic_sample_spr_i; + wire ds_cpu3_ic_scr_change_i; + wire dt_cpu0_apb_active_pclk; + wire dt_cpu0_poreset_status_ack_pclk; + wire dt_cpu0_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu0_wfx_wakeup_pclk; + wire dt_cpu1_apb_active_pclk; + wire dt_cpu1_poreset_status_ack_pclk; + wire dt_cpu1_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu1_wfx_wakeup_pclk; + wire dt_cpu2_apb_active_pclk; + wire dt_cpu2_poreset_status_ack_pclk; + wire dt_cpu2_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu2_wfx_wakeup_pclk; + wire dt_cpu3_apb_active_pclk; + wire dt_cpu3_poreset_status_ack_pclk; + wire dt_cpu3_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu3_wfx_wakeup_pclk; + wire eventi_sev; + wire [`MAIA_CN:0] ic_block_eoi_sgi_wr_o; + wire ic_cpu0_l2_dsb_block; + wire [63:0] ic_cpu0_spr_rd_data; + wire ic_cpu1_l2_dsb_block; + wire [63:0] ic_cpu1_spr_rd_data; + wire ic_cpu2_l2_dsb_block; + wire [63:0] ic_cpu2_spr_rd_data; + wire ic_cpu3_l2_dsb_block; + wire [63:0] ic_cpu3_spr_rd_data; + wire [`MAIA_CN:0] ic_el_change_complete_o; + wire [`MAIA_CN:0] ic_hcr_change_complete_o; + wire [`MAIA_CN:0] ic_ich_el2_tall0_o; + wire [`MAIA_CN:0] ic_ich_el2_tall1_o; + wire [`MAIA_CN:0] ic_ich_el2_tc_o; + wire [`MAIA_CN:0] ic_nfiq_o; + wire [`MAIA_CN:0] ic_nirq_o; + wire [`MAIA_CN:0] ic_nsei_o; + wire [`MAIA_CN:0] ic_nvfiq_o; + wire [`MAIA_CN:0] ic_nvirq_o; + wire [`MAIA_CN:0] ic_nvsei_o; + wire [31:0] ic_p_rdata; + wire ic_p_rdata_valid; + wire ic_p_ready; + wire [`MAIA_CN:0] ic_sample_spr_o; + wire [`MAIA_CN:0] ic_scr_change_complete_o; + wire [`MAIA_CN:0] ic_sra_el1ns_en_o; + wire [`MAIA_CN:0] ic_sra_el1s_en_o; + wire [`MAIA_CN:0] ic_sra_el2_en_o; + wire [`MAIA_CN:0] ic_sra_el3_en_o; + wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap_o; + wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap_o; + wire [`MAIA_CN:0] ic_sre_el1s_mon_trap_o; + wire [`MAIA_CN:0] ic_sre_el2_mon_trap_o; + wire l2_acp_flsh_rd_cnt_active_glb_l2_dly; + wire l2_acp_flsh_wr_cnt_active_glb_l2_dly; + wire l2_acp_rd_haz_vld_l2_dly_q; + wire l2_acp_wr_haz_vld_l2_dly_q; + wire l2_actlr_disable_b2b_setway_hzd_opt_x2_ns; + wire l2_actlr_disable_setway_opt; + wire l2_actlr_ncpu_rcg_enable; + wire l2_actlr_plru_dynamic; + wire l2_actlr_plru_en; + wire [1:0] l2_actlr_plru_mode; + wire l2_actlr_writeunique_disable; + wire l2_cfg_broadcastinner; + wire l2_cfg_broadcastouter; + wire l2_cpu0_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu0_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu0_snp_active; + wire l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_wr_decerr_q; + wire l2_cpu0_wr_slverr_q; + wire l2_cpu1_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu1_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu1_snp_active; + wire l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_wr_decerr_q; + wire l2_cpu1_wr_slverr_q; + wire l2_cpu2_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu2_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu2_snp_active; + wire l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_wr_decerr_q; + wire l2_cpu2_wr_slverr_q; + wire l2_cpu3_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu3_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu3_snp_active; + wire l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_wr_decerr_q; + wire l2_cpu3_wr_slverr_q; + wire l2_ctlr_x1_wr_q; + wire [9:0] l2_ctlr_x2_ns; + wire l2_idle; + wire [`MAIA_CN:0] l2_mbist1_en_b1; + wire [16:0] l2_mbist2_tbnk0_addr_b1; + wire l2_mbist2_tbnk0_all_b1; + wire [2:0] l2_mbist2_tbnk0_array_b1; + wire [17:0] l2_mbist2_tbnk0_be_b1; + wire l2_mbist2_tbnk0_en_b1; + wire [143:0] l2_mbist2_tbnk0_indata_b1; + wire [143:0] l2_mbist2_tbnk0_outdata_b3; + wire l2_mbist2_tbnk0_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp0_outdata_b2; + wire l2_mbist2_tbnk0_snp0_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp0_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp1_outdata_b2; + wire l2_mbist2_tbnk0_snp1_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp1_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp2_outdata_b2; + wire l2_mbist2_tbnk0_snp2_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp2_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp3_outdata_b2; + wire l2_mbist2_tbnk0_snp3_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp3_sel_b1; + wire l2_mbist2_tbnk0_wr_en_b1; + wire [16:0] l2_mbist2_tbnk1_addr_b1; + wire l2_mbist2_tbnk1_all_b1; + wire [2:0] l2_mbist2_tbnk1_array_b1; + wire [17:0] l2_mbist2_tbnk1_be_b1; + wire l2_mbist2_tbnk1_en_b1; + wire [143:0] l2_mbist2_tbnk1_indata_b1; + wire [143:0] l2_mbist2_tbnk1_outdata_b3; + wire l2_mbist2_tbnk1_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp0_outdata_b2; + wire l2_mbist2_tbnk1_snp0_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp0_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp1_outdata_b2; + wire l2_mbist2_tbnk1_snp1_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp1_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp2_outdata_b2; + wire l2_mbist2_tbnk1_snp2_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp2_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp3_outdata_b2; + wire l2_mbist2_tbnk1_snp3_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp3_sel_b1; + wire l2_mbist2_tbnk1_wr_en_b1; + wire l2_no_ram_acc_nxt_cycle; + wire [13:0] l2_p_addr; + wire [1:0] l2_p_cpu; + wire l2_p_nsecure; + wire [2:0] l2_p_sel; + wire [31:0] l2_p_wdata; + wire l2_p_write; + wire l2_reset3; + wire l2_rstdisable_x1_q; + wire l2_tbnk0_addr44_l3_q; + wire [44:0] l2_tbnk0_addr_l1; + wire [5:2] l2_tbnk0_addr_l6; + wire l2_tbnk0_all_tag_incl_active_l3; + wire l2_tbnk0_asq_cmp_evict_l3_q; + wire l2_tbnk0_asq_full_flsh; + wire l2_tbnk0_asq_nc_so_dev_limit; + wire [2:0] l2_tbnk0_cache_attr_l1; + wire l2_tbnk0_cfg_ecc_en; + wire l2_tbnk0_cmo_setway_l2_inv_incl_l4; + wire l2_tbnk0_cpu0_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu0_hit_l4; + wire l2_tbnk0_cpu0_l2_inv_l4_dly2; + wire l2_tbnk0_cpu0_l2hit_e_l4; + wire l2_tbnk0_cpu0_l2hit_s_l4; + wire l2_tbnk0_cpu0_peq_full_q; + wire l2_tbnk0_cpu0_peq_hit_q; + wire l2_tbnk0_cpu0_peq_self_evict_l3_q; + wire l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu0_rd_access_l4_dly; + wire l2_tbnk0_cpu0_self_evict_l4_dly_q; + wire l2_tbnk0_cpu0_single_ecc_err_l7_q; + wire l2_tbnk0_cpu0_snp_hit_e_l3; + wire l2_tbnk0_cpu0_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu0_snp_setway_addr_l3; + wire l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu0_vld_nxt_l5; + wire l2_tbnk0_cpu0_wr_access_l4_dly; + wire l2_tbnk0_cpu1_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu1_hit_l4; + wire l2_tbnk0_cpu1_l2_inv_l4_dly2; + wire l2_tbnk0_cpu1_l2hit_e_l4; + wire l2_tbnk0_cpu1_l2hit_s_l4; + wire l2_tbnk0_cpu1_peq_full_q; + wire l2_tbnk0_cpu1_peq_hit_q; + wire l2_tbnk0_cpu1_peq_self_evict_l3_q; + wire l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu1_rd_access_l4_dly; + wire l2_tbnk0_cpu1_self_evict_l4_dly_q; + wire l2_tbnk0_cpu1_single_ecc_err_l7_q; + wire l2_tbnk0_cpu1_snp_hit_e_l3; + wire l2_tbnk0_cpu1_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu1_snp_setway_addr_l3; + wire l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu1_vld_nxt_l5; + wire l2_tbnk0_cpu1_wr_access_l4_dly; + wire l2_tbnk0_cpu2_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu2_hit_l4; + wire l2_tbnk0_cpu2_l2_inv_l4_dly2; + wire l2_tbnk0_cpu2_l2hit_e_l4; + wire l2_tbnk0_cpu2_l2hit_s_l4; + wire l2_tbnk0_cpu2_peq_full_q; + wire l2_tbnk0_cpu2_peq_hit_q; + wire l2_tbnk0_cpu2_peq_self_evict_l3_q; + wire l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu2_rd_access_l4_dly; + wire l2_tbnk0_cpu2_self_evict_l4_dly_q; + wire l2_tbnk0_cpu2_single_ecc_err_l7_q; + wire l2_tbnk0_cpu2_snp_hit_e_l3; + wire l2_tbnk0_cpu2_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu2_snp_setway_addr_l3; + wire l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu2_vld_nxt_l5; + wire l2_tbnk0_cpu2_wr_access_l4_dly; + wire l2_tbnk0_cpu3_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu3_hit_l4; + wire l2_tbnk0_cpu3_l2_inv_l4_dly2; + wire l2_tbnk0_cpu3_l2hit_e_l4; + wire l2_tbnk0_cpu3_l2hit_s_l4; + wire l2_tbnk0_cpu3_peq_full_q; + wire l2_tbnk0_cpu3_peq_hit_q; + wire l2_tbnk0_cpu3_peq_self_evict_l3_q; + wire l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu3_rd_access_l4_dly; + wire l2_tbnk0_cpu3_self_evict_l4_dly_q; + wire l2_tbnk0_cpu3_single_ecc_err_l7_q; + wire l2_tbnk0_cpu3_snp_hit_e_l3; + wire l2_tbnk0_cpu3_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu3_snp_setway_addr_l3; + wire l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu3_vld_nxt_l5; + wire l2_tbnk0_cpu3_wr_access_l4_dly; + wire [3:0] l2_tbnk0_cpu_rvalid_init_nxt_l5; + wire [3:0] l2_tbnk0_cpu_rvalid_nxt_l5; + wire [3:0] l2_tbnk0_cpu_snp_hit_e_l4_q; + wire l2_tbnk0_crit_qw_nxt_l5; + wire [143:0] l2_tbnk0_data_corrected_l7_q; + wire [127:0] l2_tbnk0_data_l6; + wire l2_tbnk0_dbg_ram_acc_l5a; + wire [2:0] l2_tbnk0_dbg_ram_acc_unit_nxt; + wire [7:0] l2_tbnk0_dbg_ram_id_nxt_l5; + wire l2_tbnk0_dirty_l1; + wire l2_tbnk0_dirty_l3_q; + wire l2_tbnk0_dis_ns_dbg_arr_acc_x2; + wire l2_tbnk0_double_ecc_err_l7_q; + wire l2_tbnk0_early_rvalid_l4_q; + wire l2_tbnk0_ecc_fixup_blk_arb; + wire l2_tbnk0_ecc_fixup_inprog_dly_q; + wire l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q; + wire [31:0] l2_tbnk0_ecc_syndrome_reg_q; + wire l2_tbnk0_evict_special_hazard_l3_q; + wire l2_tbnk0_evict_special_hazard_rwvic_l3_q; + wire l2_tbnk0_excl_l1; + wire l2_tbnk0_excl_l4_q; + wire [44:6] l2_tbnk0_feq_addr_upd; + wire l2_tbnk0_feq_alloc_failed_l4; + wire l2_tbnk0_feq_axi_wr_vld_not_popped; + wire l2_tbnk0_feq_clr_l4; + wire [15:0] l2_tbnk0_feq_frc_incl_l3a; + wire l2_tbnk0_feq_kill_l3; + wire [4:0] l2_tbnk0_feq_last_id_q; + wire l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3; + wire l2_tbnk0_feq_tbnk_id_update_or_l3; + wire l2_tbnk0_full_miss_l4_q; + wire l2_tbnk0_hit_l4; + wire l2_tbnk0_hit_l7_q; + wire [3:0] l2_tbnk0_hit_way_l4_q; + wire [9:0] l2_tbnk0_id_l1; + wire [9:0] l2_tbnk0_id_l6_q; + wire [9:0] l2_tbnk0_id_nxt_l5; + wire l2_tbnk0_idle; + wire l2_tbnk0_init_req_l1; + wire l2_tbnk0_kill_l2; + wire l2_tbnk0_l2bb_fake_wr_l1; + wire l2_tbnk0_l2bb_wr_l1; + wire l2_tbnk0_l2hit_e_l4; + wire l2_tbnk0_l2hit_s_l4; + wire l2_tbnk0_l2v_s_q; + wire l2_tbnk0_l2v_vld_q; + wire l2_tbnk0_last_qw_l1; + wire l2_tbnk0_last_qw_l6_q; + wire l2_tbnk0_last_qw_nxt_l5; + wire [2:0] l2_tbnk0_lock_l1; + wire [2:0] l2_tbnk0_lock_l4; + wire [32:0] l2_tbnk0_merrsr_data; + wire [9:0] l2_tbnk0_page_attr_l1; + wire l2_tbnk0_partial_dw_wr_l1; + wire l2_tbnk0_pf_cnt_dec_l4_dly; + wire l2_tbnk0_pf_hazard_l3; + wire l2_tbnk0_pf_req_sel_for_fwd_l4; + wire l2_tbnk0_prfm_l1; + wire l2_tbnk0_prfm_nxt_l5; + wire [3:0] l2_tbnk0_prot_l1; + wire [3:0] l2_tbnk0_prot_l4_q; + wire [1:0] l2_tbnk0_qw_cnt_l1; + wire [1:0] l2_tbnk0_qw_cnt_l3_q; + wire l2_tbnk0_raw_hit_l4_q; + wire [2:0] l2_tbnk0_rbufid_nxt_l5; + wire l2_tbnk0_rd_en_nxt_l5; + wire l2_tbnk0_rd_fail_hazchk_feq_l3; + wire l2_tbnk0_rwvic_axi_read_err_l1; + wire l2_tbnk0_rwvic_axi_read_err_l3_q; + wire l2_tbnk0_rwvic_ccb_dirty_l6_q; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l1; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l3_q; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l6_q; + wire [3:0] l2_tbnk0_rwvic_ccb_way_l1; + wire l2_tbnk0_rwvic_cmo_clean_l1; + wire l2_tbnk0_rwvic_cmo_inv_l1; + wire l2_tbnk0_rwvic_cmo_inv_l7_q; + wire l2_tbnk0_rwvic_cmo_l7_q; + wire l2_tbnk0_rwvic_cmo_pou_l1; + wire l2_tbnk0_rwvic_cmo_pou_l6_q; + wire l2_tbnk0_rwvic_cmo_setway_l1; + wire l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1; + wire l2_tbnk0_rwvic_cmo_setway_ls_l6_q; + wire [2:0] l2_tbnk0_rwvic_cpu_fb_id_l1; + wire [3:0] l2_tbnk0_rwvic_cpu_id_dcd_l1; + wire l2_tbnk0_rwvic_ddi_l6_q; + wire l2_tbnk0_rwvic_feq_cmp_l3_q; + wire l2_tbnk0_rwvic_frc_l2hit_fwd_l1; + wire l2_tbnk0_rwvic_l2hit_e_l1; + wire l2_tbnk0_rwvic_l2hit_e_l3_q; + wire l2_tbnk0_rwvic_l2hit_e_l7_q; + wire l2_tbnk0_rwvic_l2v_dirty_l7_q; + wire [3:0] l2_tbnk0_rwvic_l2v_page_attr_l7_q; + wire l2_tbnk0_rwvic_l2v_vld_l6_q; + wire l2_tbnk0_rwvic_mesi_sh_l1; + wire l2_tbnk0_rwvic_non_snp_fail_hazchk_l3; + wire [2:0] l2_tbnk0_rwvic_owner_l1; + wire [2:0] l2_tbnk0_rwvic_owner_l7_q; + wire l2_tbnk0_rwvic_rd_type_l6_q; + wire l2_tbnk0_rwvic_snp_clr_dirty_l1; + wire l2_tbnk0_rwvic_snp_inv_l1; + wire l2_tbnk0_rwvic_snp_l1; + wire l2_tbnk0_rwvic_snp_l3_q; + wire l2_tbnk0_rwvic_snp_l6_q; + wire l2_tbnk0_rwvic_tag_wr_l0; + wire [3:0] l2_tbnk0_rwvic_type_l1; + wire l2_tbnk0_rwvic_wa_l1; + wire l2_tbnk0_rwvic_wa_l6_q; + wire [13:0] l2_tbnk0_sel_l1; + wire [2:0] l2_tbnk0_size_l1; + wire [2:0] l2_tbnk0_size_l4_q; + wire l2_tbnk0_snp_byp_peq_haz_pending_q; + wire l2_tbnk0_snp_dvm_cmpl_l1; + wire l2_tbnk0_snp_hit_e_l4_q; + wire l2_tbnk0_snp_hit_feq_evict_l4_dly; + wire l2_tbnk0_snp_hit_s_l4_q; + wire [4:0] l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q; + wire [7:0] l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q; + wire [7:0] l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q; + wire [44:7] l2_tbnk0_snp_tag_wr_l2_hit_addr_l1; + wire [1:0] l2_tbnk0_snp_tag_wr_l2_hit_state_l1; + wire l2_tbnk0_snp_tag_wr_l2_hit_way_l1; + wire l2_tbnk0_special_evict_hazard_l3; + wire l2_tbnk0_special_hazard_l3_q; + wire l2_tbnk0_sync_l1; + wire l2_tbnk0_tag_ecc_dbl_rmw_wr_l1; + wire l2_tbnk0_tag_ecc_err_cpu0_l4; + wire l2_tbnk0_tag_ecc_err_cpu1_l4; + wire l2_tbnk0_tag_ecc_err_cpu2_l4; + wire l2_tbnk0_tag_ecc_err_cpu3_l4; + wire l2_tbnk0_tag_ecc_err_l4; + wire [6:0] l2_tbnk0_type_l1; + wire [1:0] l2_tbnk0_ulen_l1; + wire [1:0] l2_tbnk0_ulen_l4_q; + wire l2_tbnk0_vld_init_l6_q; + wire l2_tbnk0_vld_l6_q; + wire l2_tbnk0_way_l1; + wire l2_tbnk0_way_l4_q; + wire l2_tbnk0_way_nxt_l3a; + wire [143:0] l2_tbnk0_wr_data_l3; + wire [127:0] l2_tbnk0_wr_data_l3a_q; + wire l2_tbnk0_wr_data_l4_en; + wire l2_tbnk0_wr_err_l1; + wire l2_tbnk0_wr_fail_feq_full_l3; + wire l2_tbnk0_wr_fail_hazchk_feq_l3; + wire [11:0] l2_tbnk0_wr_non_crit_id_l1; + wire [11:0] l2_tbnk0_wr_non_crit_id_l4_q; + wire [15:0] l2_tbnk0_wr_strb_mask_l3a_q; + wire l2_tbnk1_addr44_l3_q; + wire [44:0] l2_tbnk1_addr_l1; + wire [5:2] l2_tbnk1_addr_l6; + wire l2_tbnk1_all_tag_incl_active_l3; + wire l2_tbnk1_asq_cmp_evict_l3_q; + wire l2_tbnk1_asq_full_flsh; + wire l2_tbnk1_asq_nc_so_dev_limit; + wire [2:0] l2_tbnk1_cache_attr_l1; + wire l2_tbnk1_cfg_ecc_en; + wire l2_tbnk1_cmo_setway_l2_inv_incl_l4; + wire l2_tbnk1_cpu0_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu0_hit_l4; + wire l2_tbnk1_cpu0_l2_inv_l4_dly2; + wire l2_tbnk1_cpu0_l2hit_e_l4; + wire l2_tbnk1_cpu0_l2hit_s_l4; + wire l2_tbnk1_cpu0_peq_full_q; + wire l2_tbnk1_cpu0_peq_hit_q; + wire l2_tbnk1_cpu0_peq_self_evict_l3_q; + wire l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu0_rd_access_l4_dly; + wire l2_tbnk1_cpu0_self_evict_l4_dly_q; + wire l2_tbnk1_cpu0_single_ecc_err_l7_q; + wire l2_tbnk1_cpu0_snp_hit_e_l3; + wire l2_tbnk1_cpu0_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu0_snp_setway_addr_l3; + wire l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu0_vld_nxt_l5; + wire l2_tbnk1_cpu0_wr_access_l4_dly; + wire l2_tbnk1_cpu1_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu1_hit_l4; + wire l2_tbnk1_cpu1_l2_inv_l4_dly2; + wire l2_tbnk1_cpu1_l2hit_e_l4; + wire l2_tbnk1_cpu1_l2hit_s_l4; + wire l2_tbnk1_cpu1_peq_full_q; + wire l2_tbnk1_cpu1_peq_hit_q; + wire l2_tbnk1_cpu1_peq_self_evict_l3_q; + wire l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu1_rd_access_l4_dly; + wire l2_tbnk1_cpu1_self_evict_l4_dly_q; + wire l2_tbnk1_cpu1_single_ecc_err_l7_q; + wire l2_tbnk1_cpu1_snp_hit_e_l3; + wire l2_tbnk1_cpu1_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu1_snp_setway_addr_l3; + wire l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu1_vld_nxt_l5; + wire l2_tbnk1_cpu1_wr_access_l4_dly; + wire l2_tbnk1_cpu2_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu2_hit_l4; + wire l2_tbnk1_cpu2_l2_inv_l4_dly2; + wire l2_tbnk1_cpu2_l2hit_e_l4; + wire l2_tbnk1_cpu2_l2hit_s_l4; + wire l2_tbnk1_cpu2_peq_full_q; + wire l2_tbnk1_cpu2_peq_hit_q; + wire l2_tbnk1_cpu2_peq_self_evict_l3_q; + wire l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu2_rd_access_l4_dly; + wire l2_tbnk1_cpu2_self_evict_l4_dly_q; + wire l2_tbnk1_cpu2_single_ecc_err_l7_q; + wire l2_tbnk1_cpu2_snp_hit_e_l3; + wire l2_tbnk1_cpu2_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu2_snp_setway_addr_l3; + wire l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu2_vld_nxt_l5; + wire l2_tbnk1_cpu2_wr_access_l4_dly; + wire l2_tbnk1_cpu3_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu3_hit_l4; + wire l2_tbnk1_cpu3_l2_inv_l4_dly2; + wire l2_tbnk1_cpu3_l2hit_e_l4; + wire l2_tbnk1_cpu3_l2hit_s_l4; + wire l2_tbnk1_cpu3_peq_full_q; + wire l2_tbnk1_cpu3_peq_hit_q; + wire l2_tbnk1_cpu3_peq_self_evict_l3_q; + wire l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu3_rd_access_l4_dly; + wire l2_tbnk1_cpu3_self_evict_l4_dly_q; + wire l2_tbnk1_cpu3_single_ecc_err_l7_q; + wire l2_tbnk1_cpu3_snp_hit_e_l3; + wire l2_tbnk1_cpu3_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu3_snp_setway_addr_l3; + wire l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu3_vld_nxt_l5; + wire l2_tbnk1_cpu3_wr_access_l4_dly; + wire [3:0] l2_tbnk1_cpu_rvalid_init_nxt_l5; + wire [3:0] l2_tbnk1_cpu_rvalid_nxt_l5; + wire [3:0] l2_tbnk1_cpu_snp_hit_e_l4_q; + wire l2_tbnk1_crit_qw_nxt_l5; + wire [143:0] l2_tbnk1_data_corrected_l7_q; + wire [127:0] l2_tbnk1_data_l6; + wire l2_tbnk1_dbg_ram_acc_l5a; + wire [2:0] l2_tbnk1_dbg_ram_acc_unit_nxt; + wire [7:0] l2_tbnk1_dbg_ram_id_nxt_l5; + wire l2_tbnk1_dirty_l1; + wire l2_tbnk1_dirty_l3_q; + wire l2_tbnk1_dis_ns_dbg_arr_acc_x2; + wire l2_tbnk1_double_ecc_err_l7_q; + wire l2_tbnk1_early_rvalid_l4_q; + wire l2_tbnk1_ecc_fixup_blk_arb; + wire l2_tbnk1_ecc_fixup_inprog_dly_q; + wire l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q; + wire [31:0] l2_tbnk1_ecc_syndrome_reg_q; + wire l2_tbnk1_evict_special_hazard_l3_q; + wire l2_tbnk1_evict_special_hazard_rwvic_l3_q; + wire l2_tbnk1_excl_l1; + wire l2_tbnk1_excl_l4_q; + wire [44:6] l2_tbnk1_feq_addr_upd; + wire l2_tbnk1_feq_alloc_failed_l4; + wire l2_tbnk1_feq_axi_wr_vld_not_popped; + wire l2_tbnk1_feq_clr_l4; + wire [15:0] l2_tbnk1_feq_frc_incl_l3a; + wire l2_tbnk1_feq_kill_l3; + wire [4:0] l2_tbnk1_feq_last_id_q; + wire l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3; + wire l2_tbnk1_feq_tbnk_id_update_or_l3; + wire l2_tbnk1_full_miss_l4_q; + wire l2_tbnk1_hit_l4; + wire l2_tbnk1_hit_l7_q; + wire [3:0] l2_tbnk1_hit_way_l4_q; + wire [9:0] l2_tbnk1_id_l1; + wire [9:0] l2_tbnk1_id_l6_q; + wire [9:0] l2_tbnk1_id_nxt_l5; + wire l2_tbnk1_idle; + wire l2_tbnk1_init_req_l1; + wire l2_tbnk1_kill_l2; + wire l2_tbnk1_l2bb_fake_wr_l1; + wire l2_tbnk1_l2bb_wr_l1; + wire l2_tbnk1_l2hit_e_l4; + wire l2_tbnk1_l2hit_s_l4; + wire l2_tbnk1_l2v_s_q; + wire l2_tbnk1_l2v_vld_q; + wire l2_tbnk1_last_qw_l1; + wire l2_tbnk1_last_qw_l6_q; + wire l2_tbnk1_last_qw_nxt_l5; + wire [2:0] l2_tbnk1_lock_l1; + wire [2:0] l2_tbnk1_lock_l4; + wire [32:0] l2_tbnk1_merrsr_data; + wire [9:0] l2_tbnk1_page_attr_l1; + wire l2_tbnk1_partial_dw_wr_l1; + wire l2_tbnk1_pf_cnt_dec_l4_dly; + wire l2_tbnk1_pf_hazard_l3; + wire l2_tbnk1_pf_req_sel_for_fwd_l4; + wire l2_tbnk1_prfm_l1; + wire l2_tbnk1_prfm_nxt_l5; + wire [3:0] l2_tbnk1_prot_l1; + wire [3:0] l2_tbnk1_prot_l4_q; + wire [1:0] l2_tbnk1_qw_cnt_l1; + wire [1:0] l2_tbnk1_qw_cnt_l3_q; + wire l2_tbnk1_raw_hit_l4_q; + wire [2:0] l2_tbnk1_rbufid_nxt_l5; + wire l2_tbnk1_rd_en_nxt_l5; + wire l2_tbnk1_rd_fail_hazchk_feq_l3; + wire l2_tbnk1_rwvic_axi_read_err_l1; + wire l2_tbnk1_rwvic_axi_read_err_l3_q; + wire l2_tbnk1_rwvic_ccb_dirty_l6_q; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l1; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l3_q; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l6_q; + wire [3:0] l2_tbnk1_rwvic_ccb_way_l1; + wire l2_tbnk1_rwvic_cmo_clean_l1; + wire l2_tbnk1_rwvic_cmo_inv_l1; + wire l2_tbnk1_rwvic_cmo_inv_l7_q; + wire l2_tbnk1_rwvic_cmo_l7_q; + wire l2_tbnk1_rwvic_cmo_pou_l1; + wire l2_tbnk1_rwvic_cmo_pou_l6_q; + wire l2_tbnk1_rwvic_cmo_setway_l1; + wire l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1; + wire l2_tbnk1_rwvic_cmo_setway_ls_l6_q; + wire [2:0] l2_tbnk1_rwvic_cpu_fb_id_l1; + wire [3:0] l2_tbnk1_rwvic_cpu_id_dcd_l1; + wire l2_tbnk1_rwvic_ddi_l6_q; + wire l2_tbnk1_rwvic_feq_cmp_l3_q; + wire l2_tbnk1_rwvic_frc_l2hit_fwd_l1; + wire l2_tbnk1_rwvic_l2hit_e_l1; + wire l2_tbnk1_rwvic_l2hit_e_l3_q; + wire l2_tbnk1_rwvic_l2hit_e_l7_q; + wire l2_tbnk1_rwvic_l2v_dirty_l7_q; + wire [3:0] l2_tbnk1_rwvic_l2v_page_attr_l7_q; + wire l2_tbnk1_rwvic_l2v_vld_l6_q; + wire l2_tbnk1_rwvic_mesi_sh_l1; + wire l2_tbnk1_rwvic_non_snp_fail_hazchk_l3; + wire [2:0] l2_tbnk1_rwvic_owner_l1; + wire [2:0] l2_tbnk1_rwvic_owner_l7_q; + wire l2_tbnk1_rwvic_rd_type_l6_q; + wire l2_tbnk1_rwvic_snp_clr_dirty_l1; + wire l2_tbnk1_rwvic_snp_inv_l1; + wire l2_tbnk1_rwvic_snp_l1; + wire l2_tbnk1_rwvic_snp_l3_q; + wire l2_tbnk1_rwvic_snp_l6_q; + wire l2_tbnk1_rwvic_tag_wr_l0; + wire [3:0] l2_tbnk1_rwvic_type_l1; + wire l2_tbnk1_rwvic_wa_l1; + wire l2_tbnk1_rwvic_wa_l6_q; + wire [13:0] l2_tbnk1_sel_l1; + wire [2:0] l2_tbnk1_size_l1; + wire [2:0] l2_tbnk1_size_l4_q; + wire l2_tbnk1_snp_byp_peq_haz_pending_q; + wire l2_tbnk1_snp_dvm_cmpl_l1; + wire l2_tbnk1_snp_hit_e_l4_q; + wire l2_tbnk1_snp_hit_feq_evict_l4_dly; + wire l2_tbnk1_snp_hit_s_l4_q; + wire [4:0] l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q; + wire [7:0] l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q; + wire [7:0] l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q; + wire [44:7] l2_tbnk1_snp_tag_wr_l2_hit_addr_l1; + wire [1:0] l2_tbnk1_snp_tag_wr_l2_hit_state_l1; + wire l2_tbnk1_snp_tag_wr_l2_hit_way_l1; + wire l2_tbnk1_special_evict_hazard_l3; + wire l2_tbnk1_special_hazard_l3_q; + wire l2_tbnk1_sync_l1; + wire l2_tbnk1_tag_ecc_dbl_rmw_wr_l1; + wire l2_tbnk1_tag_ecc_err_cpu0_l4; + wire l2_tbnk1_tag_ecc_err_cpu1_l4; + wire l2_tbnk1_tag_ecc_err_cpu2_l4; + wire l2_tbnk1_tag_ecc_err_cpu3_l4; + wire l2_tbnk1_tag_ecc_err_l4; + wire [6:0] l2_tbnk1_type_l1; + wire [1:0] l2_tbnk1_ulen_l1; + wire [1:0] l2_tbnk1_ulen_l4_q; + wire l2_tbnk1_vld_init_l6_q; + wire l2_tbnk1_vld_l6_q; + wire l2_tbnk1_way_l1; + wire l2_tbnk1_way_l4_q; + wire l2_tbnk1_way_nxt_l3a; + wire [143:0] l2_tbnk1_wr_data_l3; + wire [127:0] l2_tbnk1_wr_data_l3a_q; + wire l2_tbnk1_wr_data_l4_en; + wire l2_tbnk1_wr_err_l1; + wire l2_tbnk1_wr_fail_feq_full_l3; + wire l2_tbnk1_wr_fail_hazchk_feq_l3; + wire [11:0] l2_tbnk1_wr_non_crit_id_l1; + wire [11:0] l2_tbnk1_wr_non_crit_id_l4_q; + wire [15:0] l2_tbnk1_wr_strb_mask_l3a_q; + wire l2_tbnk_hwrst_done_x2; + wire [13:0] l2_tbnk_hwrst_idx_x1_q; + wire [8:0] tm_cntpct_q; + wire tm_cpu0_event_sev; + wire [63:0] tm_cpu0_spr_rd_data; + wire tm_cpu1_event_sev; + wire [63:0] tm_cpu1_spr_rd_data; + wire tm_cpu2_event_sev; + wire [63:0] tm_cpu2_spr_rd_data; + wire tm_cpu3_event_sev; + wire [63:0] tm_cpu3_spr_rd_data; + wire [63:0] tm_tval_cpu0_spr_rd_data; + wire [63:0] tm_tval_cpu1_spr_rd_data; + wire [63:0] tm_tval_cpu2_spr_rd_data; + wire [63:0] tm_tval_cpu3_spr_rd_data; + + maia_timer utm( // outputs + .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), + .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), + .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), + .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tm_cpu0_event_sev (tm_cpu0_event_sev), + .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), + .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tm_cpu1_event_sev (tm_cpu1_event_sev), + .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), + .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tm_cpu2_event_sev (tm_cpu2_event_sev), + .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), + .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tm_cpu3_event_sev (tm_cpu3_event_sev), + .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), + .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), + .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), + .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), + .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]), + + // inputs + .CNTCLKEN (CNTCLKEN), + .CNTVALUEB (CNTVALUEB[63:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .ck_areset_l2 (ck_areset_l2), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .eventi_sev (eventi_sev), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable) + ); // utm + + maia_l2_logic_feq28 ul2_logic( // outputs + .ACREADYM (ACREADYM), + .ARADDRM (ARADDRM[43:0]), + .ARBARM (ARBARM[1:0]), + .ARBURSTM (ARBURSTM[1:0]), + .ARCACHEM (ARCACHEM[3:0]), + .ARDOMAINM (ARDOMAINM[1:0]), + .ARIDM (ARIDM[6:0]), + .ARLENM (ARLENM[7:0]), + .ARLOCKM (ARLOCKM), + .ARPROTM (ARPROTM[2:0]), + .ARREADYS (ARREADYS), + .ARSIZEM (ARSIZEM[2:0]), + .ARSNOOPM (ARSNOOPM[3:0]), + .ARVALIDM (ARVALIDM), + .AWADDRM (AWADDRM[43:0]), + .AWBARM (AWBARM[1:0]), + .AWBURSTM (AWBURSTM[1:0]), + .AWCACHEM (AWCACHEM[3:0]), + .AWDOMAINM (AWDOMAINM[1:0]), + .AWIDM (AWIDM[6:0]), + .AWLENM (AWLENM[7:0]), + .AWLOCKM (AWLOCKM), + .AWPROTM (AWPROTM[2:0]), + .AWREADYS (AWREADYS), + .AWSIZEM (AWSIZEM[2:0]), + .AWSNOOPM (AWSNOOPM[2:0]), + .AWUNIQUEM (AWUNIQUEM), + .AWVALIDM (AWVALIDM), + .BIDS (BIDS[4:0]), + .BREADYM (BREADYM), + .BRESPS (BRESPS[1:0]), + .BVALIDS (BVALIDS), + .CDDATAM (CDDATAM[127:0]), + .CDLASTM (CDLASTM), + .CDVALIDM (CDVALIDM), + .CRRESPM (CRRESPM[4:0]), + .CRVALIDM (CRVALIDM), + .L2FLUSHDONE (L2FLUSHDONE), + .L2QACCEPTn (L2QACCEPTn), + .L2QACTIVE (L2QACTIVE), + .L2QDENY (L2QDENY), + .RACKM (RACKM), + .RDATAS (RDATAS[127:0]), + .RDMEMATTR (RDMEMATTR[7:0]), + .RIDS (RIDS[4:0]), + .RLASTS (RLASTS), + .RREADYM (RREADYM), + .RRESPS (RRESPS[1:0]), + .RVALIDS (RVALIDS), + .WACKM (WACKM), + .WDATAM (WDATAM[127:0]), + .WIDM (WIDM[6:0]), + .WLASTM (WLASTM), + .WREADYS (WREADYS), + .WRMEMATTR (WRMEMATTR[7:0]), + .WSTRBM (WSTRBM[15:0]), + .WVALIDM (WVALIDM), + .ck_areset_l2 (ck_areset_l2), + .ck_l2_logic_clk_en (ck_l2_logic_clk_en), + .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), + .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu0_barrier_done (l2_cpu0_barrier_done), + .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddbl_ecc_err_r3), + .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idbl_ecc_err_r3), + .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu0_rd_arb (l2_cpu0_rd_arb), + .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu0_rexfail (l2_cpu0_rexfail), + .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu0_rvalid (l2_cpu0_rvalid), + .l2_cpu0_snp_active (l2_cpu0_snp_active), + .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu0_spec_valid (l2_cpu0_spec_valid), + .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu0_wr_arb (l2_cpu0_wr_arb), + .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu0_wr_decerr_q (l2_cpu0_wr_decerr_q), + .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu0_wr_slverr_q (l2_cpu0_wr_slverr_q), + .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu1_barrier_done (l2_cpu1_barrier_done), + .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddbl_ecc_err_r3), + .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idbl_ecc_err_r3), + .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu1_rd_arb (l2_cpu1_rd_arb), + .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu1_rexfail (l2_cpu1_rexfail), + .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu1_rvalid (l2_cpu1_rvalid), + .l2_cpu1_snp_active (l2_cpu1_snp_active), + .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu1_spec_valid (l2_cpu1_spec_valid), + .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu1_wr_arb (l2_cpu1_wr_arb), + .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu1_wr_decerr_q (l2_cpu1_wr_decerr_q), + .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu1_wr_slverr_q (l2_cpu1_wr_slverr_q), + .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu2_barrier_done (l2_cpu2_barrier_done), + .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddbl_ecc_err_r3), + .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idbl_ecc_err_r3), + .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu2_rd_arb (l2_cpu2_rd_arb), + .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu2_rexfail (l2_cpu2_rexfail), + .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu2_rvalid (l2_cpu2_rvalid), + .l2_cpu2_snp_active (l2_cpu2_snp_active), + .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu2_spec_valid (l2_cpu2_spec_valid), + .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu2_wr_arb (l2_cpu2_wr_arb), + .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu2_wr_decerr_q (l2_cpu2_wr_decerr_q), + .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu2_wr_slverr_q (l2_cpu2_wr_slverr_q), + .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu3_barrier_done (l2_cpu3_barrier_done), + .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddbl_ecc_err_r3), + .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idbl_ecc_err_r3), + .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu3_rd_arb (l2_cpu3_rd_arb), + .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu3_rexfail (l2_cpu3_rexfail), + .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu3_rvalid (l2_cpu3_rvalid), + .l2_cpu3_snp_active (l2_cpu3_snp_active), + .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu3_spec_valid (l2_cpu3_spec_valid), + .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu3_wr_arb (l2_cpu3_wr_arb), + .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu3_wr_decerr_q (l2_cpu3_wr_decerr_q), + .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu3_wr_slverr_q (l2_cpu3_wr_slverr_q), + .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_idle (l2_idle), + .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), + .l2_mbist2_tbnk0_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), + .l2_mbist2_tbnk0_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), + .l2_mbist2_tbnk0_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), + .l2_mbist2_tbnk0_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), + .l2_mbist2_tbnk1_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), + .l2_mbist2_tbnk1_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), + .l2_mbist2_tbnk1_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), + .l2_mbist2_tbnk1_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_p_addr (l2_p_addr[13:0]), + .l2_p_cpu (l2_p_cpu[1:0]), + .l2_p_nsecure (l2_p_nsecure), + .l2_p_sel (l2_p_sel[2:0]), + .l2_p_wdata (l2_p_wdata[31:0]), + .l2_p_write (l2_p_write), + .l2_reset3 (l2_reset3), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_tbnk0_addr_l1 (l2_tbnk0_addr_l1[44:0]), + .l2_tbnk0_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), + .l2_tbnk0_asq_full_flsh (l2_tbnk0_asq_full_flsh), + .l2_tbnk0_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), + .l2_tbnk0_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), + .l2_tbnk0_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), + .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), + .l2_tbnk0_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), + .l2_tbnk0_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), + .l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), + .l2_tbnk0_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), + .l2_tbnk0_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), + .l2_tbnk0_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), + .l2_tbnk0_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), + .l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), + .l2_tbnk0_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), + .l2_tbnk0_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), + .l2_tbnk0_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), + .l2_tbnk0_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), + .l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), + .l2_tbnk0_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), + .l2_tbnk0_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), + .l2_tbnk0_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), + .l2_tbnk0_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), + .l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), + .l2_tbnk0_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), + .l2_tbnk0_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_dirty_l1 (l2_tbnk0_dirty_l1), + .l2_tbnk0_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), + .l2_tbnk0_excl_l1 (l2_tbnk0_excl_l1), + .l2_tbnk0_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), + .l2_tbnk0_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), + .l2_tbnk0_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), + .l2_tbnk0_feq_kill_l3 (l2_tbnk0_feq_kill_l3), + .l2_tbnk0_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), + .l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk0_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), + .l2_tbnk0_id_l1 (l2_tbnk0_id_l1[9:0]), + .l2_tbnk0_init_req_l1 (l2_tbnk0_init_req_l1), + .l2_tbnk0_kill_l2 (l2_tbnk0_kill_l2), + .l2_tbnk0_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), + .l2_tbnk0_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), + .l2_tbnk0_last_qw_l1 (l2_tbnk0_last_qw_l1), + .l2_tbnk0_lock_l1 (l2_tbnk0_lock_l1[2:0]), + .l2_tbnk0_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), + .l2_tbnk0_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), + .l2_tbnk0_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), + .l2_tbnk0_prfm_l1 (l2_tbnk0_prfm_l1), + .l2_tbnk0_prot_l1 (l2_tbnk0_prot_l1[3:0]), + .l2_tbnk0_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), + .l2_tbnk0_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), + .l2_tbnk0_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), + .l2_tbnk0_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), + .l2_tbnk0_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), + .l2_tbnk0_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), + .l2_tbnk0_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), + .l2_tbnk0_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), + .l2_tbnk0_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), + .l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk0_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk0_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk0_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), + .l2_tbnk0_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk0_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), + .l2_tbnk0_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), + .l2_tbnk0_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), + .l2_tbnk0_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), + .l2_tbnk0_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), + .l2_tbnk0_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), + .l2_tbnk0_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), + .l2_tbnk0_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), + .l2_tbnk0_sel_l1 (l2_tbnk0_sel_l1[13:0]), + .l2_tbnk0_size_l1 (l2_tbnk0_size_l1[2:0]), + .l2_tbnk0_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), + .l2_tbnk0_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), + .l2_tbnk0_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), + .l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk0_sync_l1 (l2_tbnk0_sync_l1), + .l2_tbnk0_type_l1 (l2_tbnk0_type_l1[6:0]), + .l2_tbnk0_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), + .l2_tbnk0_way_l1 (l2_tbnk0_way_l1), + .l2_tbnk0_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), + .l2_tbnk0_wr_err_l1 (l2_tbnk0_wr_err_l1), + .l2_tbnk0_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), + .l2_tbnk0_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), + .l2_tbnk0_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), + .l2_tbnk0_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]), + .l2_tbnk1_addr_l1 (l2_tbnk1_addr_l1[44:0]), + .l2_tbnk1_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), + .l2_tbnk1_asq_full_flsh (l2_tbnk1_asq_full_flsh), + .l2_tbnk1_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), + .l2_tbnk1_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), + .l2_tbnk1_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), + .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), + .l2_tbnk1_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), + .l2_tbnk1_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), + .l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), + .l2_tbnk1_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), + .l2_tbnk1_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), + .l2_tbnk1_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), + .l2_tbnk1_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), + .l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), + .l2_tbnk1_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), + .l2_tbnk1_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), + .l2_tbnk1_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), + .l2_tbnk1_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), + .l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), + .l2_tbnk1_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), + .l2_tbnk1_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), + .l2_tbnk1_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), + .l2_tbnk1_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), + .l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), + .l2_tbnk1_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), + .l2_tbnk1_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_dirty_l1 (l2_tbnk1_dirty_l1), + .l2_tbnk1_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), + .l2_tbnk1_excl_l1 (l2_tbnk1_excl_l1), + .l2_tbnk1_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), + .l2_tbnk1_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), + .l2_tbnk1_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), + .l2_tbnk1_feq_kill_l3 (l2_tbnk1_feq_kill_l3), + .l2_tbnk1_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), + .l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk1_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), + .l2_tbnk1_id_l1 (l2_tbnk1_id_l1[9:0]), + .l2_tbnk1_init_req_l1 (l2_tbnk1_init_req_l1), + .l2_tbnk1_kill_l2 (l2_tbnk1_kill_l2), + .l2_tbnk1_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), + .l2_tbnk1_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), + .l2_tbnk1_last_qw_l1 (l2_tbnk1_last_qw_l1), + .l2_tbnk1_lock_l1 (l2_tbnk1_lock_l1[2:0]), + .l2_tbnk1_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), + .l2_tbnk1_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), + .l2_tbnk1_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), + .l2_tbnk1_prfm_l1 (l2_tbnk1_prfm_l1), + .l2_tbnk1_prot_l1 (l2_tbnk1_prot_l1[3:0]), + .l2_tbnk1_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), + .l2_tbnk1_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), + .l2_tbnk1_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), + .l2_tbnk1_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), + .l2_tbnk1_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), + .l2_tbnk1_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), + .l2_tbnk1_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), + .l2_tbnk1_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), + .l2_tbnk1_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), + .l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk1_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk1_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk1_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), + .l2_tbnk1_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk1_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), + .l2_tbnk1_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), + .l2_tbnk1_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), + .l2_tbnk1_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), + .l2_tbnk1_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), + .l2_tbnk1_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), + .l2_tbnk1_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), + .l2_tbnk1_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), + .l2_tbnk1_sel_l1 (l2_tbnk1_sel_l1[13:0]), + .l2_tbnk1_size_l1 (l2_tbnk1_size_l1[2:0]), + .l2_tbnk1_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), + .l2_tbnk1_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), + .l2_tbnk1_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), + .l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk1_sync_l1 (l2_tbnk1_sync_l1), + .l2_tbnk1_type_l1 (l2_tbnk1_type_l1[6:0]), + .l2_tbnk1_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), + .l2_tbnk1_way_l1 (l2_tbnk1_way_l1), + .l2_tbnk1_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), + .l2_tbnk1_wr_err_l1 (l2_tbnk1_wr_err_l1), + .l2_tbnk1_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), + .l2_tbnk1_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), + .l2_tbnk1_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), + .l2_tbnk1_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .nEXTERRIRQ (nEXTERRIRQ), + .nINTERRIRQ (nINTERRIRQ), + + // inputs + .ACADDRM (ACADDRM[43:0]), + .ACLKENM (ACLKENM), + .ACLKENS (ACLKENS), + .ACPROTM (ACPROTM[2:0]), + .ACSNOOPM (ACSNOOPM[3:0]), + .ACVALIDM (ACVALIDM), + .ARADDRS (ARADDRS[43:0]), + .ARCACHES (ARCACHES[3:0]), + .ARIDS (ARIDS[4:0]), + .ARLENS (ARLENS[7:0]), + .ARPROTS (ARPROTS[2:0]), + .ARREADYM (ARREADYM), + .ARUSERS (ARUSERS[1:0]), + .ARVALIDS (ARVALIDS), + .AWADDRS (AWADDRS[43:0]), + .AWCACHES (AWCACHES[3:0]), + .AWIDS (AWIDS[4:0]), + .AWLENS (AWLENS[7:0]), + .AWPROTS (AWPROTS[2:0]), + .AWREADYM (AWREADYM), + .AWUSERS (AWUSERS[1:0]), + .AWVALIDS (AWVALIDS), + .BIDM (BIDM[6:0]), + .BREADYS (BREADYS), + .BRESPM (BRESPM[1:0]), + .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), + .BROADCASTINNER (BROADCASTINNER), + .BROADCASTOUTER (BROADCASTOUTER), + .BVALIDM (BVALIDM), + .CDREADYM (CDREADYM), + .CRREADYM (CRREADYM), + .DBGL1RSTDISABLE (DBGL1RSTDISABLE), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .L2FLUSHREQ (L2FLUSHREQ), + .L2QREQn (L2QREQn), + .L2RSTDISABLE (L2RSTDISABLE), + .MBISTREQ (MBISTREQ), + .PERIPHBASE (PERIPHBASE[43:18]), + .RDATAM (RDATAM[127:0]), + .RIDM (RIDM[6:0]), + .RLASTM (RLASTM), + .RREADYS (RREADYS), + .RRESPM (RRESPM[3:0]), + .RVALIDM (RVALIDM), + .STANDBYWFIL2 (STANDBYWFIL2), + .SYSBARDISABLE (SYSBARDISABLE), + .WDATAS (WDATAS[127:0]), + .WLASTS (WLASTS), + .WREADYM (WREADYM), + .WSTRBS (WSTRBS[15:0]), + .WVALIDS (WVALIDS), + .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), + .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), + .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), + .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), + .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), + .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), + .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), + .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), + .ck_gclkfr (ck_gclkfr), + .ck_gclkl2 (ck_gclkl2), + .ck_l2_ace_inactive (ck_l2_ace_inactive), + .ck_l2_acp_inactive (ck_l2_acp_inactive), + .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), + .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), + .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), + .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), + .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), + .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), + .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), + .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), + .ic_p_rdata (ic_p_rdata[31:0]), + .ic_p_rdata_valid (ic_p_rdata_valid), + .ic_p_ready (ic_p_ready), + .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .l2_mbist2_tbnk0_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), + .l2_mbist2_tbnk0_all_b1 (l2_mbist2_tbnk0_all_b1), + .l2_mbist2_tbnk0_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), + .l2_mbist2_tbnk0_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), + .l2_mbist2_tbnk0_en_b1 (l2_mbist2_tbnk0_en_b1), + .l2_mbist2_tbnk0_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), + .l2_mbist2_tbnk0_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), + .l2_mbist2_tbnk0_sel_b1 (l2_mbist2_tbnk0_sel_b1), + .l2_mbist2_tbnk0_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), + .l2_mbist2_tbnk0_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), + .l2_mbist2_tbnk0_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), + .l2_mbist2_tbnk0_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), + .l2_mbist2_tbnk0_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), + .l2_mbist2_tbnk1_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), + .l2_mbist2_tbnk1_all_b1 (l2_mbist2_tbnk1_all_b1), + .l2_mbist2_tbnk1_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), + .l2_mbist2_tbnk1_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), + .l2_mbist2_tbnk1_en_b1 (l2_mbist2_tbnk1_en_b1), + .l2_mbist2_tbnk1_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), + .l2_mbist2_tbnk1_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), + .l2_mbist2_tbnk1_sel_b1 (l2_mbist2_tbnk1_sel_b1), + .l2_mbist2_tbnk1_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), + .l2_mbist2_tbnk1_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), + .l2_mbist2_tbnk1_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), + .l2_mbist2_tbnk1_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), + .l2_mbist2_tbnk1_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), + .l2_tbnk0_addr44_l3_q (l2_tbnk0_addr44_l3_q), + .l2_tbnk0_addr_l6 (l2_tbnk0_addr_l6[5:2]), + .l2_tbnk0_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), + .l2_tbnk0_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), + .l2_tbnk0_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), + .l2_tbnk0_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), + .l2_tbnk0_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), + .l2_tbnk0_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), + .l2_tbnk0_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), + .l2_tbnk0_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), + .l2_tbnk0_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), + .l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), + .l2_tbnk0_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), + .l2_tbnk0_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), + .l2_tbnk0_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), + .l2_tbnk0_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), + .l2_tbnk0_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), + .l2_tbnk0_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), + .l2_tbnk0_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), + .l2_tbnk0_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), + .l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), + .l2_tbnk0_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), + .l2_tbnk0_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), + .l2_tbnk0_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), + .l2_tbnk0_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), + .l2_tbnk0_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), + .l2_tbnk0_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), + .l2_tbnk0_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), + .l2_tbnk0_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), + .l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), + .l2_tbnk0_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), + .l2_tbnk0_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), + .l2_tbnk0_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), + .l2_tbnk0_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), + .l2_tbnk0_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), + .l2_tbnk0_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), + .l2_tbnk0_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), + .l2_tbnk0_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), + .l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), + .l2_tbnk0_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), + .l2_tbnk0_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk0_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk0_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk0_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), + .l2_tbnk0_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), + .l2_tbnk0_data_l6 (l2_tbnk0_data_l6[127:0]), + .l2_tbnk0_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), + .l2_tbnk0_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk0_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk0_dirty_l3_q (l2_tbnk0_dirty_l3_q), + .l2_tbnk0_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), + .l2_tbnk0_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), + .l2_tbnk0_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), + .l2_tbnk0_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), + .l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk0_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), + .l2_tbnk0_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), + .l2_tbnk0_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), + .l2_tbnk0_excl_l4_q (l2_tbnk0_excl_l4_q), + .l2_tbnk0_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), + .l2_tbnk0_feq_clr_l4 (l2_tbnk0_feq_clr_l4), + .l2_tbnk0_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), + .l2_tbnk0_hit_l4 (l2_tbnk0_hit_l4), + .l2_tbnk0_hit_l7_q (l2_tbnk0_hit_l7_q), + .l2_tbnk0_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), + .l2_tbnk0_id_l6_q (l2_tbnk0_id_l6_q[9:0]), + .l2_tbnk0_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), + .l2_tbnk0_idle (l2_tbnk0_idle), + .l2_tbnk0_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), + .l2_tbnk0_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), + .l2_tbnk0_l2v_s_q (l2_tbnk0_l2v_s_q), + .l2_tbnk0_l2v_vld_q (l2_tbnk0_l2v_vld_q), + .l2_tbnk0_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), + .l2_tbnk0_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), + .l2_tbnk0_lock_l4 (l2_tbnk0_lock_l4[2:0]), + .l2_tbnk0_merrsr_data (l2_tbnk0_merrsr_data[32:0]), + .l2_tbnk0_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), + .l2_tbnk0_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), + .l2_tbnk0_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), + .l2_tbnk0_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), + .l2_tbnk0_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), + .l2_tbnk0_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), + .l2_tbnk0_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), + .l2_tbnk0_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), + .l2_tbnk0_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), + .l2_tbnk0_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), + .l2_tbnk0_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk0_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk0_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), + .l2_tbnk0_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), + .l2_tbnk0_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), + .l2_tbnk0_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk0_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), + .l2_tbnk0_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), + .l2_tbnk0_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), + .l2_tbnk0_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), + .l2_tbnk0_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk0_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), + .l2_tbnk0_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk0_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), + .l2_tbnk0_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), + .l2_tbnk0_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), + .l2_tbnk0_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), + .l2_tbnk0_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), + .l2_tbnk0_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), + .l2_tbnk0_size_l4_q (l2_tbnk0_size_l4_q[2:0]), + .l2_tbnk0_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), + .l2_tbnk0_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), + .l2_tbnk0_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk0_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk0_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk0_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), + .l2_tbnk0_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), + .l2_tbnk0_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk0_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), + .l2_tbnk0_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), + .l2_tbnk0_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), + .l2_tbnk0_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), + .l2_tbnk0_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), + .l2_tbnk0_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), + .l2_tbnk0_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), + .l2_tbnk0_vld_l6_q (l2_tbnk0_vld_l6_q), + .l2_tbnk0_way_l4_q (l2_tbnk0_way_l4_q), + .l2_tbnk0_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), + .l2_tbnk0_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), + .l2_tbnk0_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), + .l2_tbnk0_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), + .l2_tbnk1_addr44_l3_q (l2_tbnk1_addr44_l3_q), + .l2_tbnk1_addr_l6 (l2_tbnk1_addr_l6[5:2]), + .l2_tbnk1_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), + .l2_tbnk1_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), + .l2_tbnk1_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), + .l2_tbnk1_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), + .l2_tbnk1_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), + .l2_tbnk1_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), + .l2_tbnk1_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), + .l2_tbnk1_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), + .l2_tbnk1_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), + .l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), + .l2_tbnk1_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), + .l2_tbnk1_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), + .l2_tbnk1_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), + .l2_tbnk1_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), + .l2_tbnk1_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), + .l2_tbnk1_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), + .l2_tbnk1_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), + .l2_tbnk1_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), + .l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), + .l2_tbnk1_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), + .l2_tbnk1_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), + .l2_tbnk1_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), + .l2_tbnk1_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), + .l2_tbnk1_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), + .l2_tbnk1_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), + .l2_tbnk1_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), + .l2_tbnk1_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), + .l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), + .l2_tbnk1_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), + .l2_tbnk1_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), + .l2_tbnk1_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), + .l2_tbnk1_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), + .l2_tbnk1_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), + .l2_tbnk1_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), + .l2_tbnk1_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), + .l2_tbnk1_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), + .l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), + .l2_tbnk1_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), + .l2_tbnk1_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk1_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk1_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk1_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), + .l2_tbnk1_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), + .l2_tbnk1_data_l6 (l2_tbnk1_data_l6[127:0]), + .l2_tbnk1_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), + .l2_tbnk1_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk1_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk1_dirty_l3_q (l2_tbnk1_dirty_l3_q), + .l2_tbnk1_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), + .l2_tbnk1_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), + .l2_tbnk1_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), + .l2_tbnk1_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), + .l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk1_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), + .l2_tbnk1_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), + .l2_tbnk1_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), + .l2_tbnk1_excl_l4_q (l2_tbnk1_excl_l4_q), + .l2_tbnk1_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), + .l2_tbnk1_feq_clr_l4 (l2_tbnk1_feq_clr_l4), + .l2_tbnk1_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), + .l2_tbnk1_hit_l4 (l2_tbnk1_hit_l4), + .l2_tbnk1_hit_l7_q (l2_tbnk1_hit_l7_q), + .l2_tbnk1_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), + .l2_tbnk1_id_l6_q (l2_tbnk1_id_l6_q[9:0]), + .l2_tbnk1_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), + .l2_tbnk1_idle (l2_tbnk1_idle), + .l2_tbnk1_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), + .l2_tbnk1_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), + .l2_tbnk1_l2v_s_q (l2_tbnk1_l2v_s_q), + .l2_tbnk1_l2v_vld_q (l2_tbnk1_l2v_vld_q), + .l2_tbnk1_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), + .l2_tbnk1_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), + .l2_tbnk1_lock_l4 (l2_tbnk1_lock_l4[2:0]), + .l2_tbnk1_merrsr_data (l2_tbnk1_merrsr_data[32:0]), + .l2_tbnk1_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), + .l2_tbnk1_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), + .l2_tbnk1_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), + .l2_tbnk1_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), + .l2_tbnk1_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), + .l2_tbnk1_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), + .l2_tbnk1_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), + .l2_tbnk1_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), + .l2_tbnk1_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), + .l2_tbnk1_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), + .l2_tbnk1_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk1_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk1_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), + .l2_tbnk1_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), + .l2_tbnk1_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), + .l2_tbnk1_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk1_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), + .l2_tbnk1_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), + .l2_tbnk1_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), + .l2_tbnk1_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), + .l2_tbnk1_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk1_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), + .l2_tbnk1_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk1_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), + .l2_tbnk1_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), + .l2_tbnk1_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), + .l2_tbnk1_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), + .l2_tbnk1_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), + .l2_tbnk1_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), + .l2_tbnk1_size_l4_q (l2_tbnk1_size_l4_q[2:0]), + .l2_tbnk1_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), + .l2_tbnk1_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), + .l2_tbnk1_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk1_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk1_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk1_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), + .l2_tbnk1_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), + .l2_tbnk1_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk1_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), + .l2_tbnk1_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), + .l2_tbnk1_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), + .l2_tbnk1_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), + .l2_tbnk1_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), + .l2_tbnk1_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), + .l2_tbnk1_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), + .l2_tbnk1_vld_l6_q (l2_tbnk1_vld_l6_q), + .l2_tbnk1_way_l4_q (l2_tbnk1_way_l4_q), + .l2_tbnk1_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), + .l2_tbnk1_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), + .l2_tbnk1_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), + .l2_tbnk1_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), + .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), + .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), + .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), + .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), + .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), + .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), + .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]) + ); // ul2_logic + + maia_l2_tbnk ul2_tbnk0( // outputs + .l2_mbist2_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), + .l2_mbist2_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), + .l2_mbist2_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), + .l2_mbist2_en_b1 (l2_mbist2_tbnk0_en_b1), + .l2_mbist2_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), + .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk0_all_b1), + .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), + .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk0_sel_b1), + .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), + .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), + .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), + .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), + .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), + .l2_tbnk_addr44_l3_q (l2_tbnk0_addr44_l3_q), + .l2_tbnk_addr_l6 (l2_tbnk0_addr_l6[5:2]), + .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), + .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), + .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), + .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), + .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), + .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), + .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), + .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), + .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), + .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), + .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), + .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), + .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), + .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), + .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), + .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), + .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), + .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), + .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), + .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), + .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), + .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), + .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), + .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), + .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), + .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), + .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), + .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), + .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), + .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), + .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), + .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), + .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), + .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), + .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), + .l2_tbnk_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), + .l2_tbnk_data_l6 (l2_tbnk0_data_l6[127:0]), + .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), + .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk_dirty_l3_q (l2_tbnk0_dirty_l3_q), + .l2_tbnk_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), + .l2_tbnk_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), + .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), + .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), + .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), + .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), + .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), + .l2_tbnk_excl_l4_q (l2_tbnk0_excl_l4_q), + .l2_tbnk_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), + .l2_tbnk_feq_clr_l4 (l2_tbnk0_feq_clr_l4), + .l2_tbnk_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), + .l2_tbnk_hit_l4 (l2_tbnk0_hit_l4), + .l2_tbnk_hit_l7_q (l2_tbnk0_hit_l7_q), + .l2_tbnk_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), + .l2_tbnk_id_l6_q (l2_tbnk0_id_l6_q[9:0]), + .l2_tbnk_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), + .l2_tbnk_idle (l2_tbnk0_idle), + .l2_tbnk_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), + .l2_tbnk_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), + .l2_tbnk_l2v_s_q (l2_tbnk0_l2v_s_q), + .l2_tbnk_l2v_vld_q (l2_tbnk0_l2v_vld_q), + .l2_tbnk_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), + .l2_tbnk_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), + .l2_tbnk_lock_l4 (l2_tbnk0_lock_l4[2:0]), + .l2_tbnk_merrsr_data (l2_tbnk0_merrsr_data[32:0]), + .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), + .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), + .l2_tbnk_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), + .l2_tbnk_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), + .l2_tbnk_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), + .l2_tbnk_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), + .l2_tbnk_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), + .l2_tbnk_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), + .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), + .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), + .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), + .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), + .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), + .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), + .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), + .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), + .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), + .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), + .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), + .l2_tbnk_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), + .l2_tbnk_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), + .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), + .l2_tbnk_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), + .l2_tbnk_size_l4_q (l2_tbnk0_size_l4_q[2:0]), + .l2_tbnk_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), + .l2_tbnk_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), + .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), + .l2_tbnk_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), + .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), + .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), + .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), + .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), + .l2_tbnk_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), + .l2_tbnk_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), + .l2_tbnk_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), + .l2_tbnk_vld_l6_q (l2_tbnk0_vld_l6_q), + .l2_tbnk_way_l4_q (l2_tbnk0_way_l4_q), + .l2_tbnk_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), + .l2_tbnk_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), + .l2_tbnk_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), + .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), + + // inputs + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ), + .ck_areset_l2 (ck_areset_l2), + .ck_gclkl2 (ck_gclkb0), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), + .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), + .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), + .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), + .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), + .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), + .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), + .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_skyros_intf (1'b0), + .l2_tbnk_addr_l1 (l2_tbnk0_addr_l1[44:0]), + .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), + .l2_tbnk_asq_full_flsh (l2_tbnk0_asq_full_flsh), + .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), + .l2_tbnk_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), + .l2_tbnk_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), + .l2_tbnk_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), + .l2_tbnk_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), + .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), + .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), + .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), + .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), + .l2_tbnk_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), + .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), + .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), + .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), + .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), + .l2_tbnk_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), + .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), + .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), + .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), + .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), + .l2_tbnk_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), + .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), + .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), + .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), + .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_dirty_l1 (l2_tbnk0_dirty_l1), + .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), + .l2_tbnk_excl_l1 (l2_tbnk0_excl_l1), + .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), + .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), + .l2_tbnk_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), + .l2_tbnk_feq_kill_l3 (l2_tbnk0_feq_kill_l3), + .l2_tbnk_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), + .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .l2_tbnk_id_l1 (l2_tbnk0_id_l1[9:0]), + .l2_tbnk_init_req_l1 (l2_tbnk0_init_req_l1), + .l2_tbnk_kill_l2 (l2_tbnk0_kill_l2), + .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), + .l2_tbnk_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), + .l2_tbnk_last_qw_l1 (l2_tbnk0_last_qw_l1), + .l2_tbnk_lock_l1 (l2_tbnk0_lock_l1[2:0]), + .l2_tbnk_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), + .l2_tbnk_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), + .l2_tbnk_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), + .l2_tbnk_prfm_l1 (l2_tbnk0_prfm_l1), + .l2_tbnk_prot_l1 (l2_tbnk0_prot_l1[3:0]), + .l2_tbnk_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), + .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), + .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), + .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), + .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), + .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), + .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), + .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), + .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), + .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), + .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), + .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), + .l2_tbnk_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), + .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), + .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), + .l2_tbnk_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), + .l2_tbnk_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), + .l2_tbnk_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), + .l2_tbnk_sel_l1 (l2_tbnk0_sel_l1[13:0]), + .l2_tbnk_size_l1 (l2_tbnk0_size_l1[2:0]), + .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), + .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), + .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), + .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_sync_l1 (l2_tbnk0_sync_l1), + .l2_tbnk_type_l1 (l2_tbnk0_type_l1[6:0]), + .l2_tbnk_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), + .l2_tbnk_way_l1 (l2_tbnk0_way_l1), + .l2_tbnk_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), + .l2_tbnk_wr_err_l1 (l2_tbnk0_wr_err_l1), + .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), + .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), + .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), + .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]) + ); // ul2_tbnk0 + + maia_l2_tbnk ul2_tbnk1( // outputs + .l2_mbist2_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), + .l2_mbist2_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), + .l2_mbist2_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), + .l2_mbist2_en_b1 (l2_mbist2_tbnk1_en_b1), + .l2_mbist2_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), + .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk1_all_b1), + .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), + .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk1_sel_b1), + .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), + .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), + .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), + .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), + .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), + .l2_tbnk_addr44_l3_q (l2_tbnk1_addr44_l3_q), + .l2_tbnk_addr_l6 (l2_tbnk1_addr_l6[5:2]), + .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), + .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), + .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), + .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), + .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), + .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), + .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), + .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), + .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), + .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), + .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), + .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), + .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), + .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), + .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), + .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), + .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), + .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), + .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), + .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), + .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), + .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), + .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), + .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), + .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), + .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), + .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), + .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), + .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), + .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), + .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), + .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), + .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), + .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), + .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), + .l2_tbnk_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), + .l2_tbnk_data_l6 (l2_tbnk1_data_l6[127:0]), + .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), + .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk_dirty_l3_q (l2_tbnk1_dirty_l3_q), + .l2_tbnk_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), + .l2_tbnk_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), + .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), + .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), + .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), + .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), + .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), + .l2_tbnk_excl_l4_q (l2_tbnk1_excl_l4_q), + .l2_tbnk_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), + .l2_tbnk_feq_clr_l4 (l2_tbnk1_feq_clr_l4), + .l2_tbnk_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), + .l2_tbnk_hit_l4 (l2_tbnk1_hit_l4), + .l2_tbnk_hit_l7_q (l2_tbnk1_hit_l7_q), + .l2_tbnk_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), + .l2_tbnk_id_l6_q (l2_tbnk1_id_l6_q[9:0]), + .l2_tbnk_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), + .l2_tbnk_idle (l2_tbnk1_idle), + .l2_tbnk_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), + .l2_tbnk_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), + .l2_tbnk_l2v_s_q (l2_tbnk1_l2v_s_q), + .l2_tbnk_l2v_vld_q (l2_tbnk1_l2v_vld_q), + .l2_tbnk_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), + .l2_tbnk_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), + .l2_tbnk_lock_l4 (l2_tbnk1_lock_l4[2:0]), + .l2_tbnk_merrsr_data (l2_tbnk1_merrsr_data[32:0]), + .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), + .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), + .l2_tbnk_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), + .l2_tbnk_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), + .l2_tbnk_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), + .l2_tbnk_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), + .l2_tbnk_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), + .l2_tbnk_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), + .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), + .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), + .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), + .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), + .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), + .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), + .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), + .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), + .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), + .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), + .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), + .l2_tbnk_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), + .l2_tbnk_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), + .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), + .l2_tbnk_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), + .l2_tbnk_size_l4_q (l2_tbnk1_size_l4_q[2:0]), + .l2_tbnk_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), + .l2_tbnk_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), + .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), + .l2_tbnk_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), + .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), + .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), + .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), + .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), + .l2_tbnk_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), + .l2_tbnk_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), + .l2_tbnk_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), + .l2_tbnk_vld_l6_q (l2_tbnk1_vld_l6_q), + .l2_tbnk_way_l4_q (l2_tbnk1_way_l4_q), + .l2_tbnk_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), + .l2_tbnk_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), + .l2_tbnk_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), + .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), + + // inputs + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ), + .ck_areset_l2 (ck_areset_l2), + .ck_gclkl2 (ck_gclkb1), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), + .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), + .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), + .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), + .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), + .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), + .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), + .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_skyros_intf (1'b0), + .l2_tbnk_addr_l1 (l2_tbnk1_addr_l1[44:0]), + .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), + .l2_tbnk_asq_full_flsh (l2_tbnk1_asq_full_flsh), + .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), + .l2_tbnk_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), + .l2_tbnk_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), + .l2_tbnk_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), + .l2_tbnk_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), + .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), + .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), + .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), + .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), + .l2_tbnk_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), + .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), + .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), + .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), + .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), + .l2_tbnk_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), + .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), + .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), + .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), + .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), + .l2_tbnk_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), + .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), + .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), + .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), + .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_dirty_l1 (l2_tbnk1_dirty_l1), + .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), + .l2_tbnk_excl_l1 (l2_tbnk1_excl_l1), + .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), + .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), + .l2_tbnk_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), + .l2_tbnk_feq_kill_l3 (l2_tbnk1_feq_kill_l3), + .l2_tbnk_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), + .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .l2_tbnk_id_l1 (l2_tbnk1_id_l1[9:0]), + .l2_tbnk_init_req_l1 (l2_tbnk1_init_req_l1), + .l2_tbnk_kill_l2 (l2_tbnk1_kill_l2), + .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), + .l2_tbnk_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), + .l2_tbnk_last_qw_l1 (l2_tbnk1_last_qw_l1), + .l2_tbnk_lock_l1 (l2_tbnk1_lock_l1[2:0]), + .l2_tbnk_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), + .l2_tbnk_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), + .l2_tbnk_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), + .l2_tbnk_prfm_l1 (l2_tbnk1_prfm_l1), + .l2_tbnk_prot_l1 (l2_tbnk1_prot_l1[3:0]), + .l2_tbnk_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), + .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), + .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), + .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), + .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), + .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), + .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), + .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), + .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), + .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), + .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), + .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), + .l2_tbnk_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), + .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), + .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), + .l2_tbnk_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), + .l2_tbnk_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), + .l2_tbnk_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), + .l2_tbnk_sel_l1 (l2_tbnk1_sel_l1[13:0]), + .l2_tbnk_size_l1 (l2_tbnk1_size_l1[2:0]), + .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), + .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), + .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), + .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_sync_l1 (l2_tbnk1_sync_l1), + .l2_tbnk_type_l1 (l2_tbnk1_type_l1[6:0]), + .l2_tbnk_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), + .l2_tbnk_way_l1 (l2_tbnk1_way_l1), + .l2_tbnk_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), + .l2_tbnk_wr_err_l1 (l2_tbnk1_wr_err_l1), + .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), + .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), + .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), + .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]) + ); // ul2_tbnk1 + + maia_dt_pclk udt_pclk( // outputs + .CTICHINACK (CTICHINACK[3:0]), + .CTICHOUT (CTICHOUT[3:0]), + .CTIIRQ (CTIIRQ[`MAIA_CN:0]), + .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), + .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), + .PRDATADBG (PRDATADBG[31:0]), + .PREADYDBG (PREADYDBG), + .PSLVERRDBG (PSLVERRDBG), + .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), + .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), + .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), + .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), + .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), + .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), + .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), + .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), + .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + + // inputs + .CIHSBYPASS (CIHSBYPASS[3:0]), + .CISBYPASS (CISBYPASS), + .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), + .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), + .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), + .CTICHIN (CTICHIN[3:0]), + .CTICHOUTACK (CTICHOUTACK[3:0]), + .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), + .DBGEN (DBGEN[`MAIA_CN:0]), + .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .EDBGRQ (EDBGRQ[`MAIA_CN:0]), + .GICCDISABLE (GICCDISABLE), + .NIDEN (NIDEN[`MAIA_CN:0]), + .PADDRDBG (PADDRDBG[21:2]), + .PADDRDBG31 (PADDRDBG31), + .PCLKDBG (PCLKDBG), + .PCLKENDBG (PCLKENDBG), + .PENABLEDBG (PENABLEDBG), + .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), + .PSELDBG (PSELDBG), + .PWDATADBG (PWDATADBG[31:0]), + .PWRITEDBG (PWRITEDBG), + .SPIDEN (SPIDEN[`MAIA_CN:0]), + .SPNIDEN (SPNIDEN[`MAIA_CN:0]), + .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), + .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), + .ck_cpu0_poreset_status (ck_cpu0_poreset_status), + .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), + .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), + .ck_cpu1_poreset_status (ck_cpu1_poreset_status), + .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), + .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), + .ck_cpu2_poreset_status (ck_cpu2_poreset_status), + .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), + .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), + .ck_cpu3_poreset_status (ck_cpu3_poreset_status), + .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), + .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), + .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), + .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), + .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), + .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), + .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), + .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), + .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), + .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), + .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), + .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), + .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), + .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), + .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), + .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), + .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), + .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), + .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), + .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), + .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), + .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), + .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), + .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), + .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .nPRESETDBG (nPRESETDBG) + ); // udt_pclk + + maia_intctrl uic( // outputs + .ICCTDATA (ICCTDATA[15:0]), + .ICCTID (ICCTID[1:0]), + .ICCTLAST (ICCTLAST), + .ICCTVALID (ICCTVALID), + .ICDTREADY (ICDTREADY), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), + .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), + .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), + .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), + .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), + .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), + .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), + .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), + .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), + .ic_el_change_complete_o (ic_el_change_complete_o[`MAIA_CN:0]), + .ic_hcr_change_complete_o (ic_hcr_change_complete_o[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .ic_p_rdata (ic_p_rdata[31:0]), + .ic_p_rdata_valid (ic_p_rdata_valid), + .ic_p_ready (ic_p_ready), + .ic_p_valid (ic_p_valid[`MAIA_CN:0]), + .ic_sample_spr_o (ic_sample_spr_o[`MAIA_CN:0]), + .ic_scr_change_complete_o (ic_scr_change_complete_o[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]), + .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), + + // inputs + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .GICCDISABLE (GICCDISABLE), + .ICCTREADY (ICCTREADY), + .ICDTDATA (ICDTDATA[15:0]), + .ICDTDEST (ICDTDEST[1:0]), + .ICDTLAST (ICDTLAST), + .ICDTVALID (ICDTVALID), + .ck_areset_l2 (ck_areset_l2), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_aa64naa32_i (ds_cpu0_ic_aa64naa32_i), + .ds_cpu0_cpsr_mode_i (ds_cpu0_ic_cpsr_mode_i[4:0]), + .ds_cpu0_hcr_change_i (ds_cpu0_ic_hcr_change_i), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu0_sample_spr_i (ds_cpu0_ic_sample_spr_i), + .ds_cpu0_scr_change_i (ds_cpu0_ic_scr_change_i), + .ds_cpu1_aa64naa32_i (ds_cpu1_ic_aa64naa32_i), + .ds_cpu1_cpsr_mode_i (ds_cpu1_ic_cpsr_mode_i[4:0]), + .ds_cpu1_hcr_change_i (ds_cpu1_ic_hcr_change_i), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu1_sample_spr_i (ds_cpu1_ic_sample_spr_i), + .ds_cpu1_scr_change_i (ds_cpu1_ic_scr_change_i), + .ds_cpu2_aa64naa32_i (ds_cpu2_ic_aa64naa32_i), + .ds_cpu2_cpsr_mode_i (ds_cpu2_ic_cpsr_mode_i[4:0]), + .ds_cpu2_hcr_change_i (ds_cpu2_ic_hcr_change_i), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu2_sample_spr_i (ds_cpu2_ic_sample_spr_i), + .ds_cpu2_scr_change_i (ds_cpu2_ic_scr_change_i), + .ds_cpu3_aa64naa32_i (ds_cpu3_ic_aa64naa32_i), + .ds_cpu3_cpsr_mode_i (ds_cpu3_ic_cpsr_mode_i[4:0]), + .ds_cpu3_hcr_change_i (ds_cpu3_ic_hcr_change_i), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_cpu3_sample_spr_i (ds_cpu3_ic_sample_spr_i), + .ds_cpu3_scr_change_i (ds_cpu3_ic_scr_change_i), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_cpu0_wr_decerr_i (l2_cpu0_wr_decerr_q), + .l2_cpu0_wr_slverr_i (l2_cpu0_wr_slverr_q), + .l2_cpu1_wr_decerr_i (l2_cpu1_wr_decerr_q), + .l2_cpu1_wr_slverr_i (l2_cpu1_wr_slverr_q), + .l2_cpu2_wr_decerr_i (l2_cpu2_wr_decerr_q), + .l2_cpu2_wr_slverr_i (l2_cpu2_wr_slverr_q), + .l2_cpu3_wr_decerr_i (l2_cpu3_wr_decerr_q), + .l2_cpu3_wr_slverr_i (l2_cpu3_wr_slverr_q), + .l2_p_addr (l2_p_addr[13:0]), + .l2_p_cpu (l2_p_cpu[1:0]), + .l2_p_nsecure (l2_p_nsecure), + .l2_p_sel (l2_p_sel[2:0]), + .l2_p_wdata (l2_p_wdata[31:0]), + .l2_p_write (l2_p_write), + .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), + .nFIQ (nFIQ[`MAIA_CN:0]), + .nIRQ (nIRQ[`MAIA_CN:0]), + .nREI (nREI[`MAIA_CN:0]), + .nSEI (nSEI[`MAIA_CN:0]), + .nVFIQ (nVFIQ[`MAIA_CN:0]), + .nVIRQ (nVIRQ[`MAIA_CN:0]), + .nVSEI (nVSEI[`MAIA_CN:0]) + ); // uic + + maia_ck_l2 uck_l2( // outputs + .ck_gclkb0 (ck_gclkb0), + .ck_gclkb1 (ck_gclkb1), + .ck_gclkfr (ck_gclkfr), + .ck_gclkl2 (ck_gclkl2), + + // inputs + .DFTL2CLKDISABLE (DFTL2CLKDISABLE), + .DFTSE (DFTSE), + .ck_gclktl2 (ck_gclktl2), + .ck_l2_logic_clk_en (ck_l2_logic_clk_en), + .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), + .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), + .l2_reset3 (l2_reset3) + ); // uck_l2 + + maia_ck_top uck_top( // outputs + .ck_gclkt (ck_gclkt[`MAIA_CN:0]), + .ck_gclktl2 (ck_gclktl2), + + // inputs + .CLK (CLK), + .CLKEN (CLKEN), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ) + ); // uck_top + + maia_ck_logic uck_logic( // outputs + .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), + .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), + .CPUQDENY (CPUQDENY[`MAIA_CN:0]), + .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), + .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), + .STANDBYWFIL2 (STANDBYWFIL2), + .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), + .ck_cpu0_commrx (ck_cpu0_commrx), + .ck_cpu0_commtx (ck_cpu0_commtx), + .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), + .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), + .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), + .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), + .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), + .ck_cpu0_event_reg (ck_cpu0_event_reg), + .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), + .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), + .ck_cpu0_ncommirq (ck_cpu0_ncommirq), + .ck_cpu0_npmuirq (ck_cpu0_npmuirq), + .ck_cpu0_poreset_status (ck_cpu0_poreset_status), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), + .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), + .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), + .ck_cpu1_commrx (ck_cpu1_commrx), + .ck_cpu1_commtx (ck_cpu1_commtx), + .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), + .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), + .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), + .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), + .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), + .ck_cpu1_event_reg (ck_cpu1_event_reg), + .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), + .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), + .ck_cpu1_ncommirq (ck_cpu1_ncommirq), + .ck_cpu1_npmuirq (ck_cpu1_npmuirq), + .ck_cpu1_poreset_status (ck_cpu1_poreset_status), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), + .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), + .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), + .ck_cpu2_commrx (ck_cpu2_commrx), + .ck_cpu2_commtx (ck_cpu2_commtx), + .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), + .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), + .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), + .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), + .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), + .ck_cpu2_event_reg (ck_cpu2_event_reg), + .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), + .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), + .ck_cpu2_ncommirq (ck_cpu2_ncommirq), + .ck_cpu2_npmuirq (ck_cpu2_npmuirq), + .ck_cpu2_poreset_status (ck_cpu2_poreset_status), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), + .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), + .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), + .ck_cpu3_commrx (ck_cpu3_commrx), + .ck_cpu3_commtx (ck_cpu3_commtx), + .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), + .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), + .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), + .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), + .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), + .ck_cpu3_event_reg (ck_cpu3_event_reg), + .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), + .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), + .ck_cpu3_ncommirq (ck_cpu3_ncommirq), + .ck_cpu3_npmuirq (ck_cpu3_npmuirq), + .ck_cpu3_poreset_status (ck_cpu3_poreset_status), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), + .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), + .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), + .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), + .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), + .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), + .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), + .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), + .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), + .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), + .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), + .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), + .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), + .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), + .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), + .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), + .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), + .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), + .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), + .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), + .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), + .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), + .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), + .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), + .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), + .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), + .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), + .ck_l2_ace_inactive (ck_l2_ace_inactive), + .ck_l2_acp_inactive (ck_l2_acp_inactive), + .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), + + // inputs + .ACINACTM (ACINACTM), + .AINACTS (AINACTS), + .CPUQREQn (CPUQREQn[`MAIA_CN:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .ck_gclkfr (ck_gclkfr), + .clrexmon_c1 (clrexmon_c1), + .commrx_cpu0_i (commrx_cpu0_i), + .commrx_cpu1_i (commrx_cpu1_i), + .commrx_cpu2_i (commrx_cpu2_i), + .commrx_cpu3_i (commrx_cpu3_i), + .commtx_cpu0_i (commtx_cpu0_i), + .commtx_cpu1_i (commtx_cpu1_i), + .commtx_cpu2_i (commtx_cpu2_i), + .commtx_cpu3_i (commtx_cpu3_i), + .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), + .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), + .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), + .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), + .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), + .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), + .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), + .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_cpu0_flush (ds_cpu0_flush), + .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), + .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), + .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_cpu0_reset_req (ds_cpu0_reset_req), + .ds_cpu0_sevl_req (ds_cpu0_sevl_req), + .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_cpu0_wfe_req (ds_cpu0_wfe_req), + .ds_cpu0_wfi_req (ds_cpu0_wfi_req), + .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_cpu1_flush (ds_cpu1_flush), + .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), + .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), + .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_cpu1_reset_req (ds_cpu1_reset_req), + .ds_cpu1_sevl_req (ds_cpu1_sevl_req), + .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_cpu1_wfe_req (ds_cpu1_wfe_req), + .ds_cpu1_wfi_req (ds_cpu1_wfi_req), + .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_cpu2_flush (ds_cpu2_flush), + .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), + .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), + .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_cpu2_reset_req (ds_cpu2_reset_req), + .ds_cpu2_sevl_req (ds_cpu2_sevl_req), + .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_cpu2_wfe_req (ds_cpu2_wfe_req), + .ds_cpu2_wfi_req (ds_cpu2_wfi_req), + .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_cpu3_flush (ds_cpu3_flush), + .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), + .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), + .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_cpu3_reset_req (ds_cpu3_reset_req), + .ds_cpu3_sevl_req (ds_cpu3_sevl_req), + .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_cpu3_wfe_req (ds_cpu3_wfe_req), + .ds_cpu3_wfi_req (ds_cpu3_wfi_req), + .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), + .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), + .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), + .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), + .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), + .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), + .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), + .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), + .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_cpu0_snp_active (l2_cpu0_snp_active), + .l2_cpu1_snp_active (l2_cpu1_snp_active), + .l2_cpu2_snp_active (l2_cpu2_snp_active), + .l2_cpu3_snp_active (l2_cpu3_snp_active), + .l2_idle (l2_idle), + .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), + .l2_reset3 (l2_reset3), + .l2_sky_link_stopped (1'b1), + .ls_cpu0_clrexmon (ls_cpu0_clrexmon), + .ls_cpu1_clrexmon (ls_cpu1_clrexmon), + .ls_cpu2_clrexmon (ls_cpu2_clrexmon), + .ls_cpu3_clrexmon (ls_cpu3_clrexmon), + .nCORERESET (nCORERESET[`MAIA_CN:0]), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .ncommirq_cpu0_i (ncommirq_cpu0_i), + .ncommirq_cpu1_i (ncommirq_cpu1_i), + .ncommirq_cpu2_i (ncommirq_cpu2_i), + .ncommirq_cpu3_i (ncommirq_cpu3_i), + .npmuirq_cpu0_i (npmuirq_cpu0_i), + .npmuirq_cpu1_i (npmuirq_cpu1_i), + .npmuirq_cpu2_i (npmuirq_cpu2_i), + .npmuirq_cpu3_i (npmuirq_cpu3_i), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_event_sev (tm_cpu0_event_sev), + .tm_cpu1_event_sev (tm_cpu1_event_sev), + .tm_cpu2_event_sev (tm_cpu2_event_sev), + .tm_cpu3_event_sev (tm_cpu3_event_sev) + ); // uck_logic + + maia_cpu_io ucpu_io( // outputs + .aa64naa32_cpu0_o (aa64naa32_cpu0_o), + .aa64naa32_cpu1_o (aa64naa32_cpu1_o), + .aa64naa32_cpu2_o (aa64naa32_cpu2_o), + .aa64naa32_cpu3_o (aa64naa32_cpu3_o), + .cfgend_cpu0_o (cfgend_cpu0_o), + .cfgend_cpu1_o (cfgend_cpu1_o), + .cfgend_cpu2_o (cfgend_cpu2_o), + .cfgend_cpu3_o (cfgend_cpu3_o), + .cfgte_cpu0_o (cfgte_cpu0_o), + .cfgte_cpu1_o (cfgte_cpu1_o), + .cfgte_cpu2_o (cfgte_cpu2_o), + .cfgte_cpu3_o (cfgte_cpu3_o), + .clrexmon_c1 (clrexmon_c1), + .clrexmonack_o (CLREXMONACK), + .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), + .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), + .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), + .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), + .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), + .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), + .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), + .commrx_o (COMMRX[`MAIA_CN:0]), + .commtx_o (COMMTX[`MAIA_CN:0]), + .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), + .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), + .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), + .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), + .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), + .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), + .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), + .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu0_o (cryptodisable_cpu0_o), + .cryptodisable_cpu1_o (cryptodisable_cpu1_o), + .cryptodisable_cpu2_o (cryptodisable_cpu2_o), + .cryptodisable_cpu3_o (cryptodisable_cpu3_o), + .dbgack_o (DBGACK[`MAIA_CN:0]), + .dbgen_cpu0_o (dbgen_cpu0_o), + .dbgen_cpu1_o (dbgen_cpu1_o), + .dbgen_cpu2_o (dbgen_cpu2_o), + .dbgen_cpu3_o (dbgen_cpu3_o), + .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), + .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), + .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), + .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), + .dbgnopwrdwn_o (DBGNOPWRDWN[`MAIA_CN:0]), + .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), + .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), + .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), + .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), + .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), + .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), + .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), + .dbgrstreq_o (DBGRSTREQ[`MAIA_CN:0]), + .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), + .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), + .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), + .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), + .dftramhold_cpu0_o (dftramhold_cpu0_o), + .dftramhold_cpu1_o (dftramhold_cpu1_o), + .dftramhold_cpu2_o (dftramhold_cpu2_o), + .dftramhold_cpu3_o (dftramhold_cpu3_o), + .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), + .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), + .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), + .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), + .dftse_cpu0_o (dftse_cpu0_o), + .dftse_cpu1_o (dftse_cpu1_o), + .dftse_cpu2_o (dftse_cpu2_o), + .dftse_cpu3_o (dftse_cpu3_o), + .eventi_sev (eventi_sev), + .evento_o (EVENTO), + .giccdisable_cpu0_o (giccdisable_cpu0_o), + .giccdisable_cpu1_o (giccdisable_cpu1_o), + .giccdisable_cpu2_o (giccdisable_cpu2_o), + .giccdisable_cpu3_o (giccdisable_cpu3_o), + .ncommirq_o (nCOMMIRQ[`MAIA_CN:0]), + .ncorereset_cpu0_o (ncorereset_cpu0_o), + .ncorereset_cpu1_o (ncorereset_cpu1_o), + .ncorereset_cpu2_o (ncorereset_cpu2_o), + .ncorereset_cpu3_o (ncorereset_cpu3_o), + .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), + .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), + .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), + .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), + .niden_cpu0_o (niden_cpu0_o), + .niden_cpu1_o (niden_cpu1_o), + .niden_cpu2_o (niden_cpu2_o), + .niden_cpu3_o (niden_cpu3_o), + .nmbistreset_cpu0_o (nmbistreset_cpu0_o), + .nmbistreset_cpu1_o (nmbistreset_cpu1_o), + .nmbistreset_cpu2_o (nmbistreset_cpu2_o), + .nmbistreset_cpu3_o (nmbistreset_cpu3_o), + .npmuirq_o (nPMUIRQ[`MAIA_CN:0]), + .pmuevent0_o (PMUEVENT0[24:0]), + .pmuevent1_o (PMUEVENT1[24:0]), + .pmuevent2_o (PMUEVENT2[24:0]), + .pmuevent3_o (PMUEVENT3[24:0]), + .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), + .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), + .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), + .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), + .smpen_o (SMPEN[`MAIA_CN:0]), + .spiden_cpu0_o (spiden_cpu0_o), + .spiden_cpu1_o (spiden_cpu1_o), + .spiden_cpu2_o (spiden_cpu2_o), + .spiden_cpu3_o (spiden_cpu3_o), + .spniden_cpu0_o (spniden_cpu0_o), + .spniden_cpu1_o (spniden_cpu1_o), + .spniden_cpu2_o (spniden_cpu2_o), + .spniden_cpu3_o (spniden_cpu3_o), + .vinithi_cpu0_o (vinithi_cpu0_o), + .vinithi_cpu1_o (vinithi_cpu1_o), + .vinithi_cpu2_o (vinithi_cpu2_o), + .vinithi_cpu3_o (vinithi_cpu3_o), + + // inputs + .aa64naa32_i (AA64nAA32[`MAIA_CN:0]), + .cfgend_i (CFGEND[`MAIA_CN:0]), + .cfgte_i (CFGTE[`MAIA_CN:0]), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), + .ck_cpu0_commrx (ck_cpu0_commrx), + .ck_cpu0_commtx (ck_cpu0_commtx), + .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), + .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), + .ck_cpu0_ncommirq (ck_cpu0_ncommirq), + .ck_cpu0_npmuirq (ck_cpu0_npmuirq), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), + .ck_cpu1_commrx (ck_cpu1_commrx), + .ck_cpu1_commtx (ck_cpu1_commtx), + .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), + .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), + .ck_cpu1_ncommirq (ck_cpu1_ncommirq), + .ck_cpu1_npmuirq (ck_cpu1_npmuirq), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), + .ck_cpu2_commrx (ck_cpu2_commrx), + .ck_cpu2_commtx (ck_cpu2_commtx), + .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), + .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), + .ck_cpu2_ncommirq (ck_cpu2_ncommirq), + .ck_cpu2_npmuirq (ck_cpu2_npmuirq), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), + .ck_cpu3_commrx (ck_cpu3_commrx), + .ck_cpu3_commtx (ck_cpu3_commtx), + .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), + .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), + .ck_cpu3_ncommirq (ck_cpu3_ncommirq), + .ck_cpu3_npmuirq (ck_cpu3_npmuirq), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), + .ck_gclkfr (ck_gclkfr), + .clrexmonreq_i (CLREXMONREQ), + .clusteridaff1_i (CLUSTERIDAFF1[7:0]), + .clusteridaff2_i (CLUSTERIDAFF2[7:0]), + .cp15sdisable_i (CP15SDISABLE[`MAIA_CN:0]), + .cryptodisable_i (CRYPTODISABLE[`MAIA_CN:0]), + .dbgack_cpu0_i (dbgack_cpu0_i), + .dbgack_cpu1_i (dbgack_cpu1_i), + .dbgack_cpu2_i (dbgack_cpu2_i), + .dbgack_cpu3_i (dbgack_cpu3_i), + .dbgen_i (DBGEN[`MAIA_CN:0]), + .dbgl1rstdisable_i (DBGL1RSTDISABLE), + .dbgromaddr_i (DBGROMADDR[43:12]), + .dbgromaddrv_i (DBGROMADDRV), + .dftcrclkdisable_i (DFTCRCLKDISABLE[`MAIA_CN:0]), + .dftramhold_i (DFTRAMHOLD), + .dftrstdisable_i (DFTRSTDISABLE), + .dftse_i (DFTSE), + .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_cpu0_sev_req (ds_cpu0_sev_req), + .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_cpu1_sev_req (ds_cpu1_sev_req), + .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_cpu2_sev_req (ds_cpu2_sev_req), + .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_cpu3_sev_req (ds_cpu3_sev_req), + .eventi_i (EVENTI), + .giccdisable_i (GICCDISABLE), + .l2_reset3 (l2_reset3), + .ncorereset_i (nCORERESET[`MAIA_CN:0]), + .ncpuporeset_i (nCPUPORESET[`MAIA_CN:0]), + .niden_i (NIDEN[`MAIA_CN:0]), + .nmbistreset_i (nMBISTRESET), + .pm_export_cpu0_i (pm_export_cpu0_i), + .pm_export_cpu1_i (pm_export_cpu1_i), + .pm_export_cpu2_i (pm_export_cpu2_i), + .pm_export_cpu3_i (pm_export_cpu3_i), + .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), + .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), + .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), + .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]), + .rvbaraddr0_i (RVBARADDR0[43:2]), + .rvbaraddr1_i (RVBARADDR1[43:2]), + .rvbaraddr2_i (RVBARADDR2[43:2]), + .rvbaraddr3_i (RVBARADDR3[43:2]), + .spiden_i (SPIDEN[`MAIA_CN:0]), + .spniden_i (SPNIDEN[`MAIA_CN:0]), + .vinithi_i (VINITHI[`MAIA_CN:0]) + ); // ucpu_io + + maia_dt_sb udt_sb( // outputs + .afreadym0_o (AFREADYM0), + .afreadym1_o (AFREADYM1), + .afreadym2_o (AFREADYM2), + .afreadym3_o (AFREADYM3), + .afvalidm_cpu0_o (afvalidm_cpu0_o), + .afvalidm_cpu1_o (afvalidm_cpu1_o), + .afvalidm_cpu2_o (afvalidm_cpu2_o), + .afvalidm_cpu3_o (afvalidm_cpu3_o), + .atbytesm0_o (ATBYTESM0[1:0]), + .atbytesm1_o (ATBYTESM1[1:0]), + .atbytesm2_o (ATBYTESM2[1:0]), + .atbytesm3_o (ATBYTESM3[1:0]), + .atclken_cpu0_o (atclken_cpu0_o), + .atclken_cpu1_o (atclken_cpu1_o), + .atclken_cpu2_o (atclken_cpu2_o), + .atclken_cpu3_o (atclken_cpu3_o), + .atdatam0_o (ATDATAM0[31:0]), + .atdatam1_o (ATDATAM1[31:0]), + .atdatam2_o (ATDATAM2[31:0]), + .atdatam3_o (ATDATAM3[31:0]), + .atidm0_o (ATIDM0[6:0]), + .atidm1_o (ATIDM1[6:0]), + .atidm2_o (ATIDM2[6:0]), + .atidm3_o (ATIDM3[6:0]), + .atreadym_cpu0_o (atreadym_cpu0_o), + .atreadym_cpu1_o (atreadym_cpu1_o), + .atreadym_cpu2_o (atreadym_cpu2_o), + .atreadym_cpu3_o (atreadym_cpu3_o), + .atvalidm0_o (ATVALIDM0), + .atvalidm1_o (ATVALIDM1), + .atvalidm2_o (ATVALIDM2), + .atvalidm3_o (ATVALIDM3), + .syncreqm_cpu0_o (syncreqm_cpu0_o), + .syncreqm_cpu1_o (syncreqm_cpu1_o), + .syncreqm_cpu2_o (syncreqm_cpu2_o), + .syncreqm_cpu3_o (syncreqm_cpu3_o), + .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), + .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), + .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), + .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), + + // inputs + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .TSVALUEB (TSVALUEB[63:0]), + .afreadym_cpu0_i (afreadym_cpu0_i), + .afreadym_cpu1_i (afreadym_cpu1_i), + .afreadym_cpu2_i (afreadym_cpu2_i), + .afreadym_cpu3_i (afreadym_cpu3_i), + .afvalidm0_i (AFVALIDM0), + .afvalidm1_i (AFVALIDM1), + .afvalidm2_i (AFVALIDM2), + .afvalidm3_i (AFVALIDM3), + .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), + .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), + .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), + .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), + .atclken_i (ATCLKEN), + .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), + .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), + .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), + .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), + .atidm_cpu0_i (atidm_cpu0_i[6:0]), + .atidm_cpu1_i (atidm_cpu1_i[6:0]), + .atidm_cpu2_i (atidm_cpu2_i[6:0]), + .atidm_cpu3_i (atidm_cpu3_i[6:0]), + .atreadym0_i (ATREADYM0), + .atreadym1_i (ATREADYM1), + .atreadym2_i (ATREADYM2), + .atreadym3_i (ATREADYM3), + .atvalidm_cpu0_i (atvalidm_cpu0_i), + .atvalidm_cpu1_i (atvalidm_cpu1_i), + .atvalidm_cpu2_i (atvalidm_cpu2_i), + .atvalidm_cpu3_i (atvalidm_cpu3_i), + .ck_gclkfr (ck_gclkfr), + .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), + .etclken_cpu0_i (etclken_cpu0_i), + .etclken_cpu1_i (etclken_cpu1_i), + .etclken_cpu2_i (etclken_cpu2_i), + .etclken_cpu3_i (etclken_cpu3_i), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nMBISTRESET (nMBISTRESET), + .syncreqm0_i (SYNCREQM0), + .syncreqm1_i (SYNCREQM1), + .syncreqm2_i (SYNCREQM2), + .syncreqm3_i (SYNCREQM3) + ); // udt_sb + + maia_ncpu_reg_rep uncpu_reg_rep( // outputs + .ds_cpu0_ic_aa64naa32_reg_o (ds_cpu0_ic_aa64naa32_i), + .ds_cpu0_ic_cpsr_mode_reg_o (ds_cpu0_ic_cpsr_mode_i[4:0]), + .ds_cpu0_ic_hcr_change_reg_o (ds_cpu0_ic_hcr_change_i), + .ds_cpu0_ic_sample_spr_reg_o (ds_cpu0_ic_sample_spr_i), + .ds_cpu0_ic_scr_change_reg_o (ds_cpu0_ic_scr_change_i), + .ds_cpu1_ic_aa64naa32_reg_o (ds_cpu1_ic_aa64naa32_i), + .ds_cpu1_ic_cpsr_mode_reg_o (ds_cpu1_ic_cpsr_mode_i[4:0]), + .ds_cpu1_ic_hcr_change_reg_o (ds_cpu1_ic_hcr_change_i), + .ds_cpu1_ic_sample_spr_reg_o (ds_cpu1_ic_sample_spr_i), + .ds_cpu1_ic_scr_change_reg_o (ds_cpu1_ic_scr_change_i), + .ds_cpu2_ic_aa64naa32_reg_o (ds_cpu2_ic_aa64naa32_i), + .ds_cpu2_ic_cpsr_mode_reg_o (ds_cpu2_ic_cpsr_mode_i[4:0]), + .ds_cpu2_ic_hcr_change_reg_o (ds_cpu2_ic_hcr_change_i), + .ds_cpu2_ic_sample_spr_reg_o (ds_cpu2_ic_sample_spr_i), + .ds_cpu2_ic_scr_change_reg_o (ds_cpu2_ic_scr_change_i), + .ds_cpu3_ic_aa64naa32_reg_o (ds_cpu3_ic_aa64naa32_i), + .ds_cpu3_ic_cpsr_mode_reg_o (ds_cpu3_ic_cpsr_mode_i[4:0]), + .ds_cpu3_ic_hcr_change_reg_o (ds_cpu3_ic_hcr_change_i), + .ds_cpu3_ic_sample_spr_reg_o (ds_cpu3_ic_sample_spr_i), + .ds_cpu3_ic_scr_change_reg_o (ds_cpu3_ic_scr_change_i), + .ic_block_eoi_sgi_wr_reg_o (ic_block_eoi_sgi_wr[`MAIA_CN:0]), + .ic_el_change_complete_reg_o (ic_el_change_complete[`MAIA_CN:0]), + .ic_hcr_change_complete_reg_o (ic_hcr_change_complete[`MAIA_CN:0]), + .ic_ich_el2_tall0_reg_o (ic_ich_el2_tall0[`MAIA_CN:0]), + .ic_ich_el2_tall1_reg_o (ic_ich_el2_tall1[`MAIA_CN:0]), + .ic_ich_el2_tc_reg_o (ic_ich_el2_tc[`MAIA_CN:0]), + .ic_nfiq_reg_o (ic_nfiq[`MAIA_CN:0]), + .ic_nirq_reg_o (ic_nirq[`MAIA_CN:0]), + .ic_nsei_reg_o (ic_nsei[`MAIA_CN:0]), + .ic_nvfiq_reg_o (ic_nvfiq[`MAIA_CN:0]), + .ic_nvirq_reg_o (ic_nvirq[`MAIA_CN:0]), + .ic_nvsei_reg_o (ic_nvsei[`MAIA_CN:0]), + .ic_sample_spr_reg_o (ic_sample_spr[`MAIA_CN:0]), + .ic_scr_change_complete_reg_o (ic_scr_change_complete[`MAIA_CN:0]), + .ic_sra_el1ns_en_reg_o (ic_sra_el1ns_en[`MAIA_CN:0]), + .ic_sra_el1s_en_reg_o (ic_sra_el1s_en[`MAIA_CN:0]), + .ic_sra_el2_en_reg_o (ic_sra_el2_en[`MAIA_CN:0]), + .ic_sra_el3_en_reg_o (ic_sra_el3_en[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap_reg_o (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap_reg_o (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap_reg_o (ic_sre_el1s_mon_trap[`MAIA_CN:0]), + .ic_sre_el2_mon_trap_reg_o (ic_sre_el2_mon_trap[`MAIA_CN:0]), + + // inputs + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), + .ic_el_change_complete (ic_el_change_complete_o[`MAIA_CN:0]), + .ic_hcr_change_complete (ic_hcr_change_complete_o[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .ic_sample_spr (ic_sample_spr_o[`MAIA_CN:0]), + .ic_scr_change_complete (ic_scr_change_complete_o[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]) + ); // uncpu_reg_rep + +//----------------------------------------------------------------------------- +// OVL Assertions +//----------------------------------------------------------------------------- +`ifdef ARM_ASSERT_ON + `include "maia_noncpu_feq28_val.v" +`endif + +endmodule // maia_noncpu_feq28 + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28_s.v b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28_s.v new file mode 100644 index 0000000000..1517a5c1ba --- /dev/null +++ b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_feq28_s.v @@ -0,0 +1,7951 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: maia_noncpu_feq28_s.v $ +// Checked In : $Date: 2015-05-06 10:47:09 -0500 (Wed, 06 May 2015) $ +// Revision : $Revision: 73443 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// +// This is top-level interconnect layer for the non-CPU blocks at the Maia top-level. +// + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +`define MAIA_CN 3 + +module maia_noncpu_feq28_s ( + CLK, + CLKEN, + nCPUPORESET, + nCORERESET, + nL2RESET, + L2RSTDISABLE, + WARMRSTREQ, + CFGEND, + VINITHI, + CFGTE, + CP15SDISABLE, + CLUSTERIDAFF1, + CLUSTERIDAFF2, + AA64nAA32, + RVBARADDR0, +// BEGIN INCLUDE FOR CPU1 + RVBARADDR1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + RVBARADDR2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + RVBARADDR3, +// END INCLUDE FOR CPU3 + CRYPTODISABLE, + nFIQ, + nIRQ, + nSEI, + nREI, + nVFIQ, + nVIRQ, + nVSEI, +// BEGIN NO-GIC pins + nVCPUMNTIRQ, +// END NO-GIC pins + PERIPHBASE, +// BEGIN NO-GIC pins + GICCDISABLE, + ICDTVALID, + ICDTREADY, + ICDTDATA, + ICDTLAST, + ICDTDEST, + ICCTVALID, + ICCTREADY, + ICCTDATA, + ICCTLAST, + ICCTID, +// END NO-GIC pins + CNTVALUEB, + CNTCLKEN, + nCNTPNSIRQ, + nCNTPSIRQ, + nCNTVIRQ, + nCNTHPIRQ, + CLREXMONREQ, + CLREXMONACK, + EVENTI, + EVENTO, + STANDBYWFI, + STANDBYWFE, + STANDBYWFIL2, + SMPEN, + CPUQACTIVE, + CPUQREQn, + CPUQACCEPTn, + CPUQDENY, + L2QACTIVE, + L2QREQn, + L2QACCEPTn, + L2QDENY, + L2FLUSHREQ, + L2FLUSHDONE, + nINTERRIRQ, + nEXTERRIRQ, + SYSBARDISABLE, + BROADCASTINNER, + BROADCASTOUTER, + BROADCASTCACHEMAINT, + SCLKEN, + SINACT, + NODEID, + TXSACTIVE, + RXSACTIVE, + TXLINKACTIVEREQ, + TXLINKACTIVEACK, + RXLINKACTIVEREQ, + RXLINKACTIVEACK, + TXREQFLITPEND, + TXREQFLITV, + TXREQFLIT, + REQMEMATTR, + TXREQLCRDV, + TXRSPFLITPEND, + TXRSPFLITV, + TXRSPFLIT, + TXRSPLCRDV, + TXDATFLITPEND, + TXDATFLITV, + TXDATFLIT, + TXDATLCRDV, + RXSNPFLITPEND, + RXSNPFLITV, + RXSNPFLIT, + RXSNPLCRDV, + RXRSPFLITPEND, + RXRSPFLITV, + RXRSPFLIT, + RXRSPLCRDV, + RXDATFLITPEND, + RXDATFLITV, + RXDATFLIT, + RXDATLCRDV, + SAMMNBASE, + SAMADDRMAP0, + SAMADDRMAP1, + SAMADDRMAP2, + SAMADDRMAP3, + SAMADDRMAP4, + SAMADDRMAP5, + SAMADDRMAP6, + SAMADDRMAP7, + SAMADDRMAP8, + SAMADDRMAP9, + SAMADDRMAP10, + SAMADDRMAP11, + SAMADDRMAP12, + SAMADDRMAP13, + SAMADDRMAP14, + SAMADDRMAP15, + SAMADDRMAP16, + SAMADDRMAP17, + SAMADDRMAP18, + SAMADDRMAP19, + SAMMNNODEID, + SAMHNI0NODEID, + SAMHNI1NODEID, + SAMHNF0NODEID, + SAMHNF1NODEID, + SAMHNF2NODEID, + SAMHNF3NODEID, + SAMHNF4NODEID, + SAMHNF5NODEID, + SAMHNF6NODEID, + SAMHNF7NODEID, + SAMHNFMODE, + ACLKENS, + AINACTS, +// BEGIN NO-ACP pins + AWREADYS, + AWVALIDS, + AWIDS, + AWADDRS, + AWLENS, + AWCACHES, + AWUSERS, + AWPROTS, + WREADYS, + WVALIDS, + WDATAS, + WSTRBS, + WLASTS, + BREADYS, + BVALIDS, + BIDS, + BRESPS, + ARREADYS, + ARVALIDS, + ARIDS, + ARADDRS, + ARLENS, + ARCACHES, + ARUSERS, + ARPROTS, + RREADYS, + RVALIDS, + RIDS, + RDATAS, + RRESPS, + RLASTS, +// END NO-ACP pins + DBGROMADDR, + DBGROMADDRV, + DBGACK, + nCOMMIRQ, + COMMRX, + COMMTX, + DBGRSTREQ, + DBGNOPWRDWN, + DBGL1RSTDISABLE, + nPMUIRQ, + PMUEVENT0, +// BEGIN INCLUDE FOR CPU1 + PMUEVENT1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + PMUEVENT2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + PMUEVENT3, +// END INCLUDE FOR CPU3 + ATCLKEN, + TSVALUEB, + ATREADYM0, + AFVALIDM0, + ATDATAM0, + ATVALIDM0, + ATBYTESM0, + AFREADYM0, + ATIDM0, + SYNCREQM0, +// BEGIN INCLUDE FOR CPU1 + ATREADYM1, + AFVALIDM1, + ATDATAM1, + ATVALIDM1, + ATBYTESM1, + AFREADYM1, + ATIDM1, + SYNCREQM1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ATREADYM2, + AFVALIDM2, + ATDATAM2, + ATVALIDM2, + ATBYTESM2, + AFREADYM2, + ATIDM2, + SYNCREQM2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ATREADYM3, + AFVALIDM3, + ATDATAM3, + ATVALIDM3, + ATBYTESM3, + AFREADYM3, + ATIDM3, + SYNCREQM3, +// END INCLUDE FOR CPU3 + PCLKDBG, + PCLKENDBG, + nPRESETDBG, + PSELDBG, + PADDRDBG, + PADDRDBG31, + PENABLEDBG, + PWRITEDBG, + PWDATADBG, + PRDATADBG, + PREADYDBG, + PSLVERRDBG, + EDBGRQ, + PMUSNAPSHOTREQ, + PMUSNAPSHOTACK, + DBGPWRDUP, + DBGPWRUPREQ, + CTICHIN, + CTICHOUTACK, + CTICHOUT, + CTICHINACK, + CISBYPASS, + CIHSBYPASS, + CTIIRQ, + CTIIRQACK, + DBGEN, + NIDEN, + SPIDEN, + SPNIDEN, + DFTSE, + DFTRSTDISABLE, + DFTCRCLKDISABLE, + DFTL2CLKDISABLE, + DFTRAMHOLD, + DFTCLKBYPASS, + DFTMCPHOLD, + nMBISTRESET, + MBISTREQ, + +//----------------------------------------------------------------------------- +// Signals from maia -> maia_cpu_io -> maia_cpu +//----------------------------------------------------------------------------- +// Outputs to maia_cpu + ncpuporeset_cpu0_o, + ncorereset_cpu0_o, + + cfgend_cpu0_o, + cfgte_cpu0_o, + cp15sdisable_cpu0_o, + vinithi_cpu0_o, + clusteridaff1_cpu0_o, + clusteridaff2_cpu0_o, + cpuid_cpu0_o, + aa64naa32_cpu0_o, + rvbaraddr_cpu0_o, + cryptodisable_cpu0_o, + giccdisable_cpu0_o, + + dbgromaddr_cpu0_o, + dbgromaddrv_cpu0_o, + dbgl1rstdisable_cpu0_o, + + dbgen_cpu0_o, + niden_cpu0_o, + spiden_cpu0_o, + spniden_cpu0_o, + + tsvalueb_cpu0_o, + + atclken_cpu0_o, + afvalidm_cpu0_o, + atreadym_cpu0_o, + syncreqm_cpu0_o, + + dftse_cpu0_o, + dftrstdisable_cpu0_o, + dftcrclkdisable_cpu0_o, + dftramhold_cpu0_o, + + nmbistreset_cpu0_o, + +// BEGIN INCLUDE FOR CPU1 + ncpuporeset_cpu1_o, + ncorereset_cpu1_o, + + cfgend_cpu1_o, + cfgte_cpu1_o, + cp15sdisable_cpu1_o, + vinithi_cpu1_o, + clusteridaff1_cpu1_o, + clusteridaff2_cpu1_o, + cpuid_cpu1_o, + aa64naa32_cpu1_o, + rvbaraddr_cpu1_o, + cryptodisable_cpu1_o, + giccdisable_cpu1_o, + + dbgromaddr_cpu1_o, + dbgromaddrv_cpu1_o, + dbgl1rstdisable_cpu1_o, + + dbgen_cpu1_o, + niden_cpu1_o, + spiden_cpu1_o, + spniden_cpu1_o, + + tsvalueb_cpu1_o, + + atclken_cpu1_o, + afvalidm_cpu1_o, + atreadym_cpu1_o, + syncreqm_cpu1_o, + + dftse_cpu1_o, + dftrstdisable_cpu1_o, + dftcrclkdisable_cpu1_o, + dftramhold_cpu1_o, + + nmbistreset_cpu1_o, +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + ncpuporeset_cpu2_o, + ncorereset_cpu2_o, + + cfgend_cpu2_o, + cfgte_cpu2_o, + cp15sdisable_cpu2_o, + vinithi_cpu2_o, + clusteridaff1_cpu2_o, + clusteridaff2_cpu2_o, + cpuid_cpu2_o, + aa64naa32_cpu2_o, + rvbaraddr_cpu2_o, + cryptodisable_cpu2_o, + giccdisable_cpu2_o, + + dbgromaddr_cpu2_o, + dbgromaddrv_cpu2_o, + dbgl1rstdisable_cpu2_o, + + dbgen_cpu2_o, + niden_cpu2_o, + spiden_cpu2_o, + spniden_cpu2_o, + + tsvalueb_cpu2_o, + + atclken_cpu2_o, + afvalidm_cpu2_o, + atreadym_cpu2_o, + syncreqm_cpu2_o, + + dftse_cpu2_o, + dftrstdisable_cpu2_o, + dftcrclkdisable_cpu2_o, + dftramhold_cpu2_o, + + nmbistreset_cpu2_o, +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + ncpuporeset_cpu3_o, + ncorereset_cpu3_o, + + cfgend_cpu3_o, + cfgte_cpu3_o, + cp15sdisable_cpu3_o, + vinithi_cpu3_o, + clusteridaff1_cpu3_o, + clusteridaff2_cpu3_o, + cpuid_cpu3_o, + aa64naa32_cpu3_o, + rvbaraddr_cpu3_o, + cryptodisable_cpu3_o, + giccdisable_cpu3_o, + + dbgromaddr_cpu3_o, + dbgromaddrv_cpu3_o, + dbgl1rstdisable_cpu3_o, + + dbgen_cpu3_o, + niden_cpu3_o, + spiden_cpu3_o, + spniden_cpu3_o, + + tsvalueb_cpu3_o, + + atclken_cpu3_o, + afvalidm_cpu3_o, + atreadym_cpu3_o, + syncreqm_cpu3_o, + + dftse_cpu3_o, + dftrstdisable_cpu3_o, + dftcrclkdisable_cpu3_o, + dftramhold_cpu3_o, + + nmbistreset_cpu3_o, +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Signals from maia_cpu -> maia_cpu_io -> maia +//----------------------------------------------------------------------------- +// Inputs from maia_cpu + ds_cpu0_sev_req, + ds_cpu0_sevl_req, + ds_cpu0_cpuectlr_smp, + + ncommirq_cpu0_i, + commrx_cpu0_i, + commtx_cpu0_i, + dbgack_cpu0_i, + dbgrstreq_cpu0_i, + dbgnopwrdwn_cpu0_i, + + npmuirq_cpu0_i, + pmuevent_cpu0_i, + pm_export_cpu0_i, + + etclken_cpu0_i, + afreadym_cpu0_i, + atbytesm_cpu0_i, + atdatam_cpu0_i, + atidm_cpu0_i, + atvalidm_cpu0_i, + +// BEGIN INCLUDE FOR CPU1 + ds_cpu1_sev_req, + ds_cpu1_sevl_req, + ds_cpu1_cpuectlr_smp, + + ncommirq_cpu1_i, + commrx_cpu1_i, + commtx_cpu1_i, + dbgack_cpu1_i, + dbgrstreq_cpu1_i, + dbgnopwrdwn_cpu1_i, + + npmuirq_cpu1_i, + pmuevent_cpu1_i, + pm_export_cpu1_i, + + etclken_cpu1_i, + afreadym_cpu1_i, + atbytesm_cpu1_i, + atdatam_cpu1_i, + atidm_cpu1_i, + atvalidm_cpu1_i, +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + ds_cpu2_sev_req, + ds_cpu2_sevl_req, + ds_cpu2_cpuectlr_smp, + + ncommirq_cpu2_i, + commrx_cpu2_i, + commtx_cpu2_i, + dbgack_cpu2_i, + dbgrstreq_cpu2_i, + dbgnopwrdwn_cpu2_i, + + npmuirq_cpu2_i, + pmuevent_cpu2_i, + pm_export_cpu2_i, + + etclken_cpu2_i, + afreadym_cpu2_i, + atbytesm_cpu2_i, + atdatam_cpu2_i, + atidm_cpu2_i, + atvalidm_cpu2_i, +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + ds_cpu3_sev_req, + ds_cpu3_sevl_req, + ds_cpu3_cpuectlr_smp, + + ncommirq_cpu3_i, + commrx_cpu3_i, + commtx_cpu3_i, + dbgack_cpu3_i, + dbgrstreq_cpu3_i, + dbgnopwrdwn_cpu3_i, + + npmuirq_cpu3_i, + pmuevent_cpu3_i, + pm_export_cpu3_i, + + etclken_cpu3_i, + afreadym_cpu3_i, + atbytesm_cpu3_i, + atdatam_cpu3_i, + atidm_cpu3_i, + atvalidm_cpu3_i, +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// L2 interface +//----------------------------------------------------------------------------- + l2_cpu0_mbist1_addr_b1, + l2_cpu0_mbist1_array_b1, + l2_cpu0_mbist1_be_b1, + l2_cpu0_mbist1_en_b1, + l2_cpu0_mbist1_rd_en_b1, + l2_cpu0_mbist1_wr_en_b1, + l2_cpu0_mbist1_all_b1, +// BEGIN INCLUDE FOR CPU1 + l2_cpu1_mbist1_addr_b1, + l2_cpu1_mbist1_array_b1, + l2_cpu1_mbist1_be_b1, + l2_cpu1_mbist1_en_b1, + l2_cpu1_mbist1_rd_en_b1, + l2_cpu1_mbist1_wr_en_b1, + l2_cpu1_mbist1_all_b1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + l2_cpu2_mbist1_addr_b1, + l2_cpu2_mbist1_array_b1, + l2_cpu2_mbist1_be_b1, + l2_cpu2_mbist1_en_b1, + l2_cpu2_mbist1_rd_en_b1, + l2_cpu2_mbist1_wr_en_b1, + l2_cpu2_mbist1_all_b1, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + l2_cpu3_mbist1_addr_b1, + l2_cpu3_mbist1_array_b1, + l2_cpu3_mbist1_be_b1, + l2_cpu3_mbist1_en_b1, + l2_cpu3_mbist1_rd_en_b1, + l2_cpu3_mbist1_wr_en_b1, + l2_cpu3_mbist1_all_b1, +// END INCLUDE FOR CPU3 + +// BEGIN L2-CPU interface + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + l2_cpu0_cfg_ecc_en, + l2_cpu0_arb_thrshld_timeout_en, + l2_cpu0_disable_clean_evict_opt, + l2_cpu0_dext_err_r2, + l2_cpu0_dext_err_type_r2, + l2_cpu0_dsngl_ecc_err_r3, + l2_cpu0_ddbl_ecc_err_r3, + l2_cpu0_ddata_r2, + l2_cpu0_barrier_done, + l2_cpu0_spec_valid, + l2_cpu0_spec_bufid, + l2_cpu0_rvalid, + l2_cpu0_rstate, + l2_cpu0_rexfail, + l2_cpu0_rbufid, + l2_cpu0_dvalid_r1, + l2_cpu0_dlast_r1, + l2_cpu0_dbufid_r1, + l2_cpu0_iext_err_r2, + l2_cpu0_iext_err_type_r2, + l2_cpu0_isngl_ecc_err_r3, + l2_cpu0_idbl_ecc_err_r3, + l2_cpu0_idata_r2, + l2_cpu0_ivalid_r1, + l2_cpu0_ibufid_r1, + l2_cpu0_ls_sync_req, + l2_cpu0_ccb_req_addr_c3, + l2_cpu0_ccb_dbg_req_c3, + l2_cpu0_ls_ccb_clken_c3, + l2_cpu0_ls_ccb_req_c3, + l2_cpu0_ccb_req_id_c3, + l2_cpu0_ccb_req_type_c3, + l2_cpu0_ccb_req_info_c3, + l2_cpu0_if_ccb_clken_c3, + l2_cpu0_if_ccb_req_c3, + l2_cpu0_if_sync_req, + l2_cpu0_tlb_ccb_clken_c3, + l2_cpu0_tlb_ccb_req_c3, + l2_cpu0_tlb_sync_req, + l2_cpu0_tlb_sync_complete, + l2_cpu0_tbw_desc_vld, + l2_cpu0_tbw_ext_err, + l2_cpu0_tbw_ext_err_type, + l2_cpu0_tbw_dbl_ecc_err, + l2_cpu0_tbw_desc_data, + l2_cpu0_spr_rd_data, + l2_cpu0_l2_cache_size, + l2_cpu0_pf_throttle_q, + + l2_cpu0_wr_ex_resp, + l2_cpu0_wr_ex_fail, + + l2_cpu0_ic_base, + l2_cpu0_no_intctrl, + + + l2_cpu0_pmu_events, + + ds_cpu0_l2_spr_en, + ds_cpu0_l2_spr_rd, + ds_cpu0_l2_spr_wr, + ds_cpu0_l2_spr_addr, + ds_cpu0_l2_spr_dw, + ds_cpu0_l2_spr_wr_data, + + l2_cpu0_wr_data_vld_x1_q, + l2_cpu0_wr_evict_x1_q, + l2_cpu0_wr_data, + l2_cpu0_ls_rd_haz_vld_arb_q, + l2_cpu0_ls_wr_haz_vld_arb_q, + l2_cpu0_dt_pmu_evt_en, + + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + l2_cpu1_cfg_ecc_en, + l2_cpu1_arb_thrshld_timeout_en, + l2_cpu1_disable_clean_evict_opt, + l2_cpu1_dext_err_r2, + l2_cpu1_dext_err_type_r2, + l2_cpu1_dsngl_ecc_err_r3, + l2_cpu1_ddbl_ecc_err_r3, + l2_cpu1_ddata_r2, + l2_cpu1_barrier_done, + l2_cpu1_spec_valid, + l2_cpu1_spec_bufid, + l2_cpu1_rvalid, + l2_cpu1_rstate, + l2_cpu1_rexfail, + l2_cpu1_rbufid, + l2_cpu1_dvalid_r1, + l2_cpu1_dlast_r1, + l2_cpu1_dbufid_r1, + l2_cpu1_iext_err_r2, + l2_cpu1_iext_err_type_r2, + l2_cpu1_isngl_ecc_err_r3, + l2_cpu1_idbl_ecc_err_r3, + l2_cpu1_idata_r2, + l2_cpu1_ivalid_r1, + l2_cpu1_ibufid_r1, + l2_cpu1_ls_sync_req, + l2_cpu1_ccb_req_addr_c3, + l2_cpu1_ccb_dbg_req_c3, + l2_cpu1_ls_ccb_clken_c3, + l2_cpu1_ls_ccb_req_c3, + l2_cpu1_ccb_req_id_c3, + l2_cpu1_ccb_req_type_c3, + l2_cpu1_ccb_req_info_c3, + l2_cpu1_if_ccb_clken_c3, + l2_cpu1_if_ccb_req_c3, + l2_cpu1_if_sync_req, + l2_cpu1_tlb_ccb_clken_c3, + l2_cpu1_tlb_ccb_req_c3, + l2_cpu1_tlb_sync_req, + l2_cpu1_tlb_sync_complete, + l2_cpu1_tbw_desc_vld, + l2_cpu1_tbw_ext_err, + l2_cpu1_tbw_ext_err_type, + l2_cpu1_tbw_dbl_ecc_err, + l2_cpu1_tbw_desc_data, + l2_cpu1_spr_rd_data, + l2_cpu1_l2_cache_size, + l2_cpu1_pf_throttle_q, + + l2_cpu1_wr_ex_resp, + l2_cpu1_wr_ex_fail, + + l2_cpu1_ic_base, + l2_cpu1_no_intctrl, + + l2_cpu1_pmu_events, + + ds_cpu1_l2_spr_en, + ds_cpu1_l2_spr_rd, + ds_cpu1_l2_spr_wr, + ds_cpu1_l2_spr_addr, + ds_cpu1_l2_spr_dw, + ds_cpu1_l2_spr_wr_data, + + l2_cpu1_wr_data_vld_x1_q, + l2_cpu1_wr_evict_x1_q, + l2_cpu1_wr_data, + l2_cpu1_ls_rd_haz_vld_arb_q, + l2_cpu1_ls_wr_haz_vld_arb_q, + l2_cpu1_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + l2_cpu2_cfg_ecc_en, + l2_cpu2_arb_thrshld_timeout_en, + l2_cpu2_disable_clean_evict_opt, + l2_cpu2_dext_err_r2, + l2_cpu2_dext_err_type_r2, + l2_cpu2_dsngl_ecc_err_r3, + l2_cpu2_ddbl_ecc_err_r3, + l2_cpu2_ddata_r2, + l2_cpu2_barrier_done, + l2_cpu2_spec_valid, + l2_cpu2_spec_bufid, + l2_cpu2_rvalid, + l2_cpu2_rstate, + l2_cpu2_rexfail, + l2_cpu2_rbufid, + l2_cpu2_dvalid_r1, + l2_cpu2_dlast_r1, + l2_cpu2_dbufid_r1, + l2_cpu2_iext_err_r2, + l2_cpu2_iext_err_type_r2, + l2_cpu2_isngl_ecc_err_r3, + l2_cpu2_idbl_ecc_err_r3, + l2_cpu2_idata_r2, + l2_cpu2_ivalid_r1, + l2_cpu2_ibufid_r1, + l2_cpu2_ls_sync_req, + l2_cpu2_ccb_req_addr_c3, + l2_cpu2_ccb_dbg_req_c3, + l2_cpu2_ls_ccb_clken_c3, + l2_cpu2_ls_ccb_req_c3, + l2_cpu2_ccb_req_id_c3, + l2_cpu2_ccb_req_type_c3, + l2_cpu2_ccb_req_info_c3, + l2_cpu2_if_ccb_clken_c3, + l2_cpu2_if_ccb_req_c3, + l2_cpu2_if_sync_req, + l2_cpu2_tlb_ccb_clken_c3, + l2_cpu2_tlb_ccb_req_c3, + l2_cpu2_tlb_sync_req, + l2_cpu2_tlb_sync_complete, + l2_cpu2_tbw_desc_vld, + l2_cpu2_tbw_ext_err, + l2_cpu2_tbw_ext_err_type, + l2_cpu2_tbw_dbl_ecc_err, + l2_cpu2_tbw_desc_data, + l2_cpu2_spr_rd_data, + l2_cpu2_l2_cache_size, + l2_cpu2_pf_throttle_q, + + l2_cpu2_wr_ex_resp, + l2_cpu2_wr_ex_fail, + + l2_cpu2_ic_base, + l2_cpu2_no_intctrl, + + l2_cpu2_pmu_events, + + ds_cpu2_l2_spr_en, + ds_cpu2_l2_spr_rd, + ds_cpu2_l2_spr_wr, + ds_cpu2_l2_spr_addr, + ds_cpu2_l2_spr_dw, + ds_cpu2_l2_spr_wr_data, + + l2_cpu2_wr_data_vld_x1_q, + l2_cpu2_wr_evict_x1_q, + l2_cpu2_wr_data, + l2_cpu2_ls_rd_haz_vld_arb_q, + l2_cpu2_ls_wr_haz_vld_arb_q, + l2_cpu2_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + l2_cpu3_cfg_ecc_en, + l2_cpu3_arb_thrshld_timeout_en, + l2_cpu3_disable_clean_evict_opt, + l2_cpu3_dext_err_r2, + l2_cpu3_dext_err_type_r2, + l2_cpu3_dsngl_ecc_err_r3, + l2_cpu3_ddbl_ecc_err_r3, + l2_cpu3_ddata_r2, + l2_cpu3_barrier_done, + l2_cpu3_spec_valid, + l2_cpu3_spec_bufid, + l2_cpu3_rvalid, + l2_cpu3_rstate, + l2_cpu3_rexfail, + l2_cpu3_rbufid, + l2_cpu3_dvalid_r1, + l2_cpu3_dlast_r1, + l2_cpu3_dbufid_r1, + l2_cpu3_iext_err_r2, + l2_cpu3_iext_err_type_r2, + l2_cpu3_isngl_ecc_err_r3, + l2_cpu3_idbl_ecc_err_r3, + l2_cpu3_idata_r2, + l2_cpu3_ivalid_r1, + l2_cpu3_ibufid_r1, + l2_cpu3_ls_sync_req, + l2_cpu3_ccb_req_addr_c3, + l2_cpu3_ccb_dbg_req_c3, + l2_cpu3_ls_ccb_clken_c3, + l2_cpu3_ls_ccb_req_c3, + l2_cpu3_ccb_req_id_c3, + l2_cpu3_ccb_req_type_c3, + l2_cpu3_ccb_req_info_c3, + l2_cpu3_if_ccb_clken_c3, + l2_cpu3_if_ccb_req_c3, + l2_cpu3_if_sync_req, + l2_cpu3_tlb_ccb_clken_c3, + l2_cpu3_tlb_ccb_req_c3, + l2_cpu3_tlb_sync_req, + l2_cpu3_tlb_sync_complete, + l2_cpu3_tbw_desc_vld, + l2_cpu3_tbw_ext_err, + l2_cpu3_tbw_ext_err_type, + l2_cpu3_tbw_dbl_ecc_err, + l2_cpu3_tbw_desc_data, + l2_cpu3_spr_rd_data, + l2_cpu3_l2_cache_size, + l2_cpu3_pf_throttle_q, + + l2_cpu3_wr_ex_resp, + l2_cpu3_wr_ex_fail, + + l2_cpu3_ic_base, + l2_cpu3_no_intctrl, + + l2_cpu3_pmu_events, + + ds_cpu3_l2_spr_en, + ds_cpu3_l2_spr_rd, + ds_cpu3_l2_spr_wr, + ds_cpu3_l2_spr_addr, + ds_cpu3_l2_spr_dw, + ds_cpu3_l2_spr_wr_data, + + l2_cpu3_wr_data_vld_x1_q, + l2_cpu3_wr_evict_x1_q, + l2_cpu3_wr_data, + l2_cpu3_ls_rd_haz_vld_arb_q, + l2_cpu3_ls_wr_haz_vld_arb_q, + l2_cpu3_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// tag_pipe / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_flsh_ls_rd_l2_dly, + l2_cpu0_flsh_ls_wr_l2_dly, + + l2_cpu0_wr_data_stall, + + l2_cpu1_flsh_ls_rd_l2_dly, + l2_cpu1_flsh_ls_wr_l2_dly, + + l2_cpu1_wr_data_stall, + + l2_cpu2_flsh_ls_rd_l2_dly, + l2_cpu2_flsh_ls_wr_l2_dly, + + l2_cpu2_wr_data_stall, + + l2_cpu3_flsh_ls_rd_l2_dly, + l2_cpu3_flsh_ls_wr_l2_dly, + + l2_cpu3_wr_data_stall, + + l2_cpu0_flsh_ls_rd_id_l2_dly, + l2_cpu0_flsh_ls_wr_id_l2_dly, + + l2_cpu1_flsh_ls_rd_id_l2_dly, + l2_cpu1_flsh_ls_wr_id_l2_dly, + + l2_cpu2_flsh_ls_rd_id_l2_dly, + l2_cpu2_flsh_ls_wr_id_l2_dly, + + l2_cpu3_flsh_ls_rd_id_l2_dly, + l2_cpu3_flsh_ls_wr_id_l2_dly, + + l2_cpu0_flsh_ls_rd_l4_dly, + l2_cpu0_flsh_if_rd_l4_dly, + l2_cpu0_flsh_tw_rd_l4_dly, + l2_cpu0_flsh_ls_wr_l4_dly, + + l2_cpu1_flsh_ls_rd_l4_dly, + l2_cpu1_flsh_if_rd_l4_dly, + l2_cpu1_flsh_tw_rd_l4_dly, + l2_cpu1_flsh_ls_wr_l4_dly, + + l2_cpu2_flsh_ls_rd_l4_dly, + l2_cpu2_flsh_if_rd_l4_dly, + l2_cpu2_flsh_tw_rd_l4_dly, + l2_cpu2_flsh_ls_wr_l4_dly, + + l2_cpu3_flsh_ls_rd_l4_dly, + l2_cpu3_flsh_if_rd_l4_dly, + l2_cpu3_flsh_tw_rd_l4_dly, + l2_cpu3_flsh_ls_wr_l4_dly, + + l2_cpu0_flsh_ls_rd_id_l4_dly, + l2_cpu0_flsh_if_rd_id_l4_dly, + l2_cpu0_flsh_ls_wr_id_l4_dly, + l2_cpu0_flsh_ls_wr_evict_l4_dly, + + l2_cpu1_flsh_ls_rd_id_l4_dly, + l2_cpu1_flsh_if_rd_id_l4_dly, + l2_cpu1_flsh_ls_wr_id_l4_dly, + l2_cpu1_flsh_ls_wr_evict_l4_dly, + + l2_cpu2_flsh_ls_rd_id_l4_dly, + l2_cpu2_flsh_if_rd_id_l4_dly, + l2_cpu2_flsh_ls_wr_id_l4_dly, + l2_cpu2_flsh_ls_wr_evict_l4_dly, + + l2_cpu3_flsh_ls_rd_id_l4_dly, + l2_cpu3_flsh_if_rd_id_l4_dly, + l2_cpu3_flsh_ls_wr_id_l4_dly, + l2_cpu3_flsh_ls_wr_evict_l4_dly, + + l2_cpu0_lrq_haz_pending, + l2_cpu1_lrq_haz_pending, + l2_cpu2_lrq_haz_pending, + l2_cpu3_lrq_haz_pending, + + l2_cpu0_ifq_haz_pending, + l2_cpu1_ifq_haz_pending, + l2_cpu2_ifq_haz_pending, + l2_cpu3_ifq_haz_pending, + + l2_cpu0_trq_haz_pending, + l2_cpu1_trq_haz_pending, + l2_cpu2_trq_haz_pending, + l2_cpu3_trq_haz_pending, + + l2_cpu0_wrq_haz_pending, + l2_cpu1_wrq_haz_pending, + l2_cpu2_wrq_haz_pending, + l2_cpu3_wrq_haz_pending, + + l2_cpu0_idle_block_reqs_q, + l2_cpu1_idle_block_reqs_q, + l2_cpu2_idle_block_reqs_q, + l2_cpu3_idle_block_reqs_q, + + l2_cpu0_ls_peq_coll_l4_dly, + l2_cpu1_ls_peq_coll_l4_dly, + l2_cpu2_ls_peq_coll_l4_dly, + l2_cpu3_ls_peq_coll_l4_dly, + +//----------------------------------------------------------------------------- +// tag_pipe +//----------------------------------------------------------------------------- + l2_tbnk0_cpu0_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu1_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu2_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu3_lrq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu1_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu2_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu3_lrq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu1_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu2_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu3_ifq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu1_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu2_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu3_ifq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_trq_clr_l4_dly2_q, + l2_tbnk0_cpu1_trq_clr_l4_dly2_q, + l2_tbnk0_cpu2_trq_clr_l4_dly2_q, + l2_tbnk0_cpu3_trq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_trq_clr_l4_dly2_q, + l2_tbnk1_cpu1_trq_clr_l4_dly2_q, + l2_tbnk1_cpu2_trq_clr_l4_dly2_q, + l2_tbnk1_cpu3_trq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu1_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu2_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu3_wrq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu1_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu2_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu3_wrq_clr_l4_dly2_q, + + +//----------------------------------------------------------------------------- +// cpu_logic / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly, + + +//----------------------------------------------------------------------------- +// feq / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_dsq_rd_data_q, + l2_cpu0_dsq_rd_byte_strb_q, + l2_cpu1_dsq_rd_data_q, + l2_cpu1_dsq_rd_byte_strb_q, + l2_cpu2_dsq_rd_data_q, + l2_cpu2_dsq_rd_byte_strb_q, + l2_cpu3_dsq_rd_data_q, + l2_cpu3_dsq_rd_byte_strb_q, + + l2_cpu0_dsq_clr_vld_q, + l2_cpu0_dsq_clr_id_q, + l2_cpu0_dsq_rd_en, + l2_cpu0_dsq_rd_en_x2, + l2_cpu0_dsq_rd_buf_id, + l2_cpu1_dsq_clr_vld_q, + l2_cpu1_dsq_clr_id_q, + l2_cpu1_dsq_rd_en, + l2_cpu1_dsq_rd_en_x2, + l2_cpu1_dsq_rd_buf_id, + l2_cpu2_dsq_clr_vld_q, + l2_cpu2_dsq_clr_id_q, + l2_cpu2_dsq_rd_en, + l2_cpu2_dsq_rd_en_x2, + l2_cpu2_dsq_rd_buf_id, + l2_cpu3_dsq_clr_vld_q, + l2_cpu3_dsq_rd_en, + l2_cpu3_dsq_rd_en_x2, + l2_cpu3_dsq_clr_id_q, + l2_cpu3_dsq_rd_buf_id, + +//----------------------------------------------------------------------------- +// arbitration +//----------------------------------------------------------------------------- + l2_cpu0_rd_vld_skid, + l2_cpu1_rd_vld_skid, + l2_cpu2_rd_vld_skid, + l2_cpu3_rd_vld_skid, + + l2_cpu0_pf_rd_vld_skid_popped, + l2_cpu1_pf_rd_vld_skid_popped, + l2_cpu2_pf_rd_vld_skid_popped, + l2_cpu3_pf_rd_vld_skid_popped, + + l2_cpu0_rd_arb, + l2_cpu1_rd_arb, + l2_cpu2_rd_arb, + l2_cpu3_rd_arb, + + l2_cpu0_wr_vld_skid, + l2_cpu1_wr_vld_skid, + l2_cpu2_wr_vld_skid, + l2_cpu3_wr_vld_skid, + + l2_cpu0_wr_arb, + l2_cpu1_wr_arb, + l2_cpu2_wr_arb, + l2_cpu3_wr_arb, + + l2_cpu0_ic_vld_skid, + l2_cpu1_ic_vld_skid, + l2_cpu2_ic_vld_skid, + l2_cpu3_ic_vld_skid, + + l2_cpu0_ic_barrier_stall_q, + l2_cpu1_ic_barrier_stall_q, + l2_cpu2_ic_barrier_stall_q, + l2_cpu3_ic_barrier_stall_q, + + l2_cpu0_blk_non_evict_wr, + l2_cpu1_blk_non_evict_wr, + l2_cpu2_blk_non_evict_wr, + l2_cpu3_blk_non_evict_wr, + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + l2_cpu0_idle_wakeup_q, + l2_cpu0_rd_arb_fast, + l2_cpu0_rd_id_arb_set, + l2_cpu0_rd_lrq_id_arb_set, + l2_cpu0_rd_type_arb_set, + l2_cpu0_rd_cache_attr_arb_set, + l2_cpu0_rd_page_attr_arb_set, + l2_cpu0_rd_elem_size_arb_set, + l2_cpu0_rd_way_arb_set, + l2_cpu0_rd_replayed_arb_set, + l2_cpu0_rd_excl_arb_set, + l2_cpu0_rd_priv_arb_set, + l2_cpu0_rd_shared_arb_set, + l2_cpu0_rd_va48_arb_set, + l2_cpu0_rd_aarch64_arb_set, + l2_cpu0_rd_asid_arb_set, + l2_cpu0_rd_prfm_arb_set, + l2_cpu0_rd_addr_arb_set, + l2_cpu0_rd_bypass_arb_set, + l2_cpu0_rd_bypass_req_can_e5, + l2_cpu0_early_rd_reqe4_e5_q, + l2_cpu0_rd_bypass_way_e5, + l2_cpu0_rd_bypass_bufid_e5, + l2_cpu0_rd_bypass_lrq_id_e5, + + l2_cpu0_wr_arb_fast, + l2_cpu0_wr_id_arb_set, + l2_cpu0_wr_partial_dw_arb_set, + l2_cpu0_wr_cache_attr_arb_set, + l2_cpu0_wr_page_attr_arb_set, + l2_cpu0_wr_elem_size_arb_set, + l2_cpu0_wr_type_arb_set, + l2_cpu0_wr_cl_id_arb_set, + l2_cpu0_wr_priv_arb_set, + l2_cpu0_wr_shared_arb_set, + l2_cpu0_wr_last_arb_set, + l2_cpu0_wr_clean_evict_arb_set, + l2_cpu0_wr_err_arb_set, + l2_cpu0_wr_way_arb_set, + l2_cpu0_wr_dirty_arb_set, + l2_cpu0_wr_1st_replayed_arb_set, + l2_cpu0_wr_addr_arb_set, + l2_cpu0_ic_arb_fast, + l2_cpu0_ic_id_arb_set, + l2_cpu0_ic_write_arb_set, + l2_cpu0_ic_excl_arb_set, + l2_cpu0_ic_elem_size_arb_set, + l2_cpu0_ic_ns_arb_set, + l2_cpu0_ic_addr_arb_set, + l2_cpu0_ic_data_arb_set, + + l2_cpu0_wrq_almost_full, + + l2_cpu0_ls_wr_req_w2a, + l2_cpu0_ls_wr_last_w2a, + l2_cpu0_ls_wr_dirty_w2a, + l2_cpu0_ls_wr_err_w2a, + l2_cpu0_ls_wr_type_w2a, + l2_cpu0_ls_wr_ccb_id_w2a, + l2_cpu0_ls_wr_data_w2a, + + l2_cpu0_ls_ccb_resp, + l2_cpu0_ls_ccb_resp_id, + l2_cpu0_ls_ccb_data_wr, + + l2_cpu0_if_ccb_resp, + l2_cpu0_if_ccb_resp_id, + + l2_cpu0_tw_ccb_resp, + l2_cpu0_tw_ccb_resp_id, + + l2_cpu0_if_sync_done_q, + l2_cpu0_tlb_sync_done_q, + + l2_cpu0_lrq_haz_clr_id_dcd_q, + l2_cpu0_wrq_haz_clr_id_dcd_q, + l2_cpu0_ls_rd_haz_id_arb_q, + l2_cpu0_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + l2_cpu1_idle_wakeup_q, + l2_cpu1_rd_arb_fast, + l2_cpu1_rd_id_arb_set, + l2_cpu1_rd_lrq_id_arb_set, + l2_cpu1_rd_type_arb_set, + l2_cpu1_rd_cache_attr_arb_set, + l2_cpu1_rd_page_attr_arb_set, + l2_cpu1_rd_elem_size_arb_set, + l2_cpu1_rd_way_arb_set, + l2_cpu1_rd_replayed_arb_set, + l2_cpu1_rd_excl_arb_set, + l2_cpu1_rd_priv_arb_set, + l2_cpu1_rd_shared_arb_set, + l2_cpu1_rd_va48_arb_set, + l2_cpu1_rd_aarch64_arb_set, + l2_cpu1_rd_asid_arb_set, + l2_cpu1_rd_prfm_arb_set, + l2_cpu1_rd_addr_arb_set, + l2_cpu1_rd_bypass_arb_set, + l2_cpu1_rd_bypass_req_can_e5, + l2_cpu1_early_rd_reqe4_e5_q, + l2_cpu1_rd_bypass_way_e5, + l2_cpu1_rd_bypass_bufid_e5, + l2_cpu1_rd_bypass_lrq_id_e5, + + l2_cpu1_wr_arb_fast, + l2_cpu1_wr_id_arb_set, + l2_cpu1_wr_partial_dw_arb_set, + l2_cpu1_wr_cache_attr_arb_set, + l2_cpu1_wr_page_attr_arb_set, + l2_cpu1_wr_elem_size_arb_set, + l2_cpu1_wr_type_arb_set, + l2_cpu1_wr_cl_id_arb_set, + l2_cpu1_wr_priv_arb_set, + l2_cpu1_wr_shared_arb_set, + l2_cpu1_wr_last_arb_set, + l2_cpu1_wr_clean_evict_arb_set, + l2_cpu1_wr_err_arb_set, + l2_cpu1_wr_way_arb_set, + l2_cpu1_wr_dirty_arb_set, + l2_cpu1_wr_1st_replayed_arb_set, + l2_cpu1_wr_addr_arb_set, + l2_cpu1_ic_arb_fast, + l2_cpu1_ic_id_arb_set, + l2_cpu1_ic_write_arb_set, + l2_cpu1_ic_excl_arb_set, + l2_cpu1_ic_elem_size_arb_set, + l2_cpu1_ic_ns_arb_set, + l2_cpu1_ic_addr_arb_set, + l2_cpu1_ic_data_arb_set, + + l2_cpu1_wrq_almost_full, + + l2_cpu1_ls_wr_req_w2a, + l2_cpu1_ls_wr_last_w2a, + l2_cpu1_ls_wr_dirty_w2a, + l2_cpu1_ls_wr_err_w2a, + l2_cpu1_ls_wr_type_w2a, + l2_cpu1_ls_wr_ccb_id_w2a, + l2_cpu1_ls_wr_data_w2a, + + l2_cpu1_ls_ccb_resp, + l2_cpu1_ls_ccb_resp_id, + l2_cpu1_ls_ccb_data_wr, + + l2_cpu1_if_ccb_resp, + l2_cpu1_if_ccb_resp_id, + + l2_cpu1_tw_ccb_resp, + l2_cpu1_tw_ccb_resp_id, + + l2_cpu1_if_sync_done_q, + l2_cpu1_tlb_sync_done_q, + + l2_cpu1_lrq_haz_clr_id_dcd_q, + l2_cpu1_wrq_haz_clr_id_dcd_q, + l2_cpu1_ls_rd_haz_id_arb_q, + l2_cpu1_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + l2_cpu2_idle_wakeup_q, + l2_cpu2_rd_arb_fast, + l2_cpu2_rd_id_arb_set, + l2_cpu2_rd_lrq_id_arb_set, + l2_cpu2_rd_type_arb_set, + l2_cpu2_rd_cache_attr_arb_set, + l2_cpu2_rd_page_attr_arb_set, + l2_cpu2_rd_elem_size_arb_set, + l2_cpu2_rd_way_arb_set, + l2_cpu2_rd_replayed_arb_set, + l2_cpu2_rd_excl_arb_set, + l2_cpu2_rd_priv_arb_set, + l2_cpu2_rd_shared_arb_set, + l2_cpu2_rd_va48_arb_set, + l2_cpu2_rd_aarch64_arb_set, + l2_cpu2_rd_asid_arb_set, + l2_cpu2_rd_prfm_arb_set, + l2_cpu2_rd_addr_arb_set, + l2_cpu2_rd_bypass_arb_set, + l2_cpu2_rd_bypass_req_can_e5, + l2_cpu2_early_rd_reqe4_e5_q, + l2_cpu2_rd_bypass_way_e5, + l2_cpu2_rd_bypass_bufid_e5, + l2_cpu2_rd_bypass_lrq_id_e5, + + l2_cpu2_wr_arb_fast, + l2_cpu2_wr_id_arb_set, + l2_cpu2_wr_partial_dw_arb_set, + l2_cpu2_wr_cache_attr_arb_set, + l2_cpu2_wr_page_attr_arb_set, + l2_cpu2_wr_elem_size_arb_set, + l2_cpu2_wr_type_arb_set, + l2_cpu2_wr_cl_id_arb_set, + l2_cpu2_wr_priv_arb_set, + l2_cpu2_wr_shared_arb_set, + l2_cpu2_wr_last_arb_set, + l2_cpu2_wr_clean_evict_arb_set, + l2_cpu2_wr_err_arb_set, + l2_cpu2_wr_way_arb_set, + l2_cpu2_wr_dirty_arb_set, + l2_cpu2_wr_1st_replayed_arb_set, + l2_cpu2_wr_addr_arb_set, + l2_cpu2_ic_arb_fast, + l2_cpu2_ic_id_arb_set, + l2_cpu2_ic_write_arb_set, + l2_cpu2_ic_excl_arb_set, + l2_cpu2_ic_elem_size_arb_set, + l2_cpu2_ic_ns_arb_set, + l2_cpu2_ic_addr_arb_set, + l2_cpu2_ic_data_arb_set, + + l2_cpu2_wrq_almost_full, + + l2_cpu2_ls_wr_req_w2a, + l2_cpu2_ls_wr_last_w2a, + l2_cpu2_ls_wr_dirty_w2a, + l2_cpu2_ls_wr_err_w2a, + l2_cpu2_ls_wr_type_w2a, + l2_cpu2_ls_wr_ccb_id_w2a, + l2_cpu2_ls_wr_data_w2a, + + l2_cpu2_ls_ccb_resp, + l2_cpu2_ls_ccb_resp_id, + l2_cpu2_ls_ccb_data_wr, + + l2_cpu2_if_ccb_resp, + l2_cpu2_if_ccb_resp_id, + + l2_cpu2_tw_ccb_resp, + l2_cpu2_tw_ccb_resp_id, + + l2_cpu2_if_sync_done_q, + l2_cpu2_tlb_sync_done_q, + + l2_cpu2_lrq_haz_clr_id_dcd_q, + l2_cpu2_wrq_haz_clr_id_dcd_q, + l2_cpu2_ls_rd_haz_id_arb_q, + l2_cpu2_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + l2_cpu3_idle_wakeup_q, + l2_cpu3_rd_arb_fast, + l2_cpu3_rd_id_arb_set, + l2_cpu3_rd_lrq_id_arb_set, + l2_cpu3_rd_type_arb_set, + l2_cpu3_rd_cache_attr_arb_set, + l2_cpu3_rd_page_attr_arb_set, + l2_cpu3_rd_elem_size_arb_set, + l2_cpu3_rd_way_arb_set, + l2_cpu3_rd_replayed_arb_set, + l2_cpu3_rd_excl_arb_set, + l2_cpu3_rd_priv_arb_set, + l2_cpu3_rd_shared_arb_set, + l2_cpu3_rd_va48_arb_set, + l2_cpu3_rd_aarch64_arb_set, + l2_cpu3_rd_asid_arb_set, + l2_cpu3_rd_prfm_arb_set, + l2_cpu3_rd_addr_arb_set, + l2_cpu3_rd_bypass_arb_set, + l2_cpu3_rd_bypass_req_can_e5, + l2_cpu3_early_rd_reqe4_e5_q, + l2_cpu3_rd_bypass_way_e5, + l2_cpu3_rd_bypass_bufid_e5, + l2_cpu3_rd_bypass_lrq_id_e5, + + l2_cpu3_wr_arb_fast, + l2_cpu3_wr_id_arb_set, + l2_cpu3_wr_partial_dw_arb_set, + l2_cpu3_wr_cache_attr_arb_set, + l2_cpu3_wr_page_attr_arb_set, + l2_cpu3_wr_elem_size_arb_set, + l2_cpu3_wr_type_arb_set, + l2_cpu3_wr_cl_id_arb_set, + l2_cpu3_wr_priv_arb_set, + l2_cpu3_wr_shared_arb_set, + l2_cpu3_wr_last_arb_set, + l2_cpu3_wr_clean_evict_arb_set, + l2_cpu3_wr_err_arb_set, + l2_cpu3_wr_way_arb_set, + l2_cpu3_wr_dirty_arb_set, + l2_cpu3_wr_1st_replayed_arb_set, + l2_cpu3_wr_addr_arb_set, + l2_cpu3_ic_arb_fast, + l2_cpu3_ic_id_arb_set, + l2_cpu3_ic_write_arb_set, + l2_cpu3_ic_excl_arb_set, + l2_cpu3_ic_elem_size_arb_set, + l2_cpu3_ic_ns_arb_set, + l2_cpu3_ic_addr_arb_set, + l2_cpu3_ic_data_arb_set, + + l2_cpu3_wrq_almost_full, + + l2_cpu3_ls_wr_req_w2a, + l2_cpu3_ls_wr_last_w2a, + l2_cpu3_ls_wr_dirty_w2a, + l2_cpu3_ls_wr_err_w2a, + l2_cpu3_ls_wr_type_w2a, + l2_cpu3_ls_wr_ccb_id_w2a, + l2_cpu3_ls_wr_data_w2a, + + l2_cpu3_ls_ccb_resp, + l2_cpu3_ls_ccb_resp_id, + l2_cpu3_ls_ccb_data_wr, + + l2_cpu3_if_ccb_resp, + l2_cpu3_if_ccb_resp_id, + + l2_cpu3_tw_ccb_resp, + l2_cpu3_tw_ccb_resp_id, + + l2_cpu3_if_sync_done_q, + l2_cpu3_tlb_sync_done_q, + + l2_cpu3_lrq_haz_clr_id_dcd_q, + l2_cpu3_wrq_haz_clr_id_dcd_q, + l2_cpu3_ls_rd_haz_id_arb_q, + l2_cpu3_ls_wr_haz_id_arb_q, + +// END L2-CPU interface + +//------------------------------------------------------------------- +// TM interface +//------------------------------------------------------------------- +// BEGIN TIMER-CPU interface + tm_cpu0_cntkctl_usr, + tm_cpu0_cnthctl_kernel, + + tm_cpu1_cntkctl_usr, + tm_cpu1_cnthctl_kernel, + + tm_cpu2_cntkctl_usr, + tm_cpu2_cnthctl_kernel, + + tm_cpu3_cntkctl_usr, + tm_cpu3_cnthctl_kernel, +// END TIMER-CPU interface + +//----------------------------------------------------------------------------- +// IC interface +//----------------------------------------------------------------------------- + ls_cpu0_imp_abort_slv, + ls_cpu0_imp_abort_ecc, + ls_cpu0_imp_abort_dec, + ls_cpu0_imp_abort_containable, + ls_cpu0_raw_eae_nonsec, + ls_cpu0_raw_eae_secure, + + ds_cpu0_ic_cpsr_mode, + ds_cpu0_ic_sample_spr, + ds_cpu0_ic_aa64naa32, + ds_cpu0_ic_hcr_change, + ds_cpu0_ic_scr_change, +// BEGIN INCLUDE FOR CPU1 + ds_cpu1_ic_cpsr_mode, + ds_cpu1_ic_sample_spr, + ds_cpu1_ic_aa64naa32, + ds_cpu1_ic_hcr_change, + ds_cpu1_ic_scr_change, + ls_cpu1_imp_abort_slv, + ls_cpu1_imp_abort_ecc, + ls_cpu1_imp_abort_dec, + ls_cpu1_imp_abort_containable, + ls_cpu1_raw_eae_nonsec, + ls_cpu1_raw_eae_secure, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ds_cpu2_ic_cpsr_mode, + ds_cpu2_ic_sample_spr, + ds_cpu2_ic_aa64naa32, + ds_cpu2_ic_hcr_change, + ds_cpu2_ic_scr_change, + ls_cpu2_imp_abort_slv, + ls_cpu2_imp_abort_ecc, + ls_cpu2_imp_abort_dec, + ls_cpu2_imp_abort_containable, + ls_cpu2_raw_eae_nonsec, + ls_cpu2_raw_eae_secure, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ds_cpu3_ic_cpsr_mode, + ds_cpu3_ic_sample_spr, + ds_cpu3_ic_aa64naa32, + ds_cpu3_ic_hcr_change, + ds_cpu3_ic_scr_change, + ls_cpu3_imp_abort_slv, + ls_cpu3_imp_abort_ecc, + ls_cpu3_imp_abort_dec, + ls_cpu3_imp_abort_containable, + ls_cpu3_raw_eae_nonsec, + ls_cpu3_raw_eae_secure, +// END INCLUDE FOR CPU3 + + ic_nfiq, + ic_nirq, + ic_nsei, + ic_nvfiq, + ic_nvirq, + ic_nvsei, + ic_p_valid, + + ic_sample_spr, + ic_hcr_change_complete, + ic_scr_change_complete, + ic_el_change_complete, + ic_ich_el2_tc, + ic_ich_el2_tall0, + ic_ich_el2_tall1, + ic_sra_el3_en, + ic_sra_el1s_en, + ic_sra_el2_en, + ic_sra_el1ns_en, + ic_sre_el1ns_hyp_trap, + ic_sre_el1ns_mon_trap, + ic_sre_el1s_mon_trap, + ic_sre_el2_mon_trap, + ic_block_eoi_sgi_wr, + +//----------------------------------------------------------------------------- +// DT interface +//----------------------------------------------------------------------------- +// BEGIN DT-CPU interface +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + dt_cpu0_et_oslock_gclk, + dt_cpu0_os_double_lock_gclk, + dt_cpu0_halt_ack_gclk, + dt_cpu0_coredbg_in_reset_gclk, + dt_cpu0_wfx_dbg_req_gclk, + dt_cpu0_hlt_dbgevt_ok_gclk, + dt_cpu0_dbif_ack_gclk, + dt_cpu0_dbif_err_gclk, + dt_cpu0_dbif_rddata_gclk, + + dt_cpu0_dbif_addr_pclk, + dt_cpu0_dbif_locked_pclk, + dt_cpu0_dbif_req_pclk, + dt_cpu0_dbif_wrdata_pclk, + dt_cpu0_dbif_write_pclk, + dt_cpu0_edecr_osuce_pclk, + dt_cpu0_edecr_rce_pclk, + dt_cpu0_edecr_ss_pclk, + dt_cpu0_edbgrq_pclk, + dt_cpu0_edacr_frc_idleack_pclk, + dt_cpu0_edprcr_corepurq_pclk, + + dt_cpu0_pmusnapshot_ack_gclk, + dt_cpu0_pmusnapshot_req_pclk, + + dt_cpu0_cti_trigin_7to4_gclk, + dt_cpu0_cti_trigin_1to0_gclk, + dt_cpu0_cti_trigoutack_7to4_gclk, + dt_cpu0_cti_trigoutack_bit1_gclk, + + dt_cpu0_cti_trigout_7to4_pclk, + dt_cpu0_cti_trigout_1to0_pclk, + dt_cpu0_cti_triginack_7to4_pclk, + dt_cpu0_cti_triginack_1to0_pclk, + + dt_cpu0_wfx_wakeup_pclk, + dt_cpu0_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + dt_cpu1_et_oslock_gclk, + dt_cpu1_os_double_lock_gclk, + dt_cpu1_halt_ack_gclk, + dt_cpu1_coredbg_in_reset_gclk, + dt_cpu1_wfx_dbg_req_gclk, + dt_cpu1_hlt_dbgevt_ok_gclk, + dt_cpu1_dbif_ack_gclk, + dt_cpu1_dbif_err_gclk, + dt_cpu1_dbif_rddata_gclk, + + dt_cpu1_dbif_addr_pclk, + dt_cpu1_dbif_locked_pclk, + dt_cpu1_dbif_req_pclk, + dt_cpu1_dbif_wrdata_pclk, + dt_cpu1_dbif_write_pclk, + dt_cpu1_edecr_osuce_pclk, + dt_cpu1_edecr_rce_pclk, + dt_cpu1_edecr_ss_pclk, + dt_cpu1_edbgrq_pclk, + dt_cpu1_edacr_frc_idleack_pclk, + dt_cpu1_edprcr_corepurq_pclk, + + dt_cpu1_pmusnapshot_ack_gclk, + dt_cpu1_pmusnapshot_req_pclk, + + dt_cpu1_cti_trigin_7to4_gclk, + dt_cpu1_cti_trigin_1to0_gclk, + dt_cpu1_cti_trigoutack_7to4_gclk, + dt_cpu1_cti_trigoutack_bit1_gclk, + + dt_cpu1_cti_trigout_7to4_pclk, + dt_cpu1_cti_trigout_1to0_pclk, + dt_cpu1_cti_triginack_7to4_pclk, + dt_cpu1_cti_triginack_1to0_pclk, + + dt_cpu1_wfx_wakeup_pclk, + dt_cpu1_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + dt_cpu2_et_oslock_gclk, + dt_cpu2_os_double_lock_gclk, + dt_cpu2_halt_ack_gclk, + dt_cpu2_coredbg_in_reset_gclk, + dt_cpu2_wfx_dbg_req_gclk, + dt_cpu2_hlt_dbgevt_ok_gclk, + dt_cpu2_dbif_ack_gclk, + dt_cpu2_dbif_err_gclk, + dt_cpu2_dbif_rddata_gclk, + + dt_cpu2_dbif_addr_pclk, + dt_cpu2_dbif_locked_pclk, + dt_cpu2_dbif_req_pclk, + dt_cpu2_dbif_wrdata_pclk, + dt_cpu2_dbif_write_pclk, + dt_cpu2_edecr_osuce_pclk, + dt_cpu2_edecr_rce_pclk, + dt_cpu2_edecr_ss_pclk, + dt_cpu2_edbgrq_pclk, + dt_cpu2_edacr_frc_idleack_pclk, + dt_cpu2_edprcr_corepurq_pclk, + + dt_cpu2_pmusnapshot_ack_gclk, + dt_cpu2_pmusnapshot_req_pclk, + + dt_cpu2_cti_trigin_7to4_gclk, + dt_cpu2_cti_trigin_1to0_gclk, + dt_cpu2_cti_trigoutack_7to4_gclk, + dt_cpu2_cti_trigoutack_bit1_gclk, + + dt_cpu2_cti_trigout_7to4_pclk, + dt_cpu2_cti_trigout_1to0_pclk, + dt_cpu2_cti_triginack_7to4_pclk, + dt_cpu2_cti_triginack_1to0_pclk, + + dt_cpu2_wfx_wakeup_pclk, + dt_cpu2_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + dt_cpu3_et_oslock_gclk, + dt_cpu3_os_double_lock_gclk, + dt_cpu3_halt_ack_gclk, + dt_cpu3_coredbg_in_reset_gclk, + dt_cpu3_wfx_dbg_req_gclk, + dt_cpu3_hlt_dbgevt_ok_gclk, + dt_cpu3_dbif_ack_gclk, + dt_cpu3_dbif_err_gclk, + dt_cpu3_dbif_rddata_gclk, + + dt_cpu3_dbif_addr_pclk, + dt_cpu3_dbif_locked_pclk, + dt_cpu3_dbif_req_pclk, + dt_cpu3_dbif_wrdata_pclk, + dt_cpu3_dbif_write_pclk, + dt_cpu3_edecr_osuce_pclk, + dt_cpu3_edecr_rce_pclk, + dt_cpu3_edecr_ss_pclk, + dt_cpu3_edbgrq_pclk, + dt_cpu3_edacr_frc_idleack_pclk, + dt_cpu3_edprcr_corepurq_pclk, + + dt_cpu3_pmusnapshot_ack_gclk, + dt_cpu3_pmusnapshot_req_pclk, + + dt_cpu3_cti_trigin_7to4_gclk, + dt_cpu3_cti_trigin_1to0_gclk, + dt_cpu3_cti_trigoutack_7to4_gclk, + dt_cpu3_cti_trigoutack_bit1_gclk, + + dt_cpu3_cti_trigout_7to4_pclk, + dt_cpu3_cti_trigout_1to0_pclk, + dt_cpu3_cti_triginack_7to4_pclk, + dt_cpu3_cti_triginack_1to0_pclk, + + dt_cpu3_wfx_wakeup_pclk, + dt_cpu3_noclkstop_pclk, +// END DT-CPU interface + +//----------------------------------------------------------------------------- +// CK interface +//----------------------------------------------------------------------------- +// BEGIN CK-CPU interface + ds_cpu0_reset_req, + ds_cpu0_wfi_req, + ds_cpu0_wfe_req, + ds_cpu0_flush, + ds_cpu0_flush_type, + ds_cpu0_imp_abrt_wfi_qual, + ds_cpu0_irq_wfi_qual, + ds_cpu0_fiq_wfi_qual, + ds_cpu0_vimp_abrt_wfi_qual, + ds_cpu0_virq_wfi_qual, + ds_cpu0_vfiq_wfi_qual, + ds_cpu0_imp_abrt_wfe_qual, + ds_cpu0_irq_wfe_qual, + ds_cpu0_fiq_wfe_qual, + ds_cpu0_vimp_abrt_wfe_qual, + ds_cpu0_virq_wfe_qual, + ds_cpu0_vfiq_wfe_qual, + ds_cpu0_hcr_va, + ds_cpu0_hcr_vi, + ds_cpu0_hcr_vf, + ds_cpu0_cpuectlr_ret, + ck_cpu0_event_reg, + ck_cpu0_wfi_ack, + ck_cpu0_wfe_ack, + ck_cpu0_crcx_clk_en_n, + + ds_cpu1_reset_req, + ds_cpu1_wfi_req, + ds_cpu1_wfe_req, + ds_cpu1_flush, + ds_cpu1_flush_type, + ds_cpu1_imp_abrt_wfi_qual, + ds_cpu1_irq_wfi_qual, + ds_cpu1_fiq_wfi_qual, + ds_cpu1_vimp_abrt_wfi_qual, + ds_cpu1_virq_wfi_qual, + ds_cpu1_vfiq_wfi_qual, + ds_cpu1_imp_abrt_wfe_qual, + ds_cpu1_irq_wfe_qual, + ds_cpu1_fiq_wfe_qual, + ds_cpu1_vimp_abrt_wfe_qual, + ds_cpu1_virq_wfe_qual, + ds_cpu1_vfiq_wfe_qual, + ds_cpu1_hcr_va, + ds_cpu1_hcr_vi, + ds_cpu1_hcr_vf, + ds_cpu1_cpuectlr_ret, + ck_cpu1_event_reg, + ck_cpu1_wfi_ack, + ck_cpu1_wfe_ack, + ck_cpu1_crcx_clk_en_n, + + ds_cpu2_reset_req, + ds_cpu2_wfi_req, + ds_cpu2_wfe_req, + ds_cpu2_flush, + ds_cpu2_flush_type, + ds_cpu2_imp_abrt_wfi_qual, + ds_cpu2_irq_wfi_qual, + ds_cpu2_fiq_wfi_qual, + ds_cpu2_vimp_abrt_wfi_qual, + ds_cpu2_virq_wfi_qual, + ds_cpu2_vfiq_wfi_qual, + ds_cpu2_imp_abrt_wfe_qual, + ds_cpu2_irq_wfe_qual, + ds_cpu2_fiq_wfe_qual, + ds_cpu2_vimp_abrt_wfe_qual, + ds_cpu2_virq_wfe_qual, + ds_cpu2_vfiq_wfe_qual, + ds_cpu2_hcr_va, + ds_cpu2_hcr_vi, + ds_cpu2_hcr_vf, + ds_cpu2_cpuectlr_ret, + ck_cpu2_event_reg, + ck_cpu2_wfi_ack, + ck_cpu2_wfe_ack, + ck_cpu2_crcx_clk_en_n, + + ds_cpu3_reset_req, + ds_cpu3_wfi_req, + ds_cpu3_wfe_req, + ds_cpu3_flush, + ds_cpu3_flush_type, + ds_cpu3_imp_abrt_wfi_qual, + ds_cpu3_irq_wfi_qual, + ds_cpu3_fiq_wfi_qual, + ds_cpu3_vimp_abrt_wfi_qual, + ds_cpu3_virq_wfi_qual, + ds_cpu3_vfiq_wfi_qual, + ds_cpu3_imp_abrt_wfe_qual, + ds_cpu3_irq_wfe_qual, + ds_cpu3_fiq_wfe_qual, + ds_cpu3_vimp_abrt_wfe_qual, + ds_cpu3_virq_wfe_qual, + ds_cpu3_vfiq_wfe_qual, + ds_cpu3_hcr_va, + ds_cpu3_hcr_vi, + ds_cpu3_hcr_vf, + ds_cpu3_cpuectlr_ret, + ck_cpu3_event_reg, + ck_cpu3_wfi_ack, + ck_cpu3_wfe_ack, + ck_cpu3_crcx_clk_en_n, + + ls_cpu0_clrexmon, + ls_cpu1_clrexmon, + ls_cpu2_clrexmon, + ls_cpu3_clrexmon, +// END CK-CPU interface + + ck_gclkt +); + +//# +//# Interface Signals +//# ================= +//# + +//----------------------------------------------------------------------------- +// Clock and Reset Signals +//----------------------------------------------------------------------------- + input CLK; // Fast Clock + input CLKEN; // Fast Clock Enable + + input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset + input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) + input nL2RESET; // L2 reset + input L2RSTDISABLE; // L2 RAMs hardware reset disable + output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request +//See also nPRESETDBG; // Debug APB reset (PCLK) + +//----------------------------------------------------------------------------- +// Static Configuration Signals +//----------------------------------------------------------------------------- +// Static configuration signals that should be tied off and not change dynamically. +// Many of the initial values specified by these inputs +// may be overridden in software using CP15 registers. + + input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) + input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors + input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) + input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers + + input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] + input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] + + input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) + input [43:2] RVBARADDR0; // RVBAR address +// BEGIN INCLUDE FOR CPU1 + input [43:2] RVBARADDR1; // RVBAR address +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input [43:2] RVBARADDR2; // RVBAR address +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input [43:2] RVBARADDR3; // RVBAR address +// END INCLUDE FOR CPU3 + input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension + +//----------------------------------------------------------------------------- +// Interrupt Controller Signals +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] nFIQ; // Fast Interrupt request + input [`MAIA_CN:0] nIRQ; // Interrupt request + input [`MAIA_CN:0] nSEI; // System Error Interrupt + input [`MAIA_CN:0] nREI; // RAM Error Interrupt + input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request + input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request + input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt + +// BEGIN NO-GIC pins + output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output +// END NO-GIC pins + + input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers +// BEGIN NO-GIC pins + input GICCDISABLE; // Put GIC into bypass mode + + input ICDTVALID; // Distrubuter AXI4 SP Message Valid + output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message + input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data + input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet + input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID + + output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid + input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message + output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data + output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet + output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID +// END NO-GIC pins + +//----------------------------------------------------------------------------- +// Timer Signals +//----------------------------------------------------------------------------- + input [63:0] CNTVALUEB; // Counter value in binary + input CNTCLKEN; // Counter clock enable + output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event + output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event + output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event + output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event + +//----------------------------------------------------------------------------- +// Power Management Signals +//----------------------------------------------------------------------------- + input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) + output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) + input EVENTI; // Event input for processor wake-up from WFE state + output EVENTO; // Event output, signal is active when SEV instruction is executed + output [`MAIA_CN:0] STANDBYWFI; // WFI mode + output [`MAIA_CN:0] STANDBYWFE; // WFE mode + output STANDBYWFIL2; // WFI mode for L2 + output [`MAIA_CN:0] SMPEN; // CPU SMP bit + + output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE + input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn + output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn + output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY + + output L2QACTIVE; // L2 Q-channel QACTIVE + input L2QREQn; // L2 Q-channel QREQn + output L2QACCEPTn; // L2 Q-channel QACCEPTn + output L2QDENY; // L2 Q-channel QDENY + + input L2FLUSHREQ; // L2 hardware flush request + output L2FLUSHDONE; // L2 hardware flush done + +//----------------------------------------------------------------------------- +// Asynchronous Error Signals +//----------------------------------------------------------------------------- + output nINTERRIRQ; // L2 RAM dbl-bit ECC error + output nEXTERRIRQ; // Write transaction error + +//----------------------------------------------------------------------------- +// Bus Configuration Signals +//----------------------------------------------------------------------------- + input SYSBARDISABLE; // Disable broadcast of barriers + input BROADCASTINNER; // Extend Inner Shared Domain + input BROADCASTOUTER; // Extend Outer Shared Domain + input BROADCASTCACHEMAINT; // Broadcast cache maint ops + +//----------------------------------------------------------------------------- +// Skyros RN-F Interface +//----------------------------------------------------------------------------- + input SCLKEN; // Skyros clock enable + input SINACT; // Skyros snoop inactive + + input [6:0] NODEID; // Skyros requestor NodeID + + output TXSACTIVE; // Skyros active - indicates pending activity on pins + input RXSACTIVE; // Skyros active - indicates pending activity on pins + + output TXLINKACTIVEREQ; // Skyros transmit link active request + input TXLINKACTIVEACK; // SKyros transmit link active acknowledge + + input RXLINKACTIVEREQ; // SKyros receive link active request + output RXLINKACTIVEACK; // Skyros receive link active acknowledge + +// TXREQ - outbound requests + output TXREQFLITPEND; // Skyros TXREQ FLIT pending + output TXREQFLITV; // Skyros TXREQ FLIT valid + output [99:0] TXREQFLIT; // Skyros TXREQ FLIT payload + output [7:0] REQMEMATTR; // Skyros TXREQ raw memory attributes + input TXREQLCRDV; // Skyros TXREQ link-layer credit valid + +// TXRSP - outbound response + output TXRSPFLITPEND; // Skyros TXRSP FLIT pending + output TXRSPFLITV; // Skyros TXRSP FLIT valid + output [44:0] TXRSPFLIT; // Skyros TXRSP FLIT payload + input TXRSPLCRDV; // Skyros TXRSP link-layer credit valid + +// TXDAT - outbound data + output TXDATFLITPEND; // Skyros TXDAT FLIT pending + output TXDATFLITV; // Skyros TXDAT FLIT valid + output [193:0] TXDATFLIT; // Skyros TXDAT FLIT payload + input TXDATLCRDV; // Skyros TXDAT link-layer credit valid + +// RXSNP - inbound snoops + input RXSNPFLITPEND; // Skyros RXSNP FLIT pending + input RXSNPFLITV; // Skyros RXSNP FLIT valid + input [64:0] RXSNPFLIT; // Skyros RXSNP FLIT payload + output RXSNPLCRDV; // Skyros RXSNP link-layer credit valid + +// RXRSP - inbound response + input RXRSPFLITPEND; // Skyros RXRSP FLIT pending + input RXRSPFLITV; // Skyros RXRSP FLIT valid + input [44:0] RXRSPFLIT; // Skyros RXRSP FLIT payload + output RXRSPLCRDV; // Skyros RXRSP link-layer credit valid + +// RXDAT - inbound data + input RXDATFLITPEND; // Skyros RXDAT FLIT pending + input RXDATFLITV; // Skyros RXDAT FLIT valid + input [193:0] RXDATFLIT; // Skyros RXDAT FLIT payload + output RXDATLCRDV; // Skyros RXDAT link-layer credit valid + + input [43:24] SAMMNBASE; // Skyros SAM MN base address + input [1:0] SAMADDRMAP0; // Skyros SAM address region 0 mapping + input [1:0] SAMADDRMAP1; // Skyros SAM address region 1 mapping + input [1:0] SAMADDRMAP2; // Skyros SAM address region 2 mapping + input [1:0] SAMADDRMAP3; // Skyros SAM address region 3 mapping + input [1:0] SAMADDRMAP4; // Skyros SAM address region 4 mapping + input [1:0] SAMADDRMAP5; // Skyros SAM address region 5 mapping + input [1:0] SAMADDRMAP6; // Skyros SAM address region 6 mapping + input [1:0] SAMADDRMAP7; // Skyros SAM address region 7 mapping + input [1:0] SAMADDRMAP8; // Skyros SAM address region 8 mapping + input [1:0] SAMADDRMAP9; // Skyros SAM address region 9 mapping + input [1:0] SAMADDRMAP10; // Skyros SAM address region 10 mapping + input [1:0] SAMADDRMAP11; // Skyros SAM address region 11 mapping + input [1:0] SAMADDRMAP12; // Skyros SAM address region 12 mapping + input [1:0] SAMADDRMAP13; // Skyros SAM address region 13 mapping + input [1:0] SAMADDRMAP14; // Skyros SAM address region 14 mapping + input [1:0] SAMADDRMAP15; // Skyros SAM address region 15 mapping + input [1:0] SAMADDRMAP16; // Skyros SAM address region 16 mapping + input [1:0] SAMADDRMAP17; // Skyros SAM address region 17 mapping + input [1:0] SAMADDRMAP18; // Skyros SAM address region 18 mapping + input [1:0] SAMADDRMAP19; // Skyros SAM address region 19 mapping + input [6:0] SAMMNNODEID; // Skyros SAM MN target ID + input [6:0] SAMHNI0NODEID; // Skyros SAM HNI0 target ID + input [6:0] SAMHNI1NODEID; // Skyros SAM HNI1 target ID + input [6:0] SAMHNF0NODEID; // Skyros SAM HNF0 target ID + input [6:0] SAMHNF1NODEID; // Skyros SAM HNF1 target ID + input [6:0] SAMHNF2NODEID; // Skyros SAM HNF2 target ID + input [6:0] SAMHNF3NODEID; // Skyros SAM HNF3 target ID + input [6:0] SAMHNF4NODEID; // Skyros SAM HNF4 target ID + input [6:0] SAMHNF5NODEID; // Skyros SAM HNF5 target ID + input [6:0] SAMHNF6NODEID; // Skyros SAM HNF6 target ID + input [6:0] SAMHNF7NODEID; // Skyros SAM HNF7 target ID + input [2:0] SAMHNFMODE; // Skyros SAM HNF interleaving mode + +//----------------------------------------------------------------------------- +// ACP AXI Slave +//----------------------------------------------------------------------------- + input ACLKENS; // AXI slave clock enable + input AINACTS; // AXI slave interface no longer active or accepting requests + +// Write Address channel signals + output AWREADYS; // Write Address ready (slave ready to accept write address) + input AWVALIDS; // Write Address valid + input [4:0] AWIDS; // Write Address ID + input [43:0] AWADDRS; // Write Address + input [7:0] AWLENS; // Write Burst Length + input [3:0] AWCACHES; // Write Cache type + input [1:0] AWUSERS; // Write inner & outer shareability + input [2:0] AWPROTS; // Write Protection type + +// Write Data channel signals + output WREADYS; // Write Data ready (slave ready to accept data) + input WVALIDS; // Write Data valid + input [127:0] WDATAS; // Write Data + input [15:0] WSTRBS; // Write byte-lane strobes + input WLASTS; // Write Data last transfer indicator + +// Write Response channel signals + input BREADYS; // Write Response ready (master ready to accept response) + output BVALIDS; // Write Response Valid + output [4:0] BIDS; // Write Response ID tag + output [1:0] BRESPS; // Write Response + +// Read Address channel signals + output ARREADYS; // Read Address ready (slave ready to accept read address) + input ARVALIDS; // Read Address valid + input [4:0] ARIDS; // Read Address ID + input [43:0] ARADDRS; // Read Address + input [7:0] ARLENS; // Read Burst Length + input [3:0] ARCACHES; // Read Cache type + input [1:0] ARUSERS; // Read inner & outer shareability + input [2:0] ARPROTS; // Read Protection type + +// Read Data channel signals + input RREADYS; // Read Data ready (master ready to accept data) + output RVALIDS; // Read Data valid + output [4:0] RIDS; // Read Data ID + output [127:0] RDATAS; // Read Data + output [1:0] RRESPS; // Read Data response + output RLASTS; // Read Data last transfer indicator + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (CLK) +//----------------------------------------------------------------------------- +// Debug CLK interface + input [43:12] DBGROMADDR; // Debug ROM base address + input DBGROMADDRV; // Debug ROM base address valid + + output [`MAIA_CN:0] DBGACK; // Debug acknowledge + output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt + output [`MAIA_CN:0] COMMRX; // Comms channel receive + output [`MAIA_CN:0] COMMTX; // Comms channel transmit + + output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request + output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request + + input DBGL1RSTDISABLE; // L1 DCache hardware reset disable + +// PMU CLK interface + output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request + output [24:0] PMUEVENT0; // PMU Event bus +// BEGIN INCLUDE FOR CPU1 + output [24:0] PMUEVENT1; // PMU Event bus +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + output [24:0] PMUEVENT2; // PMU Event bus +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + output [24:0] PMUEVENT3; // PMU Event bus +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (ATCLK) +//----------------------------------------------------------------------------- +// ETM ATB interface and Misc signals + input ATCLKEN; // ATB Clock Enable + input [63:0] TSVALUEB; // ATB Timestamp in binary + + input ATREADYM0; // ATDATA can be accepted + input AFVALIDM0; // ATB Fifo Flush Request + output [31:0] ATDATAM0; // ATB Data + output ATVALIDM0; // ATB Data Valid + output [1:0] ATBYTESM0; // ATB Data Size + output AFREADYM0; // ATB Fifo Flush Finished + output [6:0] ATIDM0; // ATB Trace Source ID + input SYNCREQM0; // ATB External synchronization request + +// BEGIN INCLUDE FOR CPU1 + input ATREADYM1; // ATDATA can be accepted + input AFVALIDM1; // ATB Fifo Flush Request + output [31:0] ATDATAM1; // ATB Data + output ATVALIDM1; // ATB Data Valid + output [1:0] ATBYTESM1; // ATB Data Size + output AFREADYM1; // ATB Fifo Flush Finished + output [6:0] ATIDM1; // ATB Trace Source ID + input SYNCREQM1; // ATB External synchronization request +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ATREADYM2; // ATDATA can be accepted + input AFVALIDM2; // ATB Fifo Flush Request + output [31:0] ATDATAM2; // ATB Data + output ATVALIDM2; // ATB Data Valid + output [1:0] ATBYTESM2; // ATB Data Size + output AFREADYM2; // ATB Fifo Flush Finished + output [6:0] ATIDM2; // ATB Trace Source ID + input SYNCREQM2; // ATB External synchronization request +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ATREADYM3; // ATDATA can be accepted + input AFVALIDM3; // ATB Fifo Flush Request + output [31:0] ATDATAM3; // ATB Data + output ATVALIDM3; // ATB Data Valid + output [1:0] ATBYTESM3; // ATB Data Size + output AFREADYM3; // ATB Fifo Flush Finished + output [6:0] ATIDM3; // ATB Trace Source ID + input SYNCREQM3; // ATB External synchronization request +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (PCLK) +//----------------------------------------------------------------------------- +// Debug-APBv3 port (APB) + input PCLKDBG; // APB Clock + input PCLKENDBG; // APB Clock Enable + input nPRESETDBG; // APB Reset + input PSELDBG; // Debug bus access + input [21:2] PADDRDBG; // APB address + input PADDRDBG31; // APB address bit[31] + input PENABLEDBG; // APB transfer complete flag + input PWRITEDBG; // APB read/write indicator + input [31:0] PWDATADBG; // APB write data + output [31:0] PRDATADBG; // APB read data + output PREADYDBG; // APB slave ready, used to extend a transfer + output PSLVERRDBG; // APB slave transfer error + +// Misc interface + input [`MAIA_CN:0] EDBGRQ; // External debug request + +// PMU Snapshot interface + input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request + output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge + +// Power-related interface + input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status + output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request + +// CTI interface + input [3:0] CTICHIN; // Channel In + input [3:0] CTICHOUTACK; // Channel Out acknowledge + output [3:0] CTICHOUT; // Channel Out + output [3:0] CTICHINACK; // Channel In acknowledge + input CISBYPASS; // Channel interface sync bypass + input [3:0] CIHSBYPASS; // Channel interface H/S bypass + output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt + input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge + +//----------------------------------------------------------------------------- +// Debug Authentication Interface (CLK & PCLK) +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] DBGEN; // Invasive debug enable + input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable + input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable + input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable + +//----------------------------------------------------------------------------- +// DFT Signals +//----------------------------------------------------------------------------- + input DFTSE; // Scan enable + input DFTRSTDISABLE; // Disable reset to cells during scan shift + input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr + input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 + input DFTRAMHOLD; // Holds data in RAMs + input DFTCLKBYPASS; // L2 RAM strobe clock bypass + input DFTMCPHOLD; // Disable multi-cycle RAM paths + +//----------------------------------------------------------------------------- +// MBIST Interface +//----------------------------------------------------------------------------- + input nMBISTRESET; // MBIST reset + input MBISTREQ; // MBIST mode request + +//----------------------------------------------------------------------------- +// Signals from maia -> maia_cpu_io -> maia_cpu +//----------------------------------------------------------------------------- +// Outputs to maia_cpu + output ncpuporeset_cpu0_o; + output ncorereset_cpu0_o; + + output cfgend_cpu0_o; + output cfgte_cpu0_o; + output cp15sdisable_cpu0_o; + output vinithi_cpu0_o; + output [7:0] clusteridaff1_cpu0_o; + output [7:0] clusteridaff2_cpu0_o; + output [1:0] cpuid_cpu0_o; + output aa64naa32_cpu0_o; + output [43:2] rvbaraddr_cpu0_o; + output cryptodisable_cpu0_o; + output giccdisable_cpu0_o; + + output [43:12] dbgromaddr_cpu0_o; + output dbgromaddrv_cpu0_o; + output dbgl1rstdisable_cpu0_o; + + output dbgen_cpu0_o; + output niden_cpu0_o; + output spiden_cpu0_o; + output spniden_cpu0_o; + + output [63:0] tsvalueb_cpu0_o; + + output atclken_cpu0_o; + output afvalidm_cpu0_o; + output atreadym_cpu0_o; + output syncreqm_cpu0_o; + + output dftse_cpu0_o; + output dftrstdisable_cpu0_o; + output dftcrclkdisable_cpu0_o; + output dftramhold_cpu0_o; + output nmbistreset_cpu0_o; + +// BEGIN INCLUDE FOR CPU1 + output ncpuporeset_cpu1_o; + output ncorereset_cpu1_o; + + output cfgend_cpu1_o; + output cfgte_cpu1_o; + output cp15sdisable_cpu1_o; + output vinithi_cpu1_o; + output [7:0] clusteridaff1_cpu1_o; + output [7:0] clusteridaff2_cpu1_o; + output [1:0] cpuid_cpu1_o; + output aa64naa32_cpu1_o; + output [43:2] rvbaraddr_cpu1_o; + output cryptodisable_cpu1_o; + output giccdisable_cpu1_o; + + output [43:12] dbgromaddr_cpu1_o; + output dbgromaddrv_cpu1_o; + output dbgl1rstdisable_cpu1_o; + + output dbgen_cpu1_o; + output niden_cpu1_o; + output spiden_cpu1_o; + output spniden_cpu1_o; + + output [63:0] tsvalueb_cpu1_o; + + output atclken_cpu1_o; + output afvalidm_cpu1_o; + output atreadym_cpu1_o; + output syncreqm_cpu1_o; + + output dftse_cpu1_o; + output dftrstdisable_cpu1_o; + output dftcrclkdisable_cpu1_o; + output dftramhold_cpu1_o; + output nmbistreset_cpu1_o; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + output ncpuporeset_cpu2_o; + output ncorereset_cpu2_o; + + output cfgend_cpu2_o; + output cfgte_cpu2_o; + output cp15sdisable_cpu2_o; + output vinithi_cpu2_o; + output [7:0] clusteridaff1_cpu2_o; + output [7:0] clusteridaff2_cpu2_o; + output [1:0] cpuid_cpu2_o; + output aa64naa32_cpu2_o; + output [43:2] rvbaraddr_cpu2_o; + output cryptodisable_cpu2_o; + output giccdisable_cpu2_o; + + output [43:12] dbgromaddr_cpu2_o; + output dbgromaddrv_cpu2_o; + output dbgl1rstdisable_cpu2_o; + + output dbgen_cpu2_o; + output niden_cpu2_o; + output spiden_cpu2_o; + output spniden_cpu2_o; + + output [63:0] tsvalueb_cpu2_o; + + output atclken_cpu2_o; + output afvalidm_cpu2_o; + output atreadym_cpu2_o; + output syncreqm_cpu2_o; + + output dftse_cpu2_o; + output dftrstdisable_cpu2_o; + output dftcrclkdisable_cpu2_o; + output dftramhold_cpu2_o; + output nmbistreset_cpu2_o; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + output ncpuporeset_cpu3_o; + output ncorereset_cpu3_o; + + output cfgend_cpu3_o; + output cfgte_cpu3_o; + output cp15sdisable_cpu3_o; + output vinithi_cpu3_o; + output [7:0] clusteridaff1_cpu3_o; + output [7:0] clusteridaff2_cpu3_o; + output [1:0] cpuid_cpu3_o; + output aa64naa32_cpu3_o; + output [43:2] rvbaraddr_cpu3_o; + output cryptodisable_cpu3_o; + output giccdisable_cpu3_o; + + output [43:12] dbgromaddr_cpu3_o; + output dbgromaddrv_cpu3_o; + output dbgl1rstdisable_cpu3_o; + + output dbgen_cpu3_o; + output niden_cpu3_o; + output spiden_cpu3_o; + output spniden_cpu3_o; + + output [63:0] tsvalueb_cpu3_o; + + output atclken_cpu3_o; + output afvalidm_cpu3_o; + output atreadym_cpu3_o; + output syncreqm_cpu3_o; + + output dftse_cpu3_o; + output dftrstdisable_cpu3_o; + output dftcrclkdisable_cpu3_o; + output dftramhold_cpu3_o; + output nmbistreset_cpu3_o; +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Signals from maia_cpu -> maia_cpu_io -> maia +//----------------------------------------------------------------------------- +// Inputs from maia_cpu + input ds_cpu0_sev_req; + input ds_cpu0_sevl_req; + input ds_cpu0_cpuectlr_smp; + + input ncommirq_cpu0_i; + input commrx_cpu0_i; + input commtx_cpu0_i; + input dbgack_cpu0_i; + input dbgrstreq_cpu0_i; + input dbgnopwrdwn_cpu0_i; + + input npmuirq_cpu0_i; + input [24:0] pmuevent_cpu0_i; + input pm_export_cpu0_i; + + input etclken_cpu0_i; + input afreadym_cpu0_i; + input [1:0] atbytesm_cpu0_i; + input [31:0] atdatam_cpu0_i; + input [6:0] atidm_cpu0_i; + input atvalidm_cpu0_i; + +// BEGIN INCLUDE FOR CPU1 + input ds_cpu1_sev_req; + input ds_cpu1_sevl_req; + input ds_cpu1_cpuectlr_smp; + + input ncommirq_cpu1_i; + input commrx_cpu1_i; + input commtx_cpu1_i; + input dbgack_cpu1_i; + input dbgrstreq_cpu1_i; + input dbgnopwrdwn_cpu1_i; + + input npmuirq_cpu1_i; + input [24:0] pmuevent_cpu1_i; + input pm_export_cpu1_i; + + input etclken_cpu1_i; + input afreadym_cpu1_i; + input [1:0] atbytesm_cpu1_i; + input [31:0] atdatam_cpu1_i; + input [6:0] atidm_cpu1_i; + input atvalidm_cpu1_i; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ds_cpu2_sev_req; + input ds_cpu2_sevl_req; + input ds_cpu2_cpuectlr_smp; + + input ncommirq_cpu2_i; + input commrx_cpu2_i; + input commtx_cpu2_i; + input dbgack_cpu2_i; + input dbgrstreq_cpu2_i; + input dbgnopwrdwn_cpu2_i; + + input npmuirq_cpu2_i; + input [24:0] pmuevent_cpu2_i; + input pm_export_cpu2_i; + + input etclken_cpu2_i; + input afreadym_cpu2_i; + input [1:0] atbytesm_cpu2_i; + input [31:0] atdatam_cpu2_i; + input [6:0] atidm_cpu2_i; + input atvalidm_cpu2_i; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ds_cpu3_sev_req; + input ds_cpu3_sevl_req; + input ds_cpu3_cpuectlr_smp; + + input ncommirq_cpu3_i; + input commrx_cpu3_i; + input commtx_cpu3_i; + input dbgack_cpu3_i; + input dbgrstreq_cpu3_i; + input dbgnopwrdwn_cpu3_i; + + input npmuirq_cpu3_i; + input [24:0] pmuevent_cpu3_i; + input pm_export_cpu3_i; + + input etclken_cpu3_i; + input afreadym_cpu3_i; + input [1:0] atbytesm_cpu3_i; + input [31:0] atdatam_cpu3_i; + input [6:0] atidm_cpu3_i; + input atvalidm_cpu3_i; +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// L2 interface +//----------------------------------------------------------------------------- + output [12:0] l2_cpu0_mbist1_addr_b1; + output [3:0] l2_cpu0_mbist1_array_b1; + output [7:0] l2_cpu0_mbist1_be_b1; + output l2_cpu0_mbist1_en_b1; + output l2_cpu0_mbist1_rd_en_b1; + output l2_cpu0_mbist1_wr_en_b1; + output l2_cpu0_mbist1_all_b1; + +// BEGIN INCLUDE FOR CPU1 + output [12:0] l2_cpu1_mbist1_addr_b1; + output [3:0] l2_cpu1_mbist1_array_b1; + output [7:0] l2_cpu1_mbist1_be_b1; + output l2_cpu1_mbist1_en_b1; + output l2_cpu1_mbist1_rd_en_b1; + output l2_cpu1_mbist1_wr_en_b1; + output l2_cpu1_mbist1_all_b1; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + output [12:0] l2_cpu2_mbist1_addr_b1; + output [3:0] l2_cpu2_mbist1_array_b1; + output [7:0] l2_cpu2_mbist1_be_b1; + output l2_cpu2_mbist1_en_b1; + output l2_cpu2_mbist1_rd_en_b1; + output l2_cpu2_mbist1_wr_en_b1; + output l2_cpu2_mbist1_all_b1; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + output [12:0] l2_cpu3_mbist1_addr_b1; + output [3:0] l2_cpu3_mbist1_array_b1; + output [7:0] l2_cpu3_mbist1_be_b1; + output l2_cpu3_mbist1_en_b1; + output l2_cpu3_mbist1_rd_en_b1; + output l2_cpu3_mbist1_wr_en_b1; + output l2_cpu3_mbist1_all_b1; +// END INCLUDE FOR CPU3 + +// BEGIN L2-CPU interface + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + output l2_cpu0_cfg_ecc_en; + output l2_cpu0_arb_thrshld_timeout_en; + output l2_cpu0_disable_clean_evict_opt; + output l2_cpu0_dext_err_r2; // LS external error + output l2_cpu0_dext_err_type_r2; // LS external error type + output l2_cpu0_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu0_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu0_ddata_r2; // LS read data + output l2_cpu0_barrier_done; // LS barrier complete + output l2_cpu0_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu0_spec_bufid; // LS read speculative response buffer id + output l2_cpu0_rvalid; // LS read response valid + output [1:0] l2_cpu0_rstate; // LS read response state + output l2_cpu0_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu0_rbufid; // LS read response buffer id + output l2_cpu0_dvalid_r1; // LS read data valid + output l2_cpu0_dlast_r1; // LS read last indicator + output [2:0] l2_cpu0_dbufid_r1; // LS read data fill buffer id + output l2_cpu0_iext_err_r2; // IF external error + output l2_cpu0_iext_err_type_r2; // IF external error type + output l2_cpu0_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu0_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu0_idata_r2; // IF read data + output l2_cpu0_ivalid_r1; // IF read data valid + output [1:0] l2_cpu0_ibufid_r1; // IF read data fill buffer id + output l2_cpu0_ls_sync_req; // LS sync req + output [48:0] l2_cpu0_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu0_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu0_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu0_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu0_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu0_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu0_ccb_req_info_c3; // LS ccb req info + output l2_cpu0_if_ccb_clken_c3; // IF ccb clken + output l2_cpu0_if_ccb_req_c3; // IF ccb req + output l2_cpu0_if_sync_req; // IF sync req + output l2_cpu0_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu0_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu0_tlb_sync_req; // TLB sync req + output l2_cpu0_tlb_sync_complete; // TLB sync complete + output l2_cpu0_tbw_desc_vld; // TBW descriptor valid + output l2_cpu0_tbw_ext_err; // TBW descriptor external error + output l2_cpu0_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu0_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu0_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu0_spr_rd_data; // DS spr read data + output [1:0] l2_cpu0_l2_cache_size; // DS L2 cache size + output l2_cpu0_pf_throttle_q; // PF throttling + + output l2_cpu0_wr_ex_resp; // store exclusive response + output l2_cpu0_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu0_ic_base; // PERIPHBASE + output l2_cpu0_no_intctrl; // INTCTLR not present + + + output [33:0] l2_cpu0_pmu_events; // L2 PMU events + + input ds_cpu0_l2_spr_en; // cpu0 early spr req for clk enables + input ds_cpu0_l2_spr_rd; // cpu0 spr read op + input ds_cpu0_l2_spr_wr; // cpu0 spr write op + input [8:0] ds_cpu0_l2_spr_addr; // cpu0 spr address + input ds_cpu0_l2_spr_dw; // cpu0 spr access dw + input [63:0] ds_cpu0_l2_spr_wr_data; // cpu0 spr write data + + input l2_cpu0_wr_data_vld_x1_q; // cpu0 write data vld x1 stage + input l2_cpu0_wr_evict_x1_q; // cpu0 write evict x1 stage + input [143:0] l2_cpu0_wr_data; + input l2_cpu0_ls_rd_haz_vld_arb_q; + input l2_cpu0_ls_wr_haz_vld_arb_q; + input l2_cpu0_dt_pmu_evt_en; // PMU enabled. + + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + output l2_cpu1_cfg_ecc_en; + output l2_cpu1_arb_thrshld_timeout_en; + output l2_cpu1_disable_clean_evict_opt; + output l2_cpu1_dext_err_r2; // LS external error + output l2_cpu1_dext_err_type_r2; // LS external error type + output l2_cpu1_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu1_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu1_ddata_r2; // LS read data + output l2_cpu1_barrier_done; // LS barrier complete + output l2_cpu1_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu1_spec_bufid; // LS read speculative response buffer id + output l2_cpu1_rvalid; // LS read response valid + output [1:0] l2_cpu1_rstate; // LS read response state + output l2_cpu1_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu1_rbufid; // LS read response buffer id + output l2_cpu1_dvalid_r1; // LS read data valid + output l2_cpu1_dlast_r1; // LS read last indicator + output [2:0] l2_cpu1_dbufid_r1; // LS read data fill buffer id + output l2_cpu1_iext_err_r2; // IF external error + output l2_cpu1_iext_err_type_r2; // IF external error type + output l2_cpu1_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu1_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu1_idata_r2; // IF read data + output l2_cpu1_ivalid_r1; // IF read data valid + output [1:0] l2_cpu1_ibufid_r1; // IF read data fill buffer id + output l2_cpu1_ls_sync_req; // LS sync req + output [48:0] l2_cpu1_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu1_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu1_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu1_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu1_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu1_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu1_ccb_req_info_c3; // LS ccb req info + output l2_cpu1_if_ccb_clken_c3; // IF ccb clken + output l2_cpu1_if_ccb_req_c3; // IF ccb req + output l2_cpu1_if_sync_req; // IF sync req + output l2_cpu1_tlb_ccb_clken_c3; // IF ccb clken + output l2_cpu1_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu1_tlb_sync_req; // TLB sync req + output l2_cpu1_tlb_sync_complete; // TLB sync complete + output l2_cpu1_tbw_desc_vld; // TBW descriptor valid + output l2_cpu1_tbw_ext_err; // TBW descriptor external error + output l2_cpu1_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu1_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu1_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu1_spr_rd_data; // DS spr read data + output [1:0] l2_cpu1_l2_cache_size; // DS L2 cache size + output l2_cpu1_pf_throttle_q; // PF throttling + + output l2_cpu1_wr_ex_resp; // store exclusive response + output l2_cpu1_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu1_ic_base; // PERIPHBASE + output l2_cpu1_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu1_pmu_events; // L2 PMU events + + input ds_cpu1_l2_spr_en; // cpu1 early spr req for clk enables + input ds_cpu1_l2_spr_rd; // cpu1 spr read op + input ds_cpu1_l2_spr_wr; // cpu1 spr write op + input [8:0] ds_cpu1_l2_spr_addr; // cpu1 spr address + input ds_cpu1_l2_spr_dw; // cpu1 spr access dw + input [63:0] ds_cpu1_l2_spr_wr_data; // cpu1 spr write data + + input l2_cpu1_wr_data_vld_x1_q; // cpu1 write data vld x1 stage + input l2_cpu1_wr_evict_x1_q; // cpu1 write evict x1 stage + input [143:0] l2_cpu1_wr_data; + input l2_cpu1_ls_rd_haz_vld_arb_q; + input l2_cpu1_ls_wr_haz_vld_arb_q; + input l2_cpu1_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + output l2_cpu2_cfg_ecc_en; + output l2_cpu2_arb_thrshld_timeout_en; + output l2_cpu2_disable_clean_evict_opt; + output l2_cpu2_dext_err_r2; // LS external error + output l2_cpu2_dext_err_type_r2; // LS external error type + output l2_cpu2_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu2_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu2_ddata_r2; // LS read data + output l2_cpu2_barrier_done; // LS barrier complete + output l2_cpu2_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu2_spec_bufid; // LS read speculative response buffer id + output l2_cpu2_rvalid; // LS read response valid + output [1:0] l2_cpu2_rstate; // LS read response state + output l2_cpu2_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu2_rbufid; // LS read response buffer id + output l2_cpu2_dvalid_r1; // LS read data valid + output l2_cpu2_dlast_r1; // LS read last indicator + output [2:0] l2_cpu2_dbufid_r1; // LS read data fill buffer id + output l2_cpu2_iext_err_r2; // IF external error + output l2_cpu2_iext_err_type_r2; // IF external error type + output l2_cpu2_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu2_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu2_idata_r2; // IF read data + output l2_cpu2_ivalid_r1; // IF read data valid + output [1:0] l2_cpu2_ibufid_r1; // IF read data fill buffer id + output l2_cpu2_ls_sync_req; // LS sync req + output [48:0] l2_cpu2_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu2_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu2_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu2_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu2_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu2_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu2_ccb_req_info_c3; // LS ccb req info + output l2_cpu2_if_ccb_clken_c3; // IF ccb clken + output l2_cpu2_if_ccb_req_c3; // IF ccb req + output l2_cpu2_if_sync_req; // IF sync req + output l2_cpu2_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu2_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu2_tlb_sync_req; // TLB sync req + output l2_cpu2_tlb_sync_complete; // TLB sync complete + output l2_cpu2_tbw_desc_vld; // TBW descriptor valid + output l2_cpu2_tbw_ext_err; // TBW descriptor external error + output l2_cpu2_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu2_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu2_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu2_spr_rd_data; // DS spr read data + output [1:0] l2_cpu2_l2_cache_size; // DS L2 cache size + output l2_cpu2_pf_throttle_q; // PF throttling + + output l2_cpu2_wr_ex_resp; // store exclusive response + output l2_cpu2_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu2_ic_base; // PERIPHBASE + output l2_cpu2_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu2_pmu_events; // L2 PMU events + + input ds_cpu2_l2_spr_en; // cpu2 early spr req for clk enables + input ds_cpu2_l2_spr_rd; // cpu2 spr read op + input ds_cpu2_l2_spr_wr; // cpu2 spr write op + input [8:0] ds_cpu2_l2_spr_addr; // cpu2 spr address + input ds_cpu2_l2_spr_dw; // cpu2 spr access dw + input [63:0] ds_cpu2_l2_spr_wr_data; // cpu2 spr write data + + input l2_cpu2_wr_data_vld_x1_q; // cpu2 write data vld x1 stage + input l2_cpu2_wr_evict_x1_q; // cpu2 write evict x1 stage + input [143:0] l2_cpu2_wr_data; + input l2_cpu2_ls_rd_haz_vld_arb_q; + input l2_cpu2_ls_wr_haz_vld_arb_q; + input l2_cpu2_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + output l2_cpu3_cfg_ecc_en; + output l2_cpu3_arb_thrshld_timeout_en; + output l2_cpu3_disable_clean_evict_opt; + output l2_cpu3_dext_err_r2; // LS external error + output l2_cpu3_dext_err_type_r2; // LS external error type + output l2_cpu3_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu3_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu3_ddata_r2; // LS read data + output l2_cpu3_barrier_done; // LS barrier complete + output l2_cpu3_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu3_spec_bufid; // LS read speculative response buffer id + output l2_cpu3_rvalid; // LS read response valid + output [1:0] l2_cpu3_rstate; // LS read response state + output l2_cpu3_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu3_rbufid; // LS read response buffer id + output l2_cpu3_dvalid_r1; // LS read data valid + output l2_cpu3_dlast_r1; // LS read last indicator + output [2:0] l2_cpu3_dbufid_r1; // LS read data fill buffer id + output l2_cpu3_iext_err_r2; // IF external error + output l2_cpu3_iext_err_type_r2; // IF external error type + output l2_cpu3_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu3_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu3_idata_r2; // IF read data + output l2_cpu3_ivalid_r1; // IF read data valid + output [1:0] l2_cpu3_ibufid_r1; // IF read data fill buffer id + output l2_cpu3_ls_sync_req; // LS sync req + output [48:0] l2_cpu3_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu3_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu3_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu3_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu3_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu3_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu3_ccb_req_info_c3; // LS ccb req info + output l2_cpu3_if_ccb_clken_c3; // IF ccb clken + output l2_cpu3_if_ccb_req_c3; // IF ccb req + output l2_cpu3_if_sync_req; // IF sync req + output l2_cpu3_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu3_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu3_tlb_sync_req; // TLB sync req + output l2_cpu3_tlb_sync_complete; // TLB sync complete + output l2_cpu3_tbw_desc_vld; // TBW descriptor valid + output l2_cpu3_tbw_ext_err; // TBW descriptor external error + output l2_cpu3_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu3_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu3_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu3_spr_rd_data; // DS spr read data + output [1:0] l2_cpu3_l2_cache_size; // DS L2 cache size + output l2_cpu3_pf_throttle_q; // PF throttling + + output l2_cpu3_wr_ex_resp; // store exclusive response + output l2_cpu3_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu3_ic_base; // PERIPHBASE + output l2_cpu3_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu3_pmu_events; // L2 PMU events + + input ds_cpu3_l2_spr_en; // cpu3 early spr req for clk enables + input ds_cpu3_l2_spr_rd; // cpu3 spr read op + input ds_cpu3_l2_spr_wr; // cpu3 spr write op + input [8:0] ds_cpu3_l2_spr_addr; // cpu3 spr address + input ds_cpu3_l2_spr_dw; // cpu3 spr access dw + input [63:0] ds_cpu3_l2_spr_wr_data; // cpu3 spr write data + + input l2_cpu3_wr_data_vld_x1_q; // cpu3 write data vld x1 stage + input l2_cpu3_wr_evict_x1_q; // cpu3 write evict x1 stage + input [143:0] l2_cpu3_wr_data; + input l2_cpu3_ls_rd_haz_vld_arb_q; + input l2_cpu3_ls_wr_haz_vld_arb_q; + input l2_cpu3_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// tag_pipe / cpu slave +//----------------------------------------------------------------------------- + output l2_cpu0_flsh_ls_rd_l2_dly; // cpu0 ls local hazard flush + output l2_cpu0_flsh_ls_wr_l2_dly; // cpu0 ls local hazard flush + + output l2_cpu0_wr_data_stall; // cpu0 write data stall + + output l2_cpu1_flsh_ls_rd_l2_dly; // cpu1 ls local hazard flush + output l2_cpu1_flsh_ls_wr_l2_dly; // cpu1 ls local hazard flush + + output l2_cpu1_wr_data_stall; // cpu1 write data stall + + output l2_cpu2_flsh_ls_rd_l2_dly; // cpu2 ls local hazard flush + output l2_cpu2_flsh_ls_wr_l2_dly; // cpu2 ls local hazard flush + + output l2_cpu2_wr_data_stall; // cpu2 write data stall + + output l2_cpu3_flsh_ls_rd_l2_dly; // cpu3 ls local hazard flush + output l2_cpu3_flsh_ls_wr_l2_dly; // cpu3 ls local hazard flush + + output l2_cpu3_wr_data_stall; // cpu3 write data stall + + output [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; // cpu0 ls id local hazard flush + output [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; // cpu0 ls id local hazard flush + + output [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; // cpu1 ls id local hazard flush + output [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; // cpu1 ls id local hazard flush + + output [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; // cpu2 ls id local hazard flush + output [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; // cpu2 ls id local hazard flush + + output [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; // cpu3 ls id local hazard flush + output [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; // cpu3 ls id local hazard flush + + output l2_cpu0_flsh_ls_rd_l4_dly; // cpu0 ls global hazard flush + output l2_cpu0_flsh_if_rd_l4_dly; // cpu0 if global hazard flush + output l2_cpu0_flsh_tw_rd_l4_dly; // cpu0 tw global hazard flush + output l2_cpu0_flsh_ls_wr_l4_dly; // cpu0 ls global hazard flush + + output l2_cpu1_flsh_ls_rd_l4_dly; // cpu1 ls global hazard flush + output l2_cpu1_flsh_if_rd_l4_dly; // cpu1 if global hazard flush + output l2_cpu1_flsh_tw_rd_l4_dly; // cpu1 tw global hazard flush + output l2_cpu1_flsh_ls_wr_l4_dly; // cpu1 ls global hazard flush + + output l2_cpu2_flsh_ls_rd_l4_dly; // cpu2 ls global hazard flush + output l2_cpu2_flsh_if_rd_l4_dly; // cpu2 if global hazard flush + output l2_cpu2_flsh_tw_rd_l4_dly; // cpu2 tw global hazard flush + output l2_cpu2_flsh_ls_wr_l4_dly; // cpu2 ls global hazard flush + + output l2_cpu3_flsh_ls_rd_l4_dly; // cpu3 ls global hazard flush + output l2_cpu3_flsh_if_rd_l4_dly; // cpu3 if global hazard flush + output l2_cpu3_flsh_tw_rd_l4_dly; // cpu3 tw global hazard flush + output l2_cpu3_flsh_ls_wr_l4_dly; // cpu3 ls global hazard flush + + output [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; // cpu0 ls id global hazard flush + output [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; // cpu0 if id global hazard flush + output [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; // cpu0 ls id global hazard flush + output l2_cpu0_flsh_ls_wr_evict_l4_dly; // cpu0 ls evict hazard + + output [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; // cpu1 ls id global hazard flush + output [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; // cpu1 if id global hazard flush + output [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; // cpu1 ls id global hazard flush + output l2_cpu1_flsh_ls_wr_evict_l4_dly; // cpu1 ls evict hazard + + output [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; // cpu2 ls id global hazard flush + output [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; // cpu2 if id global hazard flush + output [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; // cpu2 ls id global hazard flush + output l2_cpu2_flsh_ls_wr_evict_l4_dly; // cpu2 ls evict hazard + + output [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; // cpu3 ls id global hazard flush + output [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; // cpu3 if id global hazard flush + output [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; // cpu3 ls id global hazard flush + output l2_cpu3_flsh_ls_wr_evict_l4_dly; // cpu3 ls evict hazard + + output l2_cpu0_lrq_haz_pending; // cpu0 lrq hazard pending + output l2_cpu1_lrq_haz_pending; // cpu1 lrq hazard pending + output l2_cpu2_lrq_haz_pending; // cpu2 lrq hazard pending + output l2_cpu3_lrq_haz_pending; // cpu3 lrq hazard pending + + output l2_cpu0_ifq_haz_pending; // cpu0 ifq hazard pending + output l2_cpu1_ifq_haz_pending; // cpu1 ifq hazard pending + output l2_cpu2_ifq_haz_pending; // cpu2 ifq hazard pending + output l2_cpu3_ifq_haz_pending; // cpu3 ifq hazard pending + + output l2_cpu0_trq_haz_pending; // cpu0 trq hazard pending + output l2_cpu1_trq_haz_pending; // cpu1 trq hazard pending + output l2_cpu2_trq_haz_pending; // cpu2 trq hazard pending + output l2_cpu3_trq_haz_pending; // cpu3 trq hazard pending + + output l2_cpu0_wrq_haz_pending; // cpu0 wrq hazard pending + output l2_cpu1_wrq_haz_pending; // cpu1 wrq hazard pending + output l2_cpu2_wrq_haz_pending; // cpu2 wrq hazard pending + output l2_cpu3_wrq_haz_pending; // cpu3 wrq hazard pending + + output l2_cpu0_idle_block_reqs_q; // cpu0 idle block requests + output l2_cpu1_idle_block_reqs_q; // cpu1 idle block requests + output l2_cpu2_idle_block_reqs_q; // cpu2 idle block requests + output l2_cpu3_idle_block_reqs_q; // cpu3 idle block requests + + output l2_cpu0_ls_peq_coll_l4_dly; // cpu0 peq collision detected + output l2_cpu1_ls_peq_coll_l4_dly; // cpu1 peq collision detected + output l2_cpu2_ls_peq_coll_l4_dly; // cpu2 peq collision detected + output l2_cpu3_ls_peq_coll_l4_dly; // cpu3 peq collision detected + +//----------------------------------------------------------------------------- +// tag_pipe +//----------------------------------------------------------------------------- + output [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; // tbnk0 clear cpu0 lrq entry + output [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; // tbnk0 clear cpu1 lrq entry + output [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; // tbnk0 clear cpu2 lrq entry + output [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; // tbnk0 clear cpu3 lrq entry + + output [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; // tbnk1 clear cpu0 lrq entry + output [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; // tbnk1 clear cpu1 lrq entry + output [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; // tbnk1 clear cpu2 lrq entry + output [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; // tbnk1 clear cpu3 lrq entry + + output [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; // tbnk0 clear cpu0 ifq entry + output [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; // tbnk0 clear cpu1 ifq entry + output [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; // tbnk0 clear cpu2 ifq entry + output [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; // tbnk0 clear cpu3 ifq entry + + output [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; // tbnk1 clear cpu0 ifq entry + output [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; // tbnk1 clear cpu1 ifq entry + output [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; // tbnk1 clear cpu2 ifq entry + output [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; // tbnk1 clear cpu3 ifq entry + + output l2_tbnk0_cpu0_trq_clr_l4_dly2_q; // tbnk0 clear cpu0 trq entry + output l2_tbnk0_cpu1_trq_clr_l4_dly2_q; // tbnk0 clear cpu1 trq entry + output l2_tbnk0_cpu2_trq_clr_l4_dly2_q; // tbnk0 clear cpu2 trq entry + output l2_tbnk0_cpu3_trq_clr_l4_dly2_q; // tbnk0 clear cpu3 trq entry + + output l2_tbnk1_cpu0_trq_clr_l4_dly2_q; // tbnk1 clear cpu0 trq entry + output l2_tbnk1_cpu1_trq_clr_l4_dly2_q; // tbnk1 clear cpu1 trq entry + output l2_tbnk1_cpu2_trq_clr_l4_dly2_q; // tbnk1 clear cpu2 trq entry + output l2_tbnk1_cpu3_trq_clr_l4_dly2_q; // tbnk1 clear cpu3 trq entry + + output [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; // tbnk0 clear cpu0 wrq entry + output [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; // tbnk0 clear cpu1 wrq entry + output [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; // tbnk0 clear cpu2 wrq entry + output [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; // tbnk0 clear cpu3 wrq entry + + output [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; // tbnk1 clear cpu0 wrq entry + output [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; // tbnk1 clear cpu1 wrq entry + output [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; // tbnk1 clear cpu2 wrq entry + output [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; // tbnk1 clear cpu3 wrq entry + + +//----------------------------------------------------------------------------- +// cpu_logic / cpu slave +//----------------------------------------------------------------------------- + output l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu0 ls rd flsh l4 active + output l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu0 wr rd flsh l4 active + + output l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu1 ls rd flsh l4 active + output l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu1 wr rd flsh l4 active + + output l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu2 ls rd flsh l4 active + output l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu2 wr rd flsh l4 active + + output l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu3 ls rd flsh l4 active + output l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu3 wr rd flsh l4 active + + +//----------------------------------------------------------------------------- +// feq / cpu slave +//----------------------------------------------------------------------------- + input [129:0] l2_cpu0_dsq_rd_data_q; // cpu0 wrq/dsq data + input [15:0] l2_cpu0_dsq_rd_byte_strb_q; // cpu0 wrq/dsq byte strobes + input [129:0] l2_cpu1_dsq_rd_data_q; // cpu1 wrq/dsq data + input [15:0] l2_cpu1_dsq_rd_byte_strb_q; // cpu1 wrq/dsq byte strobes + input [129:0] l2_cpu2_dsq_rd_data_q; // cpu2 wrq/dsq data + input [15:0] l2_cpu2_dsq_rd_byte_strb_q; // cpu2 wrq/dsq byte strobes + input [129:0] l2_cpu3_dsq_rd_data_q; // cpu3 wrq/dsq data + input [15:0] l2_cpu3_dsq_rd_byte_strb_q; // cpu3 wrq/dsq byte strobes + + output l2_cpu0_dsq_clr_vld_q; // cpu0 dsq clear wrq vld entry + output [3:0] l2_cpu0_dsq_clr_id_q; // cpu0 dsq clear wrq buffer id + output l2_cpu0_dsq_rd_en; // cpu0 dsq/wrq data enable + output l2_cpu0_dsq_rd_en_x2; // cpu0 dsq/wrq data enable x2 + output [3:0] l2_cpu0_dsq_rd_buf_id; // cpu0 dsq/wrq data select + output l2_cpu1_dsq_clr_vld_q; // cpu1 dsq clear wrq vld entry + output [3:0] l2_cpu1_dsq_clr_id_q; // cpu1 dsq clear wrq buffer id + output l2_cpu1_dsq_rd_en; // cpu1 dsq/wrq data enable + output l2_cpu1_dsq_rd_en_x2; // cpu1 dsq/wrq data enable x2 + output [3:0] l2_cpu1_dsq_rd_buf_id; // cpu1 dsq/wrq data select + output l2_cpu2_dsq_clr_vld_q; // cpu2 dsq clear wrq vld entry + output [3:0] l2_cpu2_dsq_clr_id_q; // cpu2 dsq clear wrq buffer id + output l2_cpu2_dsq_rd_en; // cpu2 dsq/wrq data enable + output l2_cpu2_dsq_rd_en_x2; // cpu2 dsq/wrq data enable x2 + output [3:0] l2_cpu2_dsq_rd_buf_id; // cpu2 dsq/wrq data select + output l2_cpu3_dsq_clr_vld_q; // cpu3 dsq clear wrq vld entry + output l2_cpu3_dsq_rd_en; // cpu3 dsq/wrq data enable + output l2_cpu3_dsq_rd_en_x2; // cpu3 dsq/wrq data enable x2 + output [3:0] l2_cpu3_dsq_clr_id_q; // cpu3 dsq clear wrq buffer id + output [3:0] l2_cpu3_dsq_rd_buf_id; // cpu3 dsq/wrq data select + +//----------------------------------------------------------------------------- +// arbitration +//----------------------------------------------------------------------------- + output l2_cpu0_rd_vld_skid; // cpu0 read skid buffer valid + output l2_cpu1_rd_vld_skid; // cpu1 read skid buffer valid + output l2_cpu2_rd_vld_skid; // cpu2 read skid buffer valid + output l2_cpu3_rd_vld_skid; // cpu3 read skid buffer valid + + output l2_cpu0_pf_rd_vld_skid_popped; // cpu0 pf read skid buffer popped + output l2_cpu1_pf_rd_vld_skid_popped; // cpu1 pf read skid buffer popped + output l2_cpu2_pf_rd_vld_skid_popped; // cpu2 pf read skid buffer popped + output l2_cpu3_pf_rd_vld_skid_popped; // cpu3 pf read skid buffer popped + + output l2_cpu0_rd_arb; // + output l2_cpu1_rd_arb; // + output l2_cpu2_rd_arb; // + output l2_cpu3_rd_arb; // + + output l2_cpu0_wr_vld_skid; // cpu0 write skid buffer valid + output l2_cpu1_wr_vld_skid; // cpu1 write skid buffer valid + output l2_cpu2_wr_vld_skid; // cpu2 write skid buffer valid + output l2_cpu3_wr_vld_skid; // cpu3 write skid buffer valid + + output l2_cpu0_wr_arb; // + output l2_cpu1_wr_arb; // + output l2_cpu2_wr_arb; // + output l2_cpu3_wr_arb; // + + output l2_cpu0_ic_vld_skid; // cpu0 peripheral (ic) skid buffer valid + output l2_cpu1_ic_vld_skid; // cpu1 peripheral (ic) skid buffer valid + output l2_cpu2_ic_vld_skid; // cpu2 peripheral (ic) skid buffer valid + output l2_cpu3_ic_vld_skid; // cpu3 peripheral (ic) skid buffer valid + + output l2_cpu0_ic_barrier_stall_q; // cpu0 (ic) barrier stall + output l2_cpu1_ic_barrier_stall_q; // cpu1 (ic) barrier stall + output l2_cpu2_ic_barrier_stall_q; // cpu2 (ic) barrier stall + output l2_cpu3_ic_barrier_stall_q; // cpu3 (ic) barrier stall + + output l2_cpu0_blk_non_evict_wr; // cpu0 block non-evict writes from arbitrating + output l2_cpu1_blk_non_evict_wr; // cpu1 block non-evict writes from arbitrating + output l2_cpu2_blk_non_evict_wr; // cpu2 block non-evict writes from arbitrating + output l2_cpu3_blk_non_evict_wr; // cpu3 block non-evict writes from arbitrating + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + input l2_cpu0_idle_wakeup_q; // cpu0 idle wakeup + input l2_cpu0_rd_arb_fast; // cpu0 read arbitration fast request + input [4:0] l2_cpu0_rd_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu0_rd_lrq_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu0_rd_type_arb_set; // cpu0 read arbitration type + input [2:0] l2_cpu0_rd_cache_attr_arb_set; // cpu0 read arbitration cache attributes + input [7:0] l2_cpu0_rd_page_attr_arb_set; // cpu0 read arbitration page attributes + input [2:0] l2_cpu0_rd_elem_size_arb_set; // cpu0 read arbitration element size + input l2_cpu0_rd_way_arb_set; // cpu0 read arbitration way + input l2_cpu0_rd_replayed_arb_set; // cpu0 read arbitration replayed + input l2_cpu0_rd_excl_arb_set; // cpu0 read arbitration exclusive + input l2_cpu0_rd_priv_arb_set; // cpu0 read arbitration priv + input [1:0] l2_cpu0_rd_shared_arb_set; // cpu0 read arbitration shared + input l2_cpu0_rd_va48_arb_set; // cpu0 read arbitration va48 + input l2_cpu0_rd_aarch64_arb_set; // cpu0 read arbitration aarch64 + input [15:8] l2_cpu0_rd_asid_arb_set; // cpu0 read arbitration asid + input l2_cpu0_rd_prfm_arb_set; // cpu0 read arbitration prfm + input [44:0] l2_cpu0_rd_addr_arb_set; // cpu0 read arbitration address + input l2_cpu0_rd_bypass_arb_set; // cpu0 read arbitration bypass + input l2_cpu0_rd_bypass_req_can_e5; // cpu0 read arbitration bypass cancelled request + input l2_cpu0_early_rd_reqe4_e5_q; // cpu0 read arbitration bypass cancelled request + input l2_cpu0_rd_bypass_way_e5; // cpu0 read arbitration bypass way + input [2:0] l2_cpu0_rd_bypass_bufid_e5; // cpu0 read arbitration bypass bufid + input [2:0] l2_cpu0_rd_bypass_lrq_id_e5; // cpu0 read arbitration bypass bufid + + input l2_cpu0_wr_arb_fast; // cpu0 write arbitration fast request + input [3:0] l2_cpu0_wr_id_arb_set; // cpu0 write arbitration id for 1st qw + input [3:0] l2_cpu0_wr_partial_dw_arb_set; // cpu0 write partial qw byte strobe indicator + input [2:0] l2_cpu0_wr_cache_attr_arb_set; // cpu0 write arbitration cache attributes + input [7:0] l2_cpu0_wr_page_attr_arb_set; // cpu0 write arbitration page attributes + input [2:0] l2_cpu0_wr_elem_size_arb_set; // cpu0 write arbitration element size + input [2:0] l2_cpu0_wr_type_arb_set; // cpu0 write arbitration type + input [11:0] l2_cpu0_wr_cl_id_arb_set; // cpu0 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu0_wr_priv_arb_set; // cpu0 write arbitration priv + input [1:0] l2_cpu0_wr_shared_arb_set; // cpu0 write arbitration shared + input l2_cpu0_wr_last_arb_set; // cpu0 write arbitration last + input l2_cpu0_wr_clean_evict_arb_set; // cpu0 write arbitration clean eviction + input l2_cpu0_wr_err_arb_set; // cpu0 write arbitration error + input l2_cpu0_wr_way_arb_set; // cpu0 write arbitration way + input l2_cpu0_wr_dirty_arb_set; // cpu0 write arbitration dirty + input l2_cpu0_wr_1st_replayed_arb_set; // cpu0 write arbitration 1st replay indicator + input [44:0] l2_cpu0_wr_addr_arb_set; // cpu0 write arbitration address + input l2_cpu0_ic_arb_fast; // cpu0 peripheral (ic) arbitration fast request + input [2:0] l2_cpu0_ic_id_arb_set; // cpu0 peripheral (ic) fill buffer id + input l2_cpu0_ic_write_arb_set; // cpu0 peripheral (ic) write indicator + input l2_cpu0_ic_excl_arb_set; // cpu0 peripheral (ic) exclusive indicator + input [2:0] l2_cpu0_ic_elem_size_arb_set; // cpu0 peripheral (ic) element size + input l2_cpu0_ic_ns_arb_set; // cpu0 peripheral (ic) non-secure + input [15:0] l2_cpu0_ic_addr_arb_set; // cpu0 peripheral (ic) address + input [31:0] l2_cpu0_ic_data_arb_set; // cpu0 peripheral (ic) write data + + input l2_cpu0_wrq_almost_full; // cpu0 wrq almost full indicator + + input l2_cpu0_ls_wr_req_w2a; // cpu0 ls write request + input l2_cpu0_ls_wr_last_w2a; // cpu0 ls last indicator + input l2_cpu0_ls_wr_dirty_w2a; // cpu0 ls dirty indicator + input l2_cpu0_ls_wr_err_w2a; // cpu0 ls error indicator + input [2:0] l2_cpu0_ls_wr_type_w2a; // cpu0 ls write type + input [4:0] l2_cpu0_ls_wr_ccb_id_w2a; // cpu0 ls ccb id + input [127:0] l2_cpu0_ls_wr_data_w2a; // cpu0 ls write data + + input l2_cpu0_ls_ccb_resp; // cpu0 ls ccb resp + input [4:0] l2_cpu0_ls_ccb_resp_id; // cpu0 ls ccb id + input l2_cpu0_ls_ccb_data_wr; // cpu0 ls ccb data xfer + + input l2_cpu0_if_ccb_resp; // cpu0 if ccb resp + input [4:0] l2_cpu0_if_ccb_resp_id; // cpu0 if ccb id + + input l2_cpu0_tw_ccb_resp; // cpu0 tw ccb resp + input [4:0] l2_cpu0_tw_ccb_resp_id; // cpu0 tw ccb id + + input l2_cpu0_if_sync_done_q; // cpu0 sync response + input l2_cpu0_tlb_sync_done_q; // cpu0 tlb sync response + + input [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; // cpu0 lrq clear hazard id + input [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; // cpu0 wrq clear hazard id + input [3:0] l2_cpu0_ls_rd_haz_id_arb_q; // cpu0 ls rd wrq hazard id + input [2:0] l2_cpu0_ls_wr_haz_id_arb_q; // cpu0 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + input l2_cpu1_idle_wakeup_q; // cpu1 idle wakeup + input l2_cpu1_rd_arb_fast; // cpu1 read arbitration fast request + input [4:0] l2_cpu1_rd_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu1_rd_lrq_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu1_rd_type_arb_set; // cpu1 read arbitration type + input [2:0] l2_cpu1_rd_cache_attr_arb_set; // cpu1 read arbitration cache attributes + input [7:0] l2_cpu1_rd_page_attr_arb_set; // cpu1 read arbitration page attributes + input [2:0] l2_cpu1_rd_elem_size_arb_set; // cpu1 read arbitration element size + input l2_cpu1_rd_way_arb_set; // cpu1 read arbitration way + input l2_cpu1_rd_replayed_arb_set; // cpu1 read arbitration replayed + input l2_cpu1_rd_excl_arb_set; // cpu1 read arbitration exclusive + input l2_cpu1_rd_priv_arb_set; // cpu1 read arbitration priv + input [1:0] l2_cpu1_rd_shared_arb_set; // cpu1 read arbitration shared + input l2_cpu1_rd_va48_arb_set; // cpu1 read arbitration va48 + input l2_cpu1_rd_aarch64_arb_set; // cpu1 read arbitration aarch64 + input [15:8] l2_cpu1_rd_asid_arb_set; // cpu1 read arbitration asid + input l2_cpu1_rd_prfm_arb_set; // cpu1 read arbitration prfm + input [44:0] l2_cpu1_rd_addr_arb_set; // cpu1 read arbitration address + input l2_cpu1_rd_bypass_arb_set; // cpu1 read arbitration bypass + input l2_cpu1_rd_bypass_req_can_e5; // cpu1 read arbitration bypass cancelled request + input l2_cpu1_early_rd_reqe4_e5_q; // cpu1 read arbitration bypass cancelled request + input l2_cpu1_rd_bypass_way_e5; // cpu1 read arbitration bypass way + input [2:0] l2_cpu1_rd_bypass_bufid_e5; // cpu1 read arbitration bypass bufid + input [2:0] l2_cpu1_rd_bypass_lrq_id_e5; // cpu1 read arbitration bypass bufid + + input l2_cpu1_wr_arb_fast; // cpu1 write arbitration fast request + input [3:0] l2_cpu1_wr_id_arb_set; // cpu1 write arbitration id for 1st qw + input [3:0] l2_cpu1_wr_partial_dw_arb_set; // cpu1 write partial qw byte strobe indicator + input [2:0] l2_cpu1_wr_cache_attr_arb_set; // cpu1 write arbitration cache attributes + input [7:0] l2_cpu1_wr_page_attr_arb_set; // cpu1 write arbitration page attributes + input [2:0] l2_cpu1_wr_elem_size_arb_set; // cpu1 write arbitration element size + input [2:0] l2_cpu1_wr_type_arb_set; // cpu1 write arbitration type + input [11:0] l2_cpu1_wr_cl_id_arb_set; // cpu1 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu1_wr_priv_arb_set; // cpu1 write arbitration priv + input [1:0] l2_cpu1_wr_shared_arb_set; // cpu1 write arbitration shared + input l2_cpu1_wr_last_arb_set; // cpu1 write arbitration last + input l2_cpu1_wr_clean_evict_arb_set; // cpu1 write arbitration clean eviction + input l2_cpu1_wr_err_arb_set; // cpu1 write arbitration error + input l2_cpu1_wr_way_arb_set; // cpu1 write arbitration way + input l2_cpu1_wr_dirty_arb_set; // cpu1 write arbitration dirty + input l2_cpu1_wr_1st_replayed_arb_set; // cpu1 write arbitration 1st replay indicator + input [44:0] l2_cpu1_wr_addr_arb_set; // cpu1 write arbitration address + input l2_cpu1_ic_arb_fast; // cpu1 peripheral (ic) arbitration fast request + input [2:0] l2_cpu1_ic_id_arb_set; // cpu1 peripheral (ic) fill buffer id + input l2_cpu1_ic_write_arb_set; // cpu1 peripheral (ic) write indicator + input l2_cpu1_ic_excl_arb_set; // cpu1 peripheral (ic) exclusive indicator + input [2:0] l2_cpu1_ic_elem_size_arb_set; // cpu1 peripheral (ic) element size + input l2_cpu1_ic_ns_arb_set; // cpu1 peripheral (ic) non-secure + input [15:0] l2_cpu1_ic_addr_arb_set; // cpu1 peripheral (ic) address + input [31:0] l2_cpu1_ic_data_arb_set; // cpu1 peripheral (ic) write data + + input l2_cpu1_wrq_almost_full; // cpu1 wrq almost full indicator + + input l2_cpu1_ls_wr_req_w2a; // cpu1 ls write request + input l2_cpu1_ls_wr_last_w2a; // cpu1 ls last indicator + input l2_cpu1_ls_wr_dirty_w2a; // cpu1 ls dirty indicator + input l2_cpu1_ls_wr_err_w2a; // cpu1 ls error indicator + input [2:0] l2_cpu1_ls_wr_type_w2a; // cpu1 ls write type + input [4:0] l2_cpu1_ls_wr_ccb_id_w2a; // cpu1 ls ccb id + input [127:0] l2_cpu1_ls_wr_data_w2a; // cpu1 ls write data + + input l2_cpu1_ls_ccb_resp; // cpu1 ls ccb resp + input [4:0] l2_cpu1_ls_ccb_resp_id; // cpu1 ls ccb id + input l2_cpu1_ls_ccb_data_wr; // cpu1 ls ccb data xfer + + input l2_cpu1_if_ccb_resp; // cpu1 if ccb resp + input [4:0] l2_cpu1_if_ccb_resp_id; // cpu1 if ccb id + + input l2_cpu1_tw_ccb_resp; // cpu1 tw ccb resp + input [4:0] l2_cpu1_tw_ccb_resp_id; // cpu1 tw ccb id + + input l2_cpu1_if_sync_done_q; // cpu1 sync response + input l2_cpu1_tlb_sync_done_q; // cpu1 tlb sync response + + input [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; // cpu1 lrq clear hazard id + input [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; // cpu1 wrq clear hazard id + input [3:0] l2_cpu1_ls_rd_haz_id_arb_q; // cpu1 ls rd wrq hazard id + input [2:0] l2_cpu1_ls_wr_haz_id_arb_q; // cpu1 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + input l2_cpu2_idle_wakeup_q; // cpu2 idle wakeup + input l2_cpu2_rd_arb_fast; // cpu2 read arbitration fast request + input [4:0] l2_cpu2_rd_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu2_rd_lrq_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu2_rd_type_arb_set; // cpu2 read arbitration type + input [2:0] l2_cpu2_rd_cache_attr_arb_set; // cpu2 read arbitration cache attributes + input [7:0] l2_cpu2_rd_page_attr_arb_set; // cpu2 read arbitration page attributes + input [2:0] l2_cpu2_rd_elem_size_arb_set; // cpu2 read arbitration element size + input l2_cpu2_rd_way_arb_set; // cpu2 read arbitration way + input l2_cpu2_rd_replayed_arb_set; // cpu2 read arbitration replayed + input l2_cpu2_rd_excl_arb_set; // cpu2 read arbitration exclusive + input l2_cpu2_rd_priv_arb_set; // cpu2 read arbitration priv + input [1:0] l2_cpu2_rd_shared_arb_set; // cpu2 read arbitration shared + input l2_cpu2_rd_va48_arb_set; // cpu0 read arbitration va48 + input l2_cpu2_rd_aarch64_arb_set; // cpu2 read arbitration aarch64 + input [15:8] l2_cpu2_rd_asid_arb_set; // cpu2 read arbitration asid + input l2_cpu2_rd_prfm_arb_set; // cpu2 read arbitration prfm + input [44:0] l2_cpu2_rd_addr_arb_set; // cpu2 read arbitration address + input l2_cpu2_rd_bypass_arb_set; // cpu2 read arbitration bypass + input l2_cpu2_rd_bypass_req_can_e5; // cpu2 read arbitration bypass cancelled request + input l2_cpu2_early_rd_reqe4_e5_q; // cpu2 read arbitration bypass cancelled request + input l2_cpu2_rd_bypass_way_e5; // cpu2 read arbitration bypass way + input [2:0] l2_cpu2_rd_bypass_bufid_e5; // cpu2 read arbitration bypass bufid + input [2:0] l2_cpu2_rd_bypass_lrq_id_e5; // cpu2 read arbitration bypass bufid + + input l2_cpu2_wr_arb_fast; // cpu2 write arbitration fast request + input [3:0] l2_cpu2_wr_id_arb_set; // cpu2 write arbitration id for 1st qw + input [3:0] l2_cpu2_wr_partial_dw_arb_set; // cpu2 write partial qw byte strobe indicator + input [2:0] l2_cpu2_wr_cache_attr_arb_set; // cpu2 write arbitration cache attributes + input [7:0] l2_cpu2_wr_page_attr_arb_set; // cpu2 write arbitration page attributes + input [2:0] l2_cpu2_wr_elem_size_arb_set; // cpu2 write arbitration element size + input [2:0] l2_cpu2_wr_type_arb_set; // cpu2 write arbitration type + input [11:0] l2_cpu2_wr_cl_id_arb_set; // cpu2 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu2_wr_priv_arb_set; // cpu2 write arbitration priv + input [1:0] l2_cpu2_wr_shared_arb_set; // cpu2 write arbitration shared + input l2_cpu2_wr_last_arb_set; // cpu2 write arbitration last + input l2_cpu2_wr_clean_evict_arb_set; // cpu2 write arbitration clean eviction + input l2_cpu2_wr_err_arb_set; // cpu2 write arbitration error + input l2_cpu2_wr_way_arb_set; // cpu2 write arbitration way + input l2_cpu2_wr_dirty_arb_set; // cpu2 write arbitration dirty + input l2_cpu2_wr_1st_replayed_arb_set; // cpu2 write arbitration 1st replay indicator + input [44:0] l2_cpu2_wr_addr_arb_set; // cpu2 write arbitration address + input l2_cpu2_ic_arb_fast; // cpu2 peripheral (ic) arbitration fast request + input [2:0] l2_cpu2_ic_id_arb_set; // cpu2 peripheral (ic) fill buffer id + input l2_cpu2_ic_write_arb_set; // cpu2 peripheral (ic) write indicator + input l2_cpu2_ic_excl_arb_set; // cpu2 peripheral (ic) exclusive indicator + input [2:0] l2_cpu2_ic_elem_size_arb_set; // cpu2 peripheral (ic) element size + input l2_cpu2_ic_ns_arb_set; // cpu2 peripheral (ic) non-secure + input [15:0] l2_cpu2_ic_addr_arb_set; // cpu2 peripheral (ic) address + input [31:0] l2_cpu2_ic_data_arb_set; // cpu2 peripheral (ic) write data + + input l2_cpu2_wrq_almost_full; // cpu2 wrq almost full indicator + + input l2_cpu2_ls_wr_req_w2a; // cpu2 ls write request + input l2_cpu2_ls_wr_last_w2a; // cpu2 ls last indicator + input l2_cpu2_ls_wr_dirty_w2a; // cpu2 ls dirty indicator + input l2_cpu2_ls_wr_err_w2a; // cpu2 ls error indicator + input [2:0] l2_cpu2_ls_wr_type_w2a; // cpu2 ls write type + input [4:0] l2_cpu2_ls_wr_ccb_id_w2a; // cpu2 ls ccb id + input [127:0] l2_cpu2_ls_wr_data_w2a; // cpu2 ls write data + + input l2_cpu2_ls_ccb_resp; // cpu2 ls ccb resp + input [4:0] l2_cpu2_ls_ccb_resp_id; // cpu2 ls ccb id + input l2_cpu2_ls_ccb_data_wr; // cpu2 ls ccb data xfer + + input l2_cpu2_if_ccb_resp; // cpu2 if ccb resp + input [4:0] l2_cpu2_if_ccb_resp_id; // cpu2 if ccb id + + input l2_cpu2_tw_ccb_resp; // cpu2 tw ccb resp + input [4:0] l2_cpu2_tw_ccb_resp_id; // cpu2 tw ccb id + + input l2_cpu2_if_sync_done_q; // cpu2 sync response + input l2_cpu2_tlb_sync_done_q; // cpu2 tlb sync response + + input [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; // cpu2 lrq clear hazard id + input [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; // cpu2 wrq clear hazard id + input [3:0] l2_cpu2_ls_rd_haz_id_arb_q; // cpu2 ls rd wrq hazard id + input [2:0] l2_cpu2_ls_wr_haz_id_arb_q; // cpu2 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + input l2_cpu3_idle_wakeup_q; // cpu3 idle wakeup + input l2_cpu3_rd_arb_fast; // cpu3 read arbitration fast request + input [4:0] l2_cpu3_rd_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu3_rd_lrq_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu3_rd_type_arb_set; // cpu3 read arbitration type + input [2:0] l2_cpu3_rd_cache_attr_arb_set; // cpu3 read arbitration cache attributes + input [7:0] l2_cpu3_rd_page_attr_arb_set; // cpu3 read arbitration page attributes + input [2:0] l2_cpu3_rd_elem_size_arb_set; // cpu3 read arbitration element size + input l2_cpu3_rd_way_arb_set; // cpu3 read arbitration way + input l2_cpu3_rd_replayed_arb_set; // cpu3 read arbitration replayed + input l2_cpu3_rd_excl_arb_set; // cpu3 read arbitration exclusive + input l2_cpu3_rd_priv_arb_set; // cpu3 read arbitration priv + input [1:0] l2_cpu3_rd_shared_arb_set; // cpu3 read arbitration shared + input l2_cpu3_rd_va48_arb_set; // cpu3 read arbitration va48 + input l2_cpu3_rd_aarch64_arb_set; // cpu3 read arbitration aarch64 + input [15:8] l2_cpu3_rd_asid_arb_set; // cpu3 read arbitration asid + input l2_cpu3_rd_prfm_arb_set; // cpu3 read arbitration prfm + input [44:0] l2_cpu3_rd_addr_arb_set; // cpu3 read arbitration address + input l2_cpu3_rd_bypass_arb_set; // cpu3 read arbitration bypass + input l2_cpu3_rd_bypass_req_can_e5; // cpu3 read arbitration bypass cancelled request + input l2_cpu3_early_rd_reqe4_e5_q; // cpu3 read arbitration bypass cancelled request + input l2_cpu3_rd_bypass_way_e5; // cpu3 read arbitration bypass way + input [2:0] l2_cpu3_rd_bypass_bufid_e5; // cpu3 read arbitration bypass bufid + input [2:0] l2_cpu3_rd_bypass_lrq_id_e5; // cpu3 read arbitration bypass bufid + + input l2_cpu3_wr_arb_fast; // cpu3 write arbitration fast request + input [3:0] l2_cpu3_wr_id_arb_set; // cpu3 write arbitration id for 1st qw + input [3:0] l2_cpu3_wr_partial_dw_arb_set; // cpu3 write partial qw byte strobe indicator + input [2:0] l2_cpu3_wr_cache_attr_arb_set; // cpu3 write arbitration cache attributes + input [7:0] l2_cpu3_wr_page_attr_arb_set; // cpu3 write arbitration page attributes + input [2:0] l2_cpu3_wr_elem_size_arb_set; // cpu3 write arbitration element size + input [2:0] l2_cpu3_wr_type_arb_set; // cpu3 write arbitration type + input [11:0] l2_cpu3_wr_cl_id_arb_set; // cpu3 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu3_wr_priv_arb_set; // cpu3 write arbitration priv + input [1:0] l2_cpu3_wr_shared_arb_set; // cpu3 write arbitration shared + input l2_cpu3_wr_last_arb_set; // cpu3 write arbitration last + input l2_cpu3_wr_clean_evict_arb_set; // cpu3 write arbitration clean eviction + input l2_cpu3_wr_err_arb_set; // cpu3 write arbitration error + input l2_cpu3_wr_way_arb_set; // cpu3 write arbitration way + input l2_cpu3_wr_dirty_arb_set; // cpu3 write arbitration dirty + input l2_cpu3_wr_1st_replayed_arb_set; // cpu3 write arbitration 1st replay indicator + input [44:0] l2_cpu3_wr_addr_arb_set; // cpu3 write arbitration address + input l2_cpu3_ic_arb_fast; // cpu3 peripheral (ic) arbitration fast request + input [2:0] l2_cpu3_ic_id_arb_set; // cpu3 peripheral (ic) fill buffer id + input l2_cpu3_ic_write_arb_set; // cpu3 peripheral (ic) write indicator + input l2_cpu3_ic_excl_arb_set; // cpu3 peripheral (ic) exclusive indicator + input [2:0] l2_cpu3_ic_elem_size_arb_set; // cpu3 peripheral (ic) element size + input l2_cpu3_ic_ns_arb_set; // cpu3 peripheral (ic) non-secure + input [15:0] l2_cpu3_ic_addr_arb_set; // cpu3 peripheral (ic) address + input [31:0] l2_cpu3_ic_data_arb_set; // cpu3 peripheral (ic) write data + + input l2_cpu3_wrq_almost_full; // cpu3 wrq almost full indicator + + input l2_cpu3_ls_wr_req_w2a; // cpu3 ls write request + input l2_cpu3_ls_wr_last_w2a; // cpu3 ls last indicator + input l2_cpu3_ls_wr_dirty_w2a; // cpu3 ls dirty indicator + input l2_cpu3_ls_wr_err_w2a; // cpu3 ls error indicator + input [2:0] l2_cpu3_ls_wr_type_w2a; // cpu3 ls write type + input [4:0] l2_cpu3_ls_wr_ccb_id_w2a; // cpu3 ls ccb id + input [127:0] l2_cpu3_ls_wr_data_w2a; // cpu3 ls write data + + input l2_cpu3_ls_ccb_resp; // cpu3 ls ccb resp + input [4:0] l2_cpu3_ls_ccb_resp_id; // cpu3 ls ccb id + input l2_cpu3_ls_ccb_data_wr; // cpu3 ls ccb data xfer + + input l2_cpu3_if_ccb_resp; // cpu3 if ccb resp + input [4:0] l2_cpu3_if_ccb_resp_id; // cpu3 if ccb id + + input l2_cpu3_tw_ccb_resp; // cpu3 tw ccb resp + input [4:0] l2_cpu3_tw_ccb_resp_id; // cpu3 tw ccb id + + input l2_cpu3_if_sync_done_q; // cpu3 sync response + input l2_cpu3_tlb_sync_done_q; // cpu3 tlb sync response + + input [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; // cpu3 lrq clear hazard id + input [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; // cpu3 wrq clear hazard id + input [3:0] l2_cpu3_ls_rd_haz_id_arb_q; // cpu3 ls rd wrq hazard id + input [2:0] l2_cpu3_ls_wr_haz_id_arb_q; // cpu3 ls wr lrq hazard id + +// END L2-CPU interface + +//------------------------------------------------------------------- +// TM interface +//------------------------------------------------------------------- +// BEGIN TIMER-CPU interface + output [3:0] tm_cpu0_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu0_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu1_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu1_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu2_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu2_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu3_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu3_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> +// END TIMER-CPU interface + +//----------------------------------------------------------------------------- +// IC interface +//----------------------------------------------------------------------------- + input ls_cpu0_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu0_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu0_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu0_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu0_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu0_raw_eae_secure; // LS S LPAE to IC + + input ds_cpu0_ic_sample_spr; + input [4:0] ds_cpu0_ic_cpsr_mode; + input ds_cpu0_ic_aa64naa32; + input ds_cpu0_ic_hcr_change; + input ds_cpu0_ic_scr_change; +// BEGIN INCLUDE FOR CPU1 + input ds_cpu1_ic_sample_spr; + input [4:0] ds_cpu1_ic_cpsr_mode; + input ds_cpu1_ic_aa64naa32; + input ds_cpu1_ic_hcr_change; + input ds_cpu1_ic_scr_change; + input ls_cpu1_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu1_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu1_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu1_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu1_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu1_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input ds_cpu2_ic_sample_spr; + input [4:0] ds_cpu2_ic_cpsr_mode; + input ds_cpu2_ic_aa64naa32; + input ds_cpu2_ic_hcr_change; + input ds_cpu2_ic_scr_change; + input ls_cpu2_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu2_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu2_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu2_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu2_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu2_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input ds_cpu3_ic_sample_spr; + input [4:0] ds_cpu3_ic_cpsr_mode; + input ds_cpu3_ic_aa64naa32; + input ds_cpu3_ic_hcr_change; + input ds_cpu3_ic_scr_change; + input ls_cpu3_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu3_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu3_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu3_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu3_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu3_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU3 + + output [`MAIA_CN:0] ic_nfiq; // IC physical FIQ + output [`MAIA_CN:0] ic_nirq; // IC physical IRQ + output [`MAIA_CN:0] ic_nsei; // IC physical SEI + output [`MAIA_CN:0] ic_nvfiq; // IC virtual FIQ + output [`MAIA_CN:0] ic_nvirq; // IC virtual IRQ + output [`MAIA_CN:0] ic_nvsei; // IC virtual SEI + output [`MAIA_CN:0] ic_p_valid; // IC is present + + output [`MAIA_CN:0] ic_sample_spr; // IC sample signal for TC, TALL*, EL* signals + output [`MAIA_CN:0] ic_hcr_change_complete; + output [`MAIA_CN:0] ic_scr_change_complete; + output [`MAIA_CN:0] ic_el_change_complete; + output [`MAIA_CN:0] ic_ich_el2_tc; // IC trap common + output [`MAIA_CN:0] ic_ich_el2_tall0; // IC trap all grp0 + output [`MAIA_CN:0] ic_ich_el2_tall1; // IC trap all grp1 + output [`MAIA_CN:0] ic_sra_el3_en; // IC System Registers enabled in EL3 + output [`MAIA_CN:0] ic_sra_el1s_en; // IC System Registers enabled in EL1S + output [`MAIA_CN:0] ic_sra_el2_en; // IC System Registers enabled in EL2 + output [`MAIA_CN:0] ic_sra_el1ns_en; // IC System Registers enabled in EL1NS + output [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; // IC HYP_TRAP EL1NS accesses + output [`MAIA_CN:0] ic_sre_el1ns_mon_trap; // IC MON_TRAP EL1NS accesses + output [`MAIA_CN:0] ic_sre_el1s_mon_trap; // IC MON_TRAP EL1S accesses + output [`MAIA_CN:0] ic_sre_el2_mon_trap; // IC MON_TRAP EL2 accesses + output [`MAIA_CN:0] ic_block_eoi_sgi_wr; // IC Block all EOI and SGI write accesses + +//----------------------------------------------------------------------------- +// DT interface +//----------------------------------------------------------------------------- +// BEGIN DT-CPU interface +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + output dt_cpu0_dbif_req_pclk; // Debug Interface Req + output dt_cpu0_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu0_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu0_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu0_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu0_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu0_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu0_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu0_edbgrq_pclk; // External Debug Request + output dt_cpu0_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu0_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu0_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu0_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu0_et_oslock_gclk; // ETM OS Lock + input dt_cpu0_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu0_halt_ack_gclk; // Core Halted + input dt_cpu0_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu0_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu0_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu0_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu0_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu0_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu0_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu0_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu0_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu0_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu0_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu0_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu0_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu0_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu0_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + output dt_cpu1_dbif_req_pclk; // Debug Interface Req + output dt_cpu1_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu1_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu1_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu1_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu1_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu1_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu1_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu1_edbgrq_pclk; // External Debug Request + output dt_cpu1_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu1_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu1_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu1_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu1_et_oslock_gclk; // ETM OS Lock + input dt_cpu1_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu1_halt_ack_gclk; // Core Halted + input dt_cpu1_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu1_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu1_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu1_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu1_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu1_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu1_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu1_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu1_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu1_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu1_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu1_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu1_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu1_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu1_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + output dt_cpu2_dbif_req_pclk; // Debug Interface Req + output dt_cpu2_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu2_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu2_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu2_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu2_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu2_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu2_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu2_edbgrq_pclk; // External Debug Request + output dt_cpu2_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu2_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu2_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu2_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu2_et_oslock_gclk; // ETM OS Lock + input dt_cpu2_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu2_halt_ack_gclk; // Core Halted + input dt_cpu2_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu2_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu2_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu2_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu2_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu2_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu2_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu2_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu2_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu2_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu2_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu2_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu2_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu2_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu2_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + output dt_cpu3_dbif_req_pclk; // Debug Interface Req + output dt_cpu3_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu3_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu3_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu3_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu3_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu3_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu3_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu3_edbgrq_pclk; // External Debug Request + output dt_cpu3_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu3_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu3_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu3_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu3_et_oslock_gclk; // ETM OS Lock + input dt_cpu3_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu3_halt_ack_gclk; // Core Halted + input dt_cpu3_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu3_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu3_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu3_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu3_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu3_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu3_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu3_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu3_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu3_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu3_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu3_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu3_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu3_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu3_noclkstop_pclk; // force CPU clock on from DT-PCLK +// END DT-CPU interface + +//----------------------------------------------------------------------------- +// CK interface +//----------------------------------------------------------------------------- +// BEGIN CK-CPU interface + input ds_cpu0_reset_req; // Warm Reset request + input ds_cpu0_wfi_req; // WFI request + input ds_cpu0_wfe_req; // WFI request + input ds_cpu0_flush; // flush for exception rtn + input [5:0] ds_cpu0_flush_type; // flush type + input ds_cpu0_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu0_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu0_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu0_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu0_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu0_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu0_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu0_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu0_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu0_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu0_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu0_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu0_hcr_va; // virtual abort + input ds_cpu0_hcr_vi; // virtual IRQ + input ds_cpu0_hcr_vf; // virtual FIQ + input [2:0] ds_cpu0_cpuectlr_ret; // CPU Retention control + output ck_cpu0_event_reg; // WFE event reg + output ck_cpu0_wfi_ack; // WFI acknowledge to DS + output ck_cpu0_wfe_ack; // WFE acknowledge to DS + output ck_cpu0_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu1_reset_req; // Warm Reset request + input ds_cpu1_wfi_req; // WFI request + input ds_cpu1_wfe_req; // WFI request + input ds_cpu1_flush; // flush for exception rtn + input [5:0] ds_cpu1_flush_type; // flush type + input ds_cpu1_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu1_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu1_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu1_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu1_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu1_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu1_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu1_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu1_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu1_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu1_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu1_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu1_hcr_va; // virtual abort + input ds_cpu1_hcr_vi; // virtual IRQ + input ds_cpu1_hcr_vf; // virtual FIQ + input [2:0] ds_cpu1_cpuectlr_ret; // CPU Retention control + output ck_cpu1_event_reg; // WFE event reg + output ck_cpu1_wfi_ack; // WFI acknowledge to DS + output ck_cpu1_wfe_ack; // WFE acknowledge to DS + output ck_cpu1_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu2_reset_req; // Warm Reset request + input ds_cpu2_wfi_req; // WFI request + input ds_cpu2_wfe_req; // WFI request + input ds_cpu2_flush; // flush for exception rtn + input [5:0] ds_cpu2_flush_type; // flush type + input ds_cpu2_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu2_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu2_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu2_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu2_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu2_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu2_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu2_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu2_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu2_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu2_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu2_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu2_hcr_va; // virtual abort + input ds_cpu2_hcr_vi; // virtual IRQ + input ds_cpu2_hcr_vf; // virtual FIQ + input [2:0] ds_cpu2_cpuectlr_ret; // CPU Retention control + output ck_cpu2_event_reg; // WFE event reg + output ck_cpu2_wfi_ack; // WFI acknowledge to DS + output ck_cpu2_wfe_ack; // WFE acknowledge to DS + output ck_cpu2_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu3_reset_req; // Warm Reset request + input ds_cpu3_wfi_req; // WFI request + input ds_cpu3_wfe_req; // WFI request + input ds_cpu3_flush; // flush for exception rtn + input [5:0] ds_cpu3_flush_type; // flush type + input ds_cpu3_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu3_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu3_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu3_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu3_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu3_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu3_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu3_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu3_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu3_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu3_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu3_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu3_hcr_va; // virtual abort + input ds_cpu3_hcr_vi; // virtual IRQ + input ds_cpu3_hcr_vf; // virtual FIQ + input [2:0] ds_cpu3_cpuectlr_ret; // CPU Retention control + output ck_cpu3_event_reg; // WFE event reg + output ck_cpu3_wfi_ack; // WFI acknowledge to DS + output ck_cpu3_wfe_ack; // WFE acknowledge to DS + output ck_cpu3_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ls_cpu0_clrexmon; // LS global exclusive monitor + input ls_cpu1_clrexmon; // LS global exclusive monitor + input ls_cpu2_clrexmon; // LS global exclusive monitor + input ls_cpu3_clrexmon; // LS global exclusive monitor + +// END CK-CPU interface + + output [`MAIA_CN:0] ck_gclkt; + + + + // wires + wire ck_areset_l2; + wire ck_cpu0_areset_l2cpu; + wire ck_cpu0_areset_l2dt; + wire ck_cpu0_commrx; + wire ck_cpu0_commtx; + wire ck_cpu0_crcx_clk_en_n_ic; + wire ck_cpu0_dbgnopwrdwn; + wire ck_cpu0_dbgrstreq; + wire ck_cpu0_dt_standbywfx; + wire ck_cpu0_dt_wfx_ack; + wire ck_cpu0_l2_standbywfi; + wire ck_cpu0_l2_standbywfx; + wire ck_cpu0_ncommirq; + wire ck_cpu0_npmuirq; + wire ck_cpu0_poreset_status; + wire ck_cpu0_reset1_n_l2cpu; + wire ck_cpu0_reset1_n_l2dt; + wire ck_cpu1_areset_l2cpu; + wire ck_cpu1_areset_l2dt; + wire ck_cpu1_commrx; + wire ck_cpu1_commtx; + wire ck_cpu1_crcx_clk_en_n_ic; + wire ck_cpu1_dbgnopwrdwn; + wire ck_cpu1_dbgrstreq; + wire ck_cpu1_dt_standbywfx; + wire ck_cpu1_dt_wfx_ack; + wire ck_cpu1_l2_standbywfi; + wire ck_cpu1_l2_standbywfx; + wire ck_cpu1_ncommirq; + wire ck_cpu1_npmuirq; + wire ck_cpu1_poreset_status; + wire ck_cpu1_reset1_n_l2cpu; + wire ck_cpu1_reset1_n_l2dt; + wire ck_cpu2_areset_l2cpu; + wire ck_cpu2_areset_l2dt; + wire ck_cpu2_commrx; + wire ck_cpu2_commtx; + wire ck_cpu2_crcx_clk_en_n_ic; + wire ck_cpu2_dbgnopwrdwn; + wire ck_cpu2_dbgrstreq; + wire ck_cpu2_dt_standbywfx; + wire ck_cpu2_dt_wfx_ack; + wire ck_cpu2_l2_standbywfi; + wire ck_cpu2_l2_standbywfx; + wire ck_cpu2_ncommirq; + wire ck_cpu2_npmuirq; + wire ck_cpu2_poreset_status; + wire ck_cpu2_reset1_n_l2cpu; + wire ck_cpu2_reset1_n_l2dt; + wire ck_cpu3_areset_l2cpu; + wire ck_cpu3_areset_l2dt; + wire ck_cpu3_commrx; + wire ck_cpu3_commtx; + wire ck_cpu3_crcx_clk_en_n_ic; + wire ck_cpu3_dbgnopwrdwn; + wire ck_cpu3_dbgrstreq; + wire ck_cpu3_dt_standbywfx; + wire ck_cpu3_dt_wfx_ack; + wire ck_cpu3_l2_standbywfi; + wire ck_cpu3_l2_standbywfx; + wire ck_cpu3_ncommirq; + wire ck_cpu3_npmuirq; + wire ck_cpu3_poreset_status; + wire ck_cpu3_reset1_n_l2cpu; + wire ck_cpu3_reset1_n_l2dt; + wire ck_dt_cpu0_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu0_cti_trigin_1to0_gclk; + wire ck_dt_cpu0_et_oslock_gclk; + wire ck_dt_cpu0_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu0_os_double_lock_gclk; + wire ck_dt_cpu0_pmusnapshot_ack_gclk; + wire ck_dt_cpu0_wfx_dbg_req_gclk; + wire ck_dt_cpu1_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu1_cti_trigin_1to0_gclk; + wire ck_dt_cpu1_et_oslock_gclk; + wire ck_dt_cpu1_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu1_os_double_lock_gclk; + wire ck_dt_cpu1_pmusnapshot_ack_gclk; + wire ck_dt_cpu1_wfx_dbg_req_gclk; + wire ck_dt_cpu2_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu2_cti_trigin_1to0_gclk; + wire ck_dt_cpu2_et_oslock_gclk; + wire ck_dt_cpu2_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu2_os_double_lock_gclk; + wire ck_dt_cpu2_pmusnapshot_ack_gclk; + wire ck_dt_cpu2_wfx_dbg_req_gclk; + wire ck_dt_cpu3_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu3_cti_trigin_1to0_gclk; + wire ck_dt_cpu3_et_oslock_gclk; + wire ck_dt_cpu3_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu3_os_double_lock_gclk; + wire ck_dt_cpu3_pmusnapshot_ack_gclk; + wire ck_dt_cpu3_wfx_dbg_req_gclk; + wire ck_gclkb0; + wire ck_gclkb1; + wire ck_gclkfr; + wire ck_gclkl2; + wire ck_gclktl2; + wire ck_l2_ace_inactive; + wire ck_l2_acp_inactive; + wire ck_l2_logic_clk_en; + wire ck_l2_sky_link_deactivate; + wire ck_l2_tbnk0_clk_en; + wire ck_l2_tbnk1_clk_en; + wire ck_reset1_n_l2; + wire clrexmon_c1; + wire ds_cpu0_ic_aa64naa32_i; + wire [4:0] ds_cpu0_ic_cpsr_mode_i; + wire ds_cpu0_ic_hcr_change_i; + wire ds_cpu0_ic_sample_spr_i; + wire ds_cpu0_ic_scr_change_i; + wire ds_cpu1_ic_aa64naa32_i; + wire [4:0] ds_cpu1_ic_cpsr_mode_i; + wire ds_cpu1_ic_hcr_change_i; + wire ds_cpu1_ic_sample_spr_i; + wire ds_cpu1_ic_scr_change_i; + wire ds_cpu2_ic_aa64naa32_i; + wire [4:0] ds_cpu2_ic_cpsr_mode_i; + wire ds_cpu2_ic_hcr_change_i; + wire ds_cpu2_ic_sample_spr_i; + wire ds_cpu2_ic_scr_change_i; + wire ds_cpu3_ic_aa64naa32_i; + wire [4:0] ds_cpu3_ic_cpsr_mode_i; + wire ds_cpu3_ic_hcr_change_i; + wire ds_cpu3_ic_sample_spr_i; + wire ds_cpu3_ic_scr_change_i; + wire dt_cpu0_apb_active_pclk; + wire dt_cpu0_poreset_status_ack_pclk; + wire dt_cpu0_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu0_wfx_wakeup_pclk; + wire dt_cpu1_apb_active_pclk; + wire dt_cpu1_poreset_status_ack_pclk; + wire dt_cpu1_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu1_wfx_wakeup_pclk; + wire dt_cpu2_apb_active_pclk; + wire dt_cpu2_poreset_status_ack_pclk; + wire dt_cpu2_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu2_wfx_wakeup_pclk; + wire dt_cpu3_apb_active_pclk; + wire dt_cpu3_poreset_status_ack_pclk; + wire dt_cpu3_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu3_wfx_wakeup_pclk; + wire eventi_sev; + wire [`MAIA_CN:0] ic_block_eoi_sgi_wr_o; + wire ic_cpu0_l2_dsb_block; + wire [63:0] ic_cpu0_spr_rd_data; + wire ic_cpu1_l2_dsb_block; + wire [63:0] ic_cpu1_spr_rd_data; + wire ic_cpu2_l2_dsb_block; + wire [63:0] ic_cpu2_spr_rd_data; + wire ic_cpu3_l2_dsb_block; + wire [63:0] ic_cpu3_spr_rd_data; + wire [`MAIA_CN:0] ic_el_change_complete_o; + wire [`MAIA_CN:0] ic_hcr_change_complete_o; + wire [`MAIA_CN:0] ic_ich_el2_tall0_o; + wire [`MAIA_CN:0] ic_ich_el2_tall1_o; + wire [`MAIA_CN:0] ic_ich_el2_tc_o; + wire [`MAIA_CN:0] ic_nfiq_o; + wire [`MAIA_CN:0] ic_nirq_o; + wire [`MAIA_CN:0] ic_nsei_o; + wire [`MAIA_CN:0] ic_nvfiq_o; + wire [`MAIA_CN:0] ic_nvirq_o; + wire [`MAIA_CN:0] ic_nvsei_o; + wire [31:0] ic_p_rdata; + wire ic_p_rdata_valid; + wire ic_p_ready; + wire [`MAIA_CN:0] ic_sample_spr_o; + wire [`MAIA_CN:0] ic_scr_change_complete_o; + wire [`MAIA_CN:0] ic_sra_el1ns_en_o; + wire [`MAIA_CN:0] ic_sra_el1s_en_o; + wire [`MAIA_CN:0] ic_sra_el2_en_o; + wire [`MAIA_CN:0] ic_sra_el3_en_o; + wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap_o; + wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap_o; + wire [`MAIA_CN:0] ic_sre_el1s_mon_trap_o; + wire [`MAIA_CN:0] ic_sre_el2_mon_trap_o; + wire l2_acp_flsh_rd_cnt_active_glb_l2_dly; + wire l2_acp_flsh_wr_cnt_active_glb_l2_dly; + wire l2_acp_rd_haz_vld_l2_dly_q; + wire l2_acp_wr_haz_vld_l2_dly_q; + wire l2_actlr_disable_b2b_setway_hzd_opt_x2_ns; + wire l2_actlr_disable_setway_opt; + wire l2_actlr_ncpu_rcg_enable; + wire l2_actlr_plru_dynamic; + wire l2_actlr_plru_en; + wire [1:0] l2_actlr_plru_mode; + wire l2_actlr_writeunique_disable; + wire l2_cfg_broadcastinner; + wire l2_cfg_broadcastouter; + wire l2_cpu0_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu0_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu0_snp_active; + wire l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_wr_decerr_q; + wire l2_cpu0_wr_slverr_q; + wire l2_cpu1_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu1_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu1_snp_active; + wire l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_wr_decerr_q; + wire l2_cpu1_wr_slverr_q; + wire l2_cpu2_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu2_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu2_snp_active; + wire l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_wr_decerr_q; + wire l2_cpu2_wr_slverr_q; + wire l2_cpu3_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu3_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu3_snp_active; + wire l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_wr_decerr_q; + wire l2_cpu3_wr_slverr_q; + wire l2_ctlr_x1_wr_q; + wire [9:0] l2_ctlr_x2_ns; + wire l2_idle; + wire [`MAIA_CN:0] l2_mbist1_en_b1; + wire [16:0] l2_mbist2_tbnk0_addr_b1; + wire l2_mbist2_tbnk0_all_b1; + wire [2:0] l2_mbist2_tbnk0_array_b1; + wire [17:0] l2_mbist2_tbnk0_be_b1; + wire l2_mbist2_tbnk0_en_b1; + wire [143:0] l2_mbist2_tbnk0_indata_b1; + wire [143:0] l2_mbist2_tbnk0_outdata_b3; + wire l2_mbist2_tbnk0_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp0_outdata_b2; + wire l2_mbist2_tbnk0_snp0_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp0_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp1_outdata_b2; + wire l2_mbist2_tbnk0_snp1_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp1_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp2_outdata_b2; + wire l2_mbist2_tbnk0_snp2_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp2_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp3_outdata_b2; + wire l2_mbist2_tbnk0_snp3_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp3_sel_b1; + wire l2_mbist2_tbnk0_wr_en_b1; + wire [16:0] l2_mbist2_tbnk1_addr_b1; + wire l2_mbist2_tbnk1_all_b1; + wire [2:0] l2_mbist2_tbnk1_array_b1; + wire [17:0] l2_mbist2_tbnk1_be_b1; + wire l2_mbist2_tbnk1_en_b1; + wire [143:0] l2_mbist2_tbnk1_indata_b1; + wire [143:0] l2_mbist2_tbnk1_outdata_b3; + wire l2_mbist2_tbnk1_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp0_outdata_b2; + wire l2_mbist2_tbnk1_snp0_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp0_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp1_outdata_b2; + wire l2_mbist2_tbnk1_snp1_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp1_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp2_outdata_b2; + wire l2_mbist2_tbnk1_snp2_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp2_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp3_outdata_b2; + wire l2_mbist2_tbnk1_snp3_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp3_sel_b1; + wire l2_mbist2_tbnk1_wr_en_b1; + wire l2_no_ram_acc_nxt_cycle; + wire [13:0] l2_p_addr; + wire [1:0] l2_p_cpu; + wire l2_p_nsecure; + wire [2:0] l2_p_sel; + wire [31:0] l2_p_wdata; + wire l2_p_write; + wire l2_reset3; + wire l2_rstdisable_x1_q; + wire l2_sky_link_stopped; + wire l2_tbnk0_addr44_l3_q; + wire [44:0] l2_tbnk0_addr_l1; + wire [5:2] l2_tbnk0_addr_l6; + wire l2_tbnk0_all_tag_incl_active_l3; + wire l2_tbnk0_asq_cmp_evict_l3_q; + wire l2_tbnk0_asq_full_flsh; + wire l2_tbnk0_asq_nc_so_dev_limit; + wire [2:0] l2_tbnk0_cache_attr_l1; + wire l2_tbnk0_cfg_ecc_en; + wire l2_tbnk0_cmo_setway_l2_inv_incl_l4; + wire l2_tbnk0_cpu0_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu0_hit_l4; + wire l2_tbnk0_cpu0_l2_inv_l4_dly2; + wire l2_tbnk0_cpu0_l2hit_e_l4; + wire l2_tbnk0_cpu0_l2hit_s_l4; + wire l2_tbnk0_cpu0_peq_full_q; + wire l2_tbnk0_cpu0_peq_hit_q; + wire l2_tbnk0_cpu0_peq_self_evict_l3_q; + wire l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu0_rd_access_l4_dly; + wire l2_tbnk0_cpu0_self_evict_l4_dly_q; + wire l2_tbnk0_cpu0_single_ecc_err_l7_q; + wire l2_tbnk0_cpu0_snp_hit_e_l3; + wire l2_tbnk0_cpu0_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu0_snp_setway_addr_l3; + wire l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu0_vld_nxt_l5; + wire l2_tbnk0_cpu0_wr_access_l4_dly; + wire l2_tbnk0_cpu1_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu1_hit_l4; + wire l2_tbnk0_cpu1_l2_inv_l4_dly2; + wire l2_tbnk0_cpu1_l2hit_e_l4; + wire l2_tbnk0_cpu1_l2hit_s_l4; + wire l2_tbnk0_cpu1_peq_full_q; + wire l2_tbnk0_cpu1_peq_hit_q; + wire l2_tbnk0_cpu1_peq_self_evict_l3_q; + wire l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu1_rd_access_l4_dly; + wire l2_tbnk0_cpu1_self_evict_l4_dly_q; + wire l2_tbnk0_cpu1_single_ecc_err_l7_q; + wire l2_tbnk0_cpu1_snp_hit_e_l3; + wire l2_tbnk0_cpu1_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu1_snp_setway_addr_l3; + wire l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu1_vld_nxt_l5; + wire l2_tbnk0_cpu1_wr_access_l4_dly; + wire l2_tbnk0_cpu2_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu2_hit_l4; + wire l2_tbnk0_cpu2_l2_inv_l4_dly2; + wire l2_tbnk0_cpu2_l2hit_e_l4; + wire l2_tbnk0_cpu2_l2hit_s_l4; + wire l2_tbnk0_cpu2_peq_full_q; + wire l2_tbnk0_cpu2_peq_hit_q; + wire l2_tbnk0_cpu2_peq_self_evict_l3_q; + wire l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu2_rd_access_l4_dly; + wire l2_tbnk0_cpu2_self_evict_l4_dly_q; + wire l2_tbnk0_cpu2_single_ecc_err_l7_q; + wire l2_tbnk0_cpu2_snp_hit_e_l3; + wire l2_tbnk0_cpu2_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu2_snp_setway_addr_l3; + wire l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu2_vld_nxt_l5; + wire l2_tbnk0_cpu2_wr_access_l4_dly; + wire l2_tbnk0_cpu3_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu3_hit_l4; + wire l2_tbnk0_cpu3_l2_inv_l4_dly2; + wire l2_tbnk0_cpu3_l2hit_e_l4; + wire l2_tbnk0_cpu3_l2hit_s_l4; + wire l2_tbnk0_cpu3_peq_full_q; + wire l2_tbnk0_cpu3_peq_hit_q; + wire l2_tbnk0_cpu3_peq_self_evict_l3_q; + wire l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu3_rd_access_l4_dly; + wire l2_tbnk0_cpu3_self_evict_l4_dly_q; + wire l2_tbnk0_cpu3_single_ecc_err_l7_q; + wire l2_tbnk0_cpu3_snp_hit_e_l3; + wire l2_tbnk0_cpu3_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu3_snp_setway_addr_l3; + wire l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu3_vld_nxt_l5; + wire l2_tbnk0_cpu3_wr_access_l4_dly; + wire [3:0] l2_tbnk0_cpu_rvalid_init_nxt_l5; + wire [3:0] l2_tbnk0_cpu_rvalid_nxt_l5; + wire [3:0] l2_tbnk0_cpu_snp_hit_e_l4_q; + wire l2_tbnk0_crit_qw_nxt_l5; + wire [143:0] l2_tbnk0_data_corrected_l7_q; + wire [127:0] l2_tbnk0_data_l6; + wire l2_tbnk0_dbg_ram_acc_l5a; + wire [2:0] l2_tbnk0_dbg_ram_acc_unit_nxt; + wire [7:0] l2_tbnk0_dbg_ram_id_nxt_l5; + wire l2_tbnk0_dirty_l1; + wire l2_tbnk0_dirty_l3_q; + wire l2_tbnk0_dis_ns_dbg_arr_acc_x2; + wire l2_tbnk0_double_ecc_err_l7_q; + wire l2_tbnk0_early_rvalid_l4_q; + wire l2_tbnk0_ecc_fixup_blk_arb; + wire l2_tbnk0_ecc_fixup_inprog_dly_q; + wire l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q; + wire [31:0] l2_tbnk0_ecc_syndrome_reg_q; + wire l2_tbnk0_evict_special_hazard_l3_q; + wire l2_tbnk0_evict_special_hazard_rwvic_l3_q; + wire l2_tbnk0_excl_l1; + wire l2_tbnk0_excl_l4_q; + wire [44:6] l2_tbnk0_feq_addr_upd; + wire l2_tbnk0_feq_alloc_failed_l4; + wire l2_tbnk0_feq_axi_wr_vld_not_popped; + wire l2_tbnk0_feq_clr_l4; + wire [15:0] l2_tbnk0_feq_frc_incl_l3a; + wire l2_tbnk0_feq_kill_l3; + wire [4:0] l2_tbnk0_feq_last_id_q; + wire l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3; + wire l2_tbnk0_feq_tbnk_id_update_or_l3; + wire l2_tbnk0_full_miss_l4_q; + wire l2_tbnk0_hit_l4; + wire l2_tbnk0_hit_l7_q; + wire [3:0] l2_tbnk0_hit_way_l4_q; + wire [9:0] l2_tbnk0_id_l1; + wire [9:0] l2_tbnk0_id_l6_q; + wire [9:0] l2_tbnk0_id_nxt_l5; + wire l2_tbnk0_idle; + wire l2_tbnk0_init_req_l1; + wire l2_tbnk0_kill_l2; + wire l2_tbnk0_l2bb_fake_wr_l1; + wire l2_tbnk0_l2bb_wr_l1; + wire l2_tbnk0_l2hit_e_l4; + wire l2_tbnk0_l2hit_s_l4; + wire l2_tbnk0_l2v_s_q; + wire l2_tbnk0_l2v_vld_q; + wire l2_tbnk0_last_qw_l1; + wire l2_tbnk0_last_qw_l6_q; + wire l2_tbnk0_last_qw_nxt_l5; + wire [2:0] l2_tbnk0_lock_l1; + wire [2:0] l2_tbnk0_lock_l4; + wire [32:0] l2_tbnk0_merrsr_data; + wire [9:0] l2_tbnk0_page_attr_l1; + wire l2_tbnk0_partial_dw_wr_l1; + wire l2_tbnk0_pf_cnt_dec_l4_dly; + wire l2_tbnk0_pf_hazard_l3; + wire l2_tbnk0_pf_req_sel_for_fwd_l4; + wire l2_tbnk0_prfm_l1; + wire l2_tbnk0_prfm_nxt_l5; + wire [3:0] l2_tbnk0_prot_l1; + wire [3:0] l2_tbnk0_prot_l4_q; + wire [1:0] l2_tbnk0_qw_cnt_l1; + wire [1:0] l2_tbnk0_qw_cnt_l3_q; + wire l2_tbnk0_raw_hit_l4_q; + wire [2:0] l2_tbnk0_rbufid_nxt_l5; + wire l2_tbnk0_rd_en_nxt_l5; + wire l2_tbnk0_rd_fail_hazchk_feq_l3; + wire l2_tbnk0_rwvic_axi_read_err_l1; + wire l2_tbnk0_rwvic_axi_read_err_l3_q; + wire l2_tbnk0_rwvic_ccb_dirty_l6_q; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l1; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l3_q; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l6_q; + wire [3:0] l2_tbnk0_rwvic_ccb_way_l1; + wire l2_tbnk0_rwvic_cmo_clean_l1; + wire l2_tbnk0_rwvic_cmo_inv_l1; + wire l2_tbnk0_rwvic_cmo_inv_l7_q; + wire l2_tbnk0_rwvic_cmo_l7_q; + wire l2_tbnk0_rwvic_cmo_pou_l1; + wire l2_tbnk0_rwvic_cmo_pou_l6_q; + wire l2_tbnk0_rwvic_cmo_setway_l1; + wire l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1; + wire l2_tbnk0_rwvic_cmo_setway_ls_l6_q; + wire [2:0] l2_tbnk0_rwvic_cpu_fb_id_l1; + wire [3:0] l2_tbnk0_rwvic_cpu_id_dcd_l1; + wire l2_tbnk0_rwvic_ddi_l6_q; + wire l2_tbnk0_rwvic_feq_cmp_l3_q; + wire l2_tbnk0_rwvic_frc_l2hit_fwd_l1; + wire l2_tbnk0_rwvic_l2hit_e_l1; + wire l2_tbnk0_rwvic_l2hit_e_l3_q; + wire l2_tbnk0_rwvic_l2hit_e_l7_q; + wire l2_tbnk0_rwvic_l2v_dirty_l7_q; + wire [3:0] l2_tbnk0_rwvic_l2v_page_attr_l7_q; + wire l2_tbnk0_rwvic_l2v_vld_l6_q; + wire l2_tbnk0_rwvic_mesi_sh_l1; + wire l2_tbnk0_rwvic_non_snp_fail_hazchk_l3; + wire [2:0] l2_tbnk0_rwvic_owner_l1; + wire [2:0] l2_tbnk0_rwvic_owner_l7_q; + wire l2_tbnk0_rwvic_rd_type_l6_q; + wire l2_tbnk0_rwvic_snp_clr_dirty_l1; + wire l2_tbnk0_rwvic_snp_inv_l1; + wire l2_tbnk0_rwvic_snp_l1; + wire l2_tbnk0_rwvic_snp_l3_q; + wire l2_tbnk0_rwvic_snp_l6_q; + wire l2_tbnk0_rwvic_tag_wr_l0; + wire [3:0] l2_tbnk0_rwvic_type_l1; + wire l2_tbnk0_rwvic_wa_l1; + wire l2_tbnk0_rwvic_wa_l6_q; + wire [13:0] l2_tbnk0_sel_l1; + wire [2:0] l2_tbnk0_size_l1; + wire [2:0] l2_tbnk0_size_l4_q; + wire l2_tbnk0_snp_byp_peq_haz_pending_q; + wire l2_tbnk0_snp_dvm_cmpl_l1; + wire l2_tbnk0_snp_hit_e_l4_q; + wire l2_tbnk0_snp_hit_feq_evict_l4_dly; + wire l2_tbnk0_snp_hit_s_l4_q; + wire [4:0] l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q; + wire [7:0] l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q; + wire [7:0] l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q; + wire [44:7] l2_tbnk0_snp_tag_wr_l2_hit_addr_l1; + wire [1:0] l2_tbnk0_snp_tag_wr_l2_hit_state_l1; + wire l2_tbnk0_snp_tag_wr_l2_hit_way_l1; + wire l2_tbnk0_special_evict_hazard_l3; + wire l2_tbnk0_special_hazard_l3_q; + wire l2_tbnk0_sync_l1; + wire l2_tbnk0_tag_ecc_dbl_rmw_wr_l1; + wire l2_tbnk0_tag_ecc_err_cpu0_l4; + wire l2_tbnk0_tag_ecc_err_cpu1_l4; + wire l2_tbnk0_tag_ecc_err_cpu2_l4; + wire l2_tbnk0_tag_ecc_err_cpu3_l4; + wire l2_tbnk0_tag_ecc_err_l4; + wire [6:0] l2_tbnk0_type_l1; + wire [1:0] l2_tbnk0_ulen_l1; + wire [1:0] l2_tbnk0_ulen_l4_q; + wire l2_tbnk0_vld_init_l6_q; + wire l2_tbnk0_vld_l6_q; + wire l2_tbnk0_way_l1; + wire l2_tbnk0_way_l4_q; + wire l2_tbnk0_way_nxt_l3a; + wire [143:0] l2_tbnk0_wr_data_l3; + wire [127:0] l2_tbnk0_wr_data_l3a_q; + wire l2_tbnk0_wr_data_l4_en; + wire l2_tbnk0_wr_err_l1; + wire l2_tbnk0_wr_fail_feq_full_l3; + wire l2_tbnk0_wr_fail_hazchk_feq_l3; + wire [11:0] l2_tbnk0_wr_non_crit_id_l1; + wire [11:0] l2_tbnk0_wr_non_crit_id_l4_q; + wire [15:0] l2_tbnk0_wr_strb_mask_l3a_q; + wire l2_tbnk1_addr44_l3_q; + wire [44:0] l2_tbnk1_addr_l1; + wire [5:2] l2_tbnk1_addr_l6; + wire l2_tbnk1_all_tag_incl_active_l3; + wire l2_tbnk1_asq_cmp_evict_l3_q; + wire l2_tbnk1_asq_full_flsh; + wire l2_tbnk1_asq_nc_so_dev_limit; + wire [2:0] l2_tbnk1_cache_attr_l1; + wire l2_tbnk1_cfg_ecc_en; + wire l2_tbnk1_cmo_setway_l2_inv_incl_l4; + wire l2_tbnk1_cpu0_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu0_hit_l4; + wire l2_tbnk1_cpu0_l2_inv_l4_dly2; + wire l2_tbnk1_cpu0_l2hit_e_l4; + wire l2_tbnk1_cpu0_l2hit_s_l4; + wire l2_tbnk1_cpu0_peq_full_q; + wire l2_tbnk1_cpu0_peq_hit_q; + wire l2_tbnk1_cpu0_peq_self_evict_l3_q; + wire l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu0_rd_access_l4_dly; + wire l2_tbnk1_cpu0_self_evict_l4_dly_q; + wire l2_tbnk1_cpu0_single_ecc_err_l7_q; + wire l2_tbnk1_cpu0_snp_hit_e_l3; + wire l2_tbnk1_cpu0_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu0_snp_setway_addr_l3; + wire l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu0_vld_nxt_l5; + wire l2_tbnk1_cpu0_wr_access_l4_dly; + wire l2_tbnk1_cpu1_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu1_hit_l4; + wire l2_tbnk1_cpu1_l2_inv_l4_dly2; + wire l2_tbnk1_cpu1_l2hit_e_l4; + wire l2_tbnk1_cpu1_l2hit_s_l4; + wire l2_tbnk1_cpu1_peq_full_q; + wire l2_tbnk1_cpu1_peq_hit_q; + wire l2_tbnk1_cpu1_peq_self_evict_l3_q; + wire l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu1_rd_access_l4_dly; + wire l2_tbnk1_cpu1_self_evict_l4_dly_q; + wire l2_tbnk1_cpu1_single_ecc_err_l7_q; + wire l2_tbnk1_cpu1_snp_hit_e_l3; + wire l2_tbnk1_cpu1_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu1_snp_setway_addr_l3; + wire l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu1_vld_nxt_l5; + wire l2_tbnk1_cpu1_wr_access_l4_dly; + wire l2_tbnk1_cpu2_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu2_hit_l4; + wire l2_tbnk1_cpu2_l2_inv_l4_dly2; + wire l2_tbnk1_cpu2_l2hit_e_l4; + wire l2_tbnk1_cpu2_l2hit_s_l4; + wire l2_tbnk1_cpu2_peq_full_q; + wire l2_tbnk1_cpu2_peq_hit_q; + wire l2_tbnk1_cpu2_peq_self_evict_l3_q; + wire l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu2_rd_access_l4_dly; + wire l2_tbnk1_cpu2_self_evict_l4_dly_q; + wire l2_tbnk1_cpu2_single_ecc_err_l7_q; + wire l2_tbnk1_cpu2_snp_hit_e_l3; + wire l2_tbnk1_cpu2_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu2_snp_setway_addr_l3; + wire l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu2_vld_nxt_l5; + wire l2_tbnk1_cpu2_wr_access_l4_dly; + wire l2_tbnk1_cpu3_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu3_hit_l4; + wire l2_tbnk1_cpu3_l2_inv_l4_dly2; + wire l2_tbnk1_cpu3_l2hit_e_l4; + wire l2_tbnk1_cpu3_l2hit_s_l4; + wire l2_tbnk1_cpu3_peq_full_q; + wire l2_tbnk1_cpu3_peq_hit_q; + wire l2_tbnk1_cpu3_peq_self_evict_l3_q; + wire l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu3_rd_access_l4_dly; + wire l2_tbnk1_cpu3_self_evict_l4_dly_q; + wire l2_tbnk1_cpu3_single_ecc_err_l7_q; + wire l2_tbnk1_cpu3_snp_hit_e_l3; + wire l2_tbnk1_cpu3_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu3_snp_setway_addr_l3; + wire l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu3_vld_nxt_l5; + wire l2_tbnk1_cpu3_wr_access_l4_dly; + wire [3:0] l2_tbnk1_cpu_rvalid_init_nxt_l5; + wire [3:0] l2_tbnk1_cpu_rvalid_nxt_l5; + wire [3:0] l2_tbnk1_cpu_snp_hit_e_l4_q; + wire l2_tbnk1_crit_qw_nxt_l5; + wire [143:0] l2_tbnk1_data_corrected_l7_q; + wire [127:0] l2_tbnk1_data_l6; + wire l2_tbnk1_dbg_ram_acc_l5a; + wire [2:0] l2_tbnk1_dbg_ram_acc_unit_nxt; + wire [7:0] l2_tbnk1_dbg_ram_id_nxt_l5; + wire l2_tbnk1_dirty_l1; + wire l2_tbnk1_dirty_l3_q; + wire l2_tbnk1_dis_ns_dbg_arr_acc_x2; + wire l2_tbnk1_double_ecc_err_l7_q; + wire l2_tbnk1_early_rvalid_l4_q; + wire l2_tbnk1_ecc_fixup_blk_arb; + wire l2_tbnk1_ecc_fixup_inprog_dly_q; + wire l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q; + wire [31:0] l2_tbnk1_ecc_syndrome_reg_q; + wire l2_tbnk1_evict_special_hazard_l3_q; + wire l2_tbnk1_evict_special_hazard_rwvic_l3_q; + wire l2_tbnk1_excl_l1; + wire l2_tbnk1_excl_l4_q; + wire [44:6] l2_tbnk1_feq_addr_upd; + wire l2_tbnk1_feq_alloc_failed_l4; + wire l2_tbnk1_feq_axi_wr_vld_not_popped; + wire l2_tbnk1_feq_clr_l4; + wire [15:0] l2_tbnk1_feq_frc_incl_l3a; + wire l2_tbnk1_feq_kill_l3; + wire [4:0] l2_tbnk1_feq_last_id_q; + wire l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3; + wire l2_tbnk1_feq_tbnk_id_update_or_l3; + wire l2_tbnk1_full_miss_l4_q; + wire l2_tbnk1_hit_l4; + wire l2_tbnk1_hit_l7_q; + wire [3:0] l2_tbnk1_hit_way_l4_q; + wire [9:0] l2_tbnk1_id_l1; + wire [9:0] l2_tbnk1_id_l6_q; + wire [9:0] l2_tbnk1_id_nxt_l5; + wire l2_tbnk1_idle; + wire l2_tbnk1_init_req_l1; + wire l2_tbnk1_kill_l2; + wire l2_tbnk1_l2bb_fake_wr_l1; + wire l2_tbnk1_l2bb_wr_l1; + wire l2_tbnk1_l2hit_e_l4; + wire l2_tbnk1_l2hit_s_l4; + wire l2_tbnk1_l2v_s_q; + wire l2_tbnk1_l2v_vld_q; + wire l2_tbnk1_last_qw_l1; + wire l2_tbnk1_last_qw_l6_q; + wire l2_tbnk1_last_qw_nxt_l5; + wire [2:0] l2_tbnk1_lock_l1; + wire [2:0] l2_tbnk1_lock_l4; + wire [32:0] l2_tbnk1_merrsr_data; + wire [9:0] l2_tbnk1_page_attr_l1; + wire l2_tbnk1_partial_dw_wr_l1; + wire l2_tbnk1_pf_cnt_dec_l4_dly; + wire l2_tbnk1_pf_hazard_l3; + wire l2_tbnk1_pf_req_sel_for_fwd_l4; + wire l2_tbnk1_prfm_l1; + wire l2_tbnk1_prfm_nxt_l5; + wire [3:0] l2_tbnk1_prot_l1; + wire [3:0] l2_tbnk1_prot_l4_q; + wire [1:0] l2_tbnk1_qw_cnt_l1; + wire [1:0] l2_tbnk1_qw_cnt_l3_q; + wire l2_tbnk1_raw_hit_l4_q; + wire [2:0] l2_tbnk1_rbufid_nxt_l5; + wire l2_tbnk1_rd_en_nxt_l5; + wire l2_tbnk1_rd_fail_hazchk_feq_l3; + wire l2_tbnk1_rwvic_axi_read_err_l1; + wire l2_tbnk1_rwvic_axi_read_err_l3_q; + wire l2_tbnk1_rwvic_ccb_dirty_l6_q; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l1; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l3_q; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l6_q; + wire [3:0] l2_tbnk1_rwvic_ccb_way_l1; + wire l2_tbnk1_rwvic_cmo_clean_l1; + wire l2_tbnk1_rwvic_cmo_inv_l1; + wire l2_tbnk1_rwvic_cmo_inv_l7_q; + wire l2_tbnk1_rwvic_cmo_l7_q; + wire l2_tbnk1_rwvic_cmo_pou_l1; + wire l2_tbnk1_rwvic_cmo_pou_l6_q; + wire l2_tbnk1_rwvic_cmo_setway_l1; + wire l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1; + wire l2_tbnk1_rwvic_cmo_setway_ls_l6_q; + wire [2:0] l2_tbnk1_rwvic_cpu_fb_id_l1; + wire [3:0] l2_tbnk1_rwvic_cpu_id_dcd_l1; + wire l2_tbnk1_rwvic_ddi_l6_q; + wire l2_tbnk1_rwvic_feq_cmp_l3_q; + wire l2_tbnk1_rwvic_frc_l2hit_fwd_l1; + wire l2_tbnk1_rwvic_l2hit_e_l1; + wire l2_tbnk1_rwvic_l2hit_e_l3_q; + wire l2_tbnk1_rwvic_l2hit_e_l7_q; + wire l2_tbnk1_rwvic_l2v_dirty_l7_q; + wire [3:0] l2_tbnk1_rwvic_l2v_page_attr_l7_q; + wire l2_tbnk1_rwvic_l2v_vld_l6_q; + wire l2_tbnk1_rwvic_mesi_sh_l1; + wire l2_tbnk1_rwvic_non_snp_fail_hazchk_l3; + wire [2:0] l2_tbnk1_rwvic_owner_l1; + wire [2:0] l2_tbnk1_rwvic_owner_l7_q; + wire l2_tbnk1_rwvic_rd_type_l6_q; + wire l2_tbnk1_rwvic_snp_clr_dirty_l1; + wire l2_tbnk1_rwvic_snp_inv_l1; + wire l2_tbnk1_rwvic_snp_l1; + wire l2_tbnk1_rwvic_snp_l3_q; + wire l2_tbnk1_rwvic_snp_l6_q; + wire l2_tbnk1_rwvic_tag_wr_l0; + wire [3:0] l2_tbnk1_rwvic_type_l1; + wire l2_tbnk1_rwvic_wa_l1; + wire l2_tbnk1_rwvic_wa_l6_q; + wire [13:0] l2_tbnk1_sel_l1; + wire [2:0] l2_tbnk1_size_l1; + wire [2:0] l2_tbnk1_size_l4_q; + wire l2_tbnk1_snp_byp_peq_haz_pending_q; + wire l2_tbnk1_snp_dvm_cmpl_l1; + wire l2_tbnk1_snp_hit_e_l4_q; + wire l2_tbnk1_snp_hit_feq_evict_l4_dly; + wire l2_tbnk1_snp_hit_s_l4_q; + wire [4:0] l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q; + wire [7:0] l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q; + wire [7:0] l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q; + wire [44:7] l2_tbnk1_snp_tag_wr_l2_hit_addr_l1; + wire [1:0] l2_tbnk1_snp_tag_wr_l2_hit_state_l1; + wire l2_tbnk1_snp_tag_wr_l2_hit_way_l1; + wire l2_tbnk1_special_evict_hazard_l3; + wire l2_tbnk1_special_hazard_l3_q; + wire l2_tbnk1_sync_l1; + wire l2_tbnk1_tag_ecc_dbl_rmw_wr_l1; + wire l2_tbnk1_tag_ecc_err_cpu0_l4; + wire l2_tbnk1_tag_ecc_err_cpu1_l4; + wire l2_tbnk1_tag_ecc_err_cpu2_l4; + wire l2_tbnk1_tag_ecc_err_cpu3_l4; + wire l2_tbnk1_tag_ecc_err_l4; + wire [6:0] l2_tbnk1_type_l1; + wire [1:0] l2_tbnk1_ulen_l1; + wire [1:0] l2_tbnk1_ulen_l4_q; + wire l2_tbnk1_vld_init_l6_q; + wire l2_tbnk1_vld_l6_q; + wire l2_tbnk1_way_l1; + wire l2_tbnk1_way_l4_q; + wire l2_tbnk1_way_nxt_l3a; + wire [143:0] l2_tbnk1_wr_data_l3; + wire [127:0] l2_tbnk1_wr_data_l3a_q; + wire l2_tbnk1_wr_data_l4_en; + wire l2_tbnk1_wr_err_l1; + wire l2_tbnk1_wr_fail_feq_full_l3; + wire l2_tbnk1_wr_fail_hazchk_feq_l3; + wire [11:0] l2_tbnk1_wr_non_crit_id_l1; + wire [11:0] l2_tbnk1_wr_non_crit_id_l4_q; + wire [15:0] l2_tbnk1_wr_strb_mask_l3a_q; + wire l2_tbnk_hwrst_done_x2; + wire [13:0] l2_tbnk_hwrst_idx_x1_q; + wire [8:0] tm_cntpct_q; + wire tm_cpu0_event_sev; + wire [63:0] tm_cpu0_spr_rd_data; + wire tm_cpu1_event_sev; + wire [63:0] tm_cpu1_spr_rd_data; + wire tm_cpu2_event_sev; + wire [63:0] tm_cpu2_spr_rd_data; + wire tm_cpu3_event_sev; + wire [63:0] tm_cpu3_spr_rd_data; + wire [63:0] tm_tval_cpu0_spr_rd_data; + wire [63:0] tm_tval_cpu1_spr_rd_data; + wire [63:0] tm_tval_cpu2_spr_rd_data; + wire [63:0] tm_tval_cpu3_spr_rd_data; + + maia_timer utm( // outputs + .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), + .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), + .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), + .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tm_cpu0_event_sev (tm_cpu0_event_sev), + .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), + .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tm_cpu1_event_sev (tm_cpu1_event_sev), + .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), + .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tm_cpu2_event_sev (tm_cpu2_event_sev), + .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), + .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tm_cpu3_event_sev (tm_cpu3_event_sev), + .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), + .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), + .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), + .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), + .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]), + + // inputs + .CNTCLKEN (CNTCLKEN), + .CNTVALUEB (CNTVALUEB[63:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .ck_areset_l2 (ck_areset_l2), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .eventi_sev (eventi_sev), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable) + ); // utm + + maia_l2_logic_feq28_s ul2_logic( // outputs + .ARREADYS (ARREADYS), + .AWREADYS (AWREADYS), + .BIDS (BIDS[4:0]), + .BRESPS (BRESPS[1:0]), + .BVALIDS (BVALIDS), + .L2FLUSHDONE (L2FLUSHDONE), + .L2QACCEPTn (L2QACCEPTn), + .L2QACTIVE (L2QACTIVE), + .L2QDENY (L2QDENY), + .RDATAS (RDATAS[127:0]), + .REQMEMATTR (REQMEMATTR[7:0]), + .RIDS (RIDS[4:0]), + .RLASTS (RLASTS), + .RRESPS (RRESPS[1:0]), + .RVALIDS (RVALIDS), + .RXDATLCRDV (RXDATLCRDV), + .RXLINKACTIVEACK (RXLINKACTIVEACK), + .RXRSPLCRDV (RXRSPLCRDV), + .RXSNPLCRDV (RXSNPLCRDV), + .TXDATFLIT (TXDATFLIT[193:0]), + .TXDATFLITPEND (TXDATFLITPEND), + .TXDATFLITV (TXDATFLITV), + .TXLINKACTIVEREQ (TXLINKACTIVEREQ), + .TXREQFLIT (TXREQFLIT[99:0]), + .TXREQFLITPEND (TXREQFLITPEND), + .TXREQFLITV (TXREQFLITV), + .TXRSPFLIT (TXRSPFLIT[44:0]), + .TXRSPFLITPEND (TXRSPFLITPEND), + .TXRSPFLITV (TXRSPFLITV), + .TXSACTIVE (TXSACTIVE), + .WREADYS (WREADYS), + .ck_areset_l2 (ck_areset_l2), + .ck_l2_logic_clk_en (ck_l2_logic_clk_en), + .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), + .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu0_barrier_done (l2_cpu0_barrier_done), + .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddbl_ecc_err_r3), + .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idbl_ecc_err_r3), + .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu0_rd_arb (l2_cpu0_rd_arb), + .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu0_rexfail (l2_cpu0_rexfail), + .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu0_rvalid (l2_cpu0_rvalid), + .l2_cpu0_snp_active (l2_cpu0_snp_active), + .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu0_spec_valid (l2_cpu0_spec_valid), + .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu0_wr_arb (l2_cpu0_wr_arb), + .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu0_wr_decerr_q (l2_cpu0_wr_decerr_q), + .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu0_wr_slverr_q (l2_cpu0_wr_slverr_q), + .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu1_barrier_done (l2_cpu1_barrier_done), + .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddbl_ecc_err_r3), + .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idbl_ecc_err_r3), + .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu1_rd_arb (l2_cpu1_rd_arb), + .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu1_rexfail (l2_cpu1_rexfail), + .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu1_rvalid (l2_cpu1_rvalid), + .l2_cpu1_snp_active (l2_cpu1_snp_active), + .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu1_spec_valid (l2_cpu1_spec_valid), + .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu1_wr_arb (l2_cpu1_wr_arb), + .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu1_wr_decerr_q (l2_cpu1_wr_decerr_q), + .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu1_wr_slverr_q (l2_cpu1_wr_slverr_q), + .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu2_barrier_done (l2_cpu2_barrier_done), + .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddbl_ecc_err_r3), + .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idbl_ecc_err_r3), + .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu2_rd_arb (l2_cpu2_rd_arb), + .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu2_rexfail (l2_cpu2_rexfail), + .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu2_rvalid (l2_cpu2_rvalid), + .l2_cpu2_snp_active (l2_cpu2_snp_active), + .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu2_spec_valid (l2_cpu2_spec_valid), + .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu2_wr_arb (l2_cpu2_wr_arb), + .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu2_wr_decerr_q (l2_cpu2_wr_decerr_q), + .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu2_wr_slverr_q (l2_cpu2_wr_slverr_q), + .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu3_barrier_done (l2_cpu3_barrier_done), + .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddbl_ecc_err_r3), + .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idbl_ecc_err_r3), + .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu3_rd_arb (l2_cpu3_rd_arb), + .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu3_rexfail (l2_cpu3_rexfail), + .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu3_rvalid (l2_cpu3_rvalid), + .l2_cpu3_snp_active (l2_cpu3_snp_active), + .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu3_spec_valid (l2_cpu3_spec_valid), + .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu3_wr_arb (l2_cpu3_wr_arb), + .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu3_wr_decerr_q (l2_cpu3_wr_decerr_q), + .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu3_wr_slverr_q (l2_cpu3_wr_slverr_q), + .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_idle (l2_idle), + .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), + .l2_mbist2_tbnk0_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), + .l2_mbist2_tbnk0_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), + .l2_mbist2_tbnk0_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), + .l2_mbist2_tbnk0_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), + .l2_mbist2_tbnk1_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), + .l2_mbist2_tbnk1_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), + .l2_mbist2_tbnk1_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), + .l2_mbist2_tbnk1_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_p_addr (l2_p_addr[13:0]), + .l2_p_cpu (l2_p_cpu[1:0]), + .l2_p_nsecure (l2_p_nsecure), + .l2_p_sel (l2_p_sel[2:0]), + .l2_p_wdata (l2_p_wdata[31:0]), + .l2_p_write (l2_p_write), + .l2_reset3 (l2_reset3), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_sky_link_stopped (l2_sky_link_stopped), + .l2_tbnk0_addr_l1 (l2_tbnk0_addr_l1[44:0]), + .l2_tbnk0_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), + .l2_tbnk0_asq_full_flsh (l2_tbnk0_asq_full_flsh), + .l2_tbnk0_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), + .l2_tbnk0_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), + .l2_tbnk0_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), + .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), + .l2_tbnk0_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), + .l2_tbnk0_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), + .l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), + .l2_tbnk0_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), + .l2_tbnk0_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), + .l2_tbnk0_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), + .l2_tbnk0_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), + .l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), + .l2_tbnk0_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), + .l2_tbnk0_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), + .l2_tbnk0_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), + .l2_tbnk0_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), + .l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), + .l2_tbnk0_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), + .l2_tbnk0_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), + .l2_tbnk0_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), + .l2_tbnk0_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), + .l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), + .l2_tbnk0_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), + .l2_tbnk0_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_dirty_l1 (l2_tbnk0_dirty_l1), + .l2_tbnk0_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), + .l2_tbnk0_excl_l1 (l2_tbnk0_excl_l1), + .l2_tbnk0_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), + .l2_tbnk0_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), + .l2_tbnk0_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), + .l2_tbnk0_feq_kill_l3 (l2_tbnk0_feq_kill_l3), + .l2_tbnk0_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), + .l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk0_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), + .l2_tbnk0_id_l1 (l2_tbnk0_id_l1[9:0]), + .l2_tbnk0_init_req_l1 (l2_tbnk0_init_req_l1), + .l2_tbnk0_kill_l2 (l2_tbnk0_kill_l2), + .l2_tbnk0_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), + .l2_tbnk0_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), + .l2_tbnk0_last_qw_l1 (l2_tbnk0_last_qw_l1), + .l2_tbnk0_lock_l1 (l2_tbnk0_lock_l1[2:0]), + .l2_tbnk0_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), + .l2_tbnk0_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), + .l2_tbnk0_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), + .l2_tbnk0_prfm_l1 (l2_tbnk0_prfm_l1), + .l2_tbnk0_prot_l1 (l2_tbnk0_prot_l1[3:0]), + .l2_tbnk0_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), + .l2_tbnk0_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), + .l2_tbnk0_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), + .l2_tbnk0_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), + .l2_tbnk0_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), + .l2_tbnk0_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), + .l2_tbnk0_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), + .l2_tbnk0_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), + .l2_tbnk0_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), + .l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk0_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk0_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk0_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), + .l2_tbnk0_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk0_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), + .l2_tbnk0_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), + .l2_tbnk0_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), + .l2_tbnk0_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), + .l2_tbnk0_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), + .l2_tbnk0_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), + .l2_tbnk0_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), + .l2_tbnk0_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), + .l2_tbnk0_sel_l1 (l2_tbnk0_sel_l1[13:0]), + .l2_tbnk0_size_l1 (l2_tbnk0_size_l1[2:0]), + .l2_tbnk0_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), + .l2_tbnk0_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), + .l2_tbnk0_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), + .l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk0_sync_l1 (l2_tbnk0_sync_l1), + .l2_tbnk0_type_l1 (l2_tbnk0_type_l1[6:0]), + .l2_tbnk0_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), + .l2_tbnk0_way_l1 (l2_tbnk0_way_l1), + .l2_tbnk0_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), + .l2_tbnk0_wr_err_l1 (l2_tbnk0_wr_err_l1), + .l2_tbnk0_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), + .l2_tbnk0_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), + .l2_tbnk0_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), + .l2_tbnk0_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]), + .l2_tbnk1_addr_l1 (l2_tbnk1_addr_l1[44:0]), + .l2_tbnk1_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), + .l2_tbnk1_asq_full_flsh (l2_tbnk1_asq_full_flsh), + .l2_tbnk1_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), + .l2_tbnk1_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), + .l2_tbnk1_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), + .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), + .l2_tbnk1_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), + .l2_tbnk1_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), + .l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), + .l2_tbnk1_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), + .l2_tbnk1_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), + .l2_tbnk1_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), + .l2_tbnk1_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), + .l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), + .l2_tbnk1_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), + .l2_tbnk1_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), + .l2_tbnk1_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), + .l2_tbnk1_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), + .l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), + .l2_tbnk1_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), + .l2_tbnk1_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), + .l2_tbnk1_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), + .l2_tbnk1_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), + .l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), + .l2_tbnk1_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), + .l2_tbnk1_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_dirty_l1 (l2_tbnk1_dirty_l1), + .l2_tbnk1_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), + .l2_tbnk1_excl_l1 (l2_tbnk1_excl_l1), + .l2_tbnk1_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), + .l2_tbnk1_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), + .l2_tbnk1_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), + .l2_tbnk1_feq_kill_l3 (l2_tbnk1_feq_kill_l3), + .l2_tbnk1_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), + .l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk1_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), + .l2_tbnk1_id_l1 (l2_tbnk1_id_l1[9:0]), + .l2_tbnk1_init_req_l1 (l2_tbnk1_init_req_l1), + .l2_tbnk1_kill_l2 (l2_tbnk1_kill_l2), + .l2_tbnk1_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), + .l2_tbnk1_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), + .l2_tbnk1_last_qw_l1 (l2_tbnk1_last_qw_l1), + .l2_tbnk1_lock_l1 (l2_tbnk1_lock_l1[2:0]), + .l2_tbnk1_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), + .l2_tbnk1_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), + .l2_tbnk1_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), + .l2_tbnk1_prfm_l1 (l2_tbnk1_prfm_l1), + .l2_tbnk1_prot_l1 (l2_tbnk1_prot_l1[3:0]), + .l2_tbnk1_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), + .l2_tbnk1_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), + .l2_tbnk1_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), + .l2_tbnk1_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), + .l2_tbnk1_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), + .l2_tbnk1_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), + .l2_tbnk1_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), + .l2_tbnk1_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), + .l2_tbnk1_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), + .l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk1_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk1_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk1_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), + .l2_tbnk1_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk1_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), + .l2_tbnk1_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), + .l2_tbnk1_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), + .l2_tbnk1_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), + .l2_tbnk1_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), + .l2_tbnk1_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), + .l2_tbnk1_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), + .l2_tbnk1_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), + .l2_tbnk1_sel_l1 (l2_tbnk1_sel_l1[13:0]), + .l2_tbnk1_size_l1 (l2_tbnk1_size_l1[2:0]), + .l2_tbnk1_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), + .l2_tbnk1_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), + .l2_tbnk1_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), + .l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk1_sync_l1 (l2_tbnk1_sync_l1), + .l2_tbnk1_type_l1 (l2_tbnk1_type_l1[6:0]), + .l2_tbnk1_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), + .l2_tbnk1_way_l1 (l2_tbnk1_way_l1), + .l2_tbnk1_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), + .l2_tbnk1_wr_err_l1 (l2_tbnk1_wr_err_l1), + .l2_tbnk1_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), + .l2_tbnk1_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), + .l2_tbnk1_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), + .l2_tbnk1_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .nEXTERRIRQ (nEXTERRIRQ), + .nINTERRIRQ (nINTERRIRQ), + + // inputs + .ACLKENS (ACLKENS), + .ARADDRS (ARADDRS[43:0]), + .ARCACHES (ARCACHES[3:0]), + .ARIDS (ARIDS[4:0]), + .ARLENS (ARLENS[7:0]), + .ARPROTS (ARPROTS[2:0]), + .ARUSERS (ARUSERS[1:0]), + .ARVALIDS (ARVALIDS), + .AWADDRS (AWADDRS[43:0]), + .AWCACHES (AWCACHES[3:0]), + .AWIDS (AWIDS[4:0]), + .AWLENS (AWLENS[7:0]), + .AWPROTS (AWPROTS[2:0]), + .AWUSERS (AWUSERS[1:0]), + .AWVALIDS (AWVALIDS), + .BREADYS (BREADYS), + .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), + .BROADCASTINNER (BROADCASTINNER), + .BROADCASTOUTER (BROADCASTOUTER), + .DBGL1RSTDISABLE (DBGL1RSTDISABLE), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .L2FLUSHREQ (L2FLUSHREQ), + .L2QREQn (L2QREQn), + .L2RSTDISABLE (L2RSTDISABLE), + .MBISTREQ (MBISTREQ), + .NODEID (NODEID[6:0]), + .PERIPHBASE (PERIPHBASE[43:18]), + .RREADYS (RREADYS), + .RXDATFLIT (RXDATFLIT[193:0]), + .RXDATFLITPEND (RXDATFLITPEND), + .RXDATFLITV (RXDATFLITV), + .RXLINKACTIVEREQ (RXLINKACTIVEREQ), + .RXRSPFLIT (RXRSPFLIT[44:0]), + .RXRSPFLITPEND (RXRSPFLITPEND), + .RXRSPFLITV (RXRSPFLITV), + .RXSACTIVE (RXSACTIVE), + .RXSNPFLIT (RXSNPFLIT[64:0]), + .RXSNPFLITPEND (RXSNPFLITPEND), + .RXSNPFLITV (RXSNPFLITV), + .SAMADDRMAP0 (SAMADDRMAP0[1:0]), + .SAMADDRMAP1 (SAMADDRMAP1[1:0]), + .SAMADDRMAP10 (SAMADDRMAP10[1:0]), + .SAMADDRMAP11 (SAMADDRMAP11[1:0]), + .SAMADDRMAP12 (SAMADDRMAP12[1:0]), + .SAMADDRMAP13 (SAMADDRMAP13[1:0]), + .SAMADDRMAP14 (SAMADDRMAP14[1:0]), + .SAMADDRMAP15 (SAMADDRMAP15[1:0]), + .SAMADDRMAP16 (SAMADDRMAP16[1:0]), + .SAMADDRMAP17 (SAMADDRMAP17[1:0]), + .SAMADDRMAP18 (SAMADDRMAP18[1:0]), + .SAMADDRMAP19 (SAMADDRMAP19[1:0]), + .SAMADDRMAP2 (SAMADDRMAP2[1:0]), + .SAMADDRMAP3 (SAMADDRMAP3[1:0]), + .SAMADDRMAP4 (SAMADDRMAP4[1:0]), + .SAMADDRMAP5 (SAMADDRMAP5[1:0]), + .SAMADDRMAP6 (SAMADDRMAP6[1:0]), + .SAMADDRMAP7 (SAMADDRMAP7[1:0]), + .SAMADDRMAP8 (SAMADDRMAP8[1:0]), + .SAMADDRMAP9 (SAMADDRMAP9[1:0]), + .SAMHNF0NODEID (SAMHNF0NODEID[6:0]), + .SAMHNF1NODEID (SAMHNF1NODEID[6:0]), + .SAMHNF2NODEID (SAMHNF2NODEID[6:0]), + .SAMHNF3NODEID (SAMHNF3NODEID[6:0]), + .SAMHNF4NODEID (SAMHNF4NODEID[6:0]), + .SAMHNF5NODEID (SAMHNF5NODEID[6:0]), + .SAMHNF6NODEID (SAMHNF6NODEID[6:0]), + .SAMHNF7NODEID (SAMHNF7NODEID[6:0]), + .SAMHNFMODE (SAMHNFMODE[2:0]), + .SAMHNI0NODEID (SAMHNI0NODEID[6:0]), + .SAMHNI1NODEID (SAMHNI1NODEID[6:0]), + .SAMMNBASE (SAMMNBASE[43:24]), + .SAMMNNODEID (SAMMNNODEID[6:0]), + .SCLKEN (SCLKEN), + .SYSBARDISABLE (SYSBARDISABLE), + .TXDATLCRDV (TXDATLCRDV), + .TXLINKACTIVEACK (TXLINKACTIVEACK), + .TXREQLCRDV (TXREQLCRDV), + .TXRSPLCRDV (TXRSPLCRDV), + .WDATAS (WDATAS[127:0]), + .WLASTS (WLASTS), + .WSTRBS (WSTRBS[15:0]), + .WVALIDS (WVALIDS), + .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), + .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), + .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), + .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), + .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), + .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), + .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), + .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), + .ck_gclkfr (ck_gclkfr), + .ck_gclkl2 (ck_gclkl2), + .ck_l2_ace_inactive (ck_l2_ace_inactive), + .ck_l2_acp_inactive (ck_l2_acp_inactive), + .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), + .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), + .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), + .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), + .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), + .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), + .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), + .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), + .ic_p_rdata (ic_p_rdata[31:0]), + .ic_p_rdata_valid (ic_p_rdata_valid), + .ic_p_ready (ic_p_ready), + .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .l2_mbist2_tbnk0_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), + .l2_mbist2_tbnk0_all_b1 (l2_mbist2_tbnk0_all_b1), + .l2_mbist2_tbnk0_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), + .l2_mbist2_tbnk0_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), + .l2_mbist2_tbnk0_en_b1 (l2_mbist2_tbnk0_en_b1), + .l2_mbist2_tbnk0_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), + .l2_mbist2_tbnk0_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), + .l2_mbist2_tbnk0_sel_b1 (l2_mbist2_tbnk0_sel_b1), + .l2_mbist2_tbnk0_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), + .l2_mbist2_tbnk0_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), + .l2_mbist2_tbnk0_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), + .l2_mbist2_tbnk0_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), + .l2_mbist2_tbnk0_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), + .l2_mbist2_tbnk1_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), + .l2_mbist2_tbnk1_all_b1 (l2_mbist2_tbnk1_all_b1), + .l2_mbist2_tbnk1_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), + .l2_mbist2_tbnk1_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), + .l2_mbist2_tbnk1_en_b1 (l2_mbist2_tbnk1_en_b1), + .l2_mbist2_tbnk1_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), + .l2_mbist2_tbnk1_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), + .l2_mbist2_tbnk1_sel_b1 (l2_mbist2_tbnk1_sel_b1), + .l2_mbist2_tbnk1_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), + .l2_mbist2_tbnk1_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), + .l2_mbist2_tbnk1_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), + .l2_mbist2_tbnk1_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), + .l2_mbist2_tbnk1_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), + .l2_tbnk0_addr44_l3_q (l2_tbnk0_addr44_l3_q), + .l2_tbnk0_addr_l6 (l2_tbnk0_addr_l6[5:2]), + .l2_tbnk0_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), + .l2_tbnk0_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), + .l2_tbnk0_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), + .l2_tbnk0_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), + .l2_tbnk0_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), + .l2_tbnk0_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), + .l2_tbnk0_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), + .l2_tbnk0_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), + .l2_tbnk0_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), + .l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), + .l2_tbnk0_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), + .l2_tbnk0_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), + .l2_tbnk0_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), + .l2_tbnk0_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), + .l2_tbnk0_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), + .l2_tbnk0_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), + .l2_tbnk0_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), + .l2_tbnk0_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), + .l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), + .l2_tbnk0_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), + .l2_tbnk0_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), + .l2_tbnk0_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), + .l2_tbnk0_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), + .l2_tbnk0_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), + .l2_tbnk0_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), + .l2_tbnk0_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), + .l2_tbnk0_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), + .l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), + .l2_tbnk0_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), + .l2_tbnk0_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), + .l2_tbnk0_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), + .l2_tbnk0_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), + .l2_tbnk0_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), + .l2_tbnk0_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), + .l2_tbnk0_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), + .l2_tbnk0_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), + .l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), + .l2_tbnk0_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), + .l2_tbnk0_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk0_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk0_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk0_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), + .l2_tbnk0_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), + .l2_tbnk0_data_l6 (l2_tbnk0_data_l6[127:0]), + .l2_tbnk0_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), + .l2_tbnk0_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk0_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk0_dirty_l3_q (l2_tbnk0_dirty_l3_q), + .l2_tbnk0_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), + .l2_tbnk0_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), + .l2_tbnk0_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), + .l2_tbnk0_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), + .l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk0_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), + .l2_tbnk0_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), + .l2_tbnk0_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), + .l2_tbnk0_excl_l4_q (l2_tbnk0_excl_l4_q), + .l2_tbnk0_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), + .l2_tbnk0_feq_clr_l4 (l2_tbnk0_feq_clr_l4), + .l2_tbnk0_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), + .l2_tbnk0_hit_l4 (l2_tbnk0_hit_l4), + .l2_tbnk0_hit_l7_q (l2_tbnk0_hit_l7_q), + .l2_tbnk0_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), + .l2_tbnk0_id_l6_q (l2_tbnk0_id_l6_q[9:0]), + .l2_tbnk0_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), + .l2_tbnk0_idle (l2_tbnk0_idle), + .l2_tbnk0_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), + .l2_tbnk0_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), + .l2_tbnk0_l2v_s_q (l2_tbnk0_l2v_s_q), + .l2_tbnk0_l2v_vld_q (l2_tbnk0_l2v_vld_q), + .l2_tbnk0_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), + .l2_tbnk0_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), + .l2_tbnk0_lock_l4 (l2_tbnk0_lock_l4[2:0]), + .l2_tbnk0_merrsr_data (l2_tbnk0_merrsr_data[32:0]), + .l2_tbnk0_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), + .l2_tbnk0_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), + .l2_tbnk0_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), + .l2_tbnk0_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), + .l2_tbnk0_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), + .l2_tbnk0_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), + .l2_tbnk0_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), + .l2_tbnk0_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), + .l2_tbnk0_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), + .l2_tbnk0_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), + .l2_tbnk0_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk0_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk0_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), + .l2_tbnk0_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), + .l2_tbnk0_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), + .l2_tbnk0_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk0_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), + .l2_tbnk0_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), + .l2_tbnk0_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), + .l2_tbnk0_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), + .l2_tbnk0_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk0_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), + .l2_tbnk0_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk0_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), + .l2_tbnk0_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), + .l2_tbnk0_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), + .l2_tbnk0_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), + .l2_tbnk0_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), + .l2_tbnk0_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), + .l2_tbnk0_size_l4_q (l2_tbnk0_size_l4_q[2:0]), + .l2_tbnk0_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), + .l2_tbnk0_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), + .l2_tbnk0_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk0_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk0_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk0_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), + .l2_tbnk0_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), + .l2_tbnk0_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk0_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), + .l2_tbnk0_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), + .l2_tbnk0_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), + .l2_tbnk0_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), + .l2_tbnk0_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), + .l2_tbnk0_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), + .l2_tbnk0_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), + .l2_tbnk0_vld_l6_q (l2_tbnk0_vld_l6_q), + .l2_tbnk0_way_l4_q (l2_tbnk0_way_l4_q), + .l2_tbnk0_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), + .l2_tbnk0_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), + .l2_tbnk0_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), + .l2_tbnk0_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), + .l2_tbnk1_addr44_l3_q (l2_tbnk1_addr44_l3_q), + .l2_tbnk1_addr_l6 (l2_tbnk1_addr_l6[5:2]), + .l2_tbnk1_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), + .l2_tbnk1_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), + .l2_tbnk1_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), + .l2_tbnk1_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), + .l2_tbnk1_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), + .l2_tbnk1_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), + .l2_tbnk1_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), + .l2_tbnk1_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), + .l2_tbnk1_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), + .l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), + .l2_tbnk1_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), + .l2_tbnk1_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), + .l2_tbnk1_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), + .l2_tbnk1_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), + .l2_tbnk1_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), + .l2_tbnk1_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), + .l2_tbnk1_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), + .l2_tbnk1_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), + .l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), + .l2_tbnk1_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), + .l2_tbnk1_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), + .l2_tbnk1_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), + .l2_tbnk1_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), + .l2_tbnk1_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), + .l2_tbnk1_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), + .l2_tbnk1_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), + .l2_tbnk1_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), + .l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), + .l2_tbnk1_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), + .l2_tbnk1_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), + .l2_tbnk1_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), + .l2_tbnk1_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), + .l2_tbnk1_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), + .l2_tbnk1_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), + .l2_tbnk1_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), + .l2_tbnk1_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), + .l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), + .l2_tbnk1_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), + .l2_tbnk1_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk1_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk1_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk1_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), + .l2_tbnk1_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), + .l2_tbnk1_data_l6 (l2_tbnk1_data_l6[127:0]), + .l2_tbnk1_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), + .l2_tbnk1_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk1_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk1_dirty_l3_q (l2_tbnk1_dirty_l3_q), + .l2_tbnk1_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), + .l2_tbnk1_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), + .l2_tbnk1_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), + .l2_tbnk1_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), + .l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk1_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), + .l2_tbnk1_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), + .l2_tbnk1_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), + .l2_tbnk1_excl_l4_q (l2_tbnk1_excl_l4_q), + .l2_tbnk1_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), + .l2_tbnk1_feq_clr_l4 (l2_tbnk1_feq_clr_l4), + .l2_tbnk1_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), + .l2_tbnk1_hit_l4 (l2_tbnk1_hit_l4), + .l2_tbnk1_hit_l7_q (l2_tbnk1_hit_l7_q), + .l2_tbnk1_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), + .l2_tbnk1_id_l6_q (l2_tbnk1_id_l6_q[9:0]), + .l2_tbnk1_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), + .l2_tbnk1_idle (l2_tbnk1_idle), + .l2_tbnk1_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), + .l2_tbnk1_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), + .l2_tbnk1_l2v_s_q (l2_tbnk1_l2v_s_q), + .l2_tbnk1_l2v_vld_q (l2_tbnk1_l2v_vld_q), + .l2_tbnk1_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), + .l2_tbnk1_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), + .l2_tbnk1_lock_l4 (l2_tbnk1_lock_l4[2:0]), + .l2_tbnk1_merrsr_data (l2_tbnk1_merrsr_data[32:0]), + .l2_tbnk1_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), + .l2_tbnk1_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), + .l2_tbnk1_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), + .l2_tbnk1_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), + .l2_tbnk1_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), + .l2_tbnk1_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), + .l2_tbnk1_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), + .l2_tbnk1_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), + .l2_tbnk1_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), + .l2_tbnk1_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), + .l2_tbnk1_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk1_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk1_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), + .l2_tbnk1_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), + .l2_tbnk1_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), + .l2_tbnk1_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk1_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), + .l2_tbnk1_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), + .l2_tbnk1_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), + .l2_tbnk1_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), + .l2_tbnk1_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk1_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), + .l2_tbnk1_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk1_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), + .l2_tbnk1_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), + .l2_tbnk1_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), + .l2_tbnk1_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), + .l2_tbnk1_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), + .l2_tbnk1_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), + .l2_tbnk1_size_l4_q (l2_tbnk1_size_l4_q[2:0]), + .l2_tbnk1_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), + .l2_tbnk1_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), + .l2_tbnk1_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk1_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk1_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk1_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), + .l2_tbnk1_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), + .l2_tbnk1_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk1_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), + .l2_tbnk1_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), + .l2_tbnk1_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), + .l2_tbnk1_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), + .l2_tbnk1_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), + .l2_tbnk1_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), + .l2_tbnk1_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), + .l2_tbnk1_vld_l6_q (l2_tbnk1_vld_l6_q), + .l2_tbnk1_way_l4_q (l2_tbnk1_way_l4_q), + .l2_tbnk1_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), + .l2_tbnk1_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), + .l2_tbnk1_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), + .l2_tbnk1_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), + .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), + .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), + .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), + .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), + .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), + .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), + .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]) + ); // ul2_logic + + maia_l2_tbnk ul2_tbnk0( // outputs + .l2_mbist2_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), + .l2_mbist2_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), + .l2_mbist2_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), + .l2_mbist2_en_b1 (l2_mbist2_tbnk0_en_b1), + .l2_mbist2_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), + .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk0_all_b1), + .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), + .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk0_sel_b1), + .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), + .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), + .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), + .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), + .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), + .l2_tbnk_addr44_l3_q (l2_tbnk0_addr44_l3_q), + .l2_tbnk_addr_l6 (l2_tbnk0_addr_l6[5:2]), + .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), + .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), + .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), + .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), + .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), + .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), + .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), + .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), + .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), + .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), + .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), + .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), + .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), + .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), + .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), + .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), + .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), + .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), + .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), + .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), + .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), + .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), + .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), + .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), + .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), + .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), + .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), + .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), + .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), + .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), + .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), + .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), + .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), + .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), + .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), + .l2_tbnk_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), + .l2_tbnk_data_l6 (l2_tbnk0_data_l6[127:0]), + .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), + .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk_dirty_l3_q (l2_tbnk0_dirty_l3_q), + .l2_tbnk_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), + .l2_tbnk_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), + .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), + .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), + .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), + .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), + .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), + .l2_tbnk_excl_l4_q (l2_tbnk0_excl_l4_q), + .l2_tbnk_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), + .l2_tbnk_feq_clr_l4 (l2_tbnk0_feq_clr_l4), + .l2_tbnk_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), + .l2_tbnk_hit_l4 (l2_tbnk0_hit_l4), + .l2_tbnk_hit_l7_q (l2_tbnk0_hit_l7_q), + .l2_tbnk_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), + .l2_tbnk_id_l6_q (l2_tbnk0_id_l6_q[9:0]), + .l2_tbnk_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), + .l2_tbnk_idle (l2_tbnk0_idle), + .l2_tbnk_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), + .l2_tbnk_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), + .l2_tbnk_l2v_s_q (l2_tbnk0_l2v_s_q), + .l2_tbnk_l2v_vld_q (l2_tbnk0_l2v_vld_q), + .l2_tbnk_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), + .l2_tbnk_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), + .l2_tbnk_lock_l4 (l2_tbnk0_lock_l4[2:0]), + .l2_tbnk_merrsr_data (l2_tbnk0_merrsr_data[32:0]), + .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), + .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), + .l2_tbnk_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), + .l2_tbnk_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), + .l2_tbnk_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), + .l2_tbnk_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), + .l2_tbnk_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), + .l2_tbnk_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), + .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), + .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), + .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), + .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), + .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), + .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), + .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), + .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), + .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), + .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), + .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), + .l2_tbnk_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), + .l2_tbnk_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), + .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), + .l2_tbnk_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), + .l2_tbnk_size_l4_q (l2_tbnk0_size_l4_q[2:0]), + .l2_tbnk_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), + .l2_tbnk_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), + .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), + .l2_tbnk_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), + .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), + .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), + .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), + .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), + .l2_tbnk_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), + .l2_tbnk_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), + .l2_tbnk_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), + .l2_tbnk_vld_l6_q (l2_tbnk0_vld_l6_q), + .l2_tbnk_way_l4_q (l2_tbnk0_way_l4_q), + .l2_tbnk_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), + .l2_tbnk_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), + .l2_tbnk_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), + .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), + + // inputs + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ), + .ck_areset_l2 (ck_areset_l2), + .ck_gclkl2 (ck_gclkb0), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), + .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), + .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), + .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), + .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), + .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), + .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), + .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_skyros_intf (1'b1), + .l2_tbnk_addr_l1 (l2_tbnk0_addr_l1[44:0]), + .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), + .l2_tbnk_asq_full_flsh (l2_tbnk0_asq_full_flsh), + .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), + .l2_tbnk_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), + .l2_tbnk_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), + .l2_tbnk_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), + .l2_tbnk_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), + .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), + .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), + .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), + .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), + .l2_tbnk_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), + .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), + .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), + .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), + .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), + .l2_tbnk_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), + .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), + .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), + .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), + .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), + .l2_tbnk_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), + .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), + .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), + .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), + .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_dirty_l1 (l2_tbnk0_dirty_l1), + .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), + .l2_tbnk_excl_l1 (l2_tbnk0_excl_l1), + .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), + .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), + .l2_tbnk_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), + .l2_tbnk_feq_kill_l3 (l2_tbnk0_feq_kill_l3), + .l2_tbnk_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), + .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .l2_tbnk_id_l1 (l2_tbnk0_id_l1[9:0]), + .l2_tbnk_init_req_l1 (l2_tbnk0_init_req_l1), + .l2_tbnk_kill_l2 (l2_tbnk0_kill_l2), + .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), + .l2_tbnk_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), + .l2_tbnk_last_qw_l1 (l2_tbnk0_last_qw_l1), + .l2_tbnk_lock_l1 (l2_tbnk0_lock_l1[2:0]), + .l2_tbnk_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), + .l2_tbnk_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), + .l2_tbnk_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), + .l2_tbnk_prfm_l1 (l2_tbnk0_prfm_l1), + .l2_tbnk_prot_l1 (l2_tbnk0_prot_l1[3:0]), + .l2_tbnk_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), + .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), + .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), + .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), + .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), + .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), + .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), + .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), + .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), + .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), + .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), + .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), + .l2_tbnk_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), + .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), + .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), + .l2_tbnk_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), + .l2_tbnk_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), + .l2_tbnk_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), + .l2_tbnk_sel_l1 (l2_tbnk0_sel_l1[13:0]), + .l2_tbnk_size_l1 (l2_tbnk0_size_l1[2:0]), + .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), + .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), + .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), + .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_sync_l1 (l2_tbnk0_sync_l1), + .l2_tbnk_type_l1 (l2_tbnk0_type_l1[6:0]), + .l2_tbnk_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), + .l2_tbnk_way_l1 (l2_tbnk0_way_l1), + .l2_tbnk_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), + .l2_tbnk_wr_err_l1 (l2_tbnk0_wr_err_l1), + .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), + .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), + .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), + .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]) + ); // ul2_tbnk0 + + maia_l2_tbnk ul2_tbnk1( // outputs + .l2_mbist2_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), + .l2_mbist2_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), + .l2_mbist2_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), + .l2_mbist2_en_b1 (l2_mbist2_tbnk1_en_b1), + .l2_mbist2_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), + .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk1_all_b1), + .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), + .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk1_sel_b1), + .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), + .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), + .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), + .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), + .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), + .l2_tbnk_addr44_l3_q (l2_tbnk1_addr44_l3_q), + .l2_tbnk_addr_l6 (l2_tbnk1_addr_l6[5:2]), + .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), + .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), + .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), + .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), + .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), + .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), + .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), + .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), + .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), + .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), + .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), + .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), + .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), + .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), + .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), + .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), + .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), + .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), + .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), + .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), + .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), + .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), + .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), + .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), + .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), + .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), + .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), + .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), + .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), + .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), + .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), + .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), + .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), + .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), + .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), + .l2_tbnk_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), + .l2_tbnk_data_l6 (l2_tbnk1_data_l6[127:0]), + .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), + .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk_dirty_l3_q (l2_tbnk1_dirty_l3_q), + .l2_tbnk_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), + .l2_tbnk_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), + .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), + .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), + .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), + .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), + .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), + .l2_tbnk_excl_l4_q (l2_tbnk1_excl_l4_q), + .l2_tbnk_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), + .l2_tbnk_feq_clr_l4 (l2_tbnk1_feq_clr_l4), + .l2_tbnk_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), + .l2_tbnk_hit_l4 (l2_tbnk1_hit_l4), + .l2_tbnk_hit_l7_q (l2_tbnk1_hit_l7_q), + .l2_tbnk_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), + .l2_tbnk_id_l6_q (l2_tbnk1_id_l6_q[9:0]), + .l2_tbnk_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), + .l2_tbnk_idle (l2_tbnk1_idle), + .l2_tbnk_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), + .l2_tbnk_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), + .l2_tbnk_l2v_s_q (l2_tbnk1_l2v_s_q), + .l2_tbnk_l2v_vld_q (l2_tbnk1_l2v_vld_q), + .l2_tbnk_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), + .l2_tbnk_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), + .l2_tbnk_lock_l4 (l2_tbnk1_lock_l4[2:0]), + .l2_tbnk_merrsr_data (l2_tbnk1_merrsr_data[32:0]), + .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), + .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), + .l2_tbnk_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), + .l2_tbnk_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), + .l2_tbnk_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), + .l2_tbnk_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), + .l2_tbnk_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), + .l2_tbnk_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), + .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), + .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), + .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), + .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), + .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), + .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), + .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), + .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), + .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), + .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), + .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), + .l2_tbnk_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), + .l2_tbnk_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), + .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), + .l2_tbnk_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), + .l2_tbnk_size_l4_q (l2_tbnk1_size_l4_q[2:0]), + .l2_tbnk_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), + .l2_tbnk_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), + .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), + .l2_tbnk_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), + .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), + .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), + .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), + .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), + .l2_tbnk_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), + .l2_tbnk_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), + .l2_tbnk_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), + .l2_tbnk_vld_l6_q (l2_tbnk1_vld_l6_q), + .l2_tbnk_way_l4_q (l2_tbnk1_way_l4_q), + .l2_tbnk_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), + .l2_tbnk_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), + .l2_tbnk_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), + .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), + + // inputs + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ), + .ck_areset_l2 (ck_areset_l2), + .ck_gclkl2 (ck_gclkb1), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), + .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), + .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), + .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), + .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), + .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), + .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), + .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_skyros_intf (1'b1), + .l2_tbnk_addr_l1 (l2_tbnk1_addr_l1[44:0]), + .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), + .l2_tbnk_asq_full_flsh (l2_tbnk1_asq_full_flsh), + .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), + .l2_tbnk_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), + .l2_tbnk_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), + .l2_tbnk_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), + .l2_tbnk_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), + .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), + .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), + .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), + .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), + .l2_tbnk_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), + .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), + .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), + .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), + .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), + .l2_tbnk_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), + .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), + .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), + .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), + .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), + .l2_tbnk_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), + .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), + .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), + .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), + .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_dirty_l1 (l2_tbnk1_dirty_l1), + .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), + .l2_tbnk_excl_l1 (l2_tbnk1_excl_l1), + .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), + .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), + .l2_tbnk_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), + .l2_tbnk_feq_kill_l3 (l2_tbnk1_feq_kill_l3), + .l2_tbnk_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), + .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .l2_tbnk_id_l1 (l2_tbnk1_id_l1[9:0]), + .l2_tbnk_init_req_l1 (l2_tbnk1_init_req_l1), + .l2_tbnk_kill_l2 (l2_tbnk1_kill_l2), + .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), + .l2_tbnk_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), + .l2_tbnk_last_qw_l1 (l2_tbnk1_last_qw_l1), + .l2_tbnk_lock_l1 (l2_tbnk1_lock_l1[2:0]), + .l2_tbnk_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), + .l2_tbnk_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), + .l2_tbnk_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), + .l2_tbnk_prfm_l1 (l2_tbnk1_prfm_l1), + .l2_tbnk_prot_l1 (l2_tbnk1_prot_l1[3:0]), + .l2_tbnk_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), + .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), + .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), + .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), + .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), + .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), + .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), + .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), + .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), + .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), + .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), + .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), + .l2_tbnk_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), + .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), + .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), + .l2_tbnk_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), + .l2_tbnk_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), + .l2_tbnk_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), + .l2_tbnk_sel_l1 (l2_tbnk1_sel_l1[13:0]), + .l2_tbnk_size_l1 (l2_tbnk1_size_l1[2:0]), + .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), + .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), + .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), + .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_sync_l1 (l2_tbnk1_sync_l1), + .l2_tbnk_type_l1 (l2_tbnk1_type_l1[6:0]), + .l2_tbnk_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), + .l2_tbnk_way_l1 (l2_tbnk1_way_l1), + .l2_tbnk_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), + .l2_tbnk_wr_err_l1 (l2_tbnk1_wr_err_l1), + .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), + .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), + .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), + .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]) + ); // ul2_tbnk1 + + maia_dt_pclk udt_pclk( // outputs + .CTICHINACK (CTICHINACK[3:0]), + .CTICHOUT (CTICHOUT[3:0]), + .CTIIRQ (CTIIRQ[`MAIA_CN:0]), + .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), + .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), + .PRDATADBG (PRDATADBG[31:0]), + .PREADYDBG (PREADYDBG), + .PSLVERRDBG (PSLVERRDBG), + .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), + .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), + .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), + .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), + .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), + .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), + .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), + .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), + .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + + // inputs + .CIHSBYPASS (CIHSBYPASS[3:0]), + .CISBYPASS (CISBYPASS), + .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), + .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), + .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), + .CTICHIN (CTICHIN[3:0]), + .CTICHOUTACK (CTICHOUTACK[3:0]), + .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), + .DBGEN (DBGEN[`MAIA_CN:0]), + .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .EDBGRQ (EDBGRQ[`MAIA_CN:0]), + .GICCDISABLE (GICCDISABLE), + .NIDEN (NIDEN[`MAIA_CN:0]), + .PADDRDBG (PADDRDBG[21:2]), + .PADDRDBG31 (PADDRDBG31), + .PCLKDBG (PCLKDBG), + .PCLKENDBG (PCLKENDBG), + .PENABLEDBG (PENABLEDBG), + .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), + .PSELDBG (PSELDBG), + .PWDATADBG (PWDATADBG[31:0]), + .PWRITEDBG (PWRITEDBG), + .SPIDEN (SPIDEN[`MAIA_CN:0]), + .SPNIDEN (SPNIDEN[`MAIA_CN:0]), + .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), + .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), + .ck_cpu0_poreset_status (ck_cpu0_poreset_status), + .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), + .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), + .ck_cpu1_poreset_status (ck_cpu1_poreset_status), + .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), + .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), + .ck_cpu2_poreset_status (ck_cpu2_poreset_status), + .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), + .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), + .ck_cpu3_poreset_status (ck_cpu3_poreset_status), + .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), + .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), + .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), + .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), + .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), + .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), + .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), + .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), + .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), + .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), + .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), + .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), + .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), + .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), + .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), + .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), + .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), + .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), + .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), + .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), + .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), + .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), + .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), + .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), + .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .nPRESETDBG (nPRESETDBG) + ); // udt_pclk + + maia_intctrl uic( // outputs + .ICCTDATA (ICCTDATA[15:0]), + .ICCTID (ICCTID[1:0]), + .ICCTLAST (ICCTLAST), + .ICCTVALID (ICCTVALID), + .ICDTREADY (ICDTREADY), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), + .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), + .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), + .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), + .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), + .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), + .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), + .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), + .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), + .ic_el_change_complete_o (ic_el_change_complete_o[`MAIA_CN:0]), + .ic_hcr_change_complete_o (ic_hcr_change_complete_o[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .ic_p_rdata (ic_p_rdata[31:0]), + .ic_p_rdata_valid (ic_p_rdata_valid), + .ic_p_ready (ic_p_ready), + .ic_p_valid (ic_p_valid[`MAIA_CN:0]), + .ic_sample_spr_o (ic_sample_spr_o[`MAIA_CN:0]), + .ic_scr_change_complete_o (ic_scr_change_complete_o[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]), + .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), + + // inputs + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .GICCDISABLE (GICCDISABLE), + .ICCTREADY (ICCTREADY), + .ICDTDATA (ICDTDATA[15:0]), + .ICDTDEST (ICDTDEST[1:0]), + .ICDTLAST (ICDTLAST), + .ICDTVALID (ICDTVALID), + .ck_areset_l2 (ck_areset_l2), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_aa64naa32_i (ds_cpu0_ic_aa64naa32_i), + .ds_cpu0_cpsr_mode_i (ds_cpu0_ic_cpsr_mode_i[4:0]), + .ds_cpu0_hcr_change_i (ds_cpu0_ic_hcr_change_i), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu0_sample_spr_i (ds_cpu0_ic_sample_spr_i), + .ds_cpu0_scr_change_i (ds_cpu0_ic_scr_change_i), + .ds_cpu1_aa64naa32_i (ds_cpu1_ic_aa64naa32_i), + .ds_cpu1_cpsr_mode_i (ds_cpu1_ic_cpsr_mode_i[4:0]), + .ds_cpu1_hcr_change_i (ds_cpu1_ic_hcr_change_i), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu1_sample_spr_i (ds_cpu1_ic_sample_spr_i), + .ds_cpu1_scr_change_i (ds_cpu1_ic_scr_change_i), + .ds_cpu2_aa64naa32_i (ds_cpu2_ic_aa64naa32_i), + .ds_cpu2_cpsr_mode_i (ds_cpu2_ic_cpsr_mode_i[4:0]), + .ds_cpu2_hcr_change_i (ds_cpu2_ic_hcr_change_i), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu2_sample_spr_i (ds_cpu2_ic_sample_spr_i), + .ds_cpu2_scr_change_i (ds_cpu2_ic_scr_change_i), + .ds_cpu3_aa64naa32_i (ds_cpu3_ic_aa64naa32_i), + .ds_cpu3_cpsr_mode_i (ds_cpu3_ic_cpsr_mode_i[4:0]), + .ds_cpu3_hcr_change_i (ds_cpu3_ic_hcr_change_i), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_cpu3_sample_spr_i (ds_cpu3_ic_sample_spr_i), + .ds_cpu3_scr_change_i (ds_cpu3_ic_scr_change_i), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_cpu0_wr_decerr_i (l2_cpu0_wr_decerr_q), + .l2_cpu0_wr_slverr_i (l2_cpu0_wr_slverr_q), + .l2_cpu1_wr_decerr_i (l2_cpu1_wr_decerr_q), + .l2_cpu1_wr_slverr_i (l2_cpu1_wr_slverr_q), + .l2_cpu2_wr_decerr_i (l2_cpu2_wr_decerr_q), + .l2_cpu2_wr_slverr_i (l2_cpu2_wr_slverr_q), + .l2_cpu3_wr_decerr_i (l2_cpu3_wr_decerr_q), + .l2_cpu3_wr_slverr_i (l2_cpu3_wr_slverr_q), + .l2_p_addr (l2_p_addr[13:0]), + .l2_p_cpu (l2_p_cpu[1:0]), + .l2_p_nsecure (l2_p_nsecure), + .l2_p_sel (l2_p_sel[2:0]), + .l2_p_wdata (l2_p_wdata[31:0]), + .l2_p_write (l2_p_write), + .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), + .nFIQ (nFIQ[`MAIA_CN:0]), + .nIRQ (nIRQ[`MAIA_CN:0]), + .nREI (nREI[`MAIA_CN:0]), + .nSEI (nSEI[`MAIA_CN:0]), + .nVFIQ (nVFIQ[`MAIA_CN:0]), + .nVIRQ (nVIRQ[`MAIA_CN:0]), + .nVSEI (nVSEI[`MAIA_CN:0]) + ); // uic + + maia_ck_l2 uck_l2( // outputs + .ck_gclkb0 (ck_gclkb0), + .ck_gclkb1 (ck_gclkb1), + .ck_gclkfr (ck_gclkfr), + .ck_gclkl2 (ck_gclkl2), + + // inputs + .DFTL2CLKDISABLE (DFTL2CLKDISABLE), + .DFTSE (DFTSE), + .ck_gclktl2 (ck_gclktl2), + .ck_l2_logic_clk_en (ck_l2_logic_clk_en), + .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), + .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), + .l2_reset3 (l2_reset3) + ); // uck_l2 + + maia_ck_top uck_top( // outputs + .ck_gclkt (ck_gclkt[`MAIA_CN:0]), + .ck_gclktl2 (ck_gclktl2), + + // inputs + .CLK (CLK), + .CLKEN (CLKEN), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ) + ); // uck_top + + maia_ck_logic uck_logic( // outputs + .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), + .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), + .CPUQDENY (CPUQDENY[`MAIA_CN:0]), + .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), + .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), + .STANDBYWFIL2 (STANDBYWFIL2), + .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), + .ck_cpu0_commrx (ck_cpu0_commrx), + .ck_cpu0_commtx (ck_cpu0_commtx), + .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), + .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), + .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), + .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), + .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), + .ck_cpu0_event_reg (ck_cpu0_event_reg), + .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), + .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), + .ck_cpu0_ncommirq (ck_cpu0_ncommirq), + .ck_cpu0_npmuirq (ck_cpu0_npmuirq), + .ck_cpu0_poreset_status (ck_cpu0_poreset_status), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), + .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), + .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), + .ck_cpu1_commrx (ck_cpu1_commrx), + .ck_cpu1_commtx (ck_cpu1_commtx), + .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), + .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), + .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), + .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), + .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), + .ck_cpu1_event_reg (ck_cpu1_event_reg), + .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), + .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), + .ck_cpu1_ncommirq (ck_cpu1_ncommirq), + .ck_cpu1_npmuirq (ck_cpu1_npmuirq), + .ck_cpu1_poreset_status (ck_cpu1_poreset_status), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), + .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), + .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), + .ck_cpu2_commrx (ck_cpu2_commrx), + .ck_cpu2_commtx (ck_cpu2_commtx), + .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), + .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), + .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), + .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), + .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), + .ck_cpu2_event_reg (ck_cpu2_event_reg), + .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), + .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), + .ck_cpu2_ncommirq (ck_cpu2_ncommirq), + .ck_cpu2_npmuirq (ck_cpu2_npmuirq), + .ck_cpu2_poreset_status (ck_cpu2_poreset_status), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), + .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), + .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), + .ck_cpu3_commrx (ck_cpu3_commrx), + .ck_cpu3_commtx (ck_cpu3_commtx), + .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), + .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), + .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), + .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), + .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), + .ck_cpu3_event_reg (ck_cpu3_event_reg), + .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), + .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), + .ck_cpu3_ncommirq (ck_cpu3_ncommirq), + .ck_cpu3_npmuirq (ck_cpu3_npmuirq), + .ck_cpu3_poreset_status (ck_cpu3_poreset_status), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), + .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), + .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), + .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), + .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), + .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), + .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), + .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), + .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), + .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), + .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), + .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), + .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), + .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), + .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), + .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), + .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), + .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), + .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), + .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), + .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), + .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), + .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), + .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), + .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), + .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), + .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), + .ck_l2_ace_inactive (ck_l2_ace_inactive), + .ck_l2_acp_inactive (ck_l2_acp_inactive), + .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), + + // inputs + .ACINACTM (SINACT), + .AINACTS (AINACTS), + .CPUQREQn (CPUQREQn[`MAIA_CN:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .ck_gclkfr (ck_gclkfr), + .clrexmon_c1 (clrexmon_c1), + .commrx_cpu0_i (commrx_cpu0_i), + .commrx_cpu1_i (commrx_cpu1_i), + .commrx_cpu2_i (commrx_cpu2_i), + .commrx_cpu3_i (commrx_cpu3_i), + .commtx_cpu0_i (commtx_cpu0_i), + .commtx_cpu1_i (commtx_cpu1_i), + .commtx_cpu2_i (commtx_cpu2_i), + .commtx_cpu3_i (commtx_cpu3_i), + .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), + .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), + .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), + .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), + .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), + .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), + .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), + .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_cpu0_flush (ds_cpu0_flush), + .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), + .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), + .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_cpu0_reset_req (ds_cpu0_reset_req), + .ds_cpu0_sevl_req (ds_cpu0_sevl_req), + .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_cpu0_wfe_req (ds_cpu0_wfe_req), + .ds_cpu0_wfi_req (ds_cpu0_wfi_req), + .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_cpu1_flush (ds_cpu1_flush), + .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), + .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), + .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_cpu1_reset_req (ds_cpu1_reset_req), + .ds_cpu1_sevl_req (ds_cpu1_sevl_req), + .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_cpu1_wfe_req (ds_cpu1_wfe_req), + .ds_cpu1_wfi_req (ds_cpu1_wfi_req), + .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_cpu2_flush (ds_cpu2_flush), + .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), + .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), + .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_cpu2_reset_req (ds_cpu2_reset_req), + .ds_cpu2_sevl_req (ds_cpu2_sevl_req), + .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_cpu2_wfe_req (ds_cpu2_wfe_req), + .ds_cpu2_wfi_req (ds_cpu2_wfi_req), + .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_cpu3_flush (ds_cpu3_flush), + .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), + .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), + .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_cpu3_reset_req (ds_cpu3_reset_req), + .ds_cpu3_sevl_req (ds_cpu3_sevl_req), + .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_cpu3_wfe_req (ds_cpu3_wfe_req), + .ds_cpu3_wfi_req (ds_cpu3_wfi_req), + .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), + .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), + .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), + .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), + .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), + .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), + .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), + .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), + .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_cpu0_snp_active (l2_cpu0_snp_active), + .l2_cpu1_snp_active (l2_cpu1_snp_active), + .l2_cpu2_snp_active (l2_cpu2_snp_active), + .l2_cpu3_snp_active (l2_cpu3_snp_active), + .l2_idle (l2_idle), + .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), + .l2_reset3 (l2_reset3), + .l2_sky_link_stopped (l2_sky_link_stopped), + .ls_cpu0_clrexmon (ls_cpu0_clrexmon), + .ls_cpu1_clrexmon (ls_cpu1_clrexmon), + .ls_cpu2_clrexmon (ls_cpu2_clrexmon), + .ls_cpu3_clrexmon (ls_cpu3_clrexmon), + .nCORERESET (nCORERESET[`MAIA_CN:0]), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .ncommirq_cpu0_i (ncommirq_cpu0_i), + .ncommirq_cpu1_i (ncommirq_cpu1_i), + .ncommirq_cpu2_i (ncommirq_cpu2_i), + .ncommirq_cpu3_i (ncommirq_cpu3_i), + .npmuirq_cpu0_i (npmuirq_cpu0_i), + .npmuirq_cpu1_i (npmuirq_cpu1_i), + .npmuirq_cpu2_i (npmuirq_cpu2_i), + .npmuirq_cpu3_i (npmuirq_cpu3_i), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_event_sev (tm_cpu0_event_sev), + .tm_cpu1_event_sev (tm_cpu1_event_sev), + .tm_cpu2_event_sev (tm_cpu2_event_sev), + .tm_cpu3_event_sev (tm_cpu3_event_sev) + ); // uck_logic + + maia_cpu_io ucpu_io( // outputs + .aa64naa32_cpu0_o (aa64naa32_cpu0_o), + .aa64naa32_cpu1_o (aa64naa32_cpu1_o), + .aa64naa32_cpu2_o (aa64naa32_cpu2_o), + .aa64naa32_cpu3_o (aa64naa32_cpu3_o), + .cfgend_cpu0_o (cfgend_cpu0_o), + .cfgend_cpu1_o (cfgend_cpu1_o), + .cfgend_cpu2_o (cfgend_cpu2_o), + .cfgend_cpu3_o (cfgend_cpu3_o), + .cfgte_cpu0_o (cfgte_cpu0_o), + .cfgte_cpu1_o (cfgte_cpu1_o), + .cfgte_cpu2_o (cfgte_cpu2_o), + .cfgte_cpu3_o (cfgte_cpu3_o), + .clrexmon_c1 (clrexmon_c1), + .clrexmonack_o (CLREXMONACK), + .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), + .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), + .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), + .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), + .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), + .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), + .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), + .commrx_o (COMMRX[`MAIA_CN:0]), + .commtx_o (COMMTX[`MAIA_CN:0]), + .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), + .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), + .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), + .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), + .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), + .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), + .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), + .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu0_o (cryptodisable_cpu0_o), + .cryptodisable_cpu1_o (cryptodisable_cpu1_o), + .cryptodisable_cpu2_o (cryptodisable_cpu2_o), + .cryptodisable_cpu3_o (cryptodisable_cpu3_o), + .dbgack_o (DBGACK[`MAIA_CN:0]), + .dbgen_cpu0_o (dbgen_cpu0_o), + .dbgen_cpu1_o (dbgen_cpu1_o), + .dbgen_cpu2_o (dbgen_cpu2_o), + .dbgen_cpu3_o (dbgen_cpu3_o), + .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), + .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), + .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), + .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), + .dbgnopwrdwn_o (DBGNOPWRDWN[`MAIA_CN:0]), + .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), + .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), + .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), + .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), + .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), + .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), + .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), + .dbgrstreq_o (DBGRSTREQ[`MAIA_CN:0]), + .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), + .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), + .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), + .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), + .dftramhold_cpu0_o (dftramhold_cpu0_o), + .dftramhold_cpu1_o (dftramhold_cpu1_o), + .dftramhold_cpu2_o (dftramhold_cpu2_o), + .dftramhold_cpu3_o (dftramhold_cpu3_o), + .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), + .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), + .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), + .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), + .dftse_cpu0_o (dftse_cpu0_o), + .dftse_cpu1_o (dftse_cpu1_o), + .dftse_cpu2_o (dftse_cpu2_o), + .dftse_cpu3_o (dftse_cpu3_o), + .eventi_sev (eventi_sev), + .evento_o (EVENTO), + .giccdisable_cpu0_o (giccdisable_cpu0_o), + .giccdisable_cpu1_o (giccdisable_cpu1_o), + .giccdisable_cpu2_o (giccdisable_cpu2_o), + .giccdisable_cpu3_o (giccdisable_cpu3_o), + .ncommirq_o (nCOMMIRQ[`MAIA_CN:0]), + .ncorereset_cpu0_o (ncorereset_cpu0_o), + .ncorereset_cpu1_o (ncorereset_cpu1_o), + .ncorereset_cpu2_o (ncorereset_cpu2_o), + .ncorereset_cpu3_o (ncorereset_cpu3_o), + .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), + .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), + .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), + .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), + .niden_cpu0_o (niden_cpu0_o), + .niden_cpu1_o (niden_cpu1_o), + .niden_cpu2_o (niden_cpu2_o), + .niden_cpu3_o (niden_cpu3_o), + .nmbistreset_cpu0_o (nmbistreset_cpu0_o), + .nmbistreset_cpu1_o (nmbistreset_cpu1_o), + .nmbistreset_cpu2_o (nmbistreset_cpu2_o), + .nmbistreset_cpu3_o (nmbistreset_cpu3_o), + .npmuirq_o (nPMUIRQ[`MAIA_CN:0]), + .pmuevent0_o (PMUEVENT0[24:0]), + .pmuevent1_o (PMUEVENT1[24:0]), + .pmuevent2_o (PMUEVENT2[24:0]), + .pmuevent3_o (PMUEVENT3[24:0]), + .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), + .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), + .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), + .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), + .smpen_o (SMPEN[`MAIA_CN:0]), + .spiden_cpu0_o (spiden_cpu0_o), + .spiden_cpu1_o (spiden_cpu1_o), + .spiden_cpu2_o (spiden_cpu2_o), + .spiden_cpu3_o (spiden_cpu3_o), + .spniden_cpu0_o (spniden_cpu0_o), + .spniden_cpu1_o (spniden_cpu1_o), + .spniden_cpu2_o (spniden_cpu2_o), + .spniden_cpu3_o (spniden_cpu3_o), + .vinithi_cpu0_o (vinithi_cpu0_o), + .vinithi_cpu1_o (vinithi_cpu1_o), + .vinithi_cpu2_o (vinithi_cpu2_o), + .vinithi_cpu3_o (vinithi_cpu3_o), + + // inputs + .aa64naa32_i (AA64nAA32[`MAIA_CN:0]), + .cfgend_i (CFGEND[`MAIA_CN:0]), + .cfgte_i (CFGTE[`MAIA_CN:0]), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), + .ck_cpu0_commrx (ck_cpu0_commrx), + .ck_cpu0_commtx (ck_cpu0_commtx), + .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), + .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), + .ck_cpu0_ncommirq (ck_cpu0_ncommirq), + .ck_cpu0_npmuirq (ck_cpu0_npmuirq), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), + .ck_cpu1_commrx (ck_cpu1_commrx), + .ck_cpu1_commtx (ck_cpu1_commtx), + .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), + .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), + .ck_cpu1_ncommirq (ck_cpu1_ncommirq), + .ck_cpu1_npmuirq (ck_cpu1_npmuirq), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), + .ck_cpu2_commrx (ck_cpu2_commrx), + .ck_cpu2_commtx (ck_cpu2_commtx), + .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), + .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), + .ck_cpu2_ncommirq (ck_cpu2_ncommirq), + .ck_cpu2_npmuirq (ck_cpu2_npmuirq), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), + .ck_cpu3_commrx (ck_cpu3_commrx), + .ck_cpu3_commtx (ck_cpu3_commtx), + .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), + .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), + .ck_cpu3_ncommirq (ck_cpu3_ncommirq), + .ck_cpu3_npmuirq (ck_cpu3_npmuirq), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), + .ck_gclkfr (ck_gclkfr), + .clrexmonreq_i (CLREXMONREQ), + .clusteridaff1_i (CLUSTERIDAFF1[7:0]), + .clusteridaff2_i (CLUSTERIDAFF2[7:0]), + .cp15sdisable_i (CP15SDISABLE[`MAIA_CN:0]), + .cryptodisable_i (CRYPTODISABLE[`MAIA_CN:0]), + .dbgack_cpu0_i (dbgack_cpu0_i), + .dbgack_cpu1_i (dbgack_cpu1_i), + .dbgack_cpu2_i (dbgack_cpu2_i), + .dbgack_cpu3_i (dbgack_cpu3_i), + .dbgen_i (DBGEN[`MAIA_CN:0]), + .dbgl1rstdisable_i (DBGL1RSTDISABLE), + .dbgromaddr_i (DBGROMADDR[43:12]), + .dbgromaddrv_i (DBGROMADDRV), + .dftcrclkdisable_i (DFTCRCLKDISABLE[`MAIA_CN:0]), + .dftramhold_i (DFTRAMHOLD), + .dftrstdisable_i (DFTRSTDISABLE), + .dftse_i (DFTSE), + .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_cpu0_sev_req (ds_cpu0_sev_req), + .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_cpu1_sev_req (ds_cpu1_sev_req), + .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_cpu2_sev_req (ds_cpu2_sev_req), + .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_cpu3_sev_req (ds_cpu3_sev_req), + .eventi_i (EVENTI), + .giccdisable_i (GICCDISABLE), + .l2_reset3 (l2_reset3), + .ncorereset_i (nCORERESET[`MAIA_CN:0]), + .ncpuporeset_i (nCPUPORESET[`MAIA_CN:0]), + .niden_i (NIDEN[`MAIA_CN:0]), + .nmbistreset_i (nMBISTRESET), + .pm_export_cpu0_i (pm_export_cpu0_i), + .pm_export_cpu1_i (pm_export_cpu1_i), + .pm_export_cpu2_i (pm_export_cpu2_i), + .pm_export_cpu3_i (pm_export_cpu3_i), + .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), + .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), + .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), + .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]), + .rvbaraddr0_i (RVBARADDR0[43:2]), + .rvbaraddr1_i (RVBARADDR1[43:2]), + .rvbaraddr2_i (RVBARADDR2[43:2]), + .rvbaraddr3_i (RVBARADDR3[43:2]), + .spiden_i (SPIDEN[`MAIA_CN:0]), + .spniden_i (SPNIDEN[`MAIA_CN:0]), + .vinithi_i (VINITHI[`MAIA_CN:0]) + ); // ucpu_io + + maia_dt_sb udt_sb( // outputs + .afreadym0_o (AFREADYM0), + .afreadym1_o (AFREADYM1), + .afreadym2_o (AFREADYM2), + .afreadym3_o (AFREADYM3), + .afvalidm_cpu0_o (afvalidm_cpu0_o), + .afvalidm_cpu1_o (afvalidm_cpu1_o), + .afvalidm_cpu2_o (afvalidm_cpu2_o), + .afvalidm_cpu3_o (afvalidm_cpu3_o), + .atbytesm0_o (ATBYTESM0[1:0]), + .atbytesm1_o (ATBYTESM1[1:0]), + .atbytesm2_o (ATBYTESM2[1:0]), + .atbytesm3_o (ATBYTESM3[1:0]), + .atclken_cpu0_o (atclken_cpu0_o), + .atclken_cpu1_o (atclken_cpu1_o), + .atclken_cpu2_o (atclken_cpu2_o), + .atclken_cpu3_o (atclken_cpu3_o), + .atdatam0_o (ATDATAM0[31:0]), + .atdatam1_o (ATDATAM1[31:0]), + .atdatam2_o (ATDATAM2[31:0]), + .atdatam3_o (ATDATAM3[31:0]), + .atidm0_o (ATIDM0[6:0]), + .atidm1_o (ATIDM1[6:0]), + .atidm2_o (ATIDM2[6:0]), + .atidm3_o (ATIDM3[6:0]), + .atreadym_cpu0_o (atreadym_cpu0_o), + .atreadym_cpu1_o (atreadym_cpu1_o), + .atreadym_cpu2_o (atreadym_cpu2_o), + .atreadym_cpu3_o (atreadym_cpu3_o), + .atvalidm0_o (ATVALIDM0), + .atvalidm1_o (ATVALIDM1), + .atvalidm2_o (ATVALIDM2), + .atvalidm3_o (ATVALIDM3), + .syncreqm_cpu0_o (syncreqm_cpu0_o), + .syncreqm_cpu1_o (syncreqm_cpu1_o), + .syncreqm_cpu2_o (syncreqm_cpu2_o), + .syncreqm_cpu3_o (syncreqm_cpu3_o), + .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), + .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), + .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), + .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), + + // inputs + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .TSVALUEB (TSVALUEB[63:0]), + .afreadym_cpu0_i (afreadym_cpu0_i), + .afreadym_cpu1_i (afreadym_cpu1_i), + .afreadym_cpu2_i (afreadym_cpu2_i), + .afreadym_cpu3_i (afreadym_cpu3_i), + .afvalidm0_i (AFVALIDM0), + .afvalidm1_i (AFVALIDM1), + .afvalidm2_i (AFVALIDM2), + .afvalidm3_i (AFVALIDM3), + .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), + .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), + .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), + .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), + .atclken_i (ATCLKEN), + .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), + .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), + .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), + .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), + .atidm_cpu0_i (atidm_cpu0_i[6:0]), + .atidm_cpu1_i (atidm_cpu1_i[6:0]), + .atidm_cpu2_i (atidm_cpu2_i[6:0]), + .atidm_cpu3_i (atidm_cpu3_i[6:0]), + .atreadym0_i (ATREADYM0), + .atreadym1_i (ATREADYM1), + .atreadym2_i (ATREADYM2), + .atreadym3_i (ATREADYM3), + .atvalidm_cpu0_i (atvalidm_cpu0_i), + .atvalidm_cpu1_i (atvalidm_cpu1_i), + .atvalidm_cpu2_i (atvalidm_cpu2_i), + .atvalidm_cpu3_i (atvalidm_cpu3_i), + .ck_gclkfr (ck_gclkfr), + .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), + .etclken_cpu0_i (etclken_cpu0_i), + .etclken_cpu1_i (etclken_cpu1_i), + .etclken_cpu2_i (etclken_cpu2_i), + .etclken_cpu3_i (etclken_cpu3_i), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nMBISTRESET (nMBISTRESET), + .syncreqm0_i (SYNCREQM0), + .syncreqm1_i (SYNCREQM1), + .syncreqm2_i (SYNCREQM2), + .syncreqm3_i (SYNCREQM3) + ); // udt_sb + + maia_ncpu_reg_rep uncpu_reg_rep( // outputs + .ds_cpu0_ic_aa64naa32_reg_o (ds_cpu0_ic_aa64naa32_i), + .ds_cpu0_ic_cpsr_mode_reg_o (ds_cpu0_ic_cpsr_mode_i[4:0]), + .ds_cpu0_ic_hcr_change_reg_o (ds_cpu0_ic_hcr_change_i), + .ds_cpu0_ic_sample_spr_reg_o (ds_cpu0_ic_sample_spr_i), + .ds_cpu0_ic_scr_change_reg_o (ds_cpu0_ic_scr_change_i), + .ds_cpu1_ic_aa64naa32_reg_o (ds_cpu1_ic_aa64naa32_i), + .ds_cpu1_ic_cpsr_mode_reg_o (ds_cpu1_ic_cpsr_mode_i[4:0]), + .ds_cpu1_ic_hcr_change_reg_o (ds_cpu1_ic_hcr_change_i), + .ds_cpu1_ic_sample_spr_reg_o (ds_cpu1_ic_sample_spr_i), + .ds_cpu1_ic_scr_change_reg_o (ds_cpu1_ic_scr_change_i), + .ds_cpu2_ic_aa64naa32_reg_o (ds_cpu2_ic_aa64naa32_i), + .ds_cpu2_ic_cpsr_mode_reg_o (ds_cpu2_ic_cpsr_mode_i[4:0]), + .ds_cpu2_ic_hcr_change_reg_o (ds_cpu2_ic_hcr_change_i), + .ds_cpu2_ic_sample_spr_reg_o (ds_cpu2_ic_sample_spr_i), + .ds_cpu2_ic_scr_change_reg_o (ds_cpu2_ic_scr_change_i), + .ds_cpu3_ic_aa64naa32_reg_o (ds_cpu3_ic_aa64naa32_i), + .ds_cpu3_ic_cpsr_mode_reg_o (ds_cpu3_ic_cpsr_mode_i[4:0]), + .ds_cpu3_ic_hcr_change_reg_o (ds_cpu3_ic_hcr_change_i), + .ds_cpu3_ic_sample_spr_reg_o (ds_cpu3_ic_sample_spr_i), + .ds_cpu3_ic_scr_change_reg_o (ds_cpu3_ic_scr_change_i), + .ic_block_eoi_sgi_wr_reg_o (ic_block_eoi_sgi_wr[`MAIA_CN:0]), + .ic_el_change_complete_reg_o (ic_el_change_complete[`MAIA_CN:0]), + .ic_hcr_change_complete_reg_o (ic_hcr_change_complete[`MAIA_CN:0]), + .ic_ich_el2_tall0_reg_o (ic_ich_el2_tall0[`MAIA_CN:0]), + .ic_ich_el2_tall1_reg_o (ic_ich_el2_tall1[`MAIA_CN:0]), + .ic_ich_el2_tc_reg_o (ic_ich_el2_tc[`MAIA_CN:0]), + .ic_nfiq_reg_o (ic_nfiq[`MAIA_CN:0]), + .ic_nirq_reg_o (ic_nirq[`MAIA_CN:0]), + .ic_nsei_reg_o (ic_nsei[`MAIA_CN:0]), + .ic_nvfiq_reg_o (ic_nvfiq[`MAIA_CN:0]), + .ic_nvirq_reg_o (ic_nvirq[`MAIA_CN:0]), + .ic_nvsei_reg_o (ic_nvsei[`MAIA_CN:0]), + .ic_sample_spr_reg_o (ic_sample_spr[`MAIA_CN:0]), + .ic_scr_change_complete_reg_o (ic_scr_change_complete[`MAIA_CN:0]), + .ic_sra_el1ns_en_reg_o (ic_sra_el1ns_en[`MAIA_CN:0]), + .ic_sra_el1s_en_reg_o (ic_sra_el1s_en[`MAIA_CN:0]), + .ic_sra_el2_en_reg_o (ic_sra_el2_en[`MAIA_CN:0]), + .ic_sra_el3_en_reg_o (ic_sra_el3_en[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap_reg_o (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap_reg_o (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap_reg_o (ic_sre_el1s_mon_trap[`MAIA_CN:0]), + .ic_sre_el2_mon_trap_reg_o (ic_sre_el2_mon_trap[`MAIA_CN:0]), + + // inputs + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), + .ic_el_change_complete (ic_el_change_complete_o[`MAIA_CN:0]), + .ic_hcr_change_complete (ic_hcr_change_complete_o[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .ic_sample_spr (ic_sample_spr_o[`MAIA_CN:0]), + .ic_scr_change_complete (ic_scr_change_complete_o[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]) + ); // uncpu_reg_rep + +//----------------------------------------------------------------------------- +// OVL Assertions +//----------------------------------------------------------------------------- +`ifdef ARM_ASSERT_ON + `include "maia_noncpu_feq28_s_val.v" +`endif + +endmodule // maia_noncpu_feq28_s + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_s.v b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_s.v new file mode 100644 index 0000000000..431c8f5de9 --- /dev/null +++ b/Security Algo Accelerator/logical/maia/verilog/maia_noncpu_s.v @@ -0,0 +1,7952 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: maia_noncpu.v $ +// Checked In : $Date: 2015-05-06 10:47:09 -0500 (Wed, 06 May 2015) $ +// Revision : $Revision: 73443 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// +// This is top-level interconnect layer for the non-CPU blocks at the Maia top-level. +// + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +`define MAIA_CN 3 + +module maia_noncpu_s ( + CLK, + CLKEN, + nCPUPORESET, + nCORERESET, + nL2RESET, + L2RSTDISABLE, + WARMRSTREQ, + CFGEND, + VINITHI, + CFGTE, + CP15SDISABLE, + CLUSTERIDAFF1, + CLUSTERIDAFF2, + AA64nAA32, + RVBARADDR0, +// BEGIN INCLUDE FOR CPU1 + RVBARADDR1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + RVBARADDR2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + RVBARADDR3, +// END INCLUDE FOR CPU3 + CRYPTODISABLE, + nFIQ, + nIRQ, + nSEI, + nREI, + nVFIQ, + nVIRQ, + nVSEI, +// BEGIN NO-GIC pins + nVCPUMNTIRQ, +// END NO-GIC pins + PERIPHBASE, +// BEGIN NO-GIC pins + GICCDISABLE, + ICDTVALID, + ICDTREADY, + ICDTDATA, + ICDTLAST, + ICDTDEST, + ICCTVALID, + ICCTREADY, + ICCTDATA, + ICCTLAST, + ICCTID, +// END NO-GIC pins + CNTVALUEB, + CNTCLKEN, + nCNTPNSIRQ, + nCNTPSIRQ, + nCNTVIRQ, + nCNTHPIRQ, + CLREXMONREQ, + CLREXMONACK, + EVENTI, + EVENTO, + STANDBYWFI, + STANDBYWFE, + STANDBYWFIL2, + SMPEN, + CPUQACTIVE, + CPUQREQn, + CPUQACCEPTn, + CPUQDENY, + L2QACTIVE, + L2QREQn, + L2QACCEPTn, + L2QDENY, + L2FLUSHREQ, + L2FLUSHDONE, + nINTERRIRQ, + nEXTERRIRQ, + SYSBARDISABLE, + BROADCASTINNER, + BROADCASTOUTER, + BROADCASTCACHEMAINT, + SCLKEN, + SINACT, + NODEID, + TXSACTIVE, + RXSACTIVE, + TXLINKACTIVEREQ, + TXLINKACTIVEACK, + RXLINKACTIVEREQ, + RXLINKACTIVEACK, + TXREQFLITPEND, + TXREQFLITV, + TXREQFLIT, + REQMEMATTR, + TXREQLCRDV, + TXRSPFLITPEND, + TXRSPFLITV, + TXRSPFLIT, + TXRSPLCRDV, + TXDATFLITPEND, + TXDATFLITV, + TXDATFLIT, + TXDATLCRDV, + RXSNPFLITPEND, + RXSNPFLITV, + RXSNPFLIT, + RXSNPLCRDV, + RXRSPFLITPEND, + RXRSPFLITV, + RXRSPFLIT, + RXRSPLCRDV, + RXDATFLITPEND, + RXDATFLITV, + RXDATFLIT, + RXDATLCRDV, + SAMMNBASE, + SAMADDRMAP0, + SAMADDRMAP1, + SAMADDRMAP2, + SAMADDRMAP3, + SAMADDRMAP4, + SAMADDRMAP5, + SAMADDRMAP6, + SAMADDRMAP7, + SAMADDRMAP8, + SAMADDRMAP9, + SAMADDRMAP10, + SAMADDRMAP11, + SAMADDRMAP12, + SAMADDRMAP13, + SAMADDRMAP14, + SAMADDRMAP15, + SAMADDRMAP16, + SAMADDRMAP17, + SAMADDRMAP18, + SAMADDRMAP19, + SAMMNNODEID, + SAMHNI0NODEID, + SAMHNI1NODEID, + SAMHNF0NODEID, + SAMHNF1NODEID, + SAMHNF2NODEID, + SAMHNF3NODEID, + SAMHNF4NODEID, + SAMHNF5NODEID, + SAMHNF6NODEID, + SAMHNF7NODEID, + SAMHNFMODE, +// BEGIN NO-ACP pins + ACLKENS, + AINACTS, + AWREADYS, + AWVALIDS, + AWIDS, + AWADDRS, + AWLENS, + AWCACHES, + AWUSERS, + AWPROTS, + WREADYS, + WVALIDS, + WDATAS, + WSTRBS, + WLASTS, + BREADYS, + BVALIDS, + BIDS, + BRESPS, + ARREADYS, + ARVALIDS, + ARIDS, + ARADDRS, + ARLENS, + ARCACHES, + ARUSERS, + ARPROTS, + RREADYS, + RVALIDS, + RIDS, + RDATAS, + RRESPS, + RLASTS, +// END NO-ACP pins + DBGROMADDR, + DBGROMADDRV, + DBGACK, + nCOMMIRQ, + COMMRX, + COMMTX, + DBGRSTREQ, + DBGNOPWRDWN, + DBGL1RSTDISABLE, + nPMUIRQ, + PMUEVENT0, +// BEGIN INCLUDE FOR CPU1 + PMUEVENT1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + PMUEVENT2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + PMUEVENT3, +// END INCLUDE FOR CPU3 + ATCLKEN, + TSVALUEB, + ATREADYM0, + AFVALIDM0, + ATDATAM0, + ATVALIDM0, + ATBYTESM0, + AFREADYM0, + ATIDM0, + SYNCREQM0, +// BEGIN INCLUDE FOR CPU1 + ATREADYM1, + AFVALIDM1, + ATDATAM1, + ATVALIDM1, + ATBYTESM1, + AFREADYM1, + ATIDM1, + SYNCREQM1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ATREADYM2, + AFVALIDM2, + ATDATAM2, + ATVALIDM2, + ATBYTESM2, + AFREADYM2, + ATIDM2, + SYNCREQM2, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ATREADYM3, + AFVALIDM3, + ATDATAM3, + ATVALIDM3, + ATBYTESM3, + AFREADYM3, + ATIDM3, + SYNCREQM3, +// END INCLUDE FOR CPU3 + PCLKDBG, + PCLKENDBG, + nPRESETDBG, + PSELDBG, + PADDRDBG, + PADDRDBG31, + PENABLEDBG, + PWRITEDBG, + PWDATADBG, + PRDATADBG, + PREADYDBG, + PSLVERRDBG, + EDBGRQ, + PMUSNAPSHOTREQ, + PMUSNAPSHOTACK, + DBGPWRDUP, + DBGPWRUPREQ, + CTICHIN, + CTICHOUTACK, + CTICHOUT, + CTICHINACK, + CISBYPASS, + CIHSBYPASS, + CTIIRQ, + CTIIRQACK, + DBGEN, + NIDEN, + SPIDEN, + SPNIDEN, + DFTSE, + DFTRSTDISABLE, + DFTCRCLKDISABLE, + DFTL2CLKDISABLE, + DFTRAMHOLD, + DFTCLKBYPASS, + DFTMCPHOLD, + nMBISTRESET, + MBISTREQ, + +//----------------------------------------------------------------------------- +// Signals from maia -> maia_cpu_io -> maia_cpu +//----------------------------------------------------------------------------- +// Outputs to maia_cpu + ncpuporeset_cpu0_o, + ncorereset_cpu0_o, + + cfgend_cpu0_o, + cfgte_cpu0_o, + cp15sdisable_cpu0_o, + vinithi_cpu0_o, + clusteridaff1_cpu0_o, + clusteridaff2_cpu0_o, + cpuid_cpu0_o, + aa64naa32_cpu0_o, + rvbaraddr_cpu0_o, + cryptodisable_cpu0_o, + giccdisable_cpu0_o, + + dbgromaddr_cpu0_o, + dbgromaddrv_cpu0_o, + dbgl1rstdisable_cpu0_o, + + dbgen_cpu0_o, + niden_cpu0_o, + spiden_cpu0_o, + spniden_cpu0_o, + + tsvalueb_cpu0_o, + + atclken_cpu0_o, + afvalidm_cpu0_o, + atreadym_cpu0_o, + syncreqm_cpu0_o, + + dftse_cpu0_o, + dftrstdisable_cpu0_o, + dftcrclkdisable_cpu0_o, + dftramhold_cpu0_o, + + nmbistreset_cpu0_o, + +// BEGIN INCLUDE FOR CPU1 + ncpuporeset_cpu1_o, + ncorereset_cpu1_o, + + cfgend_cpu1_o, + cfgte_cpu1_o, + cp15sdisable_cpu1_o, + vinithi_cpu1_o, + clusteridaff1_cpu1_o, + clusteridaff2_cpu1_o, + cpuid_cpu1_o, + aa64naa32_cpu1_o, + rvbaraddr_cpu1_o, + cryptodisable_cpu1_o, + giccdisable_cpu1_o, + + dbgromaddr_cpu1_o, + dbgromaddrv_cpu1_o, + dbgl1rstdisable_cpu1_o, + + dbgen_cpu1_o, + niden_cpu1_o, + spiden_cpu1_o, + spniden_cpu1_o, + + tsvalueb_cpu1_o, + + atclken_cpu1_o, + afvalidm_cpu1_o, + atreadym_cpu1_o, + syncreqm_cpu1_o, + + dftse_cpu1_o, + dftrstdisable_cpu1_o, + dftcrclkdisable_cpu1_o, + dftramhold_cpu1_o, + + nmbistreset_cpu1_o, +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + ncpuporeset_cpu2_o, + ncorereset_cpu2_o, + + cfgend_cpu2_o, + cfgte_cpu2_o, + cp15sdisable_cpu2_o, + vinithi_cpu2_o, + clusteridaff1_cpu2_o, + clusteridaff2_cpu2_o, + cpuid_cpu2_o, + aa64naa32_cpu2_o, + rvbaraddr_cpu2_o, + cryptodisable_cpu2_o, + giccdisable_cpu2_o, + + dbgromaddr_cpu2_o, + dbgromaddrv_cpu2_o, + dbgl1rstdisable_cpu2_o, + + dbgen_cpu2_o, + niden_cpu2_o, + spiden_cpu2_o, + spniden_cpu2_o, + + tsvalueb_cpu2_o, + + atclken_cpu2_o, + afvalidm_cpu2_o, + atreadym_cpu2_o, + syncreqm_cpu2_o, + + dftse_cpu2_o, + dftrstdisable_cpu2_o, + dftcrclkdisable_cpu2_o, + dftramhold_cpu2_o, + + nmbistreset_cpu2_o, +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + ncpuporeset_cpu3_o, + ncorereset_cpu3_o, + + cfgend_cpu3_o, + cfgte_cpu3_o, + cp15sdisable_cpu3_o, + vinithi_cpu3_o, + clusteridaff1_cpu3_o, + clusteridaff2_cpu3_o, + cpuid_cpu3_o, + aa64naa32_cpu3_o, + rvbaraddr_cpu3_o, + cryptodisable_cpu3_o, + giccdisable_cpu3_o, + + dbgromaddr_cpu3_o, + dbgromaddrv_cpu3_o, + dbgl1rstdisable_cpu3_o, + + dbgen_cpu3_o, + niden_cpu3_o, + spiden_cpu3_o, + spniden_cpu3_o, + + tsvalueb_cpu3_o, + + atclken_cpu3_o, + afvalidm_cpu3_o, + atreadym_cpu3_o, + syncreqm_cpu3_o, + + dftse_cpu3_o, + dftrstdisable_cpu3_o, + dftcrclkdisable_cpu3_o, + dftramhold_cpu3_o, + + nmbistreset_cpu3_o, +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Signals from maia_cpu -> maia_cpu_io -> maia +//----------------------------------------------------------------------------- +// Inputs from maia_cpu + ds_cpu0_sev_req, + ds_cpu0_sevl_req, + ds_cpu0_cpuectlr_smp, + + ncommirq_cpu0_i, + commrx_cpu0_i, + commtx_cpu0_i, + dbgack_cpu0_i, + dbgrstreq_cpu0_i, + dbgnopwrdwn_cpu0_i, + + npmuirq_cpu0_i, + pmuevent_cpu0_i, + pm_export_cpu0_i, + + etclken_cpu0_i, + afreadym_cpu0_i, + atbytesm_cpu0_i, + atdatam_cpu0_i, + atidm_cpu0_i, + atvalidm_cpu0_i, + +// BEGIN INCLUDE FOR CPU1 + ds_cpu1_sev_req, + ds_cpu1_sevl_req, + ds_cpu1_cpuectlr_smp, + + ncommirq_cpu1_i, + commrx_cpu1_i, + commtx_cpu1_i, + dbgack_cpu1_i, + dbgrstreq_cpu1_i, + dbgnopwrdwn_cpu1_i, + + npmuirq_cpu1_i, + pmuevent_cpu1_i, + pm_export_cpu1_i, + + etclken_cpu1_i, + afreadym_cpu1_i, + atbytesm_cpu1_i, + atdatam_cpu1_i, + atidm_cpu1_i, + atvalidm_cpu1_i, +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + ds_cpu2_sev_req, + ds_cpu2_sevl_req, + ds_cpu2_cpuectlr_smp, + + ncommirq_cpu2_i, + commrx_cpu2_i, + commtx_cpu2_i, + dbgack_cpu2_i, + dbgrstreq_cpu2_i, + dbgnopwrdwn_cpu2_i, + + npmuirq_cpu2_i, + pmuevent_cpu2_i, + pm_export_cpu2_i, + + etclken_cpu2_i, + afreadym_cpu2_i, + atbytesm_cpu2_i, + atdatam_cpu2_i, + atidm_cpu2_i, + atvalidm_cpu2_i, +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + ds_cpu3_sev_req, + ds_cpu3_sevl_req, + ds_cpu3_cpuectlr_smp, + + ncommirq_cpu3_i, + commrx_cpu3_i, + commtx_cpu3_i, + dbgack_cpu3_i, + dbgrstreq_cpu3_i, + dbgnopwrdwn_cpu3_i, + + npmuirq_cpu3_i, + pmuevent_cpu3_i, + pm_export_cpu3_i, + + etclken_cpu3_i, + afreadym_cpu3_i, + atbytesm_cpu3_i, + atdatam_cpu3_i, + atidm_cpu3_i, + atvalidm_cpu3_i, +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// L2 interface +//----------------------------------------------------------------------------- + l2_cpu0_mbist1_addr_b1, + l2_cpu0_mbist1_array_b1, + l2_cpu0_mbist1_be_b1, + l2_cpu0_mbist1_en_b1, + l2_cpu0_mbist1_rd_en_b1, + l2_cpu0_mbist1_wr_en_b1, + l2_cpu0_mbist1_all_b1, +// BEGIN INCLUDE FOR CPU1 + l2_cpu1_mbist1_addr_b1, + l2_cpu1_mbist1_array_b1, + l2_cpu1_mbist1_be_b1, + l2_cpu1_mbist1_en_b1, + l2_cpu1_mbist1_rd_en_b1, + l2_cpu1_mbist1_wr_en_b1, + l2_cpu1_mbist1_all_b1, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + l2_cpu2_mbist1_addr_b1, + l2_cpu2_mbist1_array_b1, + l2_cpu2_mbist1_be_b1, + l2_cpu2_mbist1_en_b1, + l2_cpu2_mbist1_rd_en_b1, + l2_cpu2_mbist1_wr_en_b1, + l2_cpu2_mbist1_all_b1, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + l2_cpu3_mbist1_addr_b1, + l2_cpu3_mbist1_array_b1, + l2_cpu3_mbist1_be_b1, + l2_cpu3_mbist1_en_b1, + l2_cpu3_mbist1_rd_en_b1, + l2_cpu3_mbist1_wr_en_b1, + l2_cpu3_mbist1_all_b1, +// END INCLUDE FOR CPU3 + +// BEGIN L2-CPU interface + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + l2_cpu0_cfg_ecc_en, + l2_cpu0_arb_thrshld_timeout_en, + l2_cpu0_disable_clean_evict_opt, + l2_cpu0_dext_err_r2, + l2_cpu0_dext_err_type_r2, + l2_cpu0_dsngl_ecc_err_r3, + l2_cpu0_ddbl_ecc_err_r3, + l2_cpu0_ddata_r2, + l2_cpu0_barrier_done, + l2_cpu0_spec_valid, + l2_cpu0_spec_bufid, + l2_cpu0_rvalid, + l2_cpu0_rstate, + l2_cpu0_rexfail, + l2_cpu0_rbufid, + l2_cpu0_dvalid_r1, + l2_cpu0_dlast_r1, + l2_cpu0_dbufid_r1, + l2_cpu0_iext_err_r2, + l2_cpu0_iext_err_type_r2, + l2_cpu0_isngl_ecc_err_r3, + l2_cpu0_idbl_ecc_err_r3, + l2_cpu0_idata_r2, + l2_cpu0_ivalid_r1, + l2_cpu0_ibufid_r1, + l2_cpu0_ls_sync_req, + l2_cpu0_ccb_req_addr_c3, + l2_cpu0_ccb_dbg_req_c3, + l2_cpu0_ls_ccb_clken_c3, + l2_cpu0_ls_ccb_req_c3, + l2_cpu0_ccb_req_id_c3, + l2_cpu0_ccb_req_type_c3, + l2_cpu0_ccb_req_info_c3, + l2_cpu0_if_ccb_clken_c3, + l2_cpu0_if_ccb_req_c3, + l2_cpu0_if_sync_req, + l2_cpu0_tlb_ccb_clken_c3, + l2_cpu0_tlb_ccb_req_c3, + l2_cpu0_tlb_sync_req, + l2_cpu0_tlb_sync_complete, + l2_cpu0_tbw_desc_vld, + l2_cpu0_tbw_ext_err, + l2_cpu0_tbw_ext_err_type, + l2_cpu0_tbw_dbl_ecc_err, + l2_cpu0_tbw_desc_data, + l2_cpu0_spr_rd_data, + l2_cpu0_l2_cache_size, + l2_cpu0_pf_throttle_q, + + l2_cpu0_wr_ex_resp, + l2_cpu0_wr_ex_fail, + + l2_cpu0_ic_base, + l2_cpu0_no_intctrl, + + + l2_cpu0_pmu_events, + + ds_cpu0_l2_spr_en, + ds_cpu0_l2_spr_rd, + ds_cpu0_l2_spr_wr, + ds_cpu0_l2_spr_addr, + ds_cpu0_l2_spr_dw, + ds_cpu0_l2_spr_wr_data, + + l2_cpu0_wr_data_vld_x1_q, + l2_cpu0_wr_evict_x1_q, + l2_cpu0_wr_data, + l2_cpu0_ls_rd_haz_vld_arb_q, + l2_cpu0_ls_wr_haz_vld_arb_q, + l2_cpu0_dt_pmu_evt_en, + + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + l2_cpu1_cfg_ecc_en, + l2_cpu1_arb_thrshld_timeout_en, + l2_cpu1_disable_clean_evict_opt, + l2_cpu1_dext_err_r2, + l2_cpu1_dext_err_type_r2, + l2_cpu1_dsngl_ecc_err_r3, + l2_cpu1_ddbl_ecc_err_r3, + l2_cpu1_ddata_r2, + l2_cpu1_barrier_done, + l2_cpu1_spec_valid, + l2_cpu1_spec_bufid, + l2_cpu1_rvalid, + l2_cpu1_rstate, + l2_cpu1_rexfail, + l2_cpu1_rbufid, + l2_cpu1_dvalid_r1, + l2_cpu1_dlast_r1, + l2_cpu1_dbufid_r1, + l2_cpu1_iext_err_r2, + l2_cpu1_iext_err_type_r2, + l2_cpu1_isngl_ecc_err_r3, + l2_cpu1_idbl_ecc_err_r3, + l2_cpu1_idata_r2, + l2_cpu1_ivalid_r1, + l2_cpu1_ibufid_r1, + l2_cpu1_ls_sync_req, + l2_cpu1_ccb_req_addr_c3, + l2_cpu1_ccb_dbg_req_c3, + l2_cpu1_ls_ccb_clken_c3, + l2_cpu1_ls_ccb_req_c3, + l2_cpu1_ccb_req_id_c3, + l2_cpu1_ccb_req_type_c3, + l2_cpu1_ccb_req_info_c3, + l2_cpu1_if_ccb_clken_c3, + l2_cpu1_if_ccb_req_c3, + l2_cpu1_if_sync_req, + l2_cpu1_tlb_ccb_clken_c3, + l2_cpu1_tlb_ccb_req_c3, + l2_cpu1_tlb_sync_req, + l2_cpu1_tlb_sync_complete, + l2_cpu1_tbw_desc_vld, + l2_cpu1_tbw_ext_err, + l2_cpu1_tbw_ext_err_type, + l2_cpu1_tbw_dbl_ecc_err, + l2_cpu1_tbw_desc_data, + l2_cpu1_spr_rd_data, + l2_cpu1_l2_cache_size, + l2_cpu1_pf_throttle_q, + + l2_cpu1_wr_ex_resp, + l2_cpu1_wr_ex_fail, + + l2_cpu1_ic_base, + l2_cpu1_no_intctrl, + + l2_cpu1_pmu_events, + + ds_cpu1_l2_spr_en, + ds_cpu1_l2_spr_rd, + ds_cpu1_l2_spr_wr, + ds_cpu1_l2_spr_addr, + ds_cpu1_l2_spr_dw, + ds_cpu1_l2_spr_wr_data, + + l2_cpu1_wr_data_vld_x1_q, + l2_cpu1_wr_evict_x1_q, + l2_cpu1_wr_data, + l2_cpu1_ls_rd_haz_vld_arb_q, + l2_cpu1_ls_wr_haz_vld_arb_q, + l2_cpu1_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + l2_cpu2_cfg_ecc_en, + l2_cpu2_arb_thrshld_timeout_en, + l2_cpu2_disable_clean_evict_opt, + l2_cpu2_dext_err_r2, + l2_cpu2_dext_err_type_r2, + l2_cpu2_dsngl_ecc_err_r3, + l2_cpu2_ddbl_ecc_err_r3, + l2_cpu2_ddata_r2, + l2_cpu2_barrier_done, + l2_cpu2_spec_valid, + l2_cpu2_spec_bufid, + l2_cpu2_rvalid, + l2_cpu2_rstate, + l2_cpu2_rexfail, + l2_cpu2_rbufid, + l2_cpu2_dvalid_r1, + l2_cpu2_dlast_r1, + l2_cpu2_dbufid_r1, + l2_cpu2_iext_err_r2, + l2_cpu2_iext_err_type_r2, + l2_cpu2_isngl_ecc_err_r3, + l2_cpu2_idbl_ecc_err_r3, + l2_cpu2_idata_r2, + l2_cpu2_ivalid_r1, + l2_cpu2_ibufid_r1, + l2_cpu2_ls_sync_req, + l2_cpu2_ccb_req_addr_c3, + l2_cpu2_ccb_dbg_req_c3, + l2_cpu2_ls_ccb_clken_c3, + l2_cpu2_ls_ccb_req_c3, + l2_cpu2_ccb_req_id_c3, + l2_cpu2_ccb_req_type_c3, + l2_cpu2_ccb_req_info_c3, + l2_cpu2_if_ccb_clken_c3, + l2_cpu2_if_ccb_req_c3, + l2_cpu2_if_sync_req, + l2_cpu2_tlb_ccb_clken_c3, + l2_cpu2_tlb_ccb_req_c3, + l2_cpu2_tlb_sync_req, + l2_cpu2_tlb_sync_complete, + l2_cpu2_tbw_desc_vld, + l2_cpu2_tbw_ext_err, + l2_cpu2_tbw_ext_err_type, + l2_cpu2_tbw_dbl_ecc_err, + l2_cpu2_tbw_desc_data, + l2_cpu2_spr_rd_data, + l2_cpu2_l2_cache_size, + l2_cpu2_pf_throttle_q, + + l2_cpu2_wr_ex_resp, + l2_cpu2_wr_ex_fail, + + l2_cpu2_ic_base, + l2_cpu2_no_intctrl, + + l2_cpu2_pmu_events, + + ds_cpu2_l2_spr_en, + ds_cpu2_l2_spr_rd, + ds_cpu2_l2_spr_wr, + ds_cpu2_l2_spr_addr, + ds_cpu2_l2_spr_dw, + ds_cpu2_l2_spr_wr_data, + + l2_cpu2_wr_data_vld_x1_q, + l2_cpu2_wr_evict_x1_q, + l2_cpu2_wr_data, + l2_cpu2_ls_rd_haz_vld_arb_q, + l2_cpu2_ls_wr_haz_vld_arb_q, + l2_cpu2_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + l2_cpu3_cfg_ecc_en, + l2_cpu3_arb_thrshld_timeout_en, + l2_cpu3_disable_clean_evict_opt, + l2_cpu3_dext_err_r2, + l2_cpu3_dext_err_type_r2, + l2_cpu3_dsngl_ecc_err_r3, + l2_cpu3_ddbl_ecc_err_r3, + l2_cpu3_ddata_r2, + l2_cpu3_barrier_done, + l2_cpu3_spec_valid, + l2_cpu3_spec_bufid, + l2_cpu3_rvalid, + l2_cpu3_rstate, + l2_cpu3_rexfail, + l2_cpu3_rbufid, + l2_cpu3_dvalid_r1, + l2_cpu3_dlast_r1, + l2_cpu3_dbufid_r1, + l2_cpu3_iext_err_r2, + l2_cpu3_iext_err_type_r2, + l2_cpu3_isngl_ecc_err_r3, + l2_cpu3_idbl_ecc_err_r3, + l2_cpu3_idata_r2, + l2_cpu3_ivalid_r1, + l2_cpu3_ibufid_r1, + l2_cpu3_ls_sync_req, + l2_cpu3_ccb_req_addr_c3, + l2_cpu3_ccb_dbg_req_c3, + l2_cpu3_ls_ccb_clken_c3, + l2_cpu3_ls_ccb_req_c3, + l2_cpu3_ccb_req_id_c3, + l2_cpu3_ccb_req_type_c3, + l2_cpu3_ccb_req_info_c3, + l2_cpu3_if_ccb_clken_c3, + l2_cpu3_if_ccb_req_c3, + l2_cpu3_if_sync_req, + l2_cpu3_tlb_ccb_clken_c3, + l2_cpu3_tlb_ccb_req_c3, + l2_cpu3_tlb_sync_req, + l2_cpu3_tlb_sync_complete, + l2_cpu3_tbw_desc_vld, + l2_cpu3_tbw_ext_err, + l2_cpu3_tbw_ext_err_type, + l2_cpu3_tbw_dbl_ecc_err, + l2_cpu3_tbw_desc_data, + l2_cpu3_spr_rd_data, + l2_cpu3_l2_cache_size, + l2_cpu3_pf_throttle_q, + + l2_cpu3_wr_ex_resp, + l2_cpu3_wr_ex_fail, + + l2_cpu3_ic_base, + l2_cpu3_no_intctrl, + + l2_cpu3_pmu_events, + + ds_cpu3_l2_spr_en, + ds_cpu3_l2_spr_rd, + ds_cpu3_l2_spr_wr, + ds_cpu3_l2_spr_addr, + ds_cpu3_l2_spr_dw, + ds_cpu3_l2_spr_wr_data, + + l2_cpu3_wr_data_vld_x1_q, + l2_cpu3_wr_evict_x1_q, + l2_cpu3_wr_data, + l2_cpu3_ls_rd_haz_vld_arb_q, + l2_cpu3_ls_wr_haz_vld_arb_q, + l2_cpu3_dt_pmu_evt_en, + +//----------------------------------------------------------------------------- +// tag_pipe / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_flsh_ls_rd_l2_dly, + l2_cpu0_flsh_ls_wr_l2_dly, + + l2_cpu0_wr_data_stall, + + l2_cpu1_flsh_ls_rd_l2_dly, + l2_cpu1_flsh_ls_wr_l2_dly, + + l2_cpu1_wr_data_stall, + + l2_cpu2_flsh_ls_rd_l2_dly, + l2_cpu2_flsh_ls_wr_l2_dly, + + l2_cpu2_wr_data_stall, + + l2_cpu3_flsh_ls_rd_l2_dly, + l2_cpu3_flsh_ls_wr_l2_dly, + + l2_cpu3_wr_data_stall, + + l2_cpu0_flsh_ls_rd_id_l2_dly, + l2_cpu0_flsh_ls_wr_id_l2_dly, + + l2_cpu1_flsh_ls_rd_id_l2_dly, + l2_cpu1_flsh_ls_wr_id_l2_dly, + + l2_cpu2_flsh_ls_rd_id_l2_dly, + l2_cpu2_flsh_ls_wr_id_l2_dly, + + l2_cpu3_flsh_ls_rd_id_l2_dly, + l2_cpu3_flsh_ls_wr_id_l2_dly, + + l2_cpu0_flsh_ls_rd_l4_dly, + l2_cpu0_flsh_if_rd_l4_dly, + l2_cpu0_flsh_tw_rd_l4_dly, + l2_cpu0_flsh_ls_wr_l4_dly, + + l2_cpu1_flsh_ls_rd_l4_dly, + l2_cpu1_flsh_if_rd_l4_dly, + l2_cpu1_flsh_tw_rd_l4_dly, + l2_cpu1_flsh_ls_wr_l4_dly, + + l2_cpu2_flsh_ls_rd_l4_dly, + l2_cpu2_flsh_if_rd_l4_dly, + l2_cpu2_flsh_tw_rd_l4_dly, + l2_cpu2_flsh_ls_wr_l4_dly, + + l2_cpu3_flsh_ls_rd_l4_dly, + l2_cpu3_flsh_if_rd_l4_dly, + l2_cpu3_flsh_tw_rd_l4_dly, + l2_cpu3_flsh_ls_wr_l4_dly, + + l2_cpu0_flsh_ls_rd_id_l4_dly, + l2_cpu0_flsh_if_rd_id_l4_dly, + l2_cpu0_flsh_ls_wr_id_l4_dly, + l2_cpu0_flsh_ls_wr_evict_l4_dly, + + l2_cpu1_flsh_ls_rd_id_l4_dly, + l2_cpu1_flsh_if_rd_id_l4_dly, + l2_cpu1_flsh_ls_wr_id_l4_dly, + l2_cpu1_flsh_ls_wr_evict_l4_dly, + + l2_cpu2_flsh_ls_rd_id_l4_dly, + l2_cpu2_flsh_if_rd_id_l4_dly, + l2_cpu2_flsh_ls_wr_id_l4_dly, + l2_cpu2_flsh_ls_wr_evict_l4_dly, + + l2_cpu3_flsh_ls_rd_id_l4_dly, + l2_cpu3_flsh_if_rd_id_l4_dly, + l2_cpu3_flsh_ls_wr_id_l4_dly, + l2_cpu3_flsh_ls_wr_evict_l4_dly, + + l2_cpu0_lrq_haz_pending, + l2_cpu1_lrq_haz_pending, + l2_cpu2_lrq_haz_pending, + l2_cpu3_lrq_haz_pending, + + l2_cpu0_ifq_haz_pending, + l2_cpu1_ifq_haz_pending, + l2_cpu2_ifq_haz_pending, + l2_cpu3_ifq_haz_pending, + + l2_cpu0_trq_haz_pending, + l2_cpu1_trq_haz_pending, + l2_cpu2_trq_haz_pending, + l2_cpu3_trq_haz_pending, + + l2_cpu0_wrq_haz_pending, + l2_cpu1_wrq_haz_pending, + l2_cpu2_wrq_haz_pending, + l2_cpu3_wrq_haz_pending, + + l2_cpu0_idle_block_reqs_q, + l2_cpu1_idle_block_reqs_q, + l2_cpu2_idle_block_reqs_q, + l2_cpu3_idle_block_reqs_q, + + l2_cpu0_ls_peq_coll_l4_dly, + l2_cpu1_ls_peq_coll_l4_dly, + l2_cpu2_ls_peq_coll_l4_dly, + l2_cpu3_ls_peq_coll_l4_dly, + +//----------------------------------------------------------------------------- +// tag_pipe +//----------------------------------------------------------------------------- + l2_tbnk0_cpu0_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu1_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu2_lrq_clr_l4_dly2_q, + l2_tbnk0_cpu3_lrq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu1_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu2_lrq_clr_l4_dly2_q, + l2_tbnk1_cpu3_lrq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu1_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu2_ifq_clr_l4_dly2_q, + l2_tbnk0_cpu3_ifq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu1_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu2_ifq_clr_l4_dly2_q, + l2_tbnk1_cpu3_ifq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_trq_clr_l4_dly2_q, + l2_tbnk0_cpu1_trq_clr_l4_dly2_q, + l2_tbnk0_cpu2_trq_clr_l4_dly2_q, + l2_tbnk0_cpu3_trq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_trq_clr_l4_dly2_q, + l2_tbnk1_cpu1_trq_clr_l4_dly2_q, + l2_tbnk1_cpu2_trq_clr_l4_dly2_q, + l2_tbnk1_cpu3_trq_clr_l4_dly2_q, + + l2_tbnk0_cpu0_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu1_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu2_wrq_clr_l4_dly2_q, + l2_tbnk0_cpu3_wrq_clr_l4_dly2_q, + + l2_tbnk1_cpu0_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu1_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu2_wrq_clr_l4_dly2_q, + l2_tbnk1_cpu3_wrq_clr_l4_dly2_q, + + +//----------------------------------------------------------------------------- +// cpu_logic / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly, + + l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly, + l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly, + + +//----------------------------------------------------------------------------- +// feq / cpu slave +//----------------------------------------------------------------------------- + l2_cpu0_dsq_rd_data_q, + l2_cpu0_dsq_rd_byte_strb_q, + l2_cpu1_dsq_rd_data_q, + l2_cpu1_dsq_rd_byte_strb_q, + l2_cpu2_dsq_rd_data_q, + l2_cpu2_dsq_rd_byte_strb_q, + l2_cpu3_dsq_rd_data_q, + l2_cpu3_dsq_rd_byte_strb_q, + + l2_cpu0_dsq_clr_vld_q, + l2_cpu0_dsq_clr_id_q, + l2_cpu0_dsq_rd_en, + l2_cpu0_dsq_rd_en_x2, + l2_cpu0_dsq_rd_buf_id, + l2_cpu1_dsq_clr_vld_q, + l2_cpu1_dsq_clr_id_q, + l2_cpu1_dsq_rd_en, + l2_cpu1_dsq_rd_en_x2, + l2_cpu1_dsq_rd_buf_id, + l2_cpu2_dsq_clr_vld_q, + l2_cpu2_dsq_clr_id_q, + l2_cpu2_dsq_rd_en, + l2_cpu2_dsq_rd_en_x2, + l2_cpu2_dsq_rd_buf_id, + l2_cpu3_dsq_clr_vld_q, + l2_cpu3_dsq_rd_en, + l2_cpu3_dsq_rd_en_x2, + l2_cpu3_dsq_clr_id_q, + l2_cpu3_dsq_rd_buf_id, + +//----------------------------------------------------------------------------- +// arbitration +//----------------------------------------------------------------------------- + l2_cpu0_rd_vld_skid, + l2_cpu1_rd_vld_skid, + l2_cpu2_rd_vld_skid, + l2_cpu3_rd_vld_skid, + + l2_cpu0_pf_rd_vld_skid_popped, + l2_cpu1_pf_rd_vld_skid_popped, + l2_cpu2_pf_rd_vld_skid_popped, + l2_cpu3_pf_rd_vld_skid_popped, + + l2_cpu0_rd_arb, + l2_cpu1_rd_arb, + l2_cpu2_rd_arb, + l2_cpu3_rd_arb, + + l2_cpu0_wr_vld_skid, + l2_cpu1_wr_vld_skid, + l2_cpu2_wr_vld_skid, + l2_cpu3_wr_vld_skid, + + l2_cpu0_wr_arb, + l2_cpu1_wr_arb, + l2_cpu2_wr_arb, + l2_cpu3_wr_arb, + + l2_cpu0_ic_vld_skid, + l2_cpu1_ic_vld_skid, + l2_cpu2_ic_vld_skid, + l2_cpu3_ic_vld_skid, + + l2_cpu0_ic_barrier_stall_q, + l2_cpu1_ic_barrier_stall_q, + l2_cpu2_ic_barrier_stall_q, + l2_cpu3_ic_barrier_stall_q, + + l2_cpu0_blk_non_evict_wr, + l2_cpu1_blk_non_evict_wr, + l2_cpu2_blk_non_evict_wr, + l2_cpu3_blk_non_evict_wr, + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + l2_cpu0_idle_wakeup_q, + l2_cpu0_rd_arb_fast, + l2_cpu0_rd_id_arb_set, + l2_cpu0_rd_lrq_id_arb_set, + l2_cpu0_rd_type_arb_set, + l2_cpu0_rd_cache_attr_arb_set, + l2_cpu0_rd_page_attr_arb_set, + l2_cpu0_rd_elem_size_arb_set, + l2_cpu0_rd_way_arb_set, + l2_cpu0_rd_replayed_arb_set, + l2_cpu0_rd_excl_arb_set, + l2_cpu0_rd_priv_arb_set, + l2_cpu0_rd_shared_arb_set, + l2_cpu0_rd_va48_arb_set, + l2_cpu0_rd_aarch64_arb_set, + l2_cpu0_rd_asid_arb_set, + l2_cpu0_rd_prfm_arb_set, + l2_cpu0_rd_addr_arb_set, + l2_cpu0_rd_bypass_arb_set, + l2_cpu0_rd_bypass_req_can_e5, + l2_cpu0_early_rd_reqe4_e5_q, + l2_cpu0_rd_bypass_way_e5, + l2_cpu0_rd_bypass_bufid_e5, + l2_cpu0_rd_bypass_lrq_id_e5, + + l2_cpu0_wr_arb_fast, + l2_cpu0_wr_id_arb_set, + l2_cpu0_wr_partial_dw_arb_set, + l2_cpu0_wr_cache_attr_arb_set, + l2_cpu0_wr_page_attr_arb_set, + l2_cpu0_wr_elem_size_arb_set, + l2_cpu0_wr_type_arb_set, + l2_cpu0_wr_cl_id_arb_set, + l2_cpu0_wr_priv_arb_set, + l2_cpu0_wr_shared_arb_set, + l2_cpu0_wr_last_arb_set, + l2_cpu0_wr_clean_evict_arb_set, + l2_cpu0_wr_err_arb_set, + l2_cpu0_wr_way_arb_set, + l2_cpu0_wr_dirty_arb_set, + l2_cpu0_wr_1st_replayed_arb_set, + l2_cpu0_wr_addr_arb_set, + l2_cpu0_ic_arb_fast, + l2_cpu0_ic_id_arb_set, + l2_cpu0_ic_write_arb_set, + l2_cpu0_ic_excl_arb_set, + l2_cpu0_ic_elem_size_arb_set, + l2_cpu0_ic_ns_arb_set, + l2_cpu0_ic_addr_arb_set, + l2_cpu0_ic_data_arb_set, + + l2_cpu0_wrq_almost_full, + + l2_cpu0_ls_wr_req_w2a, + l2_cpu0_ls_wr_last_w2a, + l2_cpu0_ls_wr_dirty_w2a, + l2_cpu0_ls_wr_err_w2a, + l2_cpu0_ls_wr_type_w2a, + l2_cpu0_ls_wr_ccb_id_w2a, + l2_cpu0_ls_wr_data_w2a, + + l2_cpu0_ls_ccb_resp, + l2_cpu0_ls_ccb_resp_id, + l2_cpu0_ls_ccb_data_wr, + + l2_cpu0_if_ccb_resp, + l2_cpu0_if_ccb_resp_id, + + l2_cpu0_tw_ccb_resp, + l2_cpu0_tw_ccb_resp_id, + + l2_cpu0_if_sync_done_q, + l2_cpu0_tlb_sync_done_q, + + l2_cpu0_lrq_haz_clr_id_dcd_q, + l2_cpu0_wrq_haz_clr_id_dcd_q, + l2_cpu0_ls_rd_haz_id_arb_q, + l2_cpu0_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + l2_cpu1_idle_wakeup_q, + l2_cpu1_rd_arb_fast, + l2_cpu1_rd_id_arb_set, + l2_cpu1_rd_lrq_id_arb_set, + l2_cpu1_rd_type_arb_set, + l2_cpu1_rd_cache_attr_arb_set, + l2_cpu1_rd_page_attr_arb_set, + l2_cpu1_rd_elem_size_arb_set, + l2_cpu1_rd_way_arb_set, + l2_cpu1_rd_replayed_arb_set, + l2_cpu1_rd_excl_arb_set, + l2_cpu1_rd_priv_arb_set, + l2_cpu1_rd_shared_arb_set, + l2_cpu1_rd_va48_arb_set, + l2_cpu1_rd_aarch64_arb_set, + l2_cpu1_rd_asid_arb_set, + l2_cpu1_rd_prfm_arb_set, + l2_cpu1_rd_addr_arb_set, + l2_cpu1_rd_bypass_arb_set, + l2_cpu1_rd_bypass_req_can_e5, + l2_cpu1_early_rd_reqe4_e5_q, + l2_cpu1_rd_bypass_way_e5, + l2_cpu1_rd_bypass_bufid_e5, + l2_cpu1_rd_bypass_lrq_id_e5, + + l2_cpu1_wr_arb_fast, + l2_cpu1_wr_id_arb_set, + l2_cpu1_wr_partial_dw_arb_set, + l2_cpu1_wr_cache_attr_arb_set, + l2_cpu1_wr_page_attr_arb_set, + l2_cpu1_wr_elem_size_arb_set, + l2_cpu1_wr_type_arb_set, + l2_cpu1_wr_cl_id_arb_set, + l2_cpu1_wr_priv_arb_set, + l2_cpu1_wr_shared_arb_set, + l2_cpu1_wr_last_arb_set, + l2_cpu1_wr_clean_evict_arb_set, + l2_cpu1_wr_err_arb_set, + l2_cpu1_wr_way_arb_set, + l2_cpu1_wr_dirty_arb_set, + l2_cpu1_wr_1st_replayed_arb_set, + l2_cpu1_wr_addr_arb_set, + l2_cpu1_ic_arb_fast, + l2_cpu1_ic_id_arb_set, + l2_cpu1_ic_write_arb_set, + l2_cpu1_ic_excl_arb_set, + l2_cpu1_ic_elem_size_arb_set, + l2_cpu1_ic_ns_arb_set, + l2_cpu1_ic_addr_arb_set, + l2_cpu1_ic_data_arb_set, + + l2_cpu1_wrq_almost_full, + + l2_cpu1_ls_wr_req_w2a, + l2_cpu1_ls_wr_last_w2a, + l2_cpu1_ls_wr_dirty_w2a, + l2_cpu1_ls_wr_err_w2a, + l2_cpu1_ls_wr_type_w2a, + l2_cpu1_ls_wr_ccb_id_w2a, + l2_cpu1_ls_wr_data_w2a, + + l2_cpu1_ls_ccb_resp, + l2_cpu1_ls_ccb_resp_id, + l2_cpu1_ls_ccb_data_wr, + + l2_cpu1_if_ccb_resp, + l2_cpu1_if_ccb_resp_id, + + l2_cpu1_tw_ccb_resp, + l2_cpu1_tw_ccb_resp_id, + + l2_cpu1_if_sync_done_q, + l2_cpu1_tlb_sync_done_q, + + l2_cpu1_lrq_haz_clr_id_dcd_q, + l2_cpu1_wrq_haz_clr_id_dcd_q, + l2_cpu1_ls_rd_haz_id_arb_q, + l2_cpu1_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + l2_cpu2_idle_wakeup_q, + l2_cpu2_rd_arb_fast, + l2_cpu2_rd_id_arb_set, + l2_cpu2_rd_lrq_id_arb_set, + l2_cpu2_rd_type_arb_set, + l2_cpu2_rd_cache_attr_arb_set, + l2_cpu2_rd_page_attr_arb_set, + l2_cpu2_rd_elem_size_arb_set, + l2_cpu2_rd_way_arb_set, + l2_cpu2_rd_replayed_arb_set, + l2_cpu2_rd_excl_arb_set, + l2_cpu2_rd_priv_arb_set, + l2_cpu2_rd_shared_arb_set, + l2_cpu2_rd_va48_arb_set, + l2_cpu2_rd_aarch64_arb_set, + l2_cpu2_rd_asid_arb_set, + l2_cpu2_rd_prfm_arb_set, + l2_cpu2_rd_addr_arb_set, + l2_cpu2_rd_bypass_arb_set, + l2_cpu2_rd_bypass_req_can_e5, + l2_cpu2_early_rd_reqe4_e5_q, + l2_cpu2_rd_bypass_way_e5, + l2_cpu2_rd_bypass_bufid_e5, + l2_cpu2_rd_bypass_lrq_id_e5, + + l2_cpu2_wr_arb_fast, + l2_cpu2_wr_id_arb_set, + l2_cpu2_wr_partial_dw_arb_set, + l2_cpu2_wr_cache_attr_arb_set, + l2_cpu2_wr_page_attr_arb_set, + l2_cpu2_wr_elem_size_arb_set, + l2_cpu2_wr_type_arb_set, + l2_cpu2_wr_cl_id_arb_set, + l2_cpu2_wr_priv_arb_set, + l2_cpu2_wr_shared_arb_set, + l2_cpu2_wr_last_arb_set, + l2_cpu2_wr_clean_evict_arb_set, + l2_cpu2_wr_err_arb_set, + l2_cpu2_wr_way_arb_set, + l2_cpu2_wr_dirty_arb_set, + l2_cpu2_wr_1st_replayed_arb_set, + l2_cpu2_wr_addr_arb_set, + l2_cpu2_ic_arb_fast, + l2_cpu2_ic_id_arb_set, + l2_cpu2_ic_write_arb_set, + l2_cpu2_ic_excl_arb_set, + l2_cpu2_ic_elem_size_arb_set, + l2_cpu2_ic_ns_arb_set, + l2_cpu2_ic_addr_arb_set, + l2_cpu2_ic_data_arb_set, + + l2_cpu2_wrq_almost_full, + + l2_cpu2_ls_wr_req_w2a, + l2_cpu2_ls_wr_last_w2a, + l2_cpu2_ls_wr_dirty_w2a, + l2_cpu2_ls_wr_err_w2a, + l2_cpu2_ls_wr_type_w2a, + l2_cpu2_ls_wr_ccb_id_w2a, + l2_cpu2_ls_wr_data_w2a, + + l2_cpu2_ls_ccb_resp, + l2_cpu2_ls_ccb_resp_id, + l2_cpu2_ls_ccb_data_wr, + + l2_cpu2_if_ccb_resp, + l2_cpu2_if_ccb_resp_id, + + l2_cpu2_tw_ccb_resp, + l2_cpu2_tw_ccb_resp_id, + + l2_cpu2_if_sync_done_q, + l2_cpu2_tlb_sync_done_q, + + l2_cpu2_lrq_haz_clr_id_dcd_q, + l2_cpu2_wrq_haz_clr_id_dcd_q, + l2_cpu2_ls_rd_haz_id_arb_q, + l2_cpu2_ls_wr_haz_id_arb_q, + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + l2_cpu3_idle_wakeup_q, + l2_cpu3_rd_arb_fast, + l2_cpu3_rd_id_arb_set, + l2_cpu3_rd_lrq_id_arb_set, + l2_cpu3_rd_type_arb_set, + l2_cpu3_rd_cache_attr_arb_set, + l2_cpu3_rd_page_attr_arb_set, + l2_cpu3_rd_elem_size_arb_set, + l2_cpu3_rd_way_arb_set, + l2_cpu3_rd_replayed_arb_set, + l2_cpu3_rd_excl_arb_set, + l2_cpu3_rd_priv_arb_set, + l2_cpu3_rd_shared_arb_set, + l2_cpu3_rd_va48_arb_set, + l2_cpu3_rd_aarch64_arb_set, + l2_cpu3_rd_asid_arb_set, + l2_cpu3_rd_prfm_arb_set, + l2_cpu3_rd_addr_arb_set, + l2_cpu3_rd_bypass_arb_set, + l2_cpu3_rd_bypass_req_can_e5, + l2_cpu3_early_rd_reqe4_e5_q, + l2_cpu3_rd_bypass_way_e5, + l2_cpu3_rd_bypass_bufid_e5, + l2_cpu3_rd_bypass_lrq_id_e5, + + l2_cpu3_wr_arb_fast, + l2_cpu3_wr_id_arb_set, + l2_cpu3_wr_partial_dw_arb_set, + l2_cpu3_wr_cache_attr_arb_set, + l2_cpu3_wr_page_attr_arb_set, + l2_cpu3_wr_elem_size_arb_set, + l2_cpu3_wr_type_arb_set, + l2_cpu3_wr_cl_id_arb_set, + l2_cpu3_wr_priv_arb_set, + l2_cpu3_wr_shared_arb_set, + l2_cpu3_wr_last_arb_set, + l2_cpu3_wr_clean_evict_arb_set, + l2_cpu3_wr_err_arb_set, + l2_cpu3_wr_way_arb_set, + l2_cpu3_wr_dirty_arb_set, + l2_cpu3_wr_1st_replayed_arb_set, + l2_cpu3_wr_addr_arb_set, + l2_cpu3_ic_arb_fast, + l2_cpu3_ic_id_arb_set, + l2_cpu3_ic_write_arb_set, + l2_cpu3_ic_excl_arb_set, + l2_cpu3_ic_elem_size_arb_set, + l2_cpu3_ic_ns_arb_set, + l2_cpu3_ic_addr_arb_set, + l2_cpu3_ic_data_arb_set, + + l2_cpu3_wrq_almost_full, + + l2_cpu3_ls_wr_req_w2a, + l2_cpu3_ls_wr_last_w2a, + l2_cpu3_ls_wr_dirty_w2a, + l2_cpu3_ls_wr_err_w2a, + l2_cpu3_ls_wr_type_w2a, + l2_cpu3_ls_wr_ccb_id_w2a, + l2_cpu3_ls_wr_data_w2a, + + l2_cpu3_ls_ccb_resp, + l2_cpu3_ls_ccb_resp_id, + l2_cpu3_ls_ccb_data_wr, + + l2_cpu3_if_ccb_resp, + l2_cpu3_if_ccb_resp_id, + + l2_cpu3_tw_ccb_resp, + l2_cpu3_tw_ccb_resp_id, + + l2_cpu3_if_sync_done_q, + l2_cpu3_tlb_sync_done_q, + + l2_cpu3_lrq_haz_clr_id_dcd_q, + l2_cpu3_wrq_haz_clr_id_dcd_q, + l2_cpu3_ls_rd_haz_id_arb_q, + l2_cpu3_ls_wr_haz_id_arb_q, + +// END L2-CPU interface + +//------------------------------------------------------------------- +// TM interface +//------------------------------------------------------------------- +// BEGIN TIMER-CPU interface + tm_cpu0_cntkctl_usr, + tm_cpu0_cnthctl_kernel, + + tm_cpu1_cntkctl_usr, + tm_cpu1_cnthctl_kernel, + + tm_cpu2_cntkctl_usr, + tm_cpu2_cnthctl_kernel, + + tm_cpu3_cntkctl_usr, + tm_cpu3_cnthctl_kernel, +// END TIMER-CPU interface + +//----------------------------------------------------------------------------- +// IC interface +//----------------------------------------------------------------------------- + ls_cpu0_imp_abort_slv, + ls_cpu0_imp_abort_ecc, + ls_cpu0_imp_abort_dec, + ls_cpu0_imp_abort_containable, + ls_cpu0_raw_eae_nonsec, + ls_cpu0_raw_eae_secure, + + ds_cpu0_ic_cpsr_mode, + ds_cpu0_ic_sample_spr, + ds_cpu0_ic_aa64naa32, + ds_cpu0_ic_hcr_change, + ds_cpu0_ic_scr_change, +// BEGIN INCLUDE FOR CPU1 + ds_cpu1_ic_cpsr_mode, + ds_cpu1_ic_sample_spr, + ds_cpu1_ic_aa64naa32, + ds_cpu1_ic_hcr_change, + ds_cpu1_ic_scr_change, + ls_cpu1_imp_abort_slv, + ls_cpu1_imp_abort_ecc, + ls_cpu1_imp_abort_dec, + ls_cpu1_imp_abort_containable, + ls_cpu1_raw_eae_nonsec, + ls_cpu1_raw_eae_secure, +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + ds_cpu2_ic_cpsr_mode, + ds_cpu2_ic_sample_spr, + ds_cpu2_ic_aa64naa32, + ds_cpu2_ic_hcr_change, + ds_cpu2_ic_scr_change, + ls_cpu2_imp_abort_slv, + ls_cpu2_imp_abort_ecc, + ls_cpu2_imp_abort_dec, + ls_cpu2_imp_abort_containable, + ls_cpu2_raw_eae_nonsec, + ls_cpu2_raw_eae_secure, +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + ds_cpu3_ic_cpsr_mode, + ds_cpu3_ic_sample_spr, + ds_cpu3_ic_aa64naa32, + ds_cpu3_ic_hcr_change, + ds_cpu3_ic_scr_change, + ls_cpu3_imp_abort_slv, + ls_cpu3_imp_abort_ecc, + ls_cpu3_imp_abort_dec, + ls_cpu3_imp_abort_containable, + ls_cpu3_raw_eae_nonsec, + ls_cpu3_raw_eae_secure, +// END INCLUDE FOR CPU3 + + ic_nfiq, + ic_nirq, + ic_nsei, + ic_nvfiq, + ic_nvirq, + ic_nvsei, + ic_p_valid, + + ic_sample_spr, + ic_hcr_change_complete, + ic_scr_change_complete, + ic_el_change_complete, + ic_ich_el2_tc, + ic_ich_el2_tall0, + ic_ich_el2_tall1, + ic_sra_el3_en, + ic_sra_el1s_en, + ic_sra_el2_en, + ic_sra_el1ns_en, + ic_sre_el1ns_hyp_trap, + ic_sre_el1ns_mon_trap, + ic_sre_el1s_mon_trap, + ic_sre_el2_mon_trap, + ic_block_eoi_sgi_wr, + +//----------------------------------------------------------------------------- +// DT interface +//----------------------------------------------------------------------------- +// BEGIN DT-CPU interface +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + dt_cpu0_et_oslock_gclk, + dt_cpu0_os_double_lock_gclk, + dt_cpu0_halt_ack_gclk, + dt_cpu0_coredbg_in_reset_gclk, + dt_cpu0_wfx_dbg_req_gclk, + dt_cpu0_hlt_dbgevt_ok_gclk, + dt_cpu0_dbif_ack_gclk, + dt_cpu0_dbif_err_gclk, + dt_cpu0_dbif_rddata_gclk, + + dt_cpu0_dbif_addr_pclk, + dt_cpu0_dbif_locked_pclk, + dt_cpu0_dbif_req_pclk, + dt_cpu0_dbif_wrdata_pclk, + dt_cpu0_dbif_write_pclk, + dt_cpu0_edecr_osuce_pclk, + dt_cpu0_edecr_rce_pclk, + dt_cpu0_edecr_ss_pclk, + dt_cpu0_edbgrq_pclk, + dt_cpu0_edacr_frc_idleack_pclk, + dt_cpu0_edprcr_corepurq_pclk, + + dt_cpu0_pmusnapshot_ack_gclk, + dt_cpu0_pmusnapshot_req_pclk, + + dt_cpu0_cti_trigin_7to4_gclk, + dt_cpu0_cti_trigin_1to0_gclk, + dt_cpu0_cti_trigoutack_7to4_gclk, + dt_cpu0_cti_trigoutack_bit1_gclk, + + dt_cpu0_cti_trigout_7to4_pclk, + dt_cpu0_cti_trigout_1to0_pclk, + dt_cpu0_cti_triginack_7to4_pclk, + dt_cpu0_cti_triginack_1to0_pclk, + + dt_cpu0_wfx_wakeup_pclk, + dt_cpu0_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + dt_cpu1_et_oslock_gclk, + dt_cpu1_os_double_lock_gclk, + dt_cpu1_halt_ack_gclk, + dt_cpu1_coredbg_in_reset_gclk, + dt_cpu1_wfx_dbg_req_gclk, + dt_cpu1_hlt_dbgevt_ok_gclk, + dt_cpu1_dbif_ack_gclk, + dt_cpu1_dbif_err_gclk, + dt_cpu1_dbif_rddata_gclk, + + dt_cpu1_dbif_addr_pclk, + dt_cpu1_dbif_locked_pclk, + dt_cpu1_dbif_req_pclk, + dt_cpu1_dbif_wrdata_pclk, + dt_cpu1_dbif_write_pclk, + dt_cpu1_edecr_osuce_pclk, + dt_cpu1_edecr_rce_pclk, + dt_cpu1_edecr_ss_pclk, + dt_cpu1_edbgrq_pclk, + dt_cpu1_edacr_frc_idleack_pclk, + dt_cpu1_edprcr_corepurq_pclk, + + dt_cpu1_pmusnapshot_ack_gclk, + dt_cpu1_pmusnapshot_req_pclk, + + dt_cpu1_cti_trigin_7to4_gclk, + dt_cpu1_cti_trigin_1to0_gclk, + dt_cpu1_cti_trigoutack_7to4_gclk, + dt_cpu1_cti_trigoutack_bit1_gclk, + + dt_cpu1_cti_trigout_7to4_pclk, + dt_cpu1_cti_trigout_1to0_pclk, + dt_cpu1_cti_triginack_7to4_pclk, + dt_cpu1_cti_triginack_1to0_pclk, + + dt_cpu1_wfx_wakeup_pclk, + dt_cpu1_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + dt_cpu2_et_oslock_gclk, + dt_cpu2_os_double_lock_gclk, + dt_cpu2_halt_ack_gclk, + dt_cpu2_coredbg_in_reset_gclk, + dt_cpu2_wfx_dbg_req_gclk, + dt_cpu2_hlt_dbgevt_ok_gclk, + dt_cpu2_dbif_ack_gclk, + dt_cpu2_dbif_err_gclk, + dt_cpu2_dbif_rddata_gclk, + + dt_cpu2_dbif_addr_pclk, + dt_cpu2_dbif_locked_pclk, + dt_cpu2_dbif_req_pclk, + dt_cpu2_dbif_wrdata_pclk, + dt_cpu2_dbif_write_pclk, + dt_cpu2_edecr_osuce_pclk, + dt_cpu2_edecr_rce_pclk, + dt_cpu2_edecr_ss_pclk, + dt_cpu2_edbgrq_pclk, + dt_cpu2_edacr_frc_idleack_pclk, + dt_cpu2_edprcr_corepurq_pclk, + + dt_cpu2_pmusnapshot_ack_gclk, + dt_cpu2_pmusnapshot_req_pclk, + + dt_cpu2_cti_trigin_7to4_gclk, + dt_cpu2_cti_trigin_1to0_gclk, + dt_cpu2_cti_trigoutack_7to4_gclk, + dt_cpu2_cti_trigoutack_bit1_gclk, + + dt_cpu2_cti_trigout_7to4_pclk, + dt_cpu2_cti_trigout_1to0_pclk, + dt_cpu2_cti_triginack_7to4_pclk, + dt_cpu2_cti_triginack_1to0_pclk, + + dt_cpu2_wfx_wakeup_pclk, + dt_cpu2_noclkstop_pclk, +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + dt_cpu3_et_oslock_gclk, + dt_cpu3_os_double_lock_gclk, + dt_cpu3_halt_ack_gclk, + dt_cpu3_coredbg_in_reset_gclk, + dt_cpu3_wfx_dbg_req_gclk, + dt_cpu3_hlt_dbgevt_ok_gclk, + dt_cpu3_dbif_ack_gclk, + dt_cpu3_dbif_err_gclk, + dt_cpu3_dbif_rddata_gclk, + + dt_cpu3_dbif_addr_pclk, + dt_cpu3_dbif_locked_pclk, + dt_cpu3_dbif_req_pclk, + dt_cpu3_dbif_wrdata_pclk, + dt_cpu3_dbif_write_pclk, + dt_cpu3_edecr_osuce_pclk, + dt_cpu3_edecr_rce_pclk, + dt_cpu3_edecr_ss_pclk, + dt_cpu3_edbgrq_pclk, + dt_cpu3_edacr_frc_idleack_pclk, + dt_cpu3_edprcr_corepurq_pclk, + + dt_cpu3_pmusnapshot_ack_gclk, + dt_cpu3_pmusnapshot_req_pclk, + + dt_cpu3_cti_trigin_7to4_gclk, + dt_cpu3_cti_trigin_1to0_gclk, + dt_cpu3_cti_trigoutack_7to4_gclk, + dt_cpu3_cti_trigoutack_bit1_gclk, + + dt_cpu3_cti_trigout_7to4_pclk, + dt_cpu3_cti_trigout_1to0_pclk, + dt_cpu3_cti_triginack_7to4_pclk, + dt_cpu3_cti_triginack_1to0_pclk, + + dt_cpu3_wfx_wakeup_pclk, + dt_cpu3_noclkstop_pclk, +// END DT-CPU interface + +//----------------------------------------------------------------------------- +// CK interface +//----------------------------------------------------------------------------- +// BEGIN CK-CPU interface + ds_cpu0_reset_req, + ds_cpu0_wfi_req, + ds_cpu0_wfe_req, + ds_cpu0_flush, + ds_cpu0_flush_type, + ds_cpu0_imp_abrt_wfi_qual, + ds_cpu0_irq_wfi_qual, + ds_cpu0_fiq_wfi_qual, + ds_cpu0_vimp_abrt_wfi_qual, + ds_cpu0_virq_wfi_qual, + ds_cpu0_vfiq_wfi_qual, + ds_cpu0_imp_abrt_wfe_qual, + ds_cpu0_irq_wfe_qual, + ds_cpu0_fiq_wfe_qual, + ds_cpu0_vimp_abrt_wfe_qual, + ds_cpu0_virq_wfe_qual, + ds_cpu0_vfiq_wfe_qual, + ds_cpu0_hcr_va, + ds_cpu0_hcr_vi, + ds_cpu0_hcr_vf, + ds_cpu0_cpuectlr_ret, + ck_cpu0_event_reg, + ck_cpu0_wfi_ack, + ck_cpu0_wfe_ack, + ck_cpu0_crcx_clk_en_n, + + ds_cpu1_reset_req, + ds_cpu1_wfi_req, + ds_cpu1_wfe_req, + ds_cpu1_flush, + ds_cpu1_flush_type, + ds_cpu1_imp_abrt_wfi_qual, + ds_cpu1_irq_wfi_qual, + ds_cpu1_fiq_wfi_qual, + ds_cpu1_vimp_abrt_wfi_qual, + ds_cpu1_virq_wfi_qual, + ds_cpu1_vfiq_wfi_qual, + ds_cpu1_imp_abrt_wfe_qual, + ds_cpu1_irq_wfe_qual, + ds_cpu1_fiq_wfe_qual, + ds_cpu1_vimp_abrt_wfe_qual, + ds_cpu1_virq_wfe_qual, + ds_cpu1_vfiq_wfe_qual, + ds_cpu1_hcr_va, + ds_cpu1_hcr_vi, + ds_cpu1_hcr_vf, + ds_cpu1_cpuectlr_ret, + ck_cpu1_event_reg, + ck_cpu1_wfi_ack, + ck_cpu1_wfe_ack, + ck_cpu1_crcx_clk_en_n, + + ds_cpu2_reset_req, + ds_cpu2_wfi_req, + ds_cpu2_wfe_req, + ds_cpu2_flush, + ds_cpu2_flush_type, + ds_cpu2_imp_abrt_wfi_qual, + ds_cpu2_irq_wfi_qual, + ds_cpu2_fiq_wfi_qual, + ds_cpu2_vimp_abrt_wfi_qual, + ds_cpu2_virq_wfi_qual, + ds_cpu2_vfiq_wfi_qual, + ds_cpu2_imp_abrt_wfe_qual, + ds_cpu2_irq_wfe_qual, + ds_cpu2_fiq_wfe_qual, + ds_cpu2_vimp_abrt_wfe_qual, + ds_cpu2_virq_wfe_qual, + ds_cpu2_vfiq_wfe_qual, + ds_cpu2_hcr_va, + ds_cpu2_hcr_vi, + ds_cpu2_hcr_vf, + ds_cpu2_cpuectlr_ret, + ck_cpu2_event_reg, + ck_cpu2_wfi_ack, + ck_cpu2_wfe_ack, + ck_cpu2_crcx_clk_en_n, + + ds_cpu3_reset_req, + ds_cpu3_wfi_req, + ds_cpu3_wfe_req, + ds_cpu3_flush, + ds_cpu3_flush_type, + ds_cpu3_imp_abrt_wfi_qual, + ds_cpu3_irq_wfi_qual, + ds_cpu3_fiq_wfi_qual, + ds_cpu3_vimp_abrt_wfi_qual, + ds_cpu3_virq_wfi_qual, + ds_cpu3_vfiq_wfi_qual, + ds_cpu3_imp_abrt_wfe_qual, + ds_cpu3_irq_wfe_qual, + ds_cpu3_fiq_wfe_qual, + ds_cpu3_vimp_abrt_wfe_qual, + ds_cpu3_virq_wfe_qual, + ds_cpu3_vfiq_wfe_qual, + ds_cpu3_hcr_va, + ds_cpu3_hcr_vi, + ds_cpu3_hcr_vf, + ds_cpu3_cpuectlr_ret, + ck_cpu3_event_reg, + ck_cpu3_wfi_ack, + ck_cpu3_wfe_ack, + ck_cpu3_crcx_clk_en_n, + + ls_cpu0_clrexmon, + ls_cpu1_clrexmon, + ls_cpu2_clrexmon, + ls_cpu3_clrexmon, +// END CK-CPU interface + + ck_gclkt +); + +//# +//# Interface Signals +//# ================= +//# + +//----------------------------------------------------------------------------- +// Clock and Reset Signals +//----------------------------------------------------------------------------- + input CLK; // Fast Clock + input CLKEN; // Fast Clock Enable + + input [`MAIA_CN:0] nCPUPORESET; // CPU Power-on reset + input [`MAIA_CN:0] nCORERESET; // CPU reset (excluding DBG & ETM) + input nL2RESET; // L2 reset + input L2RSTDISABLE; // L2 RAMs hardware reset disable + output [`MAIA_CN:0] WARMRSTREQ; // CPU Warm reset request +//See also nPRESETDBG; // Debug APB reset (PCLK) + +//----------------------------------------------------------------------------- +// Static Configuration Signals +//----------------------------------------------------------------------------- +// Static configuration signals that should be tied off and not change dynamically. +// Many of the initial values specified by these inputs +// may be overridden in software using CP15 registers. + + input [`MAIA_CN:0] CFGEND; // Endianness EE bit (1:big endian) + input [`MAIA_CN:0] VINITHI; // 1: start up using high vectors + input [`MAIA_CN:0] CFGTE; // Exception handling state (0:ARM/1:Thumb) + input [`MAIA_CN:0] CP15SDISABLE; // Disable write access to some secure CP15 registers + + input [7:0] CLUSTERIDAFF1; // Value read in ClusterID Affinity1 field, MPIDR bits[15:8] + input [7:0] CLUSTERIDAFF2; // Value read in ClusterID Affinity2 field, MPIDR bits[23:16] + + input [`MAIA_CN:0] AA64nAA32; // Register Width (1:AArch64/0:AArch32) + input [43:2] RVBARADDR0; // RVBAR address +// BEGIN INCLUDE FOR CPU1 + input [43:2] RVBARADDR1; // RVBAR address +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input [43:2] RVBARADDR2; // RVBAR address +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input [43:2] RVBARADDR3; // RVBAR address +// END INCLUDE FOR CPU3 + input [`MAIA_CN:0] CRYPTODISABLE; // Disable Cryptography Extension + +//----------------------------------------------------------------------------- +// Interrupt Controller Signals +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] nFIQ; // Fast Interrupt request + input [`MAIA_CN:0] nIRQ; // Interrupt request + input [`MAIA_CN:0] nSEI; // System Error Interrupt + input [`MAIA_CN:0] nREI; // RAM Error Interrupt + input [`MAIA_CN:0] nVFIQ; // Virtual Fast Interrupt request + input [`MAIA_CN:0] nVIRQ; // Virtual Interrupt request + input [`MAIA_CN:0] nVSEI; // Virtual System Error Interrupt + +// BEGIN NO-GIC pins + output [`MAIA_CN:0] nVCPUMNTIRQ; // Virtual Maintenance Interrupt output +// END NO-GIC pins + + input [43:18] PERIPHBASE; // Base address for IC memory-mapped registers +// BEGIN NO-GIC pins + input GICCDISABLE; // Put GIC into bypass mode + + input ICDTVALID; // Distrubuter AXI4 SP Message Valid + output ICDTREADY; // GIC Ready for Distrubuter AXI4 SP Message + input [15:0] ICDTDATA; // Distrubuter AXI4 SP Message Data + input ICDTLAST; // Distrubuter AXI4 SP Message Last Packet + input [1:0] ICDTDEST; // Distrubuter AXI4 SP Message CPU ID + + output ICCTVALID; // GIC to Distributer AXI4 SP Message Valid + input ICCTREADY; // Distributer Ready for GIC AXI4 SP Message + output [15:0] ICCTDATA; // GIC to Distributer AXI4 SP Message Data + output ICCTLAST; // GIC to Distributer AXI4 SP Message Last Packet + output [1:0] ICCTID; // GIC to Distributer AXI4 SP Message CPU ID +// END NO-GIC pins + +//----------------------------------------------------------------------------- +// Timer Signals +//----------------------------------------------------------------------------- + input [63:0] CNTVALUEB; // Counter value in binary + input CNTCLKEN; // Counter clock enable + output [`MAIA_CN:0] nCNTPNSIRQ; // NS Physical Timer event + output [`MAIA_CN:0] nCNTPSIRQ; // S Physical Timer event + output [`MAIA_CN:0] nCNTVIRQ; // Virtual Timer event + output [`MAIA_CN:0] nCNTHPIRQ; // Hyp Physical Timer event + +//----------------------------------------------------------------------------- +// Power Management Signals +//----------------------------------------------------------------------------- + input CLREXMONREQ; // Clearing of external global exclusive monitor (REQ) + output CLREXMONACK; // Clearing of external global exclusive monitor (ACK) + input EVENTI; // Event input for processor wake-up from WFE state + output EVENTO; // Event output, signal is active when SEV instruction is executed + output [`MAIA_CN:0] STANDBYWFI; // WFI mode + output [`MAIA_CN:0] STANDBYWFE; // WFE mode + output STANDBYWFIL2; // WFI mode for L2 + output [`MAIA_CN:0] SMPEN; // CPU SMP bit + + output [`MAIA_CN:0] CPUQACTIVE; // CPU Q-channel QACTIVE + input [`MAIA_CN:0] CPUQREQn; // CPU Q-channel QREQn + output [`MAIA_CN:0] CPUQACCEPTn; // CPU Q-channel QACCEPTn + output [`MAIA_CN:0] CPUQDENY; // CPU Q-channel QDENY + + output L2QACTIVE; // L2 Q-channel QACTIVE + input L2QREQn; // L2 Q-channel QREQn + output L2QACCEPTn; // L2 Q-channel QACCEPTn + output L2QDENY; // L2 Q-channel QDENY + + input L2FLUSHREQ; // L2 hardware flush request + output L2FLUSHDONE; // L2 hardware flush done + +//----------------------------------------------------------------------------- +// Asynchronous Error Signals +//----------------------------------------------------------------------------- + output nINTERRIRQ; // L2 RAM dbl-bit ECC error + output nEXTERRIRQ; // Write transaction error + +//----------------------------------------------------------------------------- +// Bus Configuration Signals +//----------------------------------------------------------------------------- + input SYSBARDISABLE; // Disable broadcast of barriers + input BROADCASTINNER; // Extend Inner Shared Domain + input BROADCASTOUTER; // Extend Outer Shared Domain + input BROADCASTCACHEMAINT; // Broadcast cache maint ops + +//----------------------------------------------------------------------------- +// Skyros RN-F Interface +//----------------------------------------------------------------------------- + input SCLKEN; // Skyros clock enable + input SINACT; // Skyros snoop inactive + + input [6:0] NODEID; // Skyros requestor NodeID + + output TXSACTIVE; // Skyros active - indicates pending activity on pins + input RXSACTIVE; // Skyros active - indicates pending activity on pins + + output TXLINKACTIVEREQ; // Skyros transmit link active request + input TXLINKACTIVEACK; // SKyros transmit link active acknowledge + + input RXLINKACTIVEREQ; // SKyros receive link active request + output RXLINKACTIVEACK; // Skyros receive link active acknowledge + +// TXREQ - outbound requests + output TXREQFLITPEND; // Skyros TXREQ FLIT pending + output TXREQFLITV; // Skyros TXREQ FLIT valid + output [99:0] TXREQFLIT; // Skyros TXREQ FLIT payload + output [7:0] REQMEMATTR; // Skyros TXREQ raw memory attributes + input TXREQLCRDV; // Skyros TXREQ link-layer credit valid + +// TXRSP - outbound response + output TXRSPFLITPEND; // Skyros TXRSP FLIT pending + output TXRSPFLITV; // Skyros TXRSP FLIT valid + output [44:0] TXRSPFLIT; // Skyros TXRSP FLIT payload + input TXRSPLCRDV; // Skyros TXRSP link-layer credit valid + +// TXDAT - outbound data + output TXDATFLITPEND; // Skyros TXDAT FLIT pending + output TXDATFLITV; // Skyros TXDAT FLIT valid + output [193:0] TXDATFLIT; // Skyros TXDAT FLIT payload + input TXDATLCRDV; // Skyros TXDAT link-layer credit valid + +// RXSNP - inbound snoops + input RXSNPFLITPEND; // Skyros RXSNP FLIT pending + input RXSNPFLITV; // Skyros RXSNP FLIT valid + input [64:0] RXSNPFLIT; // Skyros RXSNP FLIT payload + output RXSNPLCRDV; // Skyros RXSNP link-layer credit valid + +// RXRSP - inbound response + input RXRSPFLITPEND; // Skyros RXRSP FLIT pending + input RXRSPFLITV; // Skyros RXRSP FLIT valid + input [44:0] RXRSPFLIT; // Skyros RXRSP FLIT payload + output RXRSPLCRDV; // Skyros RXRSP link-layer credit valid + +// RXDAT - inbound data + input RXDATFLITPEND; // Skyros RXDAT FLIT pending + input RXDATFLITV; // Skyros RXDAT FLIT valid + input [193:0] RXDATFLIT; // Skyros RXDAT FLIT payload + output RXDATLCRDV; // Skyros RXDAT link-layer credit valid + + input [43:24] SAMMNBASE; // Skyros SAM MN base address + input [1:0] SAMADDRMAP0; // Skyros SAM address region 0 mapping + input [1:0] SAMADDRMAP1; // Skyros SAM address region 1 mapping + input [1:0] SAMADDRMAP2; // Skyros SAM address region 2 mapping + input [1:0] SAMADDRMAP3; // Skyros SAM address region 3 mapping + input [1:0] SAMADDRMAP4; // Skyros SAM address region 4 mapping + input [1:0] SAMADDRMAP5; // Skyros SAM address region 5 mapping + input [1:0] SAMADDRMAP6; // Skyros SAM address region 6 mapping + input [1:0] SAMADDRMAP7; // Skyros SAM address region 7 mapping + input [1:0] SAMADDRMAP8; // Skyros SAM address region 8 mapping + input [1:0] SAMADDRMAP9; // Skyros SAM address region 9 mapping + input [1:0] SAMADDRMAP10; // Skyros SAM address region 10 mapping + input [1:0] SAMADDRMAP11; // Skyros SAM address region 11 mapping + input [1:0] SAMADDRMAP12; // Skyros SAM address region 12 mapping + input [1:0] SAMADDRMAP13; // Skyros SAM address region 13 mapping + input [1:0] SAMADDRMAP14; // Skyros SAM address region 14 mapping + input [1:0] SAMADDRMAP15; // Skyros SAM address region 15 mapping + input [1:0] SAMADDRMAP16; // Skyros SAM address region 16 mapping + input [1:0] SAMADDRMAP17; // Skyros SAM address region 17 mapping + input [1:0] SAMADDRMAP18; // Skyros SAM address region 18 mapping + input [1:0] SAMADDRMAP19; // Skyros SAM address region 19 mapping + input [6:0] SAMMNNODEID; // Skyros SAM MN target ID + input [6:0] SAMHNI0NODEID; // Skyros SAM HNI0 target ID + input [6:0] SAMHNI1NODEID; // Skyros SAM HNI1 target ID + input [6:0] SAMHNF0NODEID; // Skyros SAM HNF0 target ID + input [6:0] SAMHNF1NODEID; // Skyros SAM HNF1 target ID + input [6:0] SAMHNF2NODEID; // Skyros SAM HNF2 target ID + input [6:0] SAMHNF3NODEID; // Skyros SAM HNF3 target ID + input [6:0] SAMHNF4NODEID; // Skyros SAM HNF4 target ID + input [6:0] SAMHNF5NODEID; // Skyros SAM HNF5 target ID + input [6:0] SAMHNF6NODEID; // Skyros SAM HNF6 target ID + input [6:0] SAMHNF7NODEID; // Skyros SAM HNF7 target ID + input [2:0] SAMHNFMODE; // Skyros SAM HNF interleaving mode + +// BEGIN NO-ACP pins +//----------------------------------------------------------------------------- +// ACP AXI Slave +//----------------------------------------------------------------------------- + input ACLKENS; // AXI slave clock enable + input AINACTS; // AXI slave interface no longer active or accepting requests +// Write Address channel signals + output AWREADYS; // Write Address ready (slave ready to accept write address) + input AWVALIDS; // Write Address valid + input [4:0] AWIDS; // Write Address ID + input [43:0] AWADDRS; // Write Address + input [7:0] AWLENS; // Write Burst Length + input [3:0] AWCACHES; // Write Cache type + input [1:0] AWUSERS; // Write inner & outer shareability + input [2:0] AWPROTS; // Write Protection type + +// Write Data channel signals + output WREADYS; // Write Data ready (slave ready to accept data) + input WVALIDS; // Write Data valid + input [127:0] WDATAS; // Write Data + input [15:0] WSTRBS; // Write byte-lane strobes + input WLASTS; // Write Data last transfer indicator + +// Write Response channel signals + input BREADYS; // Write Response ready (master ready to accept response) + output BVALIDS; // Write Response Valid + output [4:0] BIDS; // Write Response ID tag + output [1:0] BRESPS; // Write Response + +// Read Address channel signals + output ARREADYS; // Read Address ready (slave ready to accept read address) + input ARVALIDS; // Read Address valid + input [4:0] ARIDS; // Read Address ID + input [43:0] ARADDRS; // Read Address + input [7:0] ARLENS; // Read Burst Length + input [3:0] ARCACHES; // Read Cache type + input [1:0] ARUSERS; // Read inner & outer shareability + input [2:0] ARPROTS; // Read Protection type + +// Read Data channel signals + input RREADYS; // Read Data ready (master ready to accept data) + output RVALIDS; // Read Data valid + output [4:0] RIDS; // Read Data ID + output [127:0] RDATAS; // Read Data + output [1:0] RRESPS; // Read Data response + output RLASTS; // Read Data last transfer indicator +// END NO-ACP pins + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (CLK) +//----------------------------------------------------------------------------- +// Debug CLK interface + input [43:12] DBGROMADDR; // Debug ROM base address + input DBGROMADDRV; // Debug ROM base address valid + + output [`MAIA_CN:0] DBGACK; // Debug acknowledge + output [`MAIA_CN:0] nCOMMIRQ; // Comms channel receive/transmit interrupt + output [`MAIA_CN:0] COMMRX; // Comms channel receive + output [`MAIA_CN:0] COMMTX; // Comms channel transmit + + output [`MAIA_CN:0] DBGRSTREQ; // Warm reset request + output [`MAIA_CN:0] DBGNOPWRDWN; // No power-down request + + input DBGL1RSTDISABLE; // L1 DCache hardware reset disable + +// PMU CLK interface + output [`MAIA_CN:0] nPMUIRQ; // PMU IRQ request + output [24:0] PMUEVENT0; // PMU Event bus +// BEGIN INCLUDE FOR CPU1 + output [24:0] PMUEVENT1; // PMU Event bus +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + output [24:0] PMUEVENT2; // PMU Event bus +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + output [24:0] PMUEVENT3; // PMU Event bus +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (ATCLK) +//----------------------------------------------------------------------------- +// ETM ATB interface and Misc signals + input ATCLKEN; // ATB Clock Enable + input [63:0] TSVALUEB; // ATB Timestamp in binary + + input ATREADYM0; // ATDATA can be accepted + input AFVALIDM0; // ATB Fifo Flush Request + output [31:0] ATDATAM0; // ATB Data + output ATVALIDM0; // ATB Data Valid + output [1:0] ATBYTESM0; // ATB Data Size + output AFREADYM0; // ATB Fifo Flush Finished + output [6:0] ATIDM0; // ATB Trace Source ID + input SYNCREQM0; // ATB External synchronization request + +// BEGIN INCLUDE FOR CPU1 + input ATREADYM1; // ATDATA can be accepted + input AFVALIDM1; // ATB Fifo Flush Request + output [31:0] ATDATAM1; // ATB Data + output ATVALIDM1; // ATB Data Valid + output [1:0] ATBYTESM1; // ATB Data Size + output AFREADYM1; // ATB Fifo Flush Finished + output [6:0] ATIDM1; // ATB Trace Source ID + input SYNCREQM1; // ATB External synchronization request +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ATREADYM2; // ATDATA can be accepted + input AFVALIDM2; // ATB Fifo Flush Request + output [31:0] ATDATAM2; // ATB Data + output ATVALIDM2; // ATB Data Valid + output [1:0] ATBYTESM2; // ATB Data Size + output AFREADYM2; // ATB Fifo Flush Finished + output [6:0] ATIDM2; // ATB Trace Source ID + input SYNCREQM2; // ATB External synchronization request +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ATREADYM3; // ATDATA can be accepted + input AFVALIDM3; // ATB Fifo Flush Request + output [31:0] ATDATAM3; // ATB Data + output ATVALIDM3; // ATB Data Valid + output [1:0] ATBYTESM3; // ATB Data Size + output AFREADYM3; // ATB Fifo Flush Finished + output [6:0] ATIDM3; // ATB Trace Source ID + input SYNCREQM3; // ATB External synchronization request +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Debug/ETM/PMU Interface (PCLK) +//----------------------------------------------------------------------------- +// Debug-APBv3 port (APB) + input PCLKDBG; // APB Clock + input PCLKENDBG; // APB Clock Enable + input nPRESETDBG; // APB Reset + input PSELDBG; // Debug bus access + input [21:2] PADDRDBG; // APB address + input PADDRDBG31; // APB address bit[31] + input PENABLEDBG; // APB transfer complete flag + input PWRITEDBG; // APB read/write indicator + input [31:0] PWDATADBG; // APB write data + output [31:0] PRDATADBG; // APB read data + output PREADYDBG; // APB slave ready, used to extend a transfer + output PSLVERRDBG; // APB slave transfer error + +// Misc interface + input [`MAIA_CN:0] EDBGRQ; // External debug request + +// PMU Snapshot interface + input [`MAIA_CN:0] PMUSNAPSHOTREQ; // PMU snapshot trigger request + output [`MAIA_CN:0] PMUSNAPSHOTACK; // PMU snapshot trigger acknowledge + +// Power-related interface + input [`MAIA_CN:0] DBGPWRDUP; // Processor power-up status + output [`MAIA_CN:0] DBGPWRUPREQ; // Processor power-up request + +// CTI interface + input [3:0] CTICHIN; // Channel In + input [3:0] CTICHOUTACK; // Channel Out acknowledge + output [3:0] CTICHOUT; // Channel Out + output [3:0] CTICHINACK; // Channel In acknowledge + input CISBYPASS; // Channel interface sync bypass + input [3:0] CIHSBYPASS; // Channel interface H/S bypass + output [`MAIA_CN:0] CTIIRQ; // CTI Interrupt + input [`MAIA_CN:0] CTIIRQACK; // CTI Interrupt acknowledge + +//----------------------------------------------------------------------------- +// Debug Authentication Interface (CLK & PCLK) +//----------------------------------------------------------------------------- + input [`MAIA_CN:0] DBGEN; // Invasive debug enable + input [`MAIA_CN:0] NIDEN; // Non-invasive debug enable + input [`MAIA_CN:0] SPIDEN; // Secure Priviledge invasive debug enable + input [`MAIA_CN:0] SPNIDEN; // Secure Priviledge non-invasive debug enable + +//----------------------------------------------------------------------------- +// DFT Signals +//----------------------------------------------------------------------------- + input DFTSE; // Scan enable + input DFTRSTDISABLE; // Disable reset to cells during scan shift + input [`MAIA_CN:0] DFTCRCLKDISABLE; // Clock grid control for ck_gclkcr + input DFTL2CLKDISABLE; // Clock grid control for ck_gclkl2 + input DFTRAMHOLD; // Holds data in RAMs + input DFTCLKBYPASS; // L2 RAM strobe clock bypass + input DFTMCPHOLD; // Disable multi-cycle RAM paths + +//----------------------------------------------------------------------------- +// MBIST Interface +//----------------------------------------------------------------------------- + input nMBISTRESET; // MBIST reset + input MBISTREQ; // MBIST mode request + +//----------------------------------------------------------------------------- +// Signals from maia -> maia_cpu_io -> maia_cpu +//----------------------------------------------------------------------------- +// Outputs to maia_cpu + output ncpuporeset_cpu0_o; + output ncorereset_cpu0_o; + + output cfgend_cpu0_o; + output cfgte_cpu0_o; + output cp15sdisable_cpu0_o; + output vinithi_cpu0_o; + output [7:0] clusteridaff1_cpu0_o; + output [7:0] clusteridaff2_cpu0_o; + output [1:0] cpuid_cpu0_o; + output aa64naa32_cpu0_o; + output [43:2] rvbaraddr_cpu0_o; + output cryptodisable_cpu0_o; + output giccdisable_cpu0_o; + + output [43:12] dbgromaddr_cpu0_o; + output dbgromaddrv_cpu0_o; + output dbgl1rstdisable_cpu0_o; + + output dbgen_cpu0_o; + output niden_cpu0_o; + output spiden_cpu0_o; + output spniden_cpu0_o; + + output [63:0] tsvalueb_cpu0_o; + + output atclken_cpu0_o; + output afvalidm_cpu0_o; + output atreadym_cpu0_o; + output syncreqm_cpu0_o; + + output dftse_cpu0_o; + output dftrstdisable_cpu0_o; + output dftcrclkdisable_cpu0_o; + output dftramhold_cpu0_o; + output nmbistreset_cpu0_o; + +// BEGIN INCLUDE FOR CPU1 + output ncpuporeset_cpu1_o; + output ncorereset_cpu1_o; + + output cfgend_cpu1_o; + output cfgte_cpu1_o; + output cp15sdisable_cpu1_o; + output vinithi_cpu1_o; + output [7:0] clusteridaff1_cpu1_o; + output [7:0] clusteridaff2_cpu1_o; + output [1:0] cpuid_cpu1_o; + output aa64naa32_cpu1_o; + output [43:2] rvbaraddr_cpu1_o; + output cryptodisable_cpu1_o; + output giccdisable_cpu1_o; + + output [43:12] dbgromaddr_cpu1_o; + output dbgromaddrv_cpu1_o; + output dbgl1rstdisable_cpu1_o; + + output dbgen_cpu1_o; + output niden_cpu1_o; + output spiden_cpu1_o; + output spniden_cpu1_o; + + output [63:0] tsvalueb_cpu1_o; + + output atclken_cpu1_o; + output afvalidm_cpu1_o; + output atreadym_cpu1_o; + output syncreqm_cpu1_o; + + output dftse_cpu1_o; + output dftrstdisable_cpu1_o; + output dftcrclkdisable_cpu1_o; + output dftramhold_cpu1_o; + output nmbistreset_cpu1_o; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + output ncpuporeset_cpu2_o; + output ncorereset_cpu2_o; + + output cfgend_cpu2_o; + output cfgte_cpu2_o; + output cp15sdisable_cpu2_o; + output vinithi_cpu2_o; + output [7:0] clusteridaff1_cpu2_o; + output [7:0] clusteridaff2_cpu2_o; + output [1:0] cpuid_cpu2_o; + output aa64naa32_cpu2_o; + output [43:2] rvbaraddr_cpu2_o; + output cryptodisable_cpu2_o; + output giccdisable_cpu2_o; + + output [43:12] dbgromaddr_cpu2_o; + output dbgromaddrv_cpu2_o; + output dbgl1rstdisable_cpu2_o; + + output dbgen_cpu2_o; + output niden_cpu2_o; + output spiden_cpu2_o; + output spniden_cpu2_o; + + output [63:0] tsvalueb_cpu2_o; + + output atclken_cpu2_o; + output afvalidm_cpu2_o; + output atreadym_cpu2_o; + output syncreqm_cpu2_o; + + output dftse_cpu2_o; + output dftrstdisable_cpu2_o; + output dftcrclkdisable_cpu2_o; + output dftramhold_cpu2_o; + output nmbistreset_cpu2_o; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + output ncpuporeset_cpu3_o; + output ncorereset_cpu3_o; + + output cfgend_cpu3_o; + output cfgte_cpu3_o; + output cp15sdisable_cpu3_o; + output vinithi_cpu3_o; + output [7:0] clusteridaff1_cpu3_o; + output [7:0] clusteridaff2_cpu3_o; + output [1:0] cpuid_cpu3_o; + output aa64naa32_cpu3_o; + output [43:2] rvbaraddr_cpu3_o; + output cryptodisable_cpu3_o; + output giccdisable_cpu3_o; + + output [43:12] dbgromaddr_cpu3_o; + output dbgromaddrv_cpu3_o; + output dbgl1rstdisable_cpu3_o; + + output dbgen_cpu3_o; + output niden_cpu3_o; + output spiden_cpu3_o; + output spniden_cpu3_o; + + output [63:0] tsvalueb_cpu3_o; + + output atclken_cpu3_o; + output afvalidm_cpu3_o; + output atreadym_cpu3_o; + output syncreqm_cpu3_o; + + output dftse_cpu3_o; + output dftrstdisable_cpu3_o; + output dftcrclkdisable_cpu3_o; + output dftramhold_cpu3_o; + output nmbistreset_cpu3_o; +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// Signals from maia_cpu -> maia_cpu_io -> maia +//----------------------------------------------------------------------------- +// Inputs from maia_cpu + input ds_cpu0_sev_req; + input ds_cpu0_sevl_req; + input ds_cpu0_cpuectlr_smp; + + input ncommirq_cpu0_i; + input commrx_cpu0_i; + input commtx_cpu0_i; + input dbgack_cpu0_i; + input dbgrstreq_cpu0_i; + input dbgnopwrdwn_cpu0_i; + + input npmuirq_cpu0_i; + input [24:0] pmuevent_cpu0_i; + input pm_export_cpu0_i; + + input etclken_cpu0_i; + input afreadym_cpu0_i; + input [1:0] atbytesm_cpu0_i; + input [31:0] atdatam_cpu0_i; + input [6:0] atidm_cpu0_i; + input atvalidm_cpu0_i; + +// BEGIN INCLUDE FOR CPU1 + input ds_cpu1_sev_req; + input ds_cpu1_sevl_req; + input ds_cpu1_cpuectlr_smp; + + input ncommirq_cpu1_i; + input commrx_cpu1_i; + input commtx_cpu1_i; + input dbgack_cpu1_i; + input dbgrstreq_cpu1_i; + input dbgnopwrdwn_cpu1_i; + + input npmuirq_cpu1_i; + input [24:0] pmuevent_cpu1_i; + input pm_export_cpu1_i; + + input etclken_cpu1_i; + input afreadym_cpu1_i; + input [1:0] atbytesm_cpu1_i; + input [31:0] atdatam_cpu1_i; + input [6:0] atidm_cpu1_i; + input atvalidm_cpu1_i; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + input ds_cpu2_sev_req; + input ds_cpu2_sevl_req; + input ds_cpu2_cpuectlr_smp; + + input ncommirq_cpu2_i; + input commrx_cpu2_i; + input commtx_cpu2_i; + input dbgack_cpu2_i; + input dbgrstreq_cpu2_i; + input dbgnopwrdwn_cpu2_i; + + input npmuirq_cpu2_i; + input [24:0] pmuevent_cpu2_i; + input pm_export_cpu2_i; + + input etclken_cpu2_i; + input afreadym_cpu2_i; + input [1:0] atbytesm_cpu2_i; + input [31:0] atdatam_cpu2_i; + input [6:0] atidm_cpu2_i; + input atvalidm_cpu2_i; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + input ds_cpu3_sev_req; + input ds_cpu3_sevl_req; + input ds_cpu3_cpuectlr_smp; + + input ncommirq_cpu3_i; + input commrx_cpu3_i; + input commtx_cpu3_i; + input dbgack_cpu3_i; + input dbgrstreq_cpu3_i; + input dbgnopwrdwn_cpu3_i; + + input npmuirq_cpu3_i; + input [24:0] pmuevent_cpu3_i; + input pm_export_cpu3_i; + + input etclken_cpu3_i; + input afreadym_cpu3_i; + input [1:0] atbytesm_cpu3_i; + input [31:0] atdatam_cpu3_i; + input [6:0] atidm_cpu3_i; + input atvalidm_cpu3_i; +// END INCLUDE FOR CPU3 + +//----------------------------------------------------------------------------- +// L2 interface +//----------------------------------------------------------------------------- + output [12:0] l2_cpu0_mbist1_addr_b1; + output [3:0] l2_cpu0_mbist1_array_b1; + output [7:0] l2_cpu0_mbist1_be_b1; + output l2_cpu0_mbist1_en_b1; + output l2_cpu0_mbist1_rd_en_b1; + output l2_cpu0_mbist1_wr_en_b1; + output l2_cpu0_mbist1_all_b1; + +// BEGIN INCLUDE FOR CPU1 + output [12:0] l2_cpu1_mbist1_addr_b1; + output [3:0] l2_cpu1_mbist1_array_b1; + output [7:0] l2_cpu1_mbist1_be_b1; + output l2_cpu1_mbist1_en_b1; + output l2_cpu1_mbist1_rd_en_b1; + output l2_cpu1_mbist1_wr_en_b1; + output l2_cpu1_mbist1_all_b1; +// END INCLUDE FOR CPU1 + +// BEGIN INCLUDE FOR CPU2 + output [12:0] l2_cpu2_mbist1_addr_b1; + output [3:0] l2_cpu2_mbist1_array_b1; + output [7:0] l2_cpu2_mbist1_be_b1; + output l2_cpu2_mbist1_en_b1; + output l2_cpu2_mbist1_rd_en_b1; + output l2_cpu2_mbist1_wr_en_b1; + output l2_cpu2_mbist1_all_b1; +// END INCLUDE FOR CPU2 + +// BEGIN INCLUDE FOR CPU3 + output [12:0] l2_cpu3_mbist1_addr_b1; + output [3:0] l2_cpu3_mbist1_array_b1; + output [7:0] l2_cpu3_mbist1_be_b1; + output l2_cpu3_mbist1_en_b1; + output l2_cpu3_mbist1_rd_en_b1; + output l2_cpu3_mbist1_wr_en_b1; + output l2_cpu3_mbist1_all_b1; +// END INCLUDE FOR CPU3 + +// BEGIN L2-CPU interface + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + output l2_cpu0_cfg_ecc_en; + output l2_cpu0_arb_thrshld_timeout_en; + output l2_cpu0_disable_clean_evict_opt; + output l2_cpu0_dext_err_r2; // LS external error + output l2_cpu0_dext_err_type_r2; // LS external error type + output l2_cpu0_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu0_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu0_ddata_r2; // LS read data + output l2_cpu0_barrier_done; // LS barrier complete + output l2_cpu0_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu0_spec_bufid; // LS read speculative response buffer id + output l2_cpu0_rvalid; // LS read response valid + output [1:0] l2_cpu0_rstate; // LS read response state + output l2_cpu0_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu0_rbufid; // LS read response buffer id + output l2_cpu0_dvalid_r1; // LS read data valid + output l2_cpu0_dlast_r1; // LS read last indicator + output [2:0] l2_cpu0_dbufid_r1; // LS read data fill buffer id + output l2_cpu0_iext_err_r2; // IF external error + output l2_cpu0_iext_err_type_r2; // IF external error type + output l2_cpu0_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu0_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu0_idata_r2; // IF read data + output l2_cpu0_ivalid_r1; // IF read data valid + output [1:0] l2_cpu0_ibufid_r1; // IF read data fill buffer id + output l2_cpu0_ls_sync_req; // LS sync req + output [48:0] l2_cpu0_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu0_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu0_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu0_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu0_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu0_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu0_ccb_req_info_c3; // LS ccb req info + output l2_cpu0_if_ccb_clken_c3; // IF ccb clken + output l2_cpu0_if_ccb_req_c3; // IF ccb req + output l2_cpu0_if_sync_req; // IF sync req + output l2_cpu0_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu0_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu0_tlb_sync_req; // TLB sync req + output l2_cpu0_tlb_sync_complete; // TLB sync complete + output l2_cpu0_tbw_desc_vld; // TBW descriptor valid + output l2_cpu0_tbw_ext_err; // TBW descriptor external error + output l2_cpu0_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu0_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu0_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu0_spr_rd_data; // DS spr read data + output [1:0] l2_cpu0_l2_cache_size; // DS L2 cache size + output l2_cpu0_pf_throttle_q; // PF throttling + + output l2_cpu0_wr_ex_resp; // store exclusive response + output l2_cpu0_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu0_ic_base; // PERIPHBASE + output l2_cpu0_no_intctrl; // INTCTLR not present + + + output [33:0] l2_cpu0_pmu_events; // L2 PMU events + + input ds_cpu0_l2_spr_en; // cpu0 early spr req for clk enables + input ds_cpu0_l2_spr_rd; // cpu0 spr read op + input ds_cpu0_l2_spr_wr; // cpu0 spr write op + input [8:0] ds_cpu0_l2_spr_addr; // cpu0 spr address + input ds_cpu0_l2_spr_dw; // cpu0 spr access dw + input [63:0] ds_cpu0_l2_spr_wr_data; // cpu0 spr write data + + input l2_cpu0_wr_data_vld_x1_q; // cpu0 write data vld x1 stage + input l2_cpu0_wr_evict_x1_q; // cpu0 write evict x1 stage + input [143:0] l2_cpu0_wr_data; + input l2_cpu0_ls_rd_haz_vld_arb_q; + input l2_cpu0_ls_wr_haz_vld_arb_q; + input l2_cpu0_dt_pmu_evt_en; // PMU enabled. + + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + output l2_cpu1_cfg_ecc_en; + output l2_cpu1_arb_thrshld_timeout_en; + output l2_cpu1_disable_clean_evict_opt; + output l2_cpu1_dext_err_r2; // LS external error + output l2_cpu1_dext_err_type_r2; // LS external error type + output l2_cpu1_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu1_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu1_ddata_r2; // LS read data + output l2_cpu1_barrier_done; // LS barrier complete + output l2_cpu1_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu1_spec_bufid; // LS read speculative response buffer id + output l2_cpu1_rvalid; // LS read response valid + output [1:0] l2_cpu1_rstate; // LS read response state + output l2_cpu1_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu1_rbufid; // LS read response buffer id + output l2_cpu1_dvalid_r1; // LS read data valid + output l2_cpu1_dlast_r1; // LS read last indicator + output [2:0] l2_cpu1_dbufid_r1; // LS read data fill buffer id + output l2_cpu1_iext_err_r2; // IF external error + output l2_cpu1_iext_err_type_r2; // IF external error type + output l2_cpu1_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu1_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu1_idata_r2; // IF read data + output l2_cpu1_ivalid_r1; // IF read data valid + output [1:0] l2_cpu1_ibufid_r1; // IF read data fill buffer id + output l2_cpu1_ls_sync_req; // LS sync req + output [48:0] l2_cpu1_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu1_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu1_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu1_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu1_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu1_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu1_ccb_req_info_c3; // LS ccb req info + output l2_cpu1_if_ccb_clken_c3; // IF ccb clken + output l2_cpu1_if_ccb_req_c3; // IF ccb req + output l2_cpu1_if_sync_req; // IF sync req + output l2_cpu1_tlb_ccb_clken_c3; // IF ccb clken + output l2_cpu1_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu1_tlb_sync_req; // TLB sync req + output l2_cpu1_tlb_sync_complete; // TLB sync complete + output l2_cpu1_tbw_desc_vld; // TBW descriptor valid + output l2_cpu1_tbw_ext_err; // TBW descriptor external error + output l2_cpu1_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu1_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu1_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu1_spr_rd_data; // DS spr read data + output [1:0] l2_cpu1_l2_cache_size; // DS L2 cache size + output l2_cpu1_pf_throttle_q; // PF throttling + + output l2_cpu1_wr_ex_resp; // store exclusive response + output l2_cpu1_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu1_ic_base; // PERIPHBASE + output l2_cpu1_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu1_pmu_events; // L2 PMU events + + input ds_cpu1_l2_spr_en; // cpu1 early spr req for clk enables + input ds_cpu1_l2_spr_rd; // cpu1 spr read op + input ds_cpu1_l2_spr_wr; // cpu1 spr write op + input [8:0] ds_cpu1_l2_spr_addr; // cpu1 spr address + input ds_cpu1_l2_spr_dw; // cpu1 spr access dw + input [63:0] ds_cpu1_l2_spr_wr_data; // cpu1 spr write data + + input l2_cpu1_wr_data_vld_x1_q; // cpu1 write data vld x1 stage + input l2_cpu1_wr_evict_x1_q; // cpu1 write evict x1 stage + input [143:0] l2_cpu1_wr_data; + input l2_cpu1_ls_rd_haz_vld_arb_q; + input l2_cpu1_ls_wr_haz_vld_arb_q; + input l2_cpu1_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + output l2_cpu2_cfg_ecc_en; + output l2_cpu2_arb_thrshld_timeout_en; + output l2_cpu2_disable_clean_evict_opt; + output l2_cpu2_dext_err_r2; // LS external error + output l2_cpu2_dext_err_type_r2; // LS external error type + output l2_cpu2_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu2_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu2_ddata_r2; // LS read data + output l2_cpu2_barrier_done; // LS barrier complete + output l2_cpu2_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu2_spec_bufid; // LS read speculative response buffer id + output l2_cpu2_rvalid; // LS read response valid + output [1:0] l2_cpu2_rstate; // LS read response state + output l2_cpu2_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu2_rbufid; // LS read response buffer id + output l2_cpu2_dvalid_r1; // LS read data valid + output l2_cpu2_dlast_r1; // LS read last indicator + output [2:0] l2_cpu2_dbufid_r1; // LS read data fill buffer id + output l2_cpu2_iext_err_r2; // IF external error + output l2_cpu2_iext_err_type_r2; // IF external error type + output l2_cpu2_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu2_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu2_idata_r2; // IF read data + output l2_cpu2_ivalid_r1; // IF read data valid + output [1:0] l2_cpu2_ibufid_r1; // IF read data fill buffer id + output l2_cpu2_ls_sync_req; // LS sync req + output [48:0] l2_cpu2_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu2_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu2_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu2_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu2_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu2_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu2_ccb_req_info_c3; // LS ccb req info + output l2_cpu2_if_ccb_clken_c3; // IF ccb clken + output l2_cpu2_if_ccb_req_c3; // IF ccb req + output l2_cpu2_if_sync_req; // IF sync req + output l2_cpu2_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu2_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu2_tlb_sync_req; // TLB sync req + output l2_cpu2_tlb_sync_complete; // TLB sync complete + output l2_cpu2_tbw_desc_vld; // TBW descriptor valid + output l2_cpu2_tbw_ext_err; // TBW descriptor external error + output l2_cpu2_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu2_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu2_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu2_spr_rd_data; // DS spr read data + output [1:0] l2_cpu2_l2_cache_size; // DS L2 cache size + output l2_cpu2_pf_throttle_q; // PF throttling + + output l2_cpu2_wr_ex_resp; // store exclusive response + output l2_cpu2_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu2_ic_base; // PERIPHBASE + output l2_cpu2_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu2_pmu_events; // L2 PMU events + + input ds_cpu2_l2_spr_en; // cpu2 early spr req for clk enables + input ds_cpu2_l2_spr_rd; // cpu2 spr read op + input ds_cpu2_l2_spr_wr; // cpu2 spr write op + input [8:0] ds_cpu2_l2_spr_addr; // cpu2 spr address + input ds_cpu2_l2_spr_dw; // cpu2 spr access dw + input [63:0] ds_cpu2_l2_spr_wr_data; // cpu2 spr write data + + input l2_cpu2_wr_data_vld_x1_q; // cpu2 write data vld x1 stage + input l2_cpu2_wr_evict_x1_q; // cpu2 write evict x1 stage + input [143:0] l2_cpu2_wr_data; + input l2_cpu2_ls_rd_haz_vld_arb_q; + input l2_cpu2_ls_wr_haz_vld_arb_q; + input l2_cpu2_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + output l2_cpu3_cfg_ecc_en; + output l2_cpu3_arb_thrshld_timeout_en; + output l2_cpu3_disable_clean_evict_opt; + output l2_cpu3_dext_err_r2; // LS external error + output l2_cpu3_dext_err_type_r2; // LS external error type + output l2_cpu3_dsngl_ecc_err_r3; // LS single-bit ecc error + output l2_cpu3_ddbl_ecc_err_r3; // LS double-bit ecc error + output [129:0] l2_cpu3_ddata_r2; // LS read data + output l2_cpu3_barrier_done; // LS barrier complete + output l2_cpu3_spec_valid; // LS read speculative response valid + output [2:0] l2_cpu3_spec_bufid; // LS read speculative response buffer id + output l2_cpu3_rvalid; // LS read response valid + output [1:0] l2_cpu3_rstate; // LS read response state + output l2_cpu3_rexfail; // LS read response exclusive fail + output [2:0] l2_cpu3_rbufid; // LS read response buffer id + output l2_cpu3_dvalid_r1; // LS read data valid + output l2_cpu3_dlast_r1; // LS read last indicator + output [2:0] l2_cpu3_dbufid_r1; // LS read data fill buffer id + output l2_cpu3_iext_err_r2; // IF external error + output l2_cpu3_iext_err_type_r2; // IF external error type + output l2_cpu3_isngl_ecc_err_r3; // IF single-bit ecc error + output l2_cpu3_idbl_ecc_err_r3; // IF double-bit ecc error + output [127:0] l2_cpu3_idata_r2; // IF read data + output l2_cpu3_ivalid_r1; // IF read data valid + output [1:0] l2_cpu3_ibufid_r1; // IF read data fill buffer id + output l2_cpu3_ls_sync_req; // LS sync req + output [48:0] l2_cpu3_ccb_req_addr_c3; // LS/IF/TLB ccb req addr + output l2_cpu3_ccb_dbg_req_c3; // CCB req is a dbg array rd + output l2_cpu3_ls_ccb_clken_c3; // LS ccb clken + output l2_cpu3_ls_ccb_req_c3; // LS ccb req + output [4:0] l2_cpu3_ccb_req_id_c3; // LS ccb req id + output [8:0] l2_cpu3_ccb_req_type_c3; // LS ccb req type + output [23:0] l2_cpu3_ccb_req_info_c3; // LS ccb req info + output l2_cpu3_if_ccb_clken_c3; // IF ccb clken + output l2_cpu3_if_ccb_req_c3; // IF ccb req + output l2_cpu3_if_sync_req; // IF sync req + output l2_cpu3_tlb_ccb_clken_c3; // TLB ccb clken + output l2_cpu3_tlb_ccb_req_c3; // TLB ccb req + output l2_cpu3_tlb_sync_req; // TLB sync req + output l2_cpu3_tlb_sync_complete; // TLB sync complete + output l2_cpu3_tbw_desc_vld; // TBW descriptor valid + output l2_cpu3_tbw_ext_err; // TBW descriptor external error + output l2_cpu3_tbw_ext_err_type; // TBW descriptor external error type + output l2_cpu3_tbw_dbl_ecc_err; // TBW descriptor double-bit ecc error + output [63:0] l2_cpu3_tbw_desc_data; // TBW descriptor data + output [63:0] l2_cpu3_spr_rd_data; // DS spr read data + output [1:0] l2_cpu3_l2_cache_size; // DS L2 cache size + output l2_cpu3_pf_throttle_q; // PF throttling + + output l2_cpu3_wr_ex_resp; // store exclusive response + output l2_cpu3_wr_ex_fail; // store exclusive failed + + output [43:18] l2_cpu3_ic_base; // PERIPHBASE + output l2_cpu3_no_intctrl; // INTCTLR not present + + output [33:0] l2_cpu3_pmu_events; // L2 PMU events + + input ds_cpu3_l2_spr_en; // cpu3 early spr req for clk enables + input ds_cpu3_l2_spr_rd; // cpu3 spr read op + input ds_cpu3_l2_spr_wr; // cpu3 spr write op + input [8:0] ds_cpu3_l2_spr_addr; // cpu3 spr address + input ds_cpu3_l2_spr_dw; // cpu3 spr access dw + input [63:0] ds_cpu3_l2_spr_wr_data; // cpu3 spr write data + + input l2_cpu3_wr_data_vld_x1_q; // cpu3 write data vld x1 stage + input l2_cpu3_wr_evict_x1_q; // cpu3 write evict x1 stage + input [143:0] l2_cpu3_wr_data; + input l2_cpu3_ls_rd_haz_vld_arb_q; + input l2_cpu3_ls_wr_haz_vld_arb_q; + input l2_cpu3_dt_pmu_evt_en; // PMU enabled. + +//----------------------------------------------------------------------------- +// tag_pipe / cpu slave +//----------------------------------------------------------------------------- + output l2_cpu0_flsh_ls_rd_l2_dly; // cpu0 ls local hazard flush + output l2_cpu0_flsh_ls_wr_l2_dly; // cpu0 ls local hazard flush + + output l2_cpu0_wr_data_stall; // cpu0 write data stall + + output l2_cpu1_flsh_ls_rd_l2_dly; // cpu1 ls local hazard flush + output l2_cpu1_flsh_ls_wr_l2_dly; // cpu1 ls local hazard flush + + output l2_cpu1_wr_data_stall; // cpu1 write data stall + + output l2_cpu2_flsh_ls_rd_l2_dly; // cpu2 ls local hazard flush + output l2_cpu2_flsh_ls_wr_l2_dly; // cpu2 ls local hazard flush + + output l2_cpu2_wr_data_stall; // cpu2 write data stall + + output l2_cpu3_flsh_ls_rd_l2_dly; // cpu3 ls local hazard flush + output l2_cpu3_flsh_ls_wr_l2_dly; // cpu3 ls local hazard flush + + output l2_cpu3_wr_data_stall; // cpu3 write data stall + + output [2:0] l2_cpu0_flsh_ls_rd_id_l2_dly; // cpu0 ls id local hazard flush + output [3:0] l2_cpu0_flsh_ls_wr_id_l2_dly; // cpu0 ls id local hazard flush + + output [2:0] l2_cpu1_flsh_ls_rd_id_l2_dly; // cpu1 ls id local hazard flush + output [3:0] l2_cpu1_flsh_ls_wr_id_l2_dly; // cpu1 ls id local hazard flush + + output [2:0] l2_cpu2_flsh_ls_rd_id_l2_dly; // cpu2 ls id local hazard flush + output [3:0] l2_cpu2_flsh_ls_wr_id_l2_dly; // cpu2 ls id local hazard flush + + output [2:0] l2_cpu3_flsh_ls_rd_id_l2_dly; // cpu3 ls id local hazard flush + output [3:0] l2_cpu3_flsh_ls_wr_id_l2_dly; // cpu3 ls id local hazard flush + + output l2_cpu0_flsh_ls_rd_l4_dly; // cpu0 ls global hazard flush + output l2_cpu0_flsh_if_rd_l4_dly; // cpu0 if global hazard flush + output l2_cpu0_flsh_tw_rd_l4_dly; // cpu0 tw global hazard flush + output l2_cpu0_flsh_ls_wr_l4_dly; // cpu0 ls global hazard flush + + output l2_cpu1_flsh_ls_rd_l4_dly; // cpu1 ls global hazard flush + output l2_cpu1_flsh_if_rd_l4_dly; // cpu1 if global hazard flush + output l2_cpu1_flsh_tw_rd_l4_dly; // cpu1 tw global hazard flush + output l2_cpu1_flsh_ls_wr_l4_dly; // cpu1 ls global hazard flush + + output l2_cpu2_flsh_ls_rd_l4_dly; // cpu2 ls global hazard flush + output l2_cpu2_flsh_if_rd_l4_dly; // cpu2 if global hazard flush + output l2_cpu2_flsh_tw_rd_l4_dly; // cpu2 tw global hazard flush + output l2_cpu2_flsh_ls_wr_l4_dly; // cpu2 ls global hazard flush + + output l2_cpu3_flsh_ls_rd_l4_dly; // cpu3 ls global hazard flush + output l2_cpu3_flsh_if_rd_l4_dly; // cpu3 if global hazard flush + output l2_cpu3_flsh_tw_rd_l4_dly; // cpu3 tw global hazard flush + output l2_cpu3_flsh_ls_wr_l4_dly; // cpu3 ls global hazard flush + + output [2:0] l2_cpu0_flsh_ls_rd_id_l4_dly; // cpu0 ls id global hazard flush + output [1:0] l2_cpu0_flsh_if_rd_id_l4_dly; // cpu0 if id global hazard flush + output [3:0] l2_cpu0_flsh_ls_wr_id_l4_dly; // cpu0 ls id global hazard flush + output l2_cpu0_flsh_ls_wr_evict_l4_dly; // cpu0 ls evict hazard + + output [2:0] l2_cpu1_flsh_ls_rd_id_l4_dly; // cpu1 ls id global hazard flush + output [1:0] l2_cpu1_flsh_if_rd_id_l4_dly; // cpu1 if id global hazard flush + output [3:0] l2_cpu1_flsh_ls_wr_id_l4_dly; // cpu1 ls id global hazard flush + output l2_cpu1_flsh_ls_wr_evict_l4_dly; // cpu1 ls evict hazard + + output [2:0] l2_cpu2_flsh_ls_rd_id_l4_dly; // cpu2 ls id global hazard flush + output [1:0] l2_cpu2_flsh_if_rd_id_l4_dly; // cpu2 if id global hazard flush + output [3:0] l2_cpu2_flsh_ls_wr_id_l4_dly; // cpu2 ls id global hazard flush + output l2_cpu2_flsh_ls_wr_evict_l4_dly; // cpu2 ls evict hazard + + output [2:0] l2_cpu3_flsh_ls_rd_id_l4_dly; // cpu3 ls id global hazard flush + output [1:0] l2_cpu3_flsh_if_rd_id_l4_dly; // cpu3 if id global hazard flush + output [3:0] l2_cpu3_flsh_ls_wr_id_l4_dly; // cpu3 ls id global hazard flush + output l2_cpu3_flsh_ls_wr_evict_l4_dly; // cpu3 ls evict hazard + + output l2_cpu0_lrq_haz_pending; // cpu0 lrq hazard pending + output l2_cpu1_lrq_haz_pending; // cpu1 lrq hazard pending + output l2_cpu2_lrq_haz_pending; // cpu2 lrq hazard pending + output l2_cpu3_lrq_haz_pending; // cpu3 lrq hazard pending + + output l2_cpu0_ifq_haz_pending; // cpu0 ifq hazard pending + output l2_cpu1_ifq_haz_pending; // cpu1 ifq hazard pending + output l2_cpu2_ifq_haz_pending; // cpu2 ifq hazard pending + output l2_cpu3_ifq_haz_pending; // cpu3 ifq hazard pending + + output l2_cpu0_trq_haz_pending; // cpu0 trq hazard pending + output l2_cpu1_trq_haz_pending; // cpu1 trq hazard pending + output l2_cpu2_trq_haz_pending; // cpu2 trq hazard pending + output l2_cpu3_trq_haz_pending; // cpu3 trq hazard pending + + output l2_cpu0_wrq_haz_pending; // cpu0 wrq hazard pending + output l2_cpu1_wrq_haz_pending; // cpu1 wrq hazard pending + output l2_cpu2_wrq_haz_pending; // cpu2 wrq hazard pending + output l2_cpu3_wrq_haz_pending; // cpu3 wrq hazard pending + + output l2_cpu0_idle_block_reqs_q; // cpu0 idle block requests + output l2_cpu1_idle_block_reqs_q; // cpu1 idle block requests + output l2_cpu2_idle_block_reqs_q; // cpu2 idle block requests + output l2_cpu3_idle_block_reqs_q; // cpu3 idle block requests + + output l2_cpu0_ls_peq_coll_l4_dly; // cpu0 peq collision detected + output l2_cpu1_ls_peq_coll_l4_dly; // cpu1 peq collision detected + output l2_cpu2_ls_peq_coll_l4_dly; // cpu2 peq collision detected + output l2_cpu3_ls_peq_coll_l4_dly; // cpu3 peq collision detected + +//----------------------------------------------------------------------------- +// tag_pipe +//----------------------------------------------------------------------------- + output [3:0] l2_tbnk0_cpu0_lrq_clr_l4_dly2_q; // tbnk0 clear cpu0 lrq entry + output [3:0] l2_tbnk0_cpu1_lrq_clr_l4_dly2_q; // tbnk0 clear cpu1 lrq entry + output [3:0] l2_tbnk0_cpu2_lrq_clr_l4_dly2_q; // tbnk0 clear cpu2 lrq entry + output [3:0] l2_tbnk0_cpu3_lrq_clr_l4_dly2_q; // tbnk0 clear cpu3 lrq entry + + output [3:0] l2_tbnk1_cpu0_lrq_clr_l4_dly2_q; // tbnk1 clear cpu0 lrq entry + output [3:0] l2_tbnk1_cpu1_lrq_clr_l4_dly2_q; // tbnk1 clear cpu1 lrq entry + output [3:0] l2_tbnk1_cpu2_lrq_clr_l4_dly2_q; // tbnk1 clear cpu2 lrq entry + output [3:0] l2_tbnk1_cpu3_lrq_clr_l4_dly2_q; // tbnk1 clear cpu3 lrq entry + + output [2:0] l2_tbnk0_cpu0_ifq_clr_l4_dly2_q; // tbnk0 clear cpu0 ifq entry + output [2:0] l2_tbnk0_cpu1_ifq_clr_l4_dly2_q; // tbnk0 clear cpu1 ifq entry + output [2:0] l2_tbnk0_cpu2_ifq_clr_l4_dly2_q; // tbnk0 clear cpu2 ifq entry + output [2:0] l2_tbnk0_cpu3_ifq_clr_l4_dly2_q; // tbnk0 clear cpu3 ifq entry + + output [2:0] l2_tbnk1_cpu0_ifq_clr_l4_dly2_q; // tbnk1 clear cpu0 ifq entry + output [2:0] l2_tbnk1_cpu1_ifq_clr_l4_dly2_q; // tbnk1 clear cpu1 ifq entry + output [2:0] l2_tbnk1_cpu2_ifq_clr_l4_dly2_q; // tbnk1 clear cpu2 ifq entry + output [2:0] l2_tbnk1_cpu3_ifq_clr_l4_dly2_q; // tbnk1 clear cpu3 ifq entry + + output l2_tbnk0_cpu0_trq_clr_l4_dly2_q; // tbnk0 clear cpu0 trq entry + output l2_tbnk0_cpu1_trq_clr_l4_dly2_q; // tbnk0 clear cpu1 trq entry + output l2_tbnk0_cpu2_trq_clr_l4_dly2_q; // tbnk0 clear cpu2 trq entry + output l2_tbnk0_cpu3_trq_clr_l4_dly2_q; // tbnk0 clear cpu3 trq entry + + output l2_tbnk1_cpu0_trq_clr_l4_dly2_q; // tbnk1 clear cpu0 trq entry + output l2_tbnk1_cpu1_trq_clr_l4_dly2_q; // tbnk1 clear cpu1 trq entry + output l2_tbnk1_cpu2_trq_clr_l4_dly2_q; // tbnk1 clear cpu2 trq entry + output l2_tbnk1_cpu3_trq_clr_l4_dly2_q; // tbnk1 clear cpu3 trq entry + + output [5:0] l2_tbnk0_cpu0_wrq_clr_l4_dly2_q; // tbnk0 clear cpu0 wrq entry + output [5:0] l2_tbnk0_cpu1_wrq_clr_l4_dly2_q; // tbnk0 clear cpu1 wrq entry + output [5:0] l2_tbnk0_cpu2_wrq_clr_l4_dly2_q; // tbnk0 clear cpu2 wrq entry + output [5:0] l2_tbnk0_cpu3_wrq_clr_l4_dly2_q; // tbnk0 clear cpu3 wrq entry + + output [5:0] l2_tbnk1_cpu0_wrq_clr_l4_dly2_q; // tbnk1 clear cpu0 wrq entry + output [5:0] l2_tbnk1_cpu1_wrq_clr_l4_dly2_q; // tbnk1 clear cpu1 wrq entry + output [5:0] l2_tbnk1_cpu2_wrq_clr_l4_dly2_q; // tbnk1 clear cpu2 wrq entry + output [5:0] l2_tbnk1_cpu3_wrq_clr_l4_dly2_q; // tbnk1 clear cpu3 wrq entry + + +//----------------------------------------------------------------------------- +// cpu_logic / cpu slave +//----------------------------------------------------------------------------- + output l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu0 ls rd flsh l4 active + output l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu0 wr rd flsh l4 active + + output l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu1 ls rd flsh l4 active + output l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu1 wr rd flsh l4 active + + output l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu2 ls rd flsh l4 active + output l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu2 wr rd flsh l4 active + + output l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly; // cpu3 ls rd flsh l4 active + output l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly; // cpu3 wr rd flsh l4 active + + +//----------------------------------------------------------------------------- +// feq / cpu slave +//----------------------------------------------------------------------------- + input [129:0] l2_cpu0_dsq_rd_data_q; // cpu0 wrq/dsq data + input [15:0] l2_cpu0_dsq_rd_byte_strb_q; // cpu0 wrq/dsq byte strobes + input [129:0] l2_cpu1_dsq_rd_data_q; // cpu1 wrq/dsq data + input [15:0] l2_cpu1_dsq_rd_byte_strb_q; // cpu1 wrq/dsq byte strobes + input [129:0] l2_cpu2_dsq_rd_data_q; // cpu2 wrq/dsq data + input [15:0] l2_cpu2_dsq_rd_byte_strb_q; // cpu2 wrq/dsq byte strobes + input [129:0] l2_cpu3_dsq_rd_data_q; // cpu3 wrq/dsq data + input [15:0] l2_cpu3_dsq_rd_byte_strb_q; // cpu3 wrq/dsq byte strobes + + output l2_cpu0_dsq_clr_vld_q; // cpu0 dsq clear wrq vld entry + output [3:0] l2_cpu0_dsq_clr_id_q; // cpu0 dsq clear wrq buffer id + output l2_cpu0_dsq_rd_en; // cpu0 dsq/wrq data enable + output l2_cpu0_dsq_rd_en_x2; // cpu0 dsq/wrq data enable x2 + output [3:0] l2_cpu0_dsq_rd_buf_id; // cpu0 dsq/wrq data select + output l2_cpu1_dsq_clr_vld_q; // cpu1 dsq clear wrq vld entry + output [3:0] l2_cpu1_dsq_clr_id_q; // cpu1 dsq clear wrq buffer id + output l2_cpu1_dsq_rd_en; // cpu1 dsq/wrq data enable + output l2_cpu1_dsq_rd_en_x2; // cpu1 dsq/wrq data enable x2 + output [3:0] l2_cpu1_dsq_rd_buf_id; // cpu1 dsq/wrq data select + output l2_cpu2_dsq_clr_vld_q; // cpu2 dsq clear wrq vld entry + output [3:0] l2_cpu2_dsq_clr_id_q; // cpu2 dsq clear wrq buffer id + output l2_cpu2_dsq_rd_en; // cpu2 dsq/wrq data enable + output l2_cpu2_dsq_rd_en_x2; // cpu2 dsq/wrq data enable x2 + output [3:0] l2_cpu2_dsq_rd_buf_id; // cpu2 dsq/wrq data select + output l2_cpu3_dsq_clr_vld_q; // cpu3 dsq clear wrq vld entry + output l2_cpu3_dsq_rd_en; // cpu3 dsq/wrq data enable + output l2_cpu3_dsq_rd_en_x2; // cpu3 dsq/wrq data enable x2 + output [3:0] l2_cpu3_dsq_clr_id_q; // cpu3 dsq clear wrq buffer id + output [3:0] l2_cpu3_dsq_rd_buf_id; // cpu3 dsq/wrq data select + +//----------------------------------------------------------------------------- +// arbitration +//----------------------------------------------------------------------------- + output l2_cpu0_rd_vld_skid; // cpu0 read skid buffer valid + output l2_cpu1_rd_vld_skid; // cpu1 read skid buffer valid + output l2_cpu2_rd_vld_skid; // cpu2 read skid buffer valid + output l2_cpu3_rd_vld_skid; // cpu3 read skid buffer valid + + output l2_cpu0_pf_rd_vld_skid_popped; // cpu0 pf read skid buffer popped + output l2_cpu1_pf_rd_vld_skid_popped; // cpu1 pf read skid buffer popped + output l2_cpu2_pf_rd_vld_skid_popped; // cpu2 pf read skid buffer popped + output l2_cpu3_pf_rd_vld_skid_popped; // cpu3 pf read skid buffer popped + + output l2_cpu0_rd_arb; // + output l2_cpu1_rd_arb; // + output l2_cpu2_rd_arb; // + output l2_cpu3_rd_arb; // + + output l2_cpu0_wr_vld_skid; // cpu0 write skid buffer valid + output l2_cpu1_wr_vld_skid; // cpu1 write skid buffer valid + output l2_cpu2_wr_vld_skid; // cpu2 write skid buffer valid + output l2_cpu3_wr_vld_skid; // cpu3 write skid buffer valid + + output l2_cpu0_wr_arb; // + output l2_cpu1_wr_arb; // + output l2_cpu2_wr_arb; // + output l2_cpu3_wr_arb; // + + output l2_cpu0_ic_vld_skid; // cpu0 peripheral (ic) skid buffer valid + output l2_cpu1_ic_vld_skid; // cpu1 peripheral (ic) skid buffer valid + output l2_cpu2_ic_vld_skid; // cpu2 peripheral (ic) skid buffer valid + output l2_cpu3_ic_vld_skid; // cpu3 peripheral (ic) skid buffer valid + + output l2_cpu0_ic_barrier_stall_q; // cpu0 (ic) barrier stall + output l2_cpu1_ic_barrier_stall_q; // cpu1 (ic) barrier stall + output l2_cpu2_ic_barrier_stall_q; // cpu2 (ic) barrier stall + output l2_cpu3_ic_barrier_stall_q; // cpu3 (ic) barrier stall + + output l2_cpu0_blk_non_evict_wr; // cpu0 block non-evict writes from arbitrating + output l2_cpu1_blk_non_evict_wr; // cpu1 block non-evict writes from arbitrating + output l2_cpu2_blk_non_evict_wr; // cpu2 block non-evict writes from arbitrating + output l2_cpu3_blk_non_evict_wr; // cpu3 block non-evict writes from arbitrating + +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + input l2_cpu0_idle_wakeup_q; // cpu0 idle wakeup + input l2_cpu0_rd_arb_fast; // cpu0 read arbitration fast request + input [4:0] l2_cpu0_rd_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu0_rd_lrq_id_arb_set; // cpu0 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu0_rd_type_arb_set; // cpu0 read arbitration type + input [2:0] l2_cpu0_rd_cache_attr_arb_set; // cpu0 read arbitration cache attributes + input [7:0] l2_cpu0_rd_page_attr_arb_set; // cpu0 read arbitration page attributes + input [2:0] l2_cpu0_rd_elem_size_arb_set; // cpu0 read arbitration element size + input l2_cpu0_rd_way_arb_set; // cpu0 read arbitration way + input l2_cpu0_rd_replayed_arb_set; // cpu0 read arbitration replayed + input l2_cpu0_rd_excl_arb_set; // cpu0 read arbitration exclusive + input l2_cpu0_rd_priv_arb_set; // cpu0 read arbitration priv + input [1:0] l2_cpu0_rd_shared_arb_set; // cpu0 read arbitration shared + input l2_cpu0_rd_va48_arb_set; // cpu0 read arbitration va48 + input l2_cpu0_rd_aarch64_arb_set; // cpu0 read arbitration aarch64 + input [15:8] l2_cpu0_rd_asid_arb_set; // cpu0 read arbitration asid + input l2_cpu0_rd_prfm_arb_set; // cpu0 read arbitration prfm + input [44:0] l2_cpu0_rd_addr_arb_set; // cpu0 read arbitration address + input l2_cpu0_rd_bypass_arb_set; // cpu0 read arbitration bypass + input l2_cpu0_rd_bypass_req_can_e5; // cpu0 read arbitration bypass cancelled request + input l2_cpu0_early_rd_reqe4_e5_q; // cpu0 read arbitration bypass cancelled request + input l2_cpu0_rd_bypass_way_e5; // cpu0 read arbitration bypass way + input [2:0] l2_cpu0_rd_bypass_bufid_e5; // cpu0 read arbitration bypass bufid + input [2:0] l2_cpu0_rd_bypass_lrq_id_e5; // cpu0 read arbitration bypass bufid + + input l2_cpu0_wr_arb_fast; // cpu0 write arbitration fast request + input [3:0] l2_cpu0_wr_id_arb_set; // cpu0 write arbitration id for 1st qw + input [3:0] l2_cpu0_wr_partial_dw_arb_set; // cpu0 write partial qw byte strobe indicator + input [2:0] l2_cpu0_wr_cache_attr_arb_set; // cpu0 write arbitration cache attributes + input [7:0] l2_cpu0_wr_page_attr_arb_set; // cpu0 write arbitration page attributes + input [2:0] l2_cpu0_wr_elem_size_arb_set; // cpu0 write arbitration element size + input [2:0] l2_cpu0_wr_type_arb_set; // cpu0 write arbitration type + input [11:0] l2_cpu0_wr_cl_id_arb_set; // cpu0 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu0_wr_priv_arb_set; // cpu0 write arbitration priv + input [1:0] l2_cpu0_wr_shared_arb_set; // cpu0 write arbitration shared + input l2_cpu0_wr_last_arb_set; // cpu0 write arbitration last + input l2_cpu0_wr_clean_evict_arb_set; // cpu0 write arbitration clean eviction + input l2_cpu0_wr_err_arb_set; // cpu0 write arbitration error + input l2_cpu0_wr_way_arb_set; // cpu0 write arbitration way + input l2_cpu0_wr_dirty_arb_set; // cpu0 write arbitration dirty + input l2_cpu0_wr_1st_replayed_arb_set; // cpu0 write arbitration 1st replay indicator + input [44:0] l2_cpu0_wr_addr_arb_set; // cpu0 write arbitration address + input l2_cpu0_ic_arb_fast; // cpu0 peripheral (ic) arbitration fast request + input [2:0] l2_cpu0_ic_id_arb_set; // cpu0 peripheral (ic) fill buffer id + input l2_cpu0_ic_write_arb_set; // cpu0 peripheral (ic) write indicator + input l2_cpu0_ic_excl_arb_set; // cpu0 peripheral (ic) exclusive indicator + input [2:0] l2_cpu0_ic_elem_size_arb_set; // cpu0 peripheral (ic) element size + input l2_cpu0_ic_ns_arb_set; // cpu0 peripheral (ic) non-secure + input [15:0] l2_cpu0_ic_addr_arb_set; // cpu0 peripheral (ic) address + input [31:0] l2_cpu0_ic_data_arb_set; // cpu0 peripheral (ic) write data + + input l2_cpu0_wrq_almost_full; // cpu0 wrq almost full indicator + + input l2_cpu0_ls_wr_req_w2a; // cpu0 ls write request + input l2_cpu0_ls_wr_last_w2a; // cpu0 ls last indicator + input l2_cpu0_ls_wr_dirty_w2a; // cpu0 ls dirty indicator + input l2_cpu0_ls_wr_err_w2a; // cpu0 ls error indicator + input [2:0] l2_cpu0_ls_wr_type_w2a; // cpu0 ls write type + input [4:0] l2_cpu0_ls_wr_ccb_id_w2a; // cpu0 ls ccb id + input [127:0] l2_cpu0_ls_wr_data_w2a; // cpu0 ls write data + + input l2_cpu0_ls_ccb_resp; // cpu0 ls ccb resp + input [4:0] l2_cpu0_ls_ccb_resp_id; // cpu0 ls ccb id + input l2_cpu0_ls_ccb_data_wr; // cpu0 ls ccb data xfer + + input l2_cpu0_if_ccb_resp; // cpu0 if ccb resp + input [4:0] l2_cpu0_if_ccb_resp_id; // cpu0 if ccb id + + input l2_cpu0_tw_ccb_resp; // cpu0 tw ccb resp + input [4:0] l2_cpu0_tw_ccb_resp_id; // cpu0 tw ccb id + + input l2_cpu0_if_sync_done_q; // cpu0 sync response + input l2_cpu0_tlb_sync_done_q; // cpu0 tlb sync response + + input [5:0] l2_cpu0_lrq_haz_clr_id_dcd_q; // cpu0 lrq clear hazard id + input [15:0] l2_cpu0_wrq_haz_clr_id_dcd_q; // cpu0 wrq clear hazard id + input [3:0] l2_cpu0_ls_rd_haz_id_arb_q; // cpu0 ls rd wrq hazard id + input [2:0] l2_cpu0_ls_wr_haz_id_arb_q; // cpu0 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + input l2_cpu1_idle_wakeup_q; // cpu1 idle wakeup + input l2_cpu1_rd_arb_fast; // cpu1 read arbitration fast request + input [4:0] l2_cpu1_rd_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu1_rd_lrq_id_arb_set; // cpu1 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu1_rd_type_arb_set; // cpu1 read arbitration type + input [2:0] l2_cpu1_rd_cache_attr_arb_set; // cpu1 read arbitration cache attributes + input [7:0] l2_cpu1_rd_page_attr_arb_set; // cpu1 read arbitration page attributes + input [2:0] l2_cpu1_rd_elem_size_arb_set; // cpu1 read arbitration element size + input l2_cpu1_rd_way_arb_set; // cpu1 read arbitration way + input l2_cpu1_rd_replayed_arb_set; // cpu1 read arbitration replayed + input l2_cpu1_rd_excl_arb_set; // cpu1 read arbitration exclusive + input l2_cpu1_rd_priv_arb_set; // cpu1 read arbitration priv + input [1:0] l2_cpu1_rd_shared_arb_set; // cpu1 read arbitration shared + input l2_cpu1_rd_va48_arb_set; // cpu1 read arbitration va48 + input l2_cpu1_rd_aarch64_arb_set; // cpu1 read arbitration aarch64 + input [15:8] l2_cpu1_rd_asid_arb_set; // cpu1 read arbitration asid + input l2_cpu1_rd_prfm_arb_set; // cpu1 read arbitration prfm + input [44:0] l2_cpu1_rd_addr_arb_set; // cpu1 read arbitration address + input l2_cpu1_rd_bypass_arb_set; // cpu1 read arbitration bypass + input l2_cpu1_rd_bypass_req_can_e5; // cpu1 read arbitration bypass cancelled request + input l2_cpu1_early_rd_reqe4_e5_q; // cpu1 read arbitration bypass cancelled request + input l2_cpu1_rd_bypass_way_e5; // cpu1 read arbitration bypass way + input [2:0] l2_cpu1_rd_bypass_bufid_e5; // cpu1 read arbitration bypass bufid + input [2:0] l2_cpu1_rd_bypass_lrq_id_e5; // cpu1 read arbitration bypass bufid + + input l2_cpu1_wr_arb_fast; // cpu1 write arbitration fast request + input [3:0] l2_cpu1_wr_id_arb_set; // cpu1 write arbitration id for 1st qw + input [3:0] l2_cpu1_wr_partial_dw_arb_set; // cpu1 write partial qw byte strobe indicator + input [2:0] l2_cpu1_wr_cache_attr_arb_set; // cpu1 write arbitration cache attributes + input [7:0] l2_cpu1_wr_page_attr_arb_set; // cpu1 write arbitration page attributes + input [2:0] l2_cpu1_wr_elem_size_arb_set; // cpu1 write arbitration element size + input [2:0] l2_cpu1_wr_type_arb_set; // cpu1 write arbitration type + input [11:0] l2_cpu1_wr_cl_id_arb_set; // cpu1 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu1_wr_priv_arb_set; // cpu1 write arbitration priv + input [1:0] l2_cpu1_wr_shared_arb_set; // cpu1 write arbitration shared + input l2_cpu1_wr_last_arb_set; // cpu1 write arbitration last + input l2_cpu1_wr_clean_evict_arb_set; // cpu1 write arbitration clean eviction + input l2_cpu1_wr_err_arb_set; // cpu1 write arbitration error + input l2_cpu1_wr_way_arb_set; // cpu1 write arbitration way + input l2_cpu1_wr_dirty_arb_set; // cpu1 write arbitration dirty + input l2_cpu1_wr_1st_replayed_arb_set; // cpu1 write arbitration 1st replay indicator + input [44:0] l2_cpu1_wr_addr_arb_set; // cpu1 write arbitration address + input l2_cpu1_ic_arb_fast; // cpu1 peripheral (ic) arbitration fast request + input [2:0] l2_cpu1_ic_id_arb_set; // cpu1 peripheral (ic) fill buffer id + input l2_cpu1_ic_write_arb_set; // cpu1 peripheral (ic) write indicator + input l2_cpu1_ic_excl_arb_set; // cpu1 peripheral (ic) exclusive indicator + input [2:0] l2_cpu1_ic_elem_size_arb_set; // cpu1 peripheral (ic) element size + input l2_cpu1_ic_ns_arb_set; // cpu1 peripheral (ic) non-secure + input [15:0] l2_cpu1_ic_addr_arb_set; // cpu1 peripheral (ic) address + input [31:0] l2_cpu1_ic_data_arb_set; // cpu1 peripheral (ic) write data + + input l2_cpu1_wrq_almost_full; // cpu1 wrq almost full indicator + + input l2_cpu1_ls_wr_req_w2a; // cpu1 ls write request + input l2_cpu1_ls_wr_last_w2a; // cpu1 ls last indicator + input l2_cpu1_ls_wr_dirty_w2a; // cpu1 ls dirty indicator + input l2_cpu1_ls_wr_err_w2a; // cpu1 ls error indicator + input [2:0] l2_cpu1_ls_wr_type_w2a; // cpu1 ls write type + input [4:0] l2_cpu1_ls_wr_ccb_id_w2a; // cpu1 ls ccb id + input [127:0] l2_cpu1_ls_wr_data_w2a; // cpu1 ls write data + + input l2_cpu1_ls_ccb_resp; // cpu1 ls ccb resp + input [4:0] l2_cpu1_ls_ccb_resp_id; // cpu1 ls ccb id + input l2_cpu1_ls_ccb_data_wr; // cpu1 ls ccb data xfer + + input l2_cpu1_if_ccb_resp; // cpu1 if ccb resp + input [4:0] l2_cpu1_if_ccb_resp_id; // cpu1 if ccb id + + input l2_cpu1_tw_ccb_resp; // cpu1 tw ccb resp + input [4:0] l2_cpu1_tw_ccb_resp_id; // cpu1 tw ccb id + + input l2_cpu1_if_sync_done_q; // cpu1 sync response + input l2_cpu1_tlb_sync_done_q; // cpu1 tlb sync response + + input [5:0] l2_cpu1_lrq_haz_clr_id_dcd_q; // cpu1 lrq clear hazard id + input [15:0] l2_cpu1_wrq_haz_clr_id_dcd_q; // cpu1 wrq clear hazard id + input [3:0] l2_cpu1_ls_rd_haz_id_arb_q; // cpu1 ls rd wrq hazard id + input [2:0] l2_cpu1_ls_wr_haz_id_arb_q; // cpu1 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + input l2_cpu2_idle_wakeup_q; // cpu2 idle wakeup + input l2_cpu2_rd_arb_fast; // cpu2 read arbitration fast request + input [4:0] l2_cpu2_rd_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu2_rd_lrq_id_arb_set; // cpu2 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu2_rd_type_arb_set; // cpu2 read arbitration type + input [2:0] l2_cpu2_rd_cache_attr_arb_set; // cpu2 read arbitration cache attributes + input [7:0] l2_cpu2_rd_page_attr_arb_set; // cpu2 read arbitration page attributes + input [2:0] l2_cpu2_rd_elem_size_arb_set; // cpu2 read arbitration element size + input l2_cpu2_rd_way_arb_set; // cpu2 read arbitration way + input l2_cpu2_rd_replayed_arb_set; // cpu2 read arbitration replayed + input l2_cpu2_rd_excl_arb_set; // cpu2 read arbitration exclusive + input l2_cpu2_rd_priv_arb_set; // cpu2 read arbitration priv + input [1:0] l2_cpu2_rd_shared_arb_set; // cpu2 read arbitration shared + input l2_cpu2_rd_va48_arb_set; // cpu0 read arbitration va48 + input l2_cpu2_rd_aarch64_arb_set; // cpu2 read arbitration aarch64 + input [15:8] l2_cpu2_rd_asid_arb_set; // cpu2 read arbitration asid + input l2_cpu2_rd_prfm_arb_set; // cpu2 read arbitration prfm + input [44:0] l2_cpu2_rd_addr_arb_set; // cpu2 read arbitration address + input l2_cpu2_rd_bypass_arb_set; // cpu2 read arbitration bypass + input l2_cpu2_rd_bypass_req_can_e5; // cpu2 read arbitration bypass cancelled request + input l2_cpu2_early_rd_reqe4_e5_q; // cpu2 read arbitration bypass cancelled request + input l2_cpu2_rd_bypass_way_e5; // cpu2 read arbitration bypass way + input [2:0] l2_cpu2_rd_bypass_bufid_e5; // cpu2 read arbitration bypass bufid + input [2:0] l2_cpu2_rd_bypass_lrq_id_e5; // cpu2 read arbitration bypass bufid + + input l2_cpu2_wr_arb_fast; // cpu2 write arbitration fast request + input [3:0] l2_cpu2_wr_id_arb_set; // cpu2 write arbitration id for 1st qw + input [3:0] l2_cpu2_wr_partial_dw_arb_set; // cpu2 write partial qw byte strobe indicator + input [2:0] l2_cpu2_wr_cache_attr_arb_set; // cpu2 write arbitration cache attributes + input [7:0] l2_cpu2_wr_page_attr_arb_set; // cpu2 write arbitration page attributes + input [2:0] l2_cpu2_wr_elem_size_arb_set; // cpu2 write arbitration element size + input [2:0] l2_cpu2_wr_type_arb_set; // cpu2 write arbitration type + input [11:0] l2_cpu2_wr_cl_id_arb_set; // cpu2 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu2_wr_priv_arb_set; // cpu2 write arbitration priv + input [1:0] l2_cpu2_wr_shared_arb_set; // cpu2 write arbitration shared + input l2_cpu2_wr_last_arb_set; // cpu2 write arbitration last + input l2_cpu2_wr_clean_evict_arb_set; // cpu2 write arbitration clean eviction + input l2_cpu2_wr_err_arb_set; // cpu2 write arbitration error + input l2_cpu2_wr_way_arb_set; // cpu2 write arbitration way + input l2_cpu2_wr_dirty_arb_set; // cpu2 write arbitration dirty + input l2_cpu2_wr_1st_replayed_arb_set; // cpu2 write arbitration 1st replay indicator + input [44:0] l2_cpu2_wr_addr_arb_set; // cpu2 write arbitration address + input l2_cpu2_ic_arb_fast; // cpu2 peripheral (ic) arbitration fast request + input [2:0] l2_cpu2_ic_id_arb_set; // cpu2 peripheral (ic) fill buffer id + input l2_cpu2_ic_write_arb_set; // cpu2 peripheral (ic) write indicator + input l2_cpu2_ic_excl_arb_set; // cpu2 peripheral (ic) exclusive indicator + input [2:0] l2_cpu2_ic_elem_size_arb_set; // cpu2 peripheral (ic) element size + input l2_cpu2_ic_ns_arb_set; // cpu2 peripheral (ic) non-secure + input [15:0] l2_cpu2_ic_addr_arb_set; // cpu2 peripheral (ic) address + input [31:0] l2_cpu2_ic_data_arb_set; // cpu2 peripheral (ic) write data + + input l2_cpu2_wrq_almost_full; // cpu2 wrq almost full indicator + + input l2_cpu2_ls_wr_req_w2a; // cpu2 ls write request + input l2_cpu2_ls_wr_last_w2a; // cpu2 ls last indicator + input l2_cpu2_ls_wr_dirty_w2a; // cpu2 ls dirty indicator + input l2_cpu2_ls_wr_err_w2a; // cpu2 ls error indicator + input [2:0] l2_cpu2_ls_wr_type_w2a; // cpu2 ls write type + input [4:0] l2_cpu2_ls_wr_ccb_id_w2a; // cpu2 ls ccb id + input [127:0] l2_cpu2_ls_wr_data_w2a; // cpu2 ls write data + + input l2_cpu2_ls_ccb_resp; // cpu2 ls ccb resp + input [4:0] l2_cpu2_ls_ccb_resp_id; // cpu2 ls ccb id + input l2_cpu2_ls_ccb_data_wr; // cpu2 ls ccb data xfer + + input l2_cpu2_if_ccb_resp; // cpu2 if ccb resp + input [4:0] l2_cpu2_if_ccb_resp_id; // cpu2 if ccb id + + input l2_cpu2_tw_ccb_resp; // cpu2 tw ccb resp + input [4:0] l2_cpu2_tw_ccb_resp_id; // cpu2 tw ccb id + + input l2_cpu2_if_sync_done_q; // cpu2 sync response + input l2_cpu2_tlb_sync_done_q; // cpu2 tlb sync response + + input [5:0] l2_cpu2_lrq_haz_clr_id_dcd_q; // cpu2 lrq clear hazard id + input [15:0] l2_cpu2_wrq_haz_clr_id_dcd_q; // cpu2 wrq clear hazard id + input [3:0] l2_cpu2_ls_rd_haz_id_arb_q; // cpu2 ls rd wrq hazard id + input [2:0] l2_cpu2_ls_wr_haz_id_arb_q; // cpu2 ls wr lrq hazard id + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + input l2_cpu3_idle_wakeup_q; // cpu3 idle wakeup + input l2_cpu3_rd_arb_fast; // cpu3 read arbitration fast request + input [4:0] l2_cpu3_rd_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator + input [2:0] l2_cpu3_rd_lrq_id_arb_set; // cpu3 read arbitration fill buffer id + I/D indicator + input [6:0] l2_cpu3_rd_type_arb_set; // cpu3 read arbitration type + input [2:0] l2_cpu3_rd_cache_attr_arb_set; // cpu3 read arbitration cache attributes + input [7:0] l2_cpu3_rd_page_attr_arb_set; // cpu3 read arbitration page attributes + input [2:0] l2_cpu3_rd_elem_size_arb_set; // cpu3 read arbitration element size + input l2_cpu3_rd_way_arb_set; // cpu3 read arbitration way + input l2_cpu3_rd_replayed_arb_set; // cpu3 read arbitration replayed + input l2_cpu3_rd_excl_arb_set; // cpu3 read arbitration exclusive + input l2_cpu3_rd_priv_arb_set; // cpu3 read arbitration priv + input [1:0] l2_cpu3_rd_shared_arb_set; // cpu3 read arbitration shared + input l2_cpu3_rd_va48_arb_set; // cpu3 read arbitration va48 + input l2_cpu3_rd_aarch64_arb_set; // cpu3 read arbitration aarch64 + input [15:8] l2_cpu3_rd_asid_arb_set; // cpu3 read arbitration asid + input l2_cpu3_rd_prfm_arb_set; // cpu3 read arbitration prfm + input [44:0] l2_cpu3_rd_addr_arb_set; // cpu3 read arbitration address + input l2_cpu3_rd_bypass_arb_set; // cpu3 read arbitration bypass + input l2_cpu3_rd_bypass_req_can_e5; // cpu3 read arbitration bypass cancelled request + input l2_cpu3_early_rd_reqe4_e5_q; // cpu3 read arbitration bypass cancelled request + input l2_cpu3_rd_bypass_way_e5; // cpu3 read arbitration bypass way + input [2:0] l2_cpu3_rd_bypass_bufid_e5; // cpu3 read arbitration bypass bufid + input [2:0] l2_cpu3_rd_bypass_lrq_id_e5; // cpu3 read arbitration bypass bufid + + input l2_cpu3_wr_arb_fast; // cpu3 write arbitration fast request + input [3:0] l2_cpu3_wr_id_arb_set; // cpu3 write arbitration id for 1st qw + input [3:0] l2_cpu3_wr_partial_dw_arb_set; // cpu3 write partial qw byte strobe indicator + input [2:0] l2_cpu3_wr_cache_attr_arb_set; // cpu3 write arbitration cache attributes + input [7:0] l2_cpu3_wr_page_attr_arb_set; // cpu3 write arbitration page attributes + input [2:0] l2_cpu3_wr_elem_size_arb_set; // cpu3 write arbitration element size + input [2:0] l2_cpu3_wr_type_arb_set; // cpu3 write arbitration type + input [11:0] l2_cpu3_wr_cl_id_arb_set; // cpu3 write arbitration cacheline ids for 2nd, 3rd, 4th qws + input l2_cpu3_wr_priv_arb_set; // cpu3 write arbitration priv + input [1:0] l2_cpu3_wr_shared_arb_set; // cpu3 write arbitration shared + input l2_cpu3_wr_last_arb_set; // cpu3 write arbitration last + input l2_cpu3_wr_clean_evict_arb_set; // cpu3 write arbitration clean eviction + input l2_cpu3_wr_err_arb_set; // cpu3 write arbitration error + input l2_cpu3_wr_way_arb_set; // cpu3 write arbitration way + input l2_cpu3_wr_dirty_arb_set; // cpu3 write arbitration dirty + input l2_cpu3_wr_1st_replayed_arb_set; // cpu3 write arbitration 1st replay indicator + input [44:0] l2_cpu3_wr_addr_arb_set; // cpu3 write arbitration address + input l2_cpu3_ic_arb_fast; // cpu3 peripheral (ic) arbitration fast request + input [2:0] l2_cpu3_ic_id_arb_set; // cpu3 peripheral (ic) fill buffer id + input l2_cpu3_ic_write_arb_set; // cpu3 peripheral (ic) write indicator + input l2_cpu3_ic_excl_arb_set; // cpu3 peripheral (ic) exclusive indicator + input [2:0] l2_cpu3_ic_elem_size_arb_set; // cpu3 peripheral (ic) element size + input l2_cpu3_ic_ns_arb_set; // cpu3 peripheral (ic) non-secure + input [15:0] l2_cpu3_ic_addr_arb_set; // cpu3 peripheral (ic) address + input [31:0] l2_cpu3_ic_data_arb_set; // cpu3 peripheral (ic) write data + + input l2_cpu3_wrq_almost_full; // cpu3 wrq almost full indicator + + input l2_cpu3_ls_wr_req_w2a; // cpu3 ls write request + input l2_cpu3_ls_wr_last_w2a; // cpu3 ls last indicator + input l2_cpu3_ls_wr_dirty_w2a; // cpu3 ls dirty indicator + input l2_cpu3_ls_wr_err_w2a; // cpu3 ls error indicator + input [2:0] l2_cpu3_ls_wr_type_w2a; // cpu3 ls write type + input [4:0] l2_cpu3_ls_wr_ccb_id_w2a; // cpu3 ls ccb id + input [127:0] l2_cpu3_ls_wr_data_w2a; // cpu3 ls write data + + input l2_cpu3_ls_ccb_resp; // cpu3 ls ccb resp + input [4:0] l2_cpu3_ls_ccb_resp_id; // cpu3 ls ccb id + input l2_cpu3_ls_ccb_data_wr; // cpu3 ls ccb data xfer + + input l2_cpu3_if_ccb_resp; // cpu3 if ccb resp + input [4:0] l2_cpu3_if_ccb_resp_id; // cpu3 if ccb id + + input l2_cpu3_tw_ccb_resp; // cpu3 tw ccb resp + input [4:0] l2_cpu3_tw_ccb_resp_id; // cpu3 tw ccb id + + input l2_cpu3_if_sync_done_q; // cpu3 sync response + input l2_cpu3_tlb_sync_done_q; // cpu3 tlb sync response + + input [5:0] l2_cpu3_lrq_haz_clr_id_dcd_q; // cpu3 lrq clear hazard id + input [15:0] l2_cpu3_wrq_haz_clr_id_dcd_q; // cpu3 wrq clear hazard id + input [3:0] l2_cpu3_ls_rd_haz_id_arb_q; // cpu3 ls rd wrq hazard id + input [2:0] l2_cpu3_ls_wr_haz_id_arb_q; // cpu3 ls wr lrq hazard id + +// END L2-CPU interface + +//------------------------------------------------------------------- +// TM interface +//------------------------------------------------------------------- +// BEGIN TIMER-CPU interface + output [3:0] tm_cpu0_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu0_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu1_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu1_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu2_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu2_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> + + output [3:0] tm_cpu3_cntkctl_usr; // User accessibility of CNTPCT,CNTVCT,CNTV_<>,CNTP_<> + output [1:0] tm_cpu3_cnthctl_kernel; // NS Kernel access of CNTPCT,CNTP_<> +// END TIMER-CPU interface + +//----------------------------------------------------------------------------- +// IC interface +//----------------------------------------------------------------------------- + input ls_cpu0_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu0_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu0_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu0_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu0_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu0_raw_eae_secure; // LS S LPAE to IC + + input ds_cpu0_ic_sample_spr; + input [4:0] ds_cpu0_ic_cpsr_mode; + input ds_cpu0_ic_aa64naa32; + input ds_cpu0_ic_hcr_change; + input ds_cpu0_ic_scr_change; +// BEGIN INCLUDE FOR CPU1 + input ds_cpu1_ic_sample_spr; + input [4:0] ds_cpu1_ic_cpsr_mode; + input ds_cpu1_ic_aa64naa32; + input ds_cpu1_ic_hcr_change; + input ds_cpu1_ic_scr_change; + input ls_cpu1_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu1_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu1_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu1_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu1_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu1_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU1 +// BEGIN INCLUDE FOR CPU2 + input ds_cpu2_ic_sample_spr; + input [4:0] ds_cpu2_ic_cpsr_mode; + input ds_cpu2_ic_hcr_change; + input ds_cpu2_ic_scr_change; + input ds_cpu2_ic_aa64naa32; + input ls_cpu2_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu2_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu2_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu2_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu2_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu2_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU2 +// BEGIN INCLUDE FOR CPU3 + input ds_cpu3_ic_sample_spr; + input [4:0] ds_cpu3_ic_cpsr_mode; + input ds_cpu3_ic_hcr_change; + input ds_cpu3_ic_scr_change; + input ds_cpu3_ic_aa64naa32; + input ls_cpu3_imp_abort_slv; // LS Imprecise Abort SEI + input ls_cpu3_imp_abort_ecc; // LS Imprecise Abort REI + input ls_cpu3_imp_abort_dec; // LS Imprecise Abort DEC + input ls_cpu3_imp_abort_containable; // LS Imprecise Abort is Containable + input ls_cpu3_raw_eae_nonsec; // LS NS LPAE to IC + input ls_cpu3_raw_eae_secure; // LS S LPAE to IC +// END INCLUDE FOR CPU3 + + output [`MAIA_CN:0] ic_nfiq; // IC physical FIQ + output [`MAIA_CN:0] ic_nirq; // IC physical IRQ + output [`MAIA_CN:0] ic_nsei; // IC physical SEI + output [`MAIA_CN:0] ic_nvfiq; // IC virtual FIQ + output [`MAIA_CN:0] ic_nvirq; // IC virtual IRQ + output [`MAIA_CN:0] ic_nvsei; // IC virtual SEI + output [`MAIA_CN:0] ic_p_valid; // IC is present + + output [`MAIA_CN:0] ic_sample_spr; // IC sample signal for TC, TALL*, EL* signals + output [`MAIA_CN:0] ic_hcr_change_complete; + output [`MAIA_CN:0] ic_scr_change_complete; + output [`MAIA_CN:0] ic_el_change_complete; + output [`MAIA_CN:0] ic_ich_el2_tc; // IC trap common + output [`MAIA_CN:0] ic_ich_el2_tall0; // IC trap all grp0 + output [`MAIA_CN:0] ic_ich_el2_tall1; // IC trap all grp1 + output [`MAIA_CN:0] ic_sra_el3_en; // IC System Registers enabled in EL3 + output [`MAIA_CN:0] ic_sra_el1s_en; // IC System Registers enabled in EL1S + output [`MAIA_CN:0] ic_sra_el2_en; // IC System Registers enabled in EL2 + output [`MAIA_CN:0] ic_sra_el1ns_en; // IC System Registers enabled in EL1NS + output [`MAIA_CN:0] ic_sre_el1ns_hyp_trap; // IC HYP_TRAP EL1NS accesses + output [`MAIA_CN:0] ic_sre_el1ns_mon_trap; // IC MON_TRAP EL1NS accesses + output [`MAIA_CN:0] ic_sre_el1s_mon_trap; // IC MON_TRAP EL1S accesses + output [`MAIA_CN:0] ic_sre_el2_mon_trap; // IC MON_TRAP EL2 accesses + output [`MAIA_CN:0] ic_block_eoi_sgi_wr; // IC Block all EOI and SGI write accesses + +//----------------------------------------------------------------------------- +// DT interface +//----------------------------------------------------------------------------- +// BEGIN DT-CPU interface +//----------------------------------------------------------------------------- +// ucpu0 +//----------------------------------------------------------------------------- + output dt_cpu0_dbif_req_pclk; // Debug Interface Req + output dt_cpu0_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu0_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu0_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu0_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu0_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu0_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu0_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu0_edbgrq_pclk; // External Debug Request + output dt_cpu0_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu0_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu0_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu0_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu0_et_oslock_gclk; // ETM OS Lock + input dt_cpu0_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu0_halt_ack_gclk; // Core Halted + input dt_cpu0_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu0_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu0_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu0_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu0_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu0_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu0_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu0_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu0_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu0_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu0_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu0_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu0_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu0_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu0_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu0_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu1 +//----------------------------------------------------------------------------- + output dt_cpu1_dbif_req_pclk; // Debug Interface Req + output dt_cpu1_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu1_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu1_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu1_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu1_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu1_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu1_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu1_edbgrq_pclk; // External Debug Request + output dt_cpu1_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu1_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu1_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu1_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu1_et_oslock_gclk; // ETM OS Lock + input dt_cpu1_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu1_halt_ack_gclk; // Core Halted + input dt_cpu1_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu1_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu1_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu1_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu1_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu1_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu1_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu1_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu1_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu1_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu1_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu1_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu1_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu1_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu1_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu1_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu2 +//----------------------------------------------------------------------------- + output dt_cpu2_dbif_req_pclk; // Debug Interface Req + output dt_cpu2_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu2_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu2_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu2_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu2_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu2_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu2_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu2_edbgrq_pclk; // External Debug Request + output dt_cpu2_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu2_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu2_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu2_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu2_et_oslock_gclk; // ETM OS Lock + input dt_cpu2_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu2_halt_ack_gclk; // Core Halted + input dt_cpu2_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu2_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu2_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu2_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu2_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu2_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu2_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu2_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu2_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu2_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu2_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu2_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu2_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu2_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu2_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu2_noclkstop_pclk; // force CPU clock on from DT-PCLK + +//----------------------------------------------------------------------------- +// ucpu3 +//----------------------------------------------------------------------------- + output dt_cpu3_dbif_req_pclk; // Debug Interface Req + output dt_cpu3_dbif_write_pclk; // Debug Interface Write/!Read + output dt_cpu3_dbif_locked_pclk; // Debug Interface Lock Value + output [31:0] dt_cpu3_dbif_wrdata_pclk; // Debug Interface Write Data + output [14:2] dt_cpu3_dbif_addr_pclk; // Debug Interface Addr + output dt_cpu3_edecr_osuce_pclk; // OS Unlock Catch Enable Bit + output dt_cpu3_edecr_rce_pclk; // EDECR Reset Catch Enable Bit + output dt_cpu3_edecr_ss_pclk; // EDECR Halting Step Enable Bit + output dt_cpu3_edbgrq_pclk; // External Debug Request + output dt_cpu3_edacr_frc_idleack_pclk; // EDACR Force Debug Idle Ack + output dt_cpu3_edprcr_corepurq_pclk; // PRCR Power Up Request + + input dt_cpu3_pmusnapshot_ack_gclk; // PMU Snapshot Trigger acknowledge + output dt_cpu3_pmusnapshot_req_pclk; // PMU Snapshot Trigger request + + input dt_cpu3_et_oslock_gclk; // ETM OS Lock + input dt_cpu3_os_double_lock_gclk; // Debug OS Double Lock + input dt_cpu3_halt_ack_gclk; // Core Halted + input dt_cpu3_coredbg_in_reset_gclk; // Core debug logic is in reset state + input dt_cpu3_wfx_dbg_req_gclk; // Debug request when core is in stand by mode + input dt_cpu3_hlt_dbgevt_ok_gclk; // Halt debug permitted to wake up the cpu from wfi/wfe + input dt_cpu3_dbif_ack_gclk; // Debug Interface Ack + input dt_cpu3_dbif_err_gclk; // Debug Interface Error + input [31:0] dt_cpu3_dbif_rddata_gclk; // Debug Interface Read Data + + output [3:0] dt_cpu3_cti_trigout_7to4_pclk; // Trigger output bits [7:4] to cpu + output [1:0] dt_cpu3_cti_trigout_1to0_pclk; // Trigger output bits [1:0] to cpu + output [3:0] dt_cpu3_cti_triginack_7to4_pclk; // Trigger input ack bits [7:4] to cpu + output [1:0] dt_cpu3_cti_triginack_1to0_pclk; // Trigger input ack bits [1:0] to cpu + + input [3:0] dt_cpu3_cti_trigin_7to4_gclk; // Trigger input bits [7:4] from cpu + input [1:0] dt_cpu3_cti_trigin_1to0_gclk; // Trigger input bits [1:0] from cpu + input [3:0] dt_cpu3_cti_trigoutack_7to4_gclk; // Trigger output ack bits [7:4] from cpu + input dt_cpu3_cti_trigoutack_bit1_gclk; // Trigger output ack bit 1 from cpu + + output dt_cpu3_wfx_wakeup_pclk; // WFI/WFE wakeup debug event + output dt_cpu3_noclkstop_pclk; // force CPU clock on from DT-PCLK +// END DT-CPU interface + +//----------------------------------------------------------------------------- +// CK interface +//----------------------------------------------------------------------------- +// BEGIN CK-CPU interface + input ds_cpu0_reset_req; // Warm Reset request + input ds_cpu0_wfi_req; // WFI request + input ds_cpu0_wfe_req; // WFI request + input ds_cpu0_flush; // flush for exception rtn + input [5:0] ds_cpu0_flush_type; // flush type + input ds_cpu0_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu0_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu0_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu0_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu0_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu0_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu0_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu0_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu0_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu0_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu0_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu0_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu0_hcr_va; // virtual abort + input ds_cpu0_hcr_vi; // virtual IRQ + input ds_cpu0_hcr_vf; // virtual FIQ + input [2:0] ds_cpu0_cpuectlr_ret; // CPU Retention control + output ck_cpu0_event_reg; // WFE event reg + output ck_cpu0_wfi_ack; // WFI acknowledge to DS + output ck_cpu0_wfe_ack; // WFE acknowledge to DS + output ck_cpu0_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu1_reset_req; // Warm Reset request + input ds_cpu1_wfi_req; // WFI request + input ds_cpu1_wfe_req; // WFI request + input ds_cpu1_flush; // flush for exception rtn + input [5:0] ds_cpu1_flush_type; // flush type + input ds_cpu1_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu1_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu1_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu1_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu1_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu1_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu1_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu1_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu1_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu1_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu1_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu1_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu1_hcr_va; // virtual abort + input ds_cpu1_hcr_vi; // virtual IRQ + input ds_cpu1_hcr_vf; // virtual FIQ + input [2:0] ds_cpu1_cpuectlr_ret; // CPU Retention control + output ck_cpu1_event_reg; // WFE event reg + output ck_cpu1_wfi_ack; // WFI acknowledge to DS + output ck_cpu1_wfe_ack; // WFE acknowledge to DS + output ck_cpu1_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu2_reset_req; // Warm Reset request + input ds_cpu2_wfi_req; // WFI request + input ds_cpu2_wfe_req; // WFI request + input ds_cpu2_flush; // flush for exception rtn + input [5:0] ds_cpu2_flush_type; // flush type + input ds_cpu2_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu2_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu2_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu2_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu2_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu2_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu2_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu2_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu2_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu2_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu2_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu2_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu2_hcr_va; // virtual abort + input ds_cpu2_hcr_vi; // virtual IRQ + input ds_cpu2_hcr_vf; // virtual FIQ + input [2:0] ds_cpu2_cpuectlr_ret; // CPU Retention control + output ck_cpu2_event_reg; // WFE event reg + output ck_cpu2_wfi_ack; // WFI acknowledge to DS + output ck_cpu2_wfe_ack; // WFE acknowledge to DS + output ck_cpu2_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ds_cpu3_reset_req; // Warm Reset request + input ds_cpu3_wfi_req; // WFI request + input ds_cpu3_wfe_req; // WFI request + input ds_cpu3_flush; // flush for exception rtn + input [5:0] ds_cpu3_flush_type; // flush type + input ds_cpu3_imp_abrt_wfi_qual; // physical abort qual for WFI + input ds_cpu3_irq_wfi_qual; // physical IRQ qual for WFI + input ds_cpu3_fiq_wfi_qual; // physical FIQ qual for WFI + input ds_cpu3_vimp_abrt_wfi_qual; // virtual abort qual for WFI + input ds_cpu3_virq_wfi_qual; // virtual IRQ qual for WFI + input ds_cpu3_vfiq_wfi_qual; // virtual FIQ qual for WFI + input ds_cpu3_imp_abrt_wfe_qual; // physical abort qual for WFE + input ds_cpu3_irq_wfe_qual; // physical IRQ qual for WFE + input ds_cpu3_fiq_wfe_qual; // physical FIQ qual for WFE + input ds_cpu3_vimp_abrt_wfe_qual; // virtual abort qual for WFE + input ds_cpu3_virq_wfe_qual; // virtual IRQ qual for WFE + input ds_cpu3_vfiq_wfe_qual; // virtual FIQ qual for WFE + input ds_cpu3_hcr_va; // virtual abort + input ds_cpu3_hcr_vi; // virtual IRQ + input ds_cpu3_hcr_vf; // virtual FIQ + input [2:0] ds_cpu3_cpuectlr_ret; // CPU Retention control + output ck_cpu3_event_reg; // WFE event reg + output ck_cpu3_wfi_ack; // WFI acknowledge to DS + output ck_cpu3_wfe_ack; // WFE acknowledge to DS + output ck_cpu3_crcx_clk_en_n; // 2nd-level CPU clock-gating enable + + input ls_cpu0_clrexmon; // LS global exclusive monitor + input ls_cpu1_clrexmon; // LS global exclusive monitor + input ls_cpu2_clrexmon; // LS global exclusive monitor + input ls_cpu3_clrexmon; // LS global exclusive monitor + +// END CK-CPU interface + + output [`MAIA_CN:0] ck_gclkt; + + + + // wires + wire ck_areset_l2; + wire ck_cpu0_areset_l2cpu; + wire ck_cpu0_areset_l2dt; + wire ck_cpu0_commrx; + wire ck_cpu0_commtx; + wire ck_cpu0_crcx_clk_en_n_ic; + wire ck_cpu0_dbgnopwrdwn; + wire ck_cpu0_dbgrstreq; + wire ck_cpu0_dt_standbywfx; + wire ck_cpu0_dt_wfx_ack; + wire ck_cpu0_l2_standbywfi; + wire ck_cpu0_l2_standbywfx; + wire ck_cpu0_ncommirq; + wire ck_cpu0_npmuirq; + wire ck_cpu0_poreset_status; + wire ck_cpu0_reset1_n_l2cpu; + wire ck_cpu0_reset1_n_l2dt; + wire ck_cpu1_areset_l2cpu; + wire ck_cpu1_areset_l2dt; + wire ck_cpu1_commrx; + wire ck_cpu1_commtx; + wire ck_cpu1_crcx_clk_en_n_ic; + wire ck_cpu1_dbgnopwrdwn; + wire ck_cpu1_dbgrstreq; + wire ck_cpu1_dt_standbywfx; + wire ck_cpu1_dt_wfx_ack; + wire ck_cpu1_l2_standbywfi; + wire ck_cpu1_l2_standbywfx; + wire ck_cpu1_ncommirq; + wire ck_cpu1_npmuirq; + wire ck_cpu1_poreset_status; + wire ck_cpu1_reset1_n_l2cpu; + wire ck_cpu1_reset1_n_l2dt; + wire ck_cpu2_areset_l2cpu; + wire ck_cpu2_areset_l2dt; + wire ck_cpu2_commrx; + wire ck_cpu2_commtx; + wire ck_cpu2_crcx_clk_en_n_ic; + wire ck_cpu2_dbgnopwrdwn; + wire ck_cpu2_dbgrstreq; + wire ck_cpu2_dt_standbywfx; + wire ck_cpu2_dt_wfx_ack; + wire ck_cpu2_l2_standbywfi; + wire ck_cpu2_l2_standbywfx; + wire ck_cpu2_ncommirq; + wire ck_cpu2_npmuirq; + wire ck_cpu2_poreset_status; + wire ck_cpu2_reset1_n_l2cpu; + wire ck_cpu2_reset1_n_l2dt; + wire ck_cpu3_areset_l2cpu; + wire ck_cpu3_areset_l2dt; + wire ck_cpu3_commrx; + wire ck_cpu3_commtx; + wire ck_cpu3_crcx_clk_en_n_ic; + wire ck_cpu3_dbgnopwrdwn; + wire ck_cpu3_dbgrstreq; + wire ck_cpu3_dt_standbywfx; + wire ck_cpu3_dt_wfx_ack; + wire ck_cpu3_l2_standbywfi; + wire ck_cpu3_l2_standbywfx; + wire ck_cpu3_ncommirq; + wire ck_cpu3_npmuirq; + wire ck_cpu3_poreset_status; + wire ck_cpu3_reset1_n_l2cpu; + wire ck_cpu3_reset1_n_l2dt; + wire ck_dt_cpu0_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu0_cti_trigin_1to0_gclk; + wire ck_dt_cpu0_et_oslock_gclk; + wire ck_dt_cpu0_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu0_os_double_lock_gclk; + wire ck_dt_cpu0_pmusnapshot_ack_gclk; + wire ck_dt_cpu0_wfx_dbg_req_gclk; + wire ck_dt_cpu1_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu1_cti_trigin_1to0_gclk; + wire ck_dt_cpu1_et_oslock_gclk; + wire ck_dt_cpu1_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu1_os_double_lock_gclk; + wire ck_dt_cpu1_pmusnapshot_ack_gclk; + wire ck_dt_cpu1_wfx_dbg_req_gclk; + wire ck_dt_cpu2_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu2_cti_trigin_1to0_gclk; + wire ck_dt_cpu2_et_oslock_gclk; + wire ck_dt_cpu2_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu2_os_double_lock_gclk; + wire ck_dt_cpu2_pmusnapshot_ack_gclk; + wire ck_dt_cpu2_wfx_dbg_req_gclk; + wire ck_dt_cpu3_coredbg_in_reset_gclk; + wire [1:0] ck_dt_cpu3_cti_trigin_1to0_gclk; + wire ck_dt_cpu3_et_oslock_gclk; + wire ck_dt_cpu3_hlt_dbgevt_ok_gclk; + wire ck_dt_cpu3_os_double_lock_gclk; + wire ck_dt_cpu3_pmusnapshot_ack_gclk; + wire ck_dt_cpu3_wfx_dbg_req_gclk; + wire ck_gclkb0; + wire ck_gclkb1; + wire ck_gclkfr; + wire ck_gclkl2; + wire ck_gclktl2; + wire ck_l2_ace_inactive; + wire ck_l2_acp_inactive; + wire ck_l2_logic_clk_en; + wire ck_l2_sky_link_deactivate; + wire ck_l2_tbnk0_clk_en; + wire ck_l2_tbnk1_clk_en; + wire ck_reset1_n_l2; + wire clrexmon_c1; + wire ds_cpu0_ic_aa64naa32_i; + wire [4:0] ds_cpu0_ic_cpsr_mode_i; + wire ds_cpu0_ic_hcr_change_i; + wire ds_cpu0_ic_sample_spr_i; + wire ds_cpu0_ic_scr_change_i; + wire ds_cpu1_ic_aa64naa32_i; + wire [4:0] ds_cpu1_ic_cpsr_mode_i; + wire ds_cpu1_ic_hcr_change_i; + wire ds_cpu1_ic_sample_spr_i; + wire ds_cpu1_ic_scr_change_i; + wire ds_cpu2_ic_aa64naa32_i; + wire [4:0] ds_cpu2_ic_cpsr_mode_i; + wire ds_cpu2_ic_hcr_change_i; + wire ds_cpu2_ic_sample_spr_i; + wire ds_cpu2_ic_scr_change_i; + wire ds_cpu3_ic_aa64naa32_i; + wire [4:0] ds_cpu3_ic_cpsr_mode_i; + wire ds_cpu3_ic_hcr_change_i; + wire ds_cpu3_ic_sample_spr_i; + wire ds_cpu3_ic_scr_change_i; + wire dt_cpu0_apb_active_pclk; + wire dt_cpu0_poreset_status_ack_pclk; + wire dt_cpu0_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu0_wfx_wakeup_pclk; + wire dt_cpu1_apb_active_pclk; + wire dt_cpu1_poreset_status_ack_pclk; + wire dt_cpu1_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu1_wfx_wakeup_pclk; + wire dt_cpu2_apb_active_pclk; + wire dt_cpu2_poreset_status_ack_pclk; + wire dt_cpu2_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu2_wfx_wakeup_pclk; + wire dt_cpu3_apb_active_pclk; + wire dt_cpu3_poreset_status_ack_pclk; + wire dt_cpu3_trcauxctlr_sb_rcg_disable_pclk; + wire dt_cpu3_wfx_wakeup_pclk; + wire eventi_sev; + wire [`MAIA_CN:0] ic_block_eoi_sgi_wr_o; + wire ic_cpu0_l2_dsb_block; + wire [63:0] ic_cpu0_spr_rd_data; + wire ic_cpu1_l2_dsb_block; + wire [63:0] ic_cpu1_spr_rd_data; + wire ic_cpu2_l2_dsb_block; + wire [63:0] ic_cpu2_spr_rd_data; + wire ic_cpu3_l2_dsb_block; + wire [63:0] ic_cpu3_spr_rd_data; + wire [`MAIA_CN:0] ic_el_change_complete_o; + wire [`MAIA_CN:0] ic_hcr_change_complete_o; + wire [`MAIA_CN:0] ic_ich_el2_tall0_o; + wire [`MAIA_CN:0] ic_ich_el2_tall1_o; + wire [`MAIA_CN:0] ic_ich_el2_tc_o; + wire [`MAIA_CN:0] ic_nfiq_o; + wire [`MAIA_CN:0] ic_nirq_o; + wire [`MAIA_CN:0] ic_nsei_o; + wire [`MAIA_CN:0] ic_nvfiq_o; + wire [`MAIA_CN:0] ic_nvirq_o; + wire [`MAIA_CN:0] ic_nvsei_o; + wire [31:0] ic_p_rdata; + wire ic_p_rdata_valid; + wire ic_p_ready; + wire [`MAIA_CN:0] ic_sample_spr_o; + wire [`MAIA_CN:0] ic_scr_change_complete_o; + wire [`MAIA_CN:0] ic_sra_el1ns_en_o; + wire [`MAIA_CN:0] ic_sra_el1s_en_o; + wire [`MAIA_CN:0] ic_sra_el2_en_o; + wire [`MAIA_CN:0] ic_sra_el3_en_o; + wire [`MAIA_CN:0] ic_sre_el1ns_hyp_trap_o; + wire [`MAIA_CN:0] ic_sre_el1ns_mon_trap_o; + wire [`MAIA_CN:0] ic_sre_el1s_mon_trap_o; + wire [`MAIA_CN:0] ic_sre_el2_mon_trap_o; + wire l2_acp_flsh_rd_cnt_active_glb_l2_dly; + wire l2_acp_flsh_wr_cnt_active_glb_l2_dly; + wire l2_acp_rd_haz_vld_l2_dly_q; + wire l2_acp_wr_haz_vld_l2_dly_q; + wire l2_actlr_disable_b2b_setway_hzd_opt_x2_ns; + wire l2_actlr_disable_setway_opt; + wire l2_actlr_ncpu_rcg_enable; + wire l2_actlr_plru_dynamic; + wire l2_actlr_plru_en; + wire [1:0] l2_actlr_plru_mode; + wire l2_actlr_writeunique_disable; + wire l2_cfg_broadcastinner; + wire l2_cfg_broadcastouter; + wire l2_cpu0_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu0_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu0_snp_active; + wire l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu0_wr_decerr_q; + wire l2_cpu0_wr_slverr_q; + wire l2_cpu1_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu1_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu1_snp_active; + wire l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu1_wr_decerr_q; + wire l2_cpu1_wr_slverr_q; + wire l2_cpu2_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu2_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu2_snp_active; + wire l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu2_wr_decerr_q; + wire l2_cpu2_wr_slverr_q; + wire l2_cpu3_ls_rd_haz_vld_l2_dly_q; + wire l2_cpu3_ls_wr_haz_vld_l2_dly_q; + wire l2_cpu3_snp_active; + wire l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly; + wire l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly; + wire l2_cpu3_wr_decerr_q; + wire l2_cpu3_wr_slverr_q; + wire l2_ctlr_x1_wr_q; + wire [9:0] l2_ctlr_x2_ns; + wire l2_idle; + wire [`MAIA_CN:0] l2_mbist1_en_b1; + wire [16:0] l2_mbist2_tbnk0_addr_b1; + wire l2_mbist2_tbnk0_all_b1; + wire [2:0] l2_mbist2_tbnk0_array_b1; + wire [17:0] l2_mbist2_tbnk0_be_b1; + wire l2_mbist2_tbnk0_en_b1; + wire [143:0] l2_mbist2_tbnk0_indata_b1; + wire [143:0] l2_mbist2_tbnk0_outdata_b3; + wire l2_mbist2_tbnk0_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp0_outdata_b2; + wire l2_mbist2_tbnk0_snp0_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp0_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp1_outdata_b2; + wire l2_mbist2_tbnk0_snp1_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp1_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp2_outdata_b2; + wire l2_mbist2_tbnk0_snp2_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp2_sel_b1; + wire [79:0] l2_mbist2_tbnk0_snp3_outdata_b2; + wire l2_mbist2_tbnk0_snp3_outdata_vld_b2; + wire l2_mbist2_tbnk0_snp3_sel_b1; + wire l2_mbist2_tbnk0_wr_en_b1; + wire [16:0] l2_mbist2_tbnk1_addr_b1; + wire l2_mbist2_tbnk1_all_b1; + wire [2:0] l2_mbist2_tbnk1_array_b1; + wire [17:0] l2_mbist2_tbnk1_be_b1; + wire l2_mbist2_tbnk1_en_b1; + wire [143:0] l2_mbist2_tbnk1_indata_b1; + wire [143:0] l2_mbist2_tbnk1_outdata_b3; + wire l2_mbist2_tbnk1_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp0_outdata_b2; + wire l2_mbist2_tbnk1_snp0_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp0_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp1_outdata_b2; + wire l2_mbist2_tbnk1_snp1_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp1_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp2_outdata_b2; + wire l2_mbist2_tbnk1_snp2_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp2_sel_b1; + wire [79:0] l2_mbist2_tbnk1_snp3_outdata_b2; + wire l2_mbist2_tbnk1_snp3_outdata_vld_b2; + wire l2_mbist2_tbnk1_snp3_sel_b1; + wire l2_mbist2_tbnk1_wr_en_b1; + wire l2_no_ram_acc_nxt_cycle; + wire [13:0] l2_p_addr; + wire [1:0] l2_p_cpu; + wire l2_p_nsecure; + wire [2:0] l2_p_sel; + wire [31:0] l2_p_wdata; + wire l2_p_write; + wire l2_reset3; + wire l2_rstdisable_x1_q; + wire l2_sky_link_stopped; + wire l2_tbnk0_addr44_l3_q; + wire [44:0] l2_tbnk0_addr_l1; + wire [5:2] l2_tbnk0_addr_l6; + wire l2_tbnk0_all_tag_incl_active_l3; + wire l2_tbnk0_asq_cmp_evict_l3_q; + wire l2_tbnk0_asq_full_flsh; + wire l2_tbnk0_asq_nc_so_dev_limit; + wire [2:0] l2_tbnk0_cache_attr_l1; + wire l2_tbnk0_cfg_ecc_en; + wire l2_tbnk0_cmo_setway_l2_inv_incl_l4; + wire l2_tbnk0_cpu0_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu0_hit_l4; + wire l2_tbnk0_cpu0_l2_inv_l4_dly2; + wire l2_tbnk0_cpu0_l2hit_e_l4; + wire l2_tbnk0_cpu0_l2hit_s_l4; + wire l2_tbnk0_cpu0_peq_full_q; + wire l2_tbnk0_cpu0_peq_hit_q; + wire l2_tbnk0_cpu0_peq_self_evict_l3_q; + wire l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu0_rd_access_l4_dly; + wire l2_tbnk0_cpu0_self_evict_l4_dly_q; + wire l2_tbnk0_cpu0_single_ecc_err_l7_q; + wire l2_tbnk0_cpu0_snp_hit_e_l3; + wire l2_tbnk0_cpu0_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu0_snp_setway_addr_l3; + wire l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu0_vld_nxt_l5; + wire l2_tbnk0_cpu0_wr_access_l4_dly; + wire l2_tbnk0_cpu1_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu1_hit_l4; + wire l2_tbnk0_cpu1_l2_inv_l4_dly2; + wire l2_tbnk0_cpu1_l2hit_e_l4; + wire l2_tbnk0_cpu1_l2hit_s_l4; + wire l2_tbnk0_cpu1_peq_full_q; + wire l2_tbnk0_cpu1_peq_hit_q; + wire l2_tbnk0_cpu1_peq_self_evict_l3_q; + wire l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu1_rd_access_l4_dly; + wire l2_tbnk0_cpu1_self_evict_l4_dly_q; + wire l2_tbnk0_cpu1_single_ecc_err_l7_q; + wire l2_tbnk0_cpu1_snp_hit_e_l3; + wire l2_tbnk0_cpu1_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu1_snp_setway_addr_l3; + wire l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu1_vld_nxt_l5; + wire l2_tbnk0_cpu1_wr_access_l4_dly; + wire l2_tbnk0_cpu2_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu2_hit_l4; + wire l2_tbnk0_cpu2_l2_inv_l4_dly2; + wire l2_tbnk0_cpu2_l2hit_e_l4; + wire l2_tbnk0_cpu2_l2hit_s_l4; + wire l2_tbnk0_cpu2_peq_full_q; + wire l2_tbnk0_cpu2_peq_hit_q; + wire l2_tbnk0_cpu2_peq_self_evict_l3_q; + wire l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu2_rd_access_l4_dly; + wire l2_tbnk0_cpu2_self_evict_l4_dly_q; + wire l2_tbnk0_cpu2_single_ecc_err_l7_q; + wire l2_tbnk0_cpu2_snp_hit_e_l3; + wire l2_tbnk0_cpu2_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu2_snp_setway_addr_l3; + wire l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu2_vld_nxt_l5; + wire l2_tbnk0_cpu2_wr_access_l4_dly; + wire l2_tbnk0_cpu3_ccb_xfer_l4_dly2; + wire l2_tbnk0_cpu3_hit_l4; + wire l2_tbnk0_cpu3_l2_inv_l4_dly2; + wire l2_tbnk0_cpu3_l2hit_e_l4; + wire l2_tbnk0_cpu3_l2hit_s_l4; + wire l2_tbnk0_cpu3_peq_full_q; + wire l2_tbnk0_cpu3_peq_hit_q; + wire l2_tbnk0_cpu3_peq_self_evict_l3_q; + wire l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q; + wire l2_tbnk0_cpu3_rd_access_l4_dly; + wire l2_tbnk0_cpu3_self_evict_l4_dly_q; + wire l2_tbnk0_cpu3_single_ecc_err_l7_q; + wire l2_tbnk0_cpu3_snp_hit_e_l3; + wire l2_tbnk0_cpu3_snp_hit_s_l3; + wire [44:14] l2_tbnk0_cpu3_snp_setway_addr_l3; + wire l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk0_cpu3_vld_nxt_l5; + wire l2_tbnk0_cpu3_wr_access_l4_dly; + wire [3:0] l2_tbnk0_cpu_rvalid_init_nxt_l5; + wire [3:0] l2_tbnk0_cpu_rvalid_nxt_l5; + wire [3:0] l2_tbnk0_cpu_snp_hit_e_l4_q; + wire l2_tbnk0_crit_qw_nxt_l5; + wire [143:0] l2_tbnk0_data_corrected_l7_q; + wire [127:0] l2_tbnk0_data_l6; + wire l2_tbnk0_dbg_ram_acc_l5a; + wire [2:0] l2_tbnk0_dbg_ram_acc_unit_nxt; + wire [7:0] l2_tbnk0_dbg_ram_id_nxt_l5; + wire l2_tbnk0_dirty_l1; + wire l2_tbnk0_dirty_l3_q; + wire l2_tbnk0_dis_ns_dbg_arr_acc_x2; + wire l2_tbnk0_double_ecc_err_l7_q; + wire l2_tbnk0_early_rvalid_l4_q; + wire l2_tbnk0_ecc_fixup_blk_arb; + wire l2_tbnk0_ecc_fixup_inprog_dly_q; + wire l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q; + wire [31:0] l2_tbnk0_ecc_syndrome_reg_q; + wire l2_tbnk0_evict_special_hazard_l3_q; + wire l2_tbnk0_evict_special_hazard_rwvic_l3_q; + wire l2_tbnk0_excl_l1; + wire l2_tbnk0_excl_l4_q; + wire [44:6] l2_tbnk0_feq_addr_upd; + wire l2_tbnk0_feq_alloc_failed_l4; + wire l2_tbnk0_feq_axi_wr_vld_not_popped; + wire l2_tbnk0_feq_clr_l4; + wire [15:0] l2_tbnk0_feq_frc_incl_l3a; + wire l2_tbnk0_feq_kill_l3; + wire [4:0] l2_tbnk0_feq_last_id_q; + wire l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3; + wire l2_tbnk0_feq_tbnk_id_update_or_l3; + wire l2_tbnk0_full_miss_l4_q; + wire l2_tbnk0_hit_l4; + wire l2_tbnk0_hit_l7_q; + wire [3:0] l2_tbnk0_hit_way_l4_q; + wire [9:0] l2_tbnk0_id_l1; + wire [9:0] l2_tbnk0_id_l6_q; + wire [9:0] l2_tbnk0_id_nxt_l5; + wire l2_tbnk0_idle; + wire l2_tbnk0_init_req_l1; + wire l2_tbnk0_kill_l2; + wire l2_tbnk0_l2bb_fake_wr_l1; + wire l2_tbnk0_l2bb_wr_l1; + wire l2_tbnk0_l2hit_e_l4; + wire l2_tbnk0_l2hit_s_l4; + wire l2_tbnk0_l2v_s_q; + wire l2_tbnk0_l2v_vld_q; + wire l2_tbnk0_last_qw_l1; + wire l2_tbnk0_last_qw_l6_q; + wire l2_tbnk0_last_qw_nxt_l5; + wire [2:0] l2_tbnk0_lock_l1; + wire [2:0] l2_tbnk0_lock_l4; + wire [32:0] l2_tbnk0_merrsr_data; + wire [9:0] l2_tbnk0_page_attr_l1; + wire l2_tbnk0_partial_dw_wr_l1; + wire l2_tbnk0_pf_cnt_dec_l4_dly; + wire l2_tbnk0_pf_hazard_l3; + wire l2_tbnk0_pf_req_sel_for_fwd_l4; + wire l2_tbnk0_prfm_l1; + wire l2_tbnk0_prfm_nxt_l5; + wire [3:0] l2_tbnk0_prot_l1; + wire [3:0] l2_tbnk0_prot_l4_q; + wire [1:0] l2_tbnk0_qw_cnt_l1; + wire [1:0] l2_tbnk0_qw_cnt_l3_q; + wire l2_tbnk0_raw_hit_l4_q; + wire [2:0] l2_tbnk0_rbufid_nxt_l5; + wire l2_tbnk0_rd_en_nxt_l5; + wire l2_tbnk0_rd_fail_hazchk_feq_l3; + wire l2_tbnk0_rwvic_axi_read_err_l1; + wire l2_tbnk0_rwvic_axi_read_err_l3_q; + wire l2_tbnk0_rwvic_ccb_dirty_l6_q; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l1; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l3_q; + wire l2_tbnk0_rwvic_ccb_ls_xfer_l6_q; + wire [3:0] l2_tbnk0_rwvic_ccb_way_l1; + wire l2_tbnk0_rwvic_cmo_clean_l1; + wire l2_tbnk0_rwvic_cmo_inv_l1; + wire l2_tbnk0_rwvic_cmo_inv_l7_q; + wire l2_tbnk0_rwvic_cmo_l7_q; + wire l2_tbnk0_rwvic_cmo_pou_l1; + wire l2_tbnk0_rwvic_cmo_pou_l6_q; + wire l2_tbnk0_rwvic_cmo_setway_l1; + wire l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1; + wire l2_tbnk0_rwvic_cmo_setway_ls_l6_q; + wire [2:0] l2_tbnk0_rwvic_cpu_fb_id_l1; + wire [3:0] l2_tbnk0_rwvic_cpu_id_dcd_l1; + wire l2_tbnk0_rwvic_ddi_l6_q; + wire l2_tbnk0_rwvic_feq_cmp_l3_q; + wire l2_tbnk0_rwvic_frc_l2hit_fwd_l1; + wire l2_tbnk0_rwvic_l2hit_e_l1; + wire l2_tbnk0_rwvic_l2hit_e_l3_q; + wire l2_tbnk0_rwvic_l2hit_e_l7_q; + wire l2_tbnk0_rwvic_l2v_dirty_l7_q; + wire [3:0] l2_tbnk0_rwvic_l2v_page_attr_l7_q; + wire l2_tbnk0_rwvic_l2v_vld_l6_q; + wire l2_tbnk0_rwvic_mesi_sh_l1; + wire l2_tbnk0_rwvic_non_snp_fail_hazchk_l3; + wire [2:0] l2_tbnk0_rwvic_owner_l1; + wire [2:0] l2_tbnk0_rwvic_owner_l7_q; + wire l2_tbnk0_rwvic_rd_type_l6_q; + wire l2_tbnk0_rwvic_snp_clr_dirty_l1; + wire l2_tbnk0_rwvic_snp_inv_l1; + wire l2_tbnk0_rwvic_snp_l1; + wire l2_tbnk0_rwvic_snp_l3_q; + wire l2_tbnk0_rwvic_snp_l6_q; + wire l2_tbnk0_rwvic_tag_wr_l0; + wire [3:0] l2_tbnk0_rwvic_type_l1; + wire l2_tbnk0_rwvic_wa_l1; + wire l2_tbnk0_rwvic_wa_l6_q; + wire [13:0] l2_tbnk0_sel_l1; + wire [2:0] l2_tbnk0_size_l1; + wire [2:0] l2_tbnk0_size_l4_q; + wire l2_tbnk0_snp_byp_peq_haz_pending_q; + wire l2_tbnk0_snp_dvm_cmpl_l1; + wire l2_tbnk0_snp_hit_e_l4_q; + wire l2_tbnk0_snp_hit_feq_evict_l4_dly; + wire l2_tbnk0_snp_hit_s_l4_q; + wire [4:0] l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q; + wire [7:0] l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q; + wire [7:0] l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q; + wire [44:7] l2_tbnk0_snp_tag_wr_l2_hit_addr_l1; + wire [1:0] l2_tbnk0_snp_tag_wr_l2_hit_state_l1; + wire l2_tbnk0_snp_tag_wr_l2_hit_way_l1; + wire l2_tbnk0_special_evict_hazard_l3; + wire l2_tbnk0_special_hazard_l3_q; + wire l2_tbnk0_sync_l1; + wire l2_tbnk0_tag_ecc_dbl_rmw_wr_l1; + wire l2_tbnk0_tag_ecc_err_cpu0_l4; + wire l2_tbnk0_tag_ecc_err_cpu1_l4; + wire l2_tbnk0_tag_ecc_err_cpu2_l4; + wire l2_tbnk0_tag_ecc_err_cpu3_l4; + wire l2_tbnk0_tag_ecc_err_l4; + wire [6:0] l2_tbnk0_type_l1; + wire [1:0] l2_tbnk0_ulen_l1; + wire [1:0] l2_tbnk0_ulen_l4_q; + wire l2_tbnk0_vld_init_l6_q; + wire l2_tbnk0_vld_l6_q; + wire l2_tbnk0_way_l1; + wire l2_tbnk0_way_l4_q; + wire l2_tbnk0_way_nxt_l3a; + wire [143:0] l2_tbnk0_wr_data_l3; + wire [127:0] l2_tbnk0_wr_data_l3a_q; + wire l2_tbnk0_wr_data_l4_en; + wire l2_tbnk0_wr_err_l1; + wire l2_tbnk0_wr_fail_feq_full_l3; + wire l2_tbnk0_wr_fail_hazchk_feq_l3; + wire [11:0] l2_tbnk0_wr_non_crit_id_l1; + wire [11:0] l2_tbnk0_wr_non_crit_id_l4_q; + wire [15:0] l2_tbnk0_wr_strb_mask_l3a_q; + wire l2_tbnk1_addr44_l3_q; + wire [44:0] l2_tbnk1_addr_l1; + wire [5:2] l2_tbnk1_addr_l6; + wire l2_tbnk1_all_tag_incl_active_l3; + wire l2_tbnk1_asq_cmp_evict_l3_q; + wire l2_tbnk1_asq_full_flsh; + wire l2_tbnk1_asq_nc_so_dev_limit; + wire [2:0] l2_tbnk1_cache_attr_l1; + wire l2_tbnk1_cfg_ecc_en; + wire l2_tbnk1_cmo_setway_l2_inv_incl_l4; + wire l2_tbnk1_cpu0_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu0_hit_l4; + wire l2_tbnk1_cpu0_l2_inv_l4_dly2; + wire l2_tbnk1_cpu0_l2hit_e_l4; + wire l2_tbnk1_cpu0_l2hit_s_l4; + wire l2_tbnk1_cpu0_peq_full_q; + wire l2_tbnk1_cpu0_peq_hit_q; + wire l2_tbnk1_cpu0_peq_self_evict_l3_q; + wire l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu0_rd_access_l4_dly; + wire l2_tbnk1_cpu0_self_evict_l4_dly_q; + wire l2_tbnk1_cpu0_single_ecc_err_l7_q; + wire l2_tbnk1_cpu0_snp_hit_e_l3; + wire l2_tbnk1_cpu0_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu0_snp_setway_addr_l3; + wire l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu0_vld_nxt_l5; + wire l2_tbnk1_cpu0_wr_access_l4_dly; + wire l2_tbnk1_cpu1_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu1_hit_l4; + wire l2_tbnk1_cpu1_l2_inv_l4_dly2; + wire l2_tbnk1_cpu1_l2hit_e_l4; + wire l2_tbnk1_cpu1_l2hit_s_l4; + wire l2_tbnk1_cpu1_peq_full_q; + wire l2_tbnk1_cpu1_peq_hit_q; + wire l2_tbnk1_cpu1_peq_self_evict_l3_q; + wire l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu1_rd_access_l4_dly; + wire l2_tbnk1_cpu1_self_evict_l4_dly_q; + wire l2_tbnk1_cpu1_single_ecc_err_l7_q; + wire l2_tbnk1_cpu1_snp_hit_e_l3; + wire l2_tbnk1_cpu1_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu1_snp_setway_addr_l3; + wire l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu1_vld_nxt_l5; + wire l2_tbnk1_cpu1_wr_access_l4_dly; + wire l2_tbnk1_cpu2_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu2_hit_l4; + wire l2_tbnk1_cpu2_l2_inv_l4_dly2; + wire l2_tbnk1_cpu2_l2hit_e_l4; + wire l2_tbnk1_cpu2_l2hit_s_l4; + wire l2_tbnk1_cpu2_peq_full_q; + wire l2_tbnk1_cpu2_peq_hit_q; + wire l2_tbnk1_cpu2_peq_self_evict_l3_q; + wire l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu2_rd_access_l4_dly; + wire l2_tbnk1_cpu2_self_evict_l4_dly_q; + wire l2_tbnk1_cpu2_single_ecc_err_l7_q; + wire l2_tbnk1_cpu2_snp_hit_e_l3; + wire l2_tbnk1_cpu2_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu2_snp_setway_addr_l3; + wire l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu2_vld_nxt_l5; + wire l2_tbnk1_cpu2_wr_access_l4_dly; + wire l2_tbnk1_cpu3_ccb_xfer_l4_dly2; + wire l2_tbnk1_cpu3_hit_l4; + wire l2_tbnk1_cpu3_l2_inv_l4_dly2; + wire l2_tbnk1_cpu3_l2hit_e_l4; + wire l2_tbnk1_cpu3_l2hit_s_l4; + wire l2_tbnk1_cpu3_peq_full_q; + wire l2_tbnk1_cpu3_peq_hit_q; + wire l2_tbnk1_cpu3_peq_self_evict_l3_q; + wire l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q; + wire l2_tbnk1_cpu3_rd_access_l4_dly; + wire l2_tbnk1_cpu3_self_evict_l4_dly_q; + wire l2_tbnk1_cpu3_single_ecc_err_l7_q; + wire l2_tbnk1_cpu3_snp_hit_e_l3; + wire l2_tbnk1_cpu3_snp_hit_s_l3; + wire [44:14] l2_tbnk1_cpu3_snp_setway_addr_l3; + wire l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q; + wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0; + wire [1:0] l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0; + wire l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly; + wire l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly; + wire l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly; + wire l2_tbnk1_cpu3_vld_nxt_l5; + wire l2_tbnk1_cpu3_wr_access_l4_dly; + wire [3:0] l2_tbnk1_cpu_rvalid_init_nxt_l5; + wire [3:0] l2_tbnk1_cpu_rvalid_nxt_l5; + wire [3:0] l2_tbnk1_cpu_snp_hit_e_l4_q; + wire l2_tbnk1_crit_qw_nxt_l5; + wire [143:0] l2_tbnk1_data_corrected_l7_q; + wire [127:0] l2_tbnk1_data_l6; + wire l2_tbnk1_dbg_ram_acc_l5a; + wire [2:0] l2_tbnk1_dbg_ram_acc_unit_nxt; + wire [7:0] l2_tbnk1_dbg_ram_id_nxt_l5; + wire l2_tbnk1_dirty_l1; + wire l2_tbnk1_dirty_l3_q; + wire l2_tbnk1_dis_ns_dbg_arr_acc_x2; + wire l2_tbnk1_double_ecc_err_l7_q; + wire l2_tbnk1_early_rvalid_l4_q; + wire l2_tbnk1_ecc_fixup_blk_arb; + wire l2_tbnk1_ecc_fixup_inprog_dly_q; + wire l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q; + wire [31:0] l2_tbnk1_ecc_syndrome_reg_q; + wire l2_tbnk1_evict_special_hazard_l3_q; + wire l2_tbnk1_evict_special_hazard_rwvic_l3_q; + wire l2_tbnk1_excl_l1; + wire l2_tbnk1_excl_l4_q; + wire [44:6] l2_tbnk1_feq_addr_upd; + wire l2_tbnk1_feq_alloc_failed_l4; + wire l2_tbnk1_feq_axi_wr_vld_not_popped; + wire l2_tbnk1_feq_clr_l4; + wire [15:0] l2_tbnk1_feq_frc_incl_l3a; + wire l2_tbnk1_feq_kill_l3; + wire [4:0] l2_tbnk1_feq_last_id_q; + wire l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3; + wire l2_tbnk1_feq_tbnk_id_update_or_l3; + wire l2_tbnk1_full_miss_l4_q; + wire l2_tbnk1_hit_l4; + wire l2_tbnk1_hit_l7_q; + wire [3:0] l2_tbnk1_hit_way_l4_q; + wire [9:0] l2_tbnk1_id_l1; + wire [9:0] l2_tbnk1_id_l6_q; + wire [9:0] l2_tbnk1_id_nxt_l5; + wire l2_tbnk1_idle; + wire l2_tbnk1_init_req_l1; + wire l2_tbnk1_kill_l2; + wire l2_tbnk1_l2bb_fake_wr_l1; + wire l2_tbnk1_l2bb_wr_l1; + wire l2_tbnk1_l2hit_e_l4; + wire l2_tbnk1_l2hit_s_l4; + wire l2_tbnk1_l2v_s_q; + wire l2_tbnk1_l2v_vld_q; + wire l2_tbnk1_last_qw_l1; + wire l2_tbnk1_last_qw_l6_q; + wire l2_tbnk1_last_qw_nxt_l5; + wire [2:0] l2_tbnk1_lock_l1; + wire [2:0] l2_tbnk1_lock_l4; + wire [32:0] l2_tbnk1_merrsr_data; + wire [9:0] l2_tbnk1_page_attr_l1; + wire l2_tbnk1_partial_dw_wr_l1; + wire l2_tbnk1_pf_cnt_dec_l4_dly; + wire l2_tbnk1_pf_hazard_l3; + wire l2_tbnk1_pf_req_sel_for_fwd_l4; + wire l2_tbnk1_prfm_l1; + wire l2_tbnk1_prfm_nxt_l5; + wire [3:0] l2_tbnk1_prot_l1; + wire [3:0] l2_tbnk1_prot_l4_q; + wire [1:0] l2_tbnk1_qw_cnt_l1; + wire [1:0] l2_tbnk1_qw_cnt_l3_q; + wire l2_tbnk1_raw_hit_l4_q; + wire [2:0] l2_tbnk1_rbufid_nxt_l5; + wire l2_tbnk1_rd_en_nxt_l5; + wire l2_tbnk1_rd_fail_hazchk_feq_l3; + wire l2_tbnk1_rwvic_axi_read_err_l1; + wire l2_tbnk1_rwvic_axi_read_err_l3_q; + wire l2_tbnk1_rwvic_ccb_dirty_l6_q; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l1; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l3_q; + wire l2_tbnk1_rwvic_ccb_ls_xfer_l6_q; + wire [3:0] l2_tbnk1_rwvic_ccb_way_l1; + wire l2_tbnk1_rwvic_cmo_clean_l1; + wire l2_tbnk1_rwvic_cmo_inv_l1; + wire l2_tbnk1_rwvic_cmo_inv_l7_q; + wire l2_tbnk1_rwvic_cmo_l7_q; + wire l2_tbnk1_rwvic_cmo_pou_l1; + wire l2_tbnk1_rwvic_cmo_pou_l6_q; + wire l2_tbnk1_rwvic_cmo_setway_l1; + wire l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1; + wire l2_tbnk1_rwvic_cmo_setway_ls_l6_q; + wire [2:0] l2_tbnk1_rwvic_cpu_fb_id_l1; + wire [3:0] l2_tbnk1_rwvic_cpu_id_dcd_l1; + wire l2_tbnk1_rwvic_ddi_l6_q; + wire l2_tbnk1_rwvic_feq_cmp_l3_q; + wire l2_tbnk1_rwvic_frc_l2hit_fwd_l1; + wire l2_tbnk1_rwvic_l2hit_e_l1; + wire l2_tbnk1_rwvic_l2hit_e_l3_q; + wire l2_tbnk1_rwvic_l2hit_e_l7_q; + wire l2_tbnk1_rwvic_l2v_dirty_l7_q; + wire [3:0] l2_tbnk1_rwvic_l2v_page_attr_l7_q; + wire l2_tbnk1_rwvic_l2v_vld_l6_q; + wire l2_tbnk1_rwvic_mesi_sh_l1; + wire l2_tbnk1_rwvic_non_snp_fail_hazchk_l3; + wire [2:0] l2_tbnk1_rwvic_owner_l1; + wire [2:0] l2_tbnk1_rwvic_owner_l7_q; + wire l2_tbnk1_rwvic_rd_type_l6_q; + wire l2_tbnk1_rwvic_snp_clr_dirty_l1; + wire l2_tbnk1_rwvic_snp_inv_l1; + wire l2_tbnk1_rwvic_snp_l1; + wire l2_tbnk1_rwvic_snp_l3_q; + wire l2_tbnk1_rwvic_snp_l6_q; + wire l2_tbnk1_rwvic_tag_wr_l0; + wire [3:0] l2_tbnk1_rwvic_type_l1; + wire l2_tbnk1_rwvic_wa_l1; + wire l2_tbnk1_rwvic_wa_l6_q; + wire [13:0] l2_tbnk1_sel_l1; + wire [2:0] l2_tbnk1_size_l1; + wire [2:0] l2_tbnk1_size_l4_q; + wire l2_tbnk1_snp_byp_peq_haz_pending_q; + wire l2_tbnk1_snp_dvm_cmpl_l1; + wire l2_tbnk1_snp_hit_e_l4_q; + wire l2_tbnk1_snp_hit_feq_evict_l4_dly; + wire l2_tbnk1_snp_hit_s_l4_q; + wire [4:0] l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q; + wire [7:0] l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q; + wire [7:0] l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q; + wire [44:7] l2_tbnk1_snp_tag_wr_l2_hit_addr_l1; + wire [1:0] l2_tbnk1_snp_tag_wr_l2_hit_state_l1; + wire l2_tbnk1_snp_tag_wr_l2_hit_way_l1; + wire l2_tbnk1_special_evict_hazard_l3; + wire l2_tbnk1_special_hazard_l3_q; + wire l2_tbnk1_sync_l1; + wire l2_tbnk1_tag_ecc_dbl_rmw_wr_l1; + wire l2_tbnk1_tag_ecc_err_cpu0_l4; + wire l2_tbnk1_tag_ecc_err_cpu1_l4; + wire l2_tbnk1_tag_ecc_err_cpu2_l4; + wire l2_tbnk1_tag_ecc_err_cpu3_l4; + wire l2_tbnk1_tag_ecc_err_l4; + wire [6:0] l2_tbnk1_type_l1; + wire [1:0] l2_tbnk1_ulen_l1; + wire [1:0] l2_tbnk1_ulen_l4_q; + wire l2_tbnk1_vld_init_l6_q; + wire l2_tbnk1_vld_l6_q; + wire l2_tbnk1_way_l1; + wire l2_tbnk1_way_l4_q; + wire l2_tbnk1_way_nxt_l3a; + wire [143:0] l2_tbnk1_wr_data_l3; + wire [127:0] l2_tbnk1_wr_data_l3a_q; + wire l2_tbnk1_wr_data_l4_en; + wire l2_tbnk1_wr_err_l1; + wire l2_tbnk1_wr_fail_feq_full_l3; + wire l2_tbnk1_wr_fail_hazchk_feq_l3; + wire [11:0] l2_tbnk1_wr_non_crit_id_l1; + wire [11:0] l2_tbnk1_wr_non_crit_id_l4_q; + wire [15:0] l2_tbnk1_wr_strb_mask_l3a_q; + wire l2_tbnk_hwrst_done_x2; + wire [13:0] l2_tbnk_hwrst_idx_x1_q; + wire [8:0] tm_cntpct_q; + wire tm_cpu0_event_sev; + wire [63:0] tm_cpu0_spr_rd_data; + wire tm_cpu1_event_sev; + wire [63:0] tm_cpu1_spr_rd_data; + wire tm_cpu2_event_sev; + wire [63:0] tm_cpu2_spr_rd_data; + wire tm_cpu3_event_sev; + wire [63:0] tm_cpu3_spr_rd_data; + wire [63:0] tm_tval_cpu0_spr_rd_data; + wire [63:0] tm_tval_cpu1_spr_rd_data; + wire [63:0] tm_tval_cpu2_spr_rd_data; + wire [63:0] tm_tval_cpu3_spr_rd_data; + + maia_timer utm( // outputs + .nCNTHPIRQ (nCNTHPIRQ[`MAIA_CN:0]), + .nCNTPNSIRQ (nCNTPNSIRQ[`MAIA_CN:0]), + .nCNTPSIRQ (nCNTPSIRQ[`MAIA_CN:0]), + .nCNTVIRQ (nCNTVIRQ[`MAIA_CN:0]), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_cnthctl_kernel (tm_cpu0_cnthctl_kernel[1:0]), + .tm_cpu0_cntkctl_usr (tm_cpu0_cntkctl_usr[3:0]), + .tm_cpu0_event_sev (tm_cpu0_event_sev), + .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), + .tm_cpu1_cnthctl_kernel (tm_cpu1_cnthctl_kernel[1:0]), + .tm_cpu1_cntkctl_usr (tm_cpu1_cntkctl_usr[3:0]), + .tm_cpu1_event_sev (tm_cpu1_event_sev), + .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), + .tm_cpu2_cnthctl_kernel (tm_cpu2_cnthctl_kernel[1:0]), + .tm_cpu2_cntkctl_usr (tm_cpu2_cntkctl_usr[3:0]), + .tm_cpu2_event_sev (tm_cpu2_event_sev), + .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), + .tm_cpu3_cnthctl_kernel (tm_cpu3_cnthctl_kernel[1:0]), + .tm_cpu3_cntkctl_usr (tm_cpu3_cntkctl_usr[3:0]), + .tm_cpu3_event_sev (tm_cpu3_event_sev), + .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), + .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), + .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), + .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), + .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]), + + // inputs + .CNTCLKEN (CNTCLKEN), + .CNTVALUEB (CNTVALUEB[63:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .ck_areset_l2 (ck_areset_l2), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .eventi_sev (eventi_sev), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable) + ); // utm + + maia_l2_logic_s ul2_logic( // outputs + .ARREADYS (ARREADYS), + .AWREADYS (AWREADYS), + .BIDS (BIDS[4:0]), + .BRESPS (BRESPS[1:0]), + .BVALIDS (BVALIDS), + .L2FLUSHDONE (L2FLUSHDONE), + .L2QACCEPTn (L2QACCEPTn), + .L2QACTIVE (L2QACTIVE), + .L2QDENY (L2QDENY), + .RDATAS (RDATAS[127:0]), + .REQMEMATTR (REQMEMATTR[7:0]), + .RIDS (RIDS[4:0]), + .RLASTS (RLASTS), + .RRESPS (RRESPS[1:0]), + .RVALIDS (RVALIDS), + .RXDATLCRDV (RXDATLCRDV), + .RXLINKACTIVEACK (RXLINKACTIVEACK), + .RXRSPLCRDV (RXRSPLCRDV), + .RXSNPLCRDV (RXSNPLCRDV), + .TXDATFLIT (TXDATFLIT[193:0]), + .TXDATFLITPEND (TXDATFLITPEND), + .TXDATFLITV (TXDATFLITV), + .TXLINKACTIVEREQ (TXLINKACTIVEREQ), + .TXREQFLIT (TXREQFLIT[99:0]), + .TXREQFLITPEND (TXREQFLITPEND), + .TXREQFLITV (TXREQFLITV), + .TXRSPFLIT (TXRSPFLIT[44:0]), + .TXRSPFLITPEND (TXRSPFLITPEND), + .TXRSPFLITV (TXRSPFLITV), + .TXSACTIVE (TXSACTIVE), + .WREADYS (WREADYS), + .ck_areset_l2 (ck_areset_l2), + .ck_l2_logic_clk_en (ck_l2_logic_clk_en), + .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), + .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_arb_thrshld_timeout_en (l2_cpu0_arb_thrshld_timeout_en), + .l2_cpu0_barrier_done (l2_cpu0_barrier_done), + .l2_cpu0_blk_non_evict_wr (l2_cpu0_blk_non_evict_wr), + .l2_cpu0_ccb_dbg_req_c3 (l2_cpu0_ccb_dbg_req_c3), + .l2_cpu0_ccb_req_addr_c3 (l2_cpu0_ccb_req_addr_c3[48:0]), + .l2_cpu0_ccb_req_id_c3 (l2_cpu0_ccb_req_id_c3[4:0]), + .l2_cpu0_ccb_req_info_c3 (l2_cpu0_ccb_req_info_c3[23:0]), + .l2_cpu0_ccb_req_type_c3 (l2_cpu0_ccb_req_type_c3[8:0]), + .l2_cpu0_cfg_ecc_en (l2_cpu0_cfg_ecc_en), + .l2_cpu0_dbufid_r1 (l2_cpu0_dbufid_r1[2:0]), + .l2_cpu0_ddata_r2 (l2_cpu0_ddata_r2[129:0]), + .l2_cpu0_ddbl_ecc_err_r3 (l2_cpu0_ddbl_ecc_err_r3), + .l2_cpu0_dext_err_r2 (l2_cpu0_dext_err_r2), + .l2_cpu0_dext_err_type_r2 (l2_cpu0_dext_err_type_r2), + .l2_cpu0_disable_clean_evict_opt (l2_cpu0_disable_clean_evict_opt), + .l2_cpu0_dlast_r1 (l2_cpu0_dlast_r1), + .l2_cpu0_dsngl_ecc_err_r3 (l2_cpu0_dsngl_ecc_err_r3), + .l2_cpu0_dsq_clr_id_q (l2_cpu0_dsq_clr_id_q[3:0]), + .l2_cpu0_dsq_clr_vld_q (l2_cpu0_dsq_clr_vld_q), + .l2_cpu0_dsq_rd_buf_id (l2_cpu0_dsq_rd_buf_id[3:0]), + .l2_cpu0_dsq_rd_en (l2_cpu0_dsq_rd_en), + .l2_cpu0_dsq_rd_en_x2 (l2_cpu0_dsq_rd_en_x2), + .l2_cpu0_dvalid_r1 (l2_cpu0_dvalid_r1), + .l2_cpu0_flsh_if_rd_id_l4_dly (l2_cpu0_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu0_flsh_if_rd_l4_dly (l2_cpu0_flsh_if_rd_l4_dly), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_rd_id_l2_dly (l2_cpu0_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu0_flsh_ls_rd_id_l4_dly (l2_cpu0_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu0_flsh_ls_rd_l2_dly (l2_cpu0_flsh_ls_rd_l2_dly), + .l2_cpu0_flsh_ls_rd_l4_dly (l2_cpu0_flsh_ls_rd_l4_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_evict_l4_dly (l2_cpu0_flsh_ls_wr_evict_l4_dly), + .l2_cpu0_flsh_ls_wr_id_l2_dly (l2_cpu0_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu0_flsh_ls_wr_id_l4_dly (l2_cpu0_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu0_flsh_ls_wr_l2_dly (l2_cpu0_flsh_ls_wr_l2_dly), + .l2_cpu0_flsh_ls_wr_l4_dly (l2_cpu0_flsh_ls_wr_l4_dly), + .l2_cpu0_flsh_tw_rd_l4_dly (l2_cpu0_flsh_tw_rd_l4_dly), + .l2_cpu0_ibufid_r1 (l2_cpu0_ibufid_r1[1:0]), + .l2_cpu0_ic_barrier_stall_q (l2_cpu0_ic_barrier_stall_q), + .l2_cpu0_ic_base (l2_cpu0_ic_base[43:18]), + .l2_cpu0_ic_vld_skid (l2_cpu0_ic_vld_skid), + .l2_cpu0_idata_r2 (l2_cpu0_idata_r2[127:0]), + .l2_cpu0_idbl_ecc_err_r3 (l2_cpu0_idbl_ecc_err_r3), + .l2_cpu0_idle_block_reqs_q (l2_cpu0_idle_block_reqs_q), + .l2_cpu0_iext_err_r2 (l2_cpu0_iext_err_r2), + .l2_cpu0_iext_err_type_r2 (l2_cpu0_iext_err_type_r2), + .l2_cpu0_if_ccb_clken_c3 (l2_cpu0_if_ccb_clken_c3), + .l2_cpu0_if_ccb_req_c3 (l2_cpu0_if_ccb_req_c3), + .l2_cpu0_if_sync_req (l2_cpu0_if_sync_req), + .l2_cpu0_ifq_haz_pending (l2_cpu0_ifq_haz_pending), + .l2_cpu0_isngl_ecc_err_r3 (l2_cpu0_isngl_ecc_err_r3), + .l2_cpu0_ivalid_r1 (l2_cpu0_ivalid_r1), + .l2_cpu0_l2_cache_size (l2_cpu0_l2_cache_size[1:0]), + .l2_cpu0_lrq_haz_pending (l2_cpu0_lrq_haz_pending), + .l2_cpu0_ls_ccb_clken_c3 (l2_cpu0_ls_ccb_clken_c3), + .l2_cpu0_ls_ccb_req_c3 (l2_cpu0_ls_ccb_req_c3), + .l2_cpu0_ls_peq_coll_l4_dly (l2_cpu0_ls_peq_coll_l4_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_sync_req (l2_cpu0_ls_sync_req), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu0_mbist1_addr_b1 (l2_cpu0_mbist1_addr_b1[12:0]), + .l2_cpu0_mbist1_all_b1 (l2_cpu0_mbist1_all_b1), + .l2_cpu0_mbist1_array_b1 (l2_cpu0_mbist1_array_b1[3:0]), + .l2_cpu0_mbist1_be_b1 (l2_cpu0_mbist1_be_b1[7:0]), + .l2_cpu0_mbist1_en_b1 (l2_cpu0_mbist1_en_b1), + .l2_cpu0_mbist1_rd_en_b1 (l2_cpu0_mbist1_rd_en_b1), + .l2_cpu0_mbist1_wr_en_b1 (l2_cpu0_mbist1_wr_en_b1), + .l2_cpu0_no_intctrl (l2_cpu0_no_intctrl), + .l2_cpu0_pf_rd_vld_skid_popped (l2_cpu0_pf_rd_vld_skid_popped), + .l2_cpu0_pf_throttle_q (l2_cpu0_pf_throttle_q), + .l2_cpu0_pmu_events (l2_cpu0_pmu_events[33:0]), + .l2_cpu0_rbufid (l2_cpu0_rbufid[2:0]), + .l2_cpu0_rd_arb (l2_cpu0_rd_arb), + .l2_cpu0_rd_vld_skid (l2_cpu0_rd_vld_skid), + .l2_cpu0_rexfail (l2_cpu0_rexfail), + .l2_cpu0_rstate (l2_cpu0_rstate[1:0]), + .l2_cpu0_rvalid (l2_cpu0_rvalid), + .l2_cpu0_snp_active (l2_cpu0_snp_active), + .l2_cpu0_spec_bufid (l2_cpu0_spec_bufid[2:0]), + .l2_cpu0_spec_valid (l2_cpu0_spec_valid), + .l2_cpu0_spr_rd_data (l2_cpu0_spr_rd_data[63:0]), + .l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_tbw_dbl_ecc_err (l2_cpu0_tbw_dbl_ecc_err), + .l2_cpu0_tbw_desc_data (l2_cpu0_tbw_desc_data[63:0]), + .l2_cpu0_tbw_desc_vld (l2_cpu0_tbw_desc_vld), + .l2_cpu0_tbw_ext_err (l2_cpu0_tbw_ext_err), + .l2_cpu0_tbw_ext_err_type (l2_cpu0_tbw_ext_err_type), + .l2_cpu0_tlb_ccb_clken_c3 (l2_cpu0_tlb_ccb_clken_c3), + .l2_cpu0_tlb_ccb_req_c3 (l2_cpu0_tlb_ccb_req_c3), + .l2_cpu0_tlb_sync_complete (l2_cpu0_tlb_sync_complete), + .l2_cpu0_tlb_sync_req (l2_cpu0_tlb_sync_req), + .l2_cpu0_trq_haz_pending (l2_cpu0_trq_haz_pending), + .l2_cpu0_wr_arb (l2_cpu0_wr_arb), + .l2_cpu0_wr_data_stall (l2_cpu0_wr_data_stall), + .l2_cpu0_wr_decerr_q (l2_cpu0_wr_decerr_q), + .l2_cpu0_wr_ex_fail (l2_cpu0_wr_ex_fail), + .l2_cpu0_wr_ex_resp (l2_cpu0_wr_ex_resp), + .l2_cpu0_wr_slverr_q (l2_cpu0_wr_slverr_q), + .l2_cpu0_wr_vld_skid (l2_cpu0_wr_vld_skid), + .l2_cpu0_wrq_haz_pending (l2_cpu0_wrq_haz_pending), + .l2_cpu1_arb_thrshld_timeout_en (l2_cpu1_arb_thrshld_timeout_en), + .l2_cpu1_barrier_done (l2_cpu1_barrier_done), + .l2_cpu1_blk_non_evict_wr (l2_cpu1_blk_non_evict_wr), + .l2_cpu1_ccb_dbg_req_c3 (l2_cpu1_ccb_dbg_req_c3), + .l2_cpu1_ccb_req_addr_c3 (l2_cpu1_ccb_req_addr_c3[48:0]), + .l2_cpu1_ccb_req_id_c3 (l2_cpu1_ccb_req_id_c3[4:0]), + .l2_cpu1_ccb_req_info_c3 (l2_cpu1_ccb_req_info_c3[23:0]), + .l2_cpu1_ccb_req_type_c3 (l2_cpu1_ccb_req_type_c3[8:0]), + .l2_cpu1_cfg_ecc_en (l2_cpu1_cfg_ecc_en), + .l2_cpu1_dbufid_r1 (l2_cpu1_dbufid_r1[2:0]), + .l2_cpu1_ddata_r2 (l2_cpu1_ddata_r2[129:0]), + .l2_cpu1_ddbl_ecc_err_r3 (l2_cpu1_ddbl_ecc_err_r3), + .l2_cpu1_dext_err_r2 (l2_cpu1_dext_err_r2), + .l2_cpu1_dext_err_type_r2 (l2_cpu1_dext_err_type_r2), + .l2_cpu1_disable_clean_evict_opt (l2_cpu1_disable_clean_evict_opt), + .l2_cpu1_dlast_r1 (l2_cpu1_dlast_r1), + .l2_cpu1_dsngl_ecc_err_r3 (l2_cpu1_dsngl_ecc_err_r3), + .l2_cpu1_dsq_clr_id_q (l2_cpu1_dsq_clr_id_q[3:0]), + .l2_cpu1_dsq_clr_vld_q (l2_cpu1_dsq_clr_vld_q), + .l2_cpu1_dsq_rd_buf_id (l2_cpu1_dsq_rd_buf_id[3:0]), + .l2_cpu1_dsq_rd_en (l2_cpu1_dsq_rd_en), + .l2_cpu1_dsq_rd_en_x2 (l2_cpu1_dsq_rd_en_x2), + .l2_cpu1_dvalid_r1 (l2_cpu1_dvalid_r1), + .l2_cpu1_flsh_if_rd_id_l4_dly (l2_cpu1_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu1_flsh_if_rd_l4_dly (l2_cpu1_flsh_if_rd_l4_dly), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_rd_id_l2_dly (l2_cpu1_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu1_flsh_ls_rd_id_l4_dly (l2_cpu1_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu1_flsh_ls_rd_l2_dly (l2_cpu1_flsh_ls_rd_l2_dly), + .l2_cpu1_flsh_ls_rd_l4_dly (l2_cpu1_flsh_ls_rd_l4_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_evict_l4_dly (l2_cpu1_flsh_ls_wr_evict_l4_dly), + .l2_cpu1_flsh_ls_wr_id_l2_dly (l2_cpu1_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu1_flsh_ls_wr_id_l4_dly (l2_cpu1_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu1_flsh_ls_wr_l2_dly (l2_cpu1_flsh_ls_wr_l2_dly), + .l2_cpu1_flsh_ls_wr_l4_dly (l2_cpu1_flsh_ls_wr_l4_dly), + .l2_cpu1_flsh_tw_rd_l4_dly (l2_cpu1_flsh_tw_rd_l4_dly), + .l2_cpu1_ibufid_r1 (l2_cpu1_ibufid_r1[1:0]), + .l2_cpu1_ic_barrier_stall_q (l2_cpu1_ic_barrier_stall_q), + .l2_cpu1_ic_base (l2_cpu1_ic_base[43:18]), + .l2_cpu1_ic_vld_skid (l2_cpu1_ic_vld_skid), + .l2_cpu1_idata_r2 (l2_cpu1_idata_r2[127:0]), + .l2_cpu1_idbl_ecc_err_r3 (l2_cpu1_idbl_ecc_err_r3), + .l2_cpu1_idle_block_reqs_q (l2_cpu1_idle_block_reqs_q), + .l2_cpu1_iext_err_r2 (l2_cpu1_iext_err_r2), + .l2_cpu1_iext_err_type_r2 (l2_cpu1_iext_err_type_r2), + .l2_cpu1_if_ccb_clken_c3 (l2_cpu1_if_ccb_clken_c3), + .l2_cpu1_if_ccb_req_c3 (l2_cpu1_if_ccb_req_c3), + .l2_cpu1_if_sync_req (l2_cpu1_if_sync_req), + .l2_cpu1_ifq_haz_pending (l2_cpu1_ifq_haz_pending), + .l2_cpu1_isngl_ecc_err_r3 (l2_cpu1_isngl_ecc_err_r3), + .l2_cpu1_ivalid_r1 (l2_cpu1_ivalid_r1), + .l2_cpu1_l2_cache_size (l2_cpu1_l2_cache_size[1:0]), + .l2_cpu1_lrq_haz_pending (l2_cpu1_lrq_haz_pending), + .l2_cpu1_ls_ccb_clken_c3 (l2_cpu1_ls_ccb_clken_c3), + .l2_cpu1_ls_ccb_req_c3 (l2_cpu1_ls_ccb_req_c3), + .l2_cpu1_ls_peq_coll_l4_dly (l2_cpu1_ls_peq_coll_l4_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_sync_req (l2_cpu1_ls_sync_req), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_mbist1_addr_b1 (l2_cpu1_mbist1_addr_b1[12:0]), + .l2_cpu1_mbist1_all_b1 (l2_cpu1_mbist1_all_b1), + .l2_cpu1_mbist1_array_b1 (l2_cpu1_mbist1_array_b1[3:0]), + .l2_cpu1_mbist1_be_b1 (l2_cpu1_mbist1_be_b1[7:0]), + .l2_cpu1_mbist1_en_b1 (l2_cpu1_mbist1_en_b1), + .l2_cpu1_mbist1_rd_en_b1 (l2_cpu1_mbist1_rd_en_b1), + .l2_cpu1_mbist1_wr_en_b1 (l2_cpu1_mbist1_wr_en_b1), + .l2_cpu1_no_intctrl (l2_cpu1_no_intctrl), + .l2_cpu1_pf_rd_vld_skid_popped (l2_cpu1_pf_rd_vld_skid_popped), + .l2_cpu1_pf_throttle_q (l2_cpu1_pf_throttle_q), + .l2_cpu1_pmu_events (l2_cpu1_pmu_events[33:0]), + .l2_cpu1_rbufid (l2_cpu1_rbufid[2:0]), + .l2_cpu1_rd_arb (l2_cpu1_rd_arb), + .l2_cpu1_rd_vld_skid (l2_cpu1_rd_vld_skid), + .l2_cpu1_rexfail (l2_cpu1_rexfail), + .l2_cpu1_rstate (l2_cpu1_rstate[1:0]), + .l2_cpu1_rvalid (l2_cpu1_rvalid), + .l2_cpu1_snp_active (l2_cpu1_snp_active), + .l2_cpu1_spec_bufid (l2_cpu1_spec_bufid[2:0]), + .l2_cpu1_spec_valid (l2_cpu1_spec_valid), + .l2_cpu1_spr_rd_data (l2_cpu1_spr_rd_data[63:0]), + .l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_tbw_dbl_ecc_err (l2_cpu1_tbw_dbl_ecc_err), + .l2_cpu1_tbw_desc_data (l2_cpu1_tbw_desc_data[63:0]), + .l2_cpu1_tbw_desc_vld (l2_cpu1_tbw_desc_vld), + .l2_cpu1_tbw_ext_err (l2_cpu1_tbw_ext_err), + .l2_cpu1_tbw_ext_err_type (l2_cpu1_tbw_ext_err_type), + .l2_cpu1_tlb_ccb_clken_c3 (l2_cpu1_tlb_ccb_clken_c3), + .l2_cpu1_tlb_ccb_req_c3 (l2_cpu1_tlb_ccb_req_c3), + .l2_cpu1_tlb_sync_complete (l2_cpu1_tlb_sync_complete), + .l2_cpu1_tlb_sync_req (l2_cpu1_tlb_sync_req), + .l2_cpu1_trq_haz_pending (l2_cpu1_trq_haz_pending), + .l2_cpu1_wr_arb (l2_cpu1_wr_arb), + .l2_cpu1_wr_data_stall (l2_cpu1_wr_data_stall), + .l2_cpu1_wr_decerr_q (l2_cpu1_wr_decerr_q), + .l2_cpu1_wr_ex_fail (l2_cpu1_wr_ex_fail), + .l2_cpu1_wr_ex_resp (l2_cpu1_wr_ex_resp), + .l2_cpu1_wr_slverr_q (l2_cpu1_wr_slverr_q), + .l2_cpu1_wr_vld_skid (l2_cpu1_wr_vld_skid), + .l2_cpu1_wrq_haz_pending (l2_cpu1_wrq_haz_pending), + .l2_cpu2_arb_thrshld_timeout_en (l2_cpu2_arb_thrshld_timeout_en), + .l2_cpu2_barrier_done (l2_cpu2_barrier_done), + .l2_cpu2_blk_non_evict_wr (l2_cpu2_blk_non_evict_wr), + .l2_cpu2_ccb_dbg_req_c3 (l2_cpu2_ccb_dbg_req_c3), + .l2_cpu2_ccb_req_addr_c3 (l2_cpu2_ccb_req_addr_c3[48:0]), + .l2_cpu2_ccb_req_id_c3 (l2_cpu2_ccb_req_id_c3[4:0]), + .l2_cpu2_ccb_req_info_c3 (l2_cpu2_ccb_req_info_c3[23:0]), + .l2_cpu2_ccb_req_type_c3 (l2_cpu2_ccb_req_type_c3[8:0]), + .l2_cpu2_cfg_ecc_en (l2_cpu2_cfg_ecc_en), + .l2_cpu2_dbufid_r1 (l2_cpu2_dbufid_r1[2:0]), + .l2_cpu2_ddata_r2 (l2_cpu2_ddata_r2[129:0]), + .l2_cpu2_ddbl_ecc_err_r3 (l2_cpu2_ddbl_ecc_err_r3), + .l2_cpu2_dext_err_r2 (l2_cpu2_dext_err_r2), + .l2_cpu2_dext_err_type_r2 (l2_cpu2_dext_err_type_r2), + .l2_cpu2_disable_clean_evict_opt (l2_cpu2_disable_clean_evict_opt), + .l2_cpu2_dlast_r1 (l2_cpu2_dlast_r1), + .l2_cpu2_dsngl_ecc_err_r3 (l2_cpu2_dsngl_ecc_err_r3), + .l2_cpu2_dsq_clr_id_q (l2_cpu2_dsq_clr_id_q[3:0]), + .l2_cpu2_dsq_clr_vld_q (l2_cpu2_dsq_clr_vld_q), + .l2_cpu2_dsq_rd_buf_id (l2_cpu2_dsq_rd_buf_id[3:0]), + .l2_cpu2_dsq_rd_en (l2_cpu2_dsq_rd_en), + .l2_cpu2_dsq_rd_en_x2 (l2_cpu2_dsq_rd_en_x2), + .l2_cpu2_dvalid_r1 (l2_cpu2_dvalid_r1), + .l2_cpu2_flsh_if_rd_id_l4_dly (l2_cpu2_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu2_flsh_if_rd_l4_dly (l2_cpu2_flsh_if_rd_l4_dly), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_rd_id_l2_dly (l2_cpu2_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu2_flsh_ls_rd_id_l4_dly (l2_cpu2_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu2_flsh_ls_rd_l2_dly (l2_cpu2_flsh_ls_rd_l2_dly), + .l2_cpu2_flsh_ls_rd_l4_dly (l2_cpu2_flsh_ls_rd_l4_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_evict_l4_dly (l2_cpu2_flsh_ls_wr_evict_l4_dly), + .l2_cpu2_flsh_ls_wr_id_l2_dly (l2_cpu2_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu2_flsh_ls_wr_id_l4_dly (l2_cpu2_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu2_flsh_ls_wr_l2_dly (l2_cpu2_flsh_ls_wr_l2_dly), + .l2_cpu2_flsh_ls_wr_l4_dly (l2_cpu2_flsh_ls_wr_l4_dly), + .l2_cpu2_flsh_tw_rd_l4_dly (l2_cpu2_flsh_tw_rd_l4_dly), + .l2_cpu2_ibufid_r1 (l2_cpu2_ibufid_r1[1:0]), + .l2_cpu2_ic_barrier_stall_q (l2_cpu2_ic_barrier_stall_q), + .l2_cpu2_ic_base (l2_cpu2_ic_base[43:18]), + .l2_cpu2_ic_vld_skid (l2_cpu2_ic_vld_skid), + .l2_cpu2_idata_r2 (l2_cpu2_idata_r2[127:0]), + .l2_cpu2_idbl_ecc_err_r3 (l2_cpu2_idbl_ecc_err_r3), + .l2_cpu2_idle_block_reqs_q (l2_cpu2_idle_block_reqs_q), + .l2_cpu2_iext_err_r2 (l2_cpu2_iext_err_r2), + .l2_cpu2_iext_err_type_r2 (l2_cpu2_iext_err_type_r2), + .l2_cpu2_if_ccb_clken_c3 (l2_cpu2_if_ccb_clken_c3), + .l2_cpu2_if_ccb_req_c3 (l2_cpu2_if_ccb_req_c3), + .l2_cpu2_if_sync_req (l2_cpu2_if_sync_req), + .l2_cpu2_ifq_haz_pending (l2_cpu2_ifq_haz_pending), + .l2_cpu2_isngl_ecc_err_r3 (l2_cpu2_isngl_ecc_err_r3), + .l2_cpu2_ivalid_r1 (l2_cpu2_ivalid_r1), + .l2_cpu2_l2_cache_size (l2_cpu2_l2_cache_size[1:0]), + .l2_cpu2_lrq_haz_pending (l2_cpu2_lrq_haz_pending), + .l2_cpu2_ls_ccb_clken_c3 (l2_cpu2_ls_ccb_clken_c3), + .l2_cpu2_ls_ccb_req_c3 (l2_cpu2_ls_ccb_req_c3), + .l2_cpu2_ls_peq_coll_l4_dly (l2_cpu2_ls_peq_coll_l4_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_sync_req (l2_cpu2_ls_sync_req), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_mbist1_addr_b1 (l2_cpu2_mbist1_addr_b1[12:0]), + .l2_cpu2_mbist1_all_b1 (l2_cpu2_mbist1_all_b1), + .l2_cpu2_mbist1_array_b1 (l2_cpu2_mbist1_array_b1[3:0]), + .l2_cpu2_mbist1_be_b1 (l2_cpu2_mbist1_be_b1[7:0]), + .l2_cpu2_mbist1_en_b1 (l2_cpu2_mbist1_en_b1), + .l2_cpu2_mbist1_rd_en_b1 (l2_cpu2_mbist1_rd_en_b1), + .l2_cpu2_mbist1_wr_en_b1 (l2_cpu2_mbist1_wr_en_b1), + .l2_cpu2_no_intctrl (l2_cpu2_no_intctrl), + .l2_cpu2_pf_rd_vld_skid_popped (l2_cpu2_pf_rd_vld_skid_popped), + .l2_cpu2_pf_throttle_q (l2_cpu2_pf_throttle_q), + .l2_cpu2_pmu_events (l2_cpu2_pmu_events[33:0]), + .l2_cpu2_rbufid (l2_cpu2_rbufid[2:0]), + .l2_cpu2_rd_arb (l2_cpu2_rd_arb), + .l2_cpu2_rd_vld_skid (l2_cpu2_rd_vld_skid), + .l2_cpu2_rexfail (l2_cpu2_rexfail), + .l2_cpu2_rstate (l2_cpu2_rstate[1:0]), + .l2_cpu2_rvalid (l2_cpu2_rvalid), + .l2_cpu2_snp_active (l2_cpu2_snp_active), + .l2_cpu2_spec_bufid (l2_cpu2_spec_bufid[2:0]), + .l2_cpu2_spec_valid (l2_cpu2_spec_valid), + .l2_cpu2_spr_rd_data (l2_cpu2_spr_rd_data[63:0]), + .l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_tbw_dbl_ecc_err (l2_cpu2_tbw_dbl_ecc_err), + .l2_cpu2_tbw_desc_data (l2_cpu2_tbw_desc_data[63:0]), + .l2_cpu2_tbw_desc_vld (l2_cpu2_tbw_desc_vld), + .l2_cpu2_tbw_ext_err (l2_cpu2_tbw_ext_err), + .l2_cpu2_tbw_ext_err_type (l2_cpu2_tbw_ext_err_type), + .l2_cpu2_tlb_ccb_clken_c3 (l2_cpu2_tlb_ccb_clken_c3), + .l2_cpu2_tlb_ccb_req_c3 (l2_cpu2_tlb_ccb_req_c3), + .l2_cpu2_tlb_sync_complete (l2_cpu2_tlb_sync_complete), + .l2_cpu2_tlb_sync_req (l2_cpu2_tlb_sync_req), + .l2_cpu2_trq_haz_pending (l2_cpu2_trq_haz_pending), + .l2_cpu2_wr_arb (l2_cpu2_wr_arb), + .l2_cpu2_wr_data_stall (l2_cpu2_wr_data_stall), + .l2_cpu2_wr_decerr_q (l2_cpu2_wr_decerr_q), + .l2_cpu2_wr_ex_fail (l2_cpu2_wr_ex_fail), + .l2_cpu2_wr_ex_resp (l2_cpu2_wr_ex_resp), + .l2_cpu2_wr_slverr_q (l2_cpu2_wr_slverr_q), + .l2_cpu2_wr_vld_skid (l2_cpu2_wr_vld_skid), + .l2_cpu2_wrq_haz_pending (l2_cpu2_wrq_haz_pending), + .l2_cpu3_arb_thrshld_timeout_en (l2_cpu3_arb_thrshld_timeout_en), + .l2_cpu3_barrier_done (l2_cpu3_barrier_done), + .l2_cpu3_blk_non_evict_wr (l2_cpu3_blk_non_evict_wr), + .l2_cpu3_ccb_dbg_req_c3 (l2_cpu3_ccb_dbg_req_c3), + .l2_cpu3_ccb_req_addr_c3 (l2_cpu3_ccb_req_addr_c3[48:0]), + .l2_cpu3_ccb_req_id_c3 (l2_cpu3_ccb_req_id_c3[4:0]), + .l2_cpu3_ccb_req_info_c3 (l2_cpu3_ccb_req_info_c3[23:0]), + .l2_cpu3_ccb_req_type_c3 (l2_cpu3_ccb_req_type_c3[8:0]), + .l2_cpu3_cfg_ecc_en (l2_cpu3_cfg_ecc_en), + .l2_cpu3_dbufid_r1 (l2_cpu3_dbufid_r1[2:0]), + .l2_cpu3_ddata_r2 (l2_cpu3_ddata_r2[129:0]), + .l2_cpu3_ddbl_ecc_err_r3 (l2_cpu3_ddbl_ecc_err_r3), + .l2_cpu3_dext_err_r2 (l2_cpu3_dext_err_r2), + .l2_cpu3_dext_err_type_r2 (l2_cpu3_dext_err_type_r2), + .l2_cpu3_disable_clean_evict_opt (l2_cpu3_disable_clean_evict_opt), + .l2_cpu3_dlast_r1 (l2_cpu3_dlast_r1), + .l2_cpu3_dsngl_ecc_err_r3 (l2_cpu3_dsngl_ecc_err_r3), + .l2_cpu3_dsq_clr_id_q (l2_cpu3_dsq_clr_id_q[3:0]), + .l2_cpu3_dsq_clr_vld_q (l2_cpu3_dsq_clr_vld_q), + .l2_cpu3_dsq_rd_buf_id (l2_cpu3_dsq_rd_buf_id[3:0]), + .l2_cpu3_dsq_rd_en (l2_cpu3_dsq_rd_en), + .l2_cpu3_dsq_rd_en_x2 (l2_cpu3_dsq_rd_en_x2), + .l2_cpu3_dvalid_r1 (l2_cpu3_dvalid_r1), + .l2_cpu3_flsh_if_rd_id_l4_dly (l2_cpu3_flsh_if_rd_id_l4_dly[1:0]), + .l2_cpu3_flsh_if_rd_l4_dly (l2_cpu3_flsh_if_rd_l4_dly), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_rd_id_l2_dly (l2_cpu3_flsh_ls_rd_id_l2_dly[2:0]), + .l2_cpu3_flsh_ls_rd_id_l4_dly (l2_cpu3_flsh_ls_rd_id_l4_dly[2:0]), + .l2_cpu3_flsh_ls_rd_l2_dly (l2_cpu3_flsh_ls_rd_l2_dly), + .l2_cpu3_flsh_ls_rd_l4_dly (l2_cpu3_flsh_ls_rd_l4_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_evict_l4_dly (l2_cpu3_flsh_ls_wr_evict_l4_dly), + .l2_cpu3_flsh_ls_wr_id_l2_dly (l2_cpu3_flsh_ls_wr_id_l2_dly[3:0]), + .l2_cpu3_flsh_ls_wr_id_l4_dly (l2_cpu3_flsh_ls_wr_id_l4_dly[3:0]), + .l2_cpu3_flsh_ls_wr_l2_dly (l2_cpu3_flsh_ls_wr_l2_dly), + .l2_cpu3_flsh_ls_wr_l4_dly (l2_cpu3_flsh_ls_wr_l4_dly), + .l2_cpu3_flsh_tw_rd_l4_dly (l2_cpu3_flsh_tw_rd_l4_dly), + .l2_cpu3_ibufid_r1 (l2_cpu3_ibufid_r1[1:0]), + .l2_cpu3_ic_barrier_stall_q (l2_cpu3_ic_barrier_stall_q), + .l2_cpu3_ic_base (l2_cpu3_ic_base[43:18]), + .l2_cpu3_ic_vld_skid (l2_cpu3_ic_vld_skid), + .l2_cpu3_idata_r2 (l2_cpu3_idata_r2[127:0]), + .l2_cpu3_idbl_ecc_err_r3 (l2_cpu3_idbl_ecc_err_r3), + .l2_cpu3_idle_block_reqs_q (l2_cpu3_idle_block_reqs_q), + .l2_cpu3_iext_err_r2 (l2_cpu3_iext_err_r2), + .l2_cpu3_iext_err_type_r2 (l2_cpu3_iext_err_type_r2), + .l2_cpu3_if_ccb_clken_c3 (l2_cpu3_if_ccb_clken_c3), + .l2_cpu3_if_ccb_req_c3 (l2_cpu3_if_ccb_req_c3), + .l2_cpu3_if_sync_req (l2_cpu3_if_sync_req), + .l2_cpu3_ifq_haz_pending (l2_cpu3_ifq_haz_pending), + .l2_cpu3_isngl_ecc_err_r3 (l2_cpu3_isngl_ecc_err_r3), + .l2_cpu3_ivalid_r1 (l2_cpu3_ivalid_r1), + .l2_cpu3_l2_cache_size (l2_cpu3_l2_cache_size[1:0]), + .l2_cpu3_lrq_haz_pending (l2_cpu3_lrq_haz_pending), + .l2_cpu3_ls_ccb_clken_c3 (l2_cpu3_ls_ccb_clken_c3), + .l2_cpu3_ls_ccb_req_c3 (l2_cpu3_ls_ccb_req_c3), + .l2_cpu3_ls_peq_coll_l4_dly (l2_cpu3_ls_peq_coll_l4_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_sync_req (l2_cpu3_ls_sync_req), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_mbist1_addr_b1 (l2_cpu3_mbist1_addr_b1[12:0]), + .l2_cpu3_mbist1_all_b1 (l2_cpu3_mbist1_all_b1), + .l2_cpu3_mbist1_array_b1 (l2_cpu3_mbist1_array_b1[3:0]), + .l2_cpu3_mbist1_be_b1 (l2_cpu3_mbist1_be_b1[7:0]), + .l2_cpu3_mbist1_en_b1 (l2_cpu3_mbist1_en_b1), + .l2_cpu3_mbist1_rd_en_b1 (l2_cpu3_mbist1_rd_en_b1), + .l2_cpu3_mbist1_wr_en_b1 (l2_cpu3_mbist1_wr_en_b1), + .l2_cpu3_no_intctrl (l2_cpu3_no_intctrl), + .l2_cpu3_pf_rd_vld_skid_popped (l2_cpu3_pf_rd_vld_skid_popped), + .l2_cpu3_pf_throttle_q (l2_cpu3_pf_throttle_q), + .l2_cpu3_pmu_events (l2_cpu3_pmu_events[33:0]), + .l2_cpu3_rbufid (l2_cpu3_rbufid[2:0]), + .l2_cpu3_rd_arb (l2_cpu3_rd_arb), + .l2_cpu3_rd_vld_skid (l2_cpu3_rd_vld_skid), + .l2_cpu3_rexfail (l2_cpu3_rexfail), + .l2_cpu3_rstate (l2_cpu3_rstate[1:0]), + .l2_cpu3_rvalid (l2_cpu3_rvalid), + .l2_cpu3_snp_active (l2_cpu3_snp_active), + .l2_cpu3_spec_bufid (l2_cpu3_spec_bufid[2:0]), + .l2_cpu3_spec_valid (l2_cpu3_spec_valid), + .l2_cpu3_spr_rd_data (l2_cpu3_spr_rd_data[63:0]), + .l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_tbw_dbl_ecc_err (l2_cpu3_tbw_dbl_ecc_err), + .l2_cpu3_tbw_desc_data (l2_cpu3_tbw_desc_data[63:0]), + .l2_cpu3_tbw_desc_vld (l2_cpu3_tbw_desc_vld), + .l2_cpu3_tbw_ext_err (l2_cpu3_tbw_ext_err), + .l2_cpu3_tbw_ext_err_type (l2_cpu3_tbw_ext_err_type), + .l2_cpu3_tlb_ccb_clken_c3 (l2_cpu3_tlb_ccb_clken_c3), + .l2_cpu3_tlb_ccb_req_c3 (l2_cpu3_tlb_ccb_req_c3), + .l2_cpu3_tlb_sync_complete (l2_cpu3_tlb_sync_complete), + .l2_cpu3_tlb_sync_req (l2_cpu3_tlb_sync_req), + .l2_cpu3_trq_haz_pending (l2_cpu3_trq_haz_pending), + .l2_cpu3_wr_arb (l2_cpu3_wr_arb), + .l2_cpu3_wr_data_stall (l2_cpu3_wr_data_stall), + .l2_cpu3_wr_decerr_q (l2_cpu3_wr_decerr_q), + .l2_cpu3_wr_ex_fail (l2_cpu3_wr_ex_fail), + .l2_cpu3_wr_ex_resp (l2_cpu3_wr_ex_resp), + .l2_cpu3_wr_slverr_q (l2_cpu3_wr_slverr_q), + .l2_cpu3_wr_vld_skid (l2_cpu3_wr_vld_skid), + .l2_cpu3_wrq_haz_pending (l2_cpu3_wrq_haz_pending), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_idle (l2_idle), + .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), + .l2_mbist2_tbnk0_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), + .l2_mbist2_tbnk0_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), + .l2_mbist2_tbnk0_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), + .l2_mbist2_tbnk0_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), + .l2_mbist2_tbnk0_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), + .l2_mbist2_tbnk1_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), + .l2_mbist2_tbnk1_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), + .l2_mbist2_tbnk1_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), + .l2_mbist2_tbnk1_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), + .l2_mbist2_tbnk1_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_p_addr (l2_p_addr[13:0]), + .l2_p_cpu (l2_p_cpu[1:0]), + .l2_p_nsecure (l2_p_nsecure), + .l2_p_sel (l2_p_sel[2:0]), + .l2_p_wdata (l2_p_wdata[31:0]), + .l2_p_write (l2_p_write), + .l2_reset3 (l2_reset3), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_sky_link_stopped (l2_sky_link_stopped), + .l2_tbnk0_addr_l1 (l2_tbnk0_addr_l1[44:0]), + .l2_tbnk0_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), + .l2_tbnk0_asq_full_flsh (l2_tbnk0_asq_full_flsh), + .l2_tbnk0_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), + .l2_tbnk0_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), + .l2_tbnk0_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), + .l2_tbnk0_cpu0_ifq_clr_l4_dly2_q (l2_tbnk0_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu0_lrq_clr_l4_dly2_q (l2_tbnk0_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), + .l2_tbnk0_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), + .l2_tbnk0_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), + .l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), + .l2_tbnk0_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), + .l2_tbnk0_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu0_trq_clr_l4_dly2_q (l2_tbnk0_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu0_wrq_clr_l4_dly2_q (l2_tbnk0_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu1_ifq_clr_l4_dly2_q (l2_tbnk0_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu1_lrq_clr_l4_dly2_q (l2_tbnk0_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), + .l2_tbnk0_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), + .l2_tbnk0_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), + .l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), + .l2_tbnk0_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), + .l2_tbnk0_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu1_trq_clr_l4_dly2_q (l2_tbnk0_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu1_wrq_clr_l4_dly2_q (l2_tbnk0_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu2_ifq_clr_l4_dly2_q (l2_tbnk0_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu2_lrq_clr_l4_dly2_q (l2_tbnk0_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), + .l2_tbnk0_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), + .l2_tbnk0_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), + .l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), + .l2_tbnk0_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), + .l2_tbnk0_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu2_trq_clr_l4_dly2_q (l2_tbnk0_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu2_wrq_clr_l4_dly2_q (l2_tbnk0_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_cpu3_ifq_clr_l4_dly2_q (l2_tbnk0_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk0_cpu3_lrq_clr_l4_dly2_q (l2_tbnk0_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk0_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), + .l2_tbnk0_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), + .l2_tbnk0_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), + .l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk0_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), + .l2_tbnk0_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), + .l2_tbnk0_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk0_cpu3_trq_clr_l4_dly2_q (l2_tbnk0_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk0_cpu3_wrq_clr_l4_dly2_q (l2_tbnk0_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk0_dirty_l1 (l2_tbnk0_dirty_l1), + .l2_tbnk0_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), + .l2_tbnk0_excl_l1 (l2_tbnk0_excl_l1), + .l2_tbnk0_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), + .l2_tbnk0_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), + .l2_tbnk0_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), + .l2_tbnk0_feq_kill_l3 (l2_tbnk0_feq_kill_l3), + .l2_tbnk0_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), + .l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk0_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), + .l2_tbnk0_id_l1 (l2_tbnk0_id_l1[9:0]), + .l2_tbnk0_init_req_l1 (l2_tbnk0_init_req_l1), + .l2_tbnk0_kill_l2 (l2_tbnk0_kill_l2), + .l2_tbnk0_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), + .l2_tbnk0_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), + .l2_tbnk0_last_qw_l1 (l2_tbnk0_last_qw_l1), + .l2_tbnk0_lock_l1 (l2_tbnk0_lock_l1[2:0]), + .l2_tbnk0_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), + .l2_tbnk0_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), + .l2_tbnk0_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), + .l2_tbnk0_prfm_l1 (l2_tbnk0_prfm_l1), + .l2_tbnk0_prot_l1 (l2_tbnk0_prot_l1[3:0]), + .l2_tbnk0_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), + .l2_tbnk0_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), + .l2_tbnk0_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), + .l2_tbnk0_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), + .l2_tbnk0_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), + .l2_tbnk0_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), + .l2_tbnk0_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), + .l2_tbnk0_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), + .l2_tbnk0_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), + .l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk0_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk0_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk0_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), + .l2_tbnk0_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk0_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), + .l2_tbnk0_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), + .l2_tbnk0_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), + .l2_tbnk0_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), + .l2_tbnk0_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), + .l2_tbnk0_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), + .l2_tbnk0_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), + .l2_tbnk0_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), + .l2_tbnk0_sel_l1 (l2_tbnk0_sel_l1[13:0]), + .l2_tbnk0_size_l1 (l2_tbnk0_size_l1[2:0]), + .l2_tbnk0_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), + .l2_tbnk0_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), + .l2_tbnk0_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), + .l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk0_sync_l1 (l2_tbnk0_sync_l1), + .l2_tbnk0_type_l1 (l2_tbnk0_type_l1[6:0]), + .l2_tbnk0_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), + .l2_tbnk0_way_l1 (l2_tbnk0_way_l1), + .l2_tbnk0_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), + .l2_tbnk0_wr_err_l1 (l2_tbnk0_wr_err_l1), + .l2_tbnk0_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), + .l2_tbnk0_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), + .l2_tbnk0_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), + .l2_tbnk0_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]), + .l2_tbnk1_addr_l1 (l2_tbnk1_addr_l1[44:0]), + .l2_tbnk1_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), + .l2_tbnk1_asq_full_flsh (l2_tbnk1_asq_full_flsh), + .l2_tbnk1_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), + .l2_tbnk1_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), + .l2_tbnk1_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), + .l2_tbnk1_cpu0_ifq_clr_l4_dly2_q (l2_tbnk1_cpu0_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu0_lrq_clr_l4_dly2_q (l2_tbnk1_cpu0_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), + .l2_tbnk1_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), + .l2_tbnk1_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), + .l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), + .l2_tbnk1_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), + .l2_tbnk1_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu0_trq_clr_l4_dly2_q (l2_tbnk1_cpu0_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu0_wrq_clr_l4_dly2_q (l2_tbnk1_cpu0_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu1_ifq_clr_l4_dly2_q (l2_tbnk1_cpu1_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu1_lrq_clr_l4_dly2_q (l2_tbnk1_cpu1_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), + .l2_tbnk1_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), + .l2_tbnk1_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), + .l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), + .l2_tbnk1_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), + .l2_tbnk1_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu1_trq_clr_l4_dly2_q (l2_tbnk1_cpu1_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu1_wrq_clr_l4_dly2_q (l2_tbnk1_cpu1_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu2_ifq_clr_l4_dly2_q (l2_tbnk1_cpu2_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu2_lrq_clr_l4_dly2_q (l2_tbnk1_cpu2_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), + .l2_tbnk1_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), + .l2_tbnk1_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), + .l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), + .l2_tbnk1_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), + .l2_tbnk1_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu2_trq_clr_l4_dly2_q (l2_tbnk1_cpu2_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu2_wrq_clr_l4_dly2_q (l2_tbnk1_cpu2_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_cpu3_ifq_clr_l4_dly2_q (l2_tbnk1_cpu3_ifq_clr_l4_dly2_q[2:0]), + .l2_tbnk1_cpu3_lrq_clr_l4_dly2_q (l2_tbnk1_cpu3_lrq_clr_l4_dly2_q[3:0]), + .l2_tbnk1_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), + .l2_tbnk1_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), + .l2_tbnk1_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), + .l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk1_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), + .l2_tbnk1_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), + .l2_tbnk1_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk1_cpu3_trq_clr_l4_dly2_q (l2_tbnk1_cpu3_trq_clr_l4_dly2_q), + .l2_tbnk1_cpu3_wrq_clr_l4_dly2_q (l2_tbnk1_cpu3_wrq_clr_l4_dly2_q[5:0]), + .l2_tbnk1_dirty_l1 (l2_tbnk1_dirty_l1), + .l2_tbnk1_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), + .l2_tbnk1_excl_l1 (l2_tbnk1_excl_l1), + .l2_tbnk1_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), + .l2_tbnk1_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), + .l2_tbnk1_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), + .l2_tbnk1_feq_kill_l3 (l2_tbnk1_feq_kill_l3), + .l2_tbnk1_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), + .l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk1_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), + .l2_tbnk1_id_l1 (l2_tbnk1_id_l1[9:0]), + .l2_tbnk1_init_req_l1 (l2_tbnk1_init_req_l1), + .l2_tbnk1_kill_l2 (l2_tbnk1_kill_l2), + .l2_tbnk1_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), + .l2_tbnk1_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), + .l2_tbnk1_last_qw_l1 (l2_tbnk1_last_qw_l1), + .l2_tbnk1_lock_l1 (l2_tbnk1_lock_l1[2:0]), + .l2_tbnk1_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), + .l2_tbnk1_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), + .l2_tbnk1_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), + .l2_tbnk1_prfm_l1 (l2_tbnk1_prfm_l1), + .l2_tbnk1_prot_l1 (l2_tbnk1_prot_l1[3:0]), + .l2_tbnk1_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), + .l2_tbnk1_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), + .l2_tbnk1_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), + .l2_tbnk1_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), + .l2_tbnk1_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), + .l2_tbnk1_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), + .l2_tbnk1_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), + .l2_tbnk1_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), + .l2_tbnk1_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), + .l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk1_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk1_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk1_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), + .l2_tbnk1_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk1_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), + .l2_tbnk1_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), + .l2_tbnk1_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), + .l2_tbnk1_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), + .l2_tbnk1_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), + .l2_tbnk1_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), + .l2_tbnk1_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), + .l2_tbnk1_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), + .l2_tbnk1_sel_l1 (l2_tbnk1_sel_l1[13:0]), + .l2_tbnk1_size_l1 (l2_tbnk1_size_l1[2:0]), + .l2_tbnk1_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), + .l2_tbnk1_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), + .l2_tbnk1_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), + .l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk1_sync_l1 (l2_tbnk1_sync_l1), + .l2_tbnk1_type_l1 (l2_tbnk1_type_l1[6:0]), + .l2_tbnk1_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), + .l2_tbnk1_way_l1 (l2_tbnk1_way_l1), + .l2_tbnk1_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), + .l2_tbnk1_wr_err_l1 (l2_tbnk1_wr_err_l1), + .l2_tbnk1_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), + .l2_tbnk1_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), + .l2_tbnk1_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), + .l2_tbnk1_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .nEXTERRIRQ (nEXTERRIRQ), + .nINTERRIRQ (nINTERRIRQ), + + // inputs + .ACLKENS (ACLKENS), + .ARADDRS (ARADDRS[43:0]), + .ARCACHES (ARCACHES[3:0]), + .ARIDS (ARIDS[4:0]), + .ARLENS (ARLENS[7:0]), + .ARPROTS (ARPROTS[2:0]), + .ARUSERS (ARUSERS[1:0]), + .ARVALIDS (ARVALIDS), + .AWADDRS (AWADDRS[43:0]), + .AWCACHES (AWCACHES[3:0]), + .AWIDS (AWIDS[4:0]), + .AWLENS (AWLENS[7:0]), + .AWPROTS (AWPROTS[2:0]), + .AWUSERS (AWUSERS[1:0]), + .AWVALIDS (AWVALIDS), + .BREADYS (BREADYS), + .BROADCASTCACHEMAINT (BROADCASTCACHEMAINT), + .BROADCASTINNER (BROADCASTINNER), + .BROADCASTOUTER (BROADCASTOUTER), + .DBGL1RSTDISABLE (DBGL1RSTDISABLE), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .L2FLUSHREQ (L2FLUSHREQ), + .L2QREQn (L2QREQn), + .L2RSTDISABLE (L2RSTDISABLE), + .MBISTREQ (MBISTREQ), + .NODEID (NODEID[6:0]), + .PERIPHBASE (PERIPHBASE[43:18]), + .RREADYS (RREADYS), + .RXDATFLIT (RXDATFLIT[193:0]), + .RXDATFLITPEND (RXDATFLITPEND), + .RXDATFLITV (RXDATFLITV), + .RXLINKACTIVEREQ (RXLINKACTIVEREQ), + .RXRSPFLIT (RXRSPFLIT[44:0]), + .RXRSPFLITPEND (RXRSPFLITPEND), + .RXRSPFLITV (RXRSPFLITV), + .RXSACTIVE (RXSACTIVE), + .RXSNPFLIT (RXSNPFLIT[64:0]), + .RXSNPFLITPEND (RXSNPFLITPEND), + .RXSNPFLITV (RXSNPFLITV), + .SAMADDRMAP0 (SAMADDRMAP0[1:0]), + .SAMADDRMAP1 (SAMADDRMAP1[1:0]), + .SAMADDRMAP10 (SAMADDRMAP10[1:0]), + .SAMADDRMAP11 (SAMADDRMAP11[1:0]), + .SAMADDRMAP12 (SAMADDRMAP12[1:0]), + .SAMADDRMAP13 (SAMADDRMAP13[1:0]), + .SAMADDRMAP14 (SAMADDRMAP14[1:0]), + .SAMADDRMAP15 (SAMADDRMAP15[1:0]), + .SAMADDRMAP16 (SAMADDRMAP16[1:0]), + .SAMADDRMAP17 (SAMADDRMAP17[1:0]), + .SAMADDRMAP18 (SAMADDRMAP18[1:0]), + .SAMADDRMAP19 (SAMADDRMAP19[1:0]), + .SAMADDRMAP2 (SAMADDRMAP2[1:0]), + .SAMADDRMAP3 (SAMADDRMAP3[1:0]), + .SAMADDRMAP4 (SAMADDRMAP4[1:0]), + .SAMADDRMAP5 (SAMADDRMAP5[1:0]), + .SAMADDRMAP6 (SAMADDRMAP6[1:0]), + .SAMADDRMAP7 (SAMADDRMAP7[1:0]), + .SAMADDRMAP8 (SAMADDRMAP8[1:0]), + .SAMADDRMAP9 (SAMADDRMAP9[1:0]), + .SAMHNF0NODEID (SAMHNF0NODEID[6:0]), + .SAMHNF1NODEID (SAMHNF1NODEID[6:0]), + .SAMHNF2NODEID (SAMHNF2NODEID[6:0]), + .SAMHNF3NODEID (SAMHNF3NODEID[6:0]), + .SAMHNF4NODEID (SAMHNF4NODEID[6:0]), + .SAMHNF5NODEID (SAMHNF5NODEID[6:0]), + .SAMHNF6NODEID (SAMHNF6NODEID[6:0]), + .SAMHNF7NODEID (SAMHNF7NODEID[6:0]), + .SAMHNFMODE (SAMHNFMODE[2:0]), + .SAMHNI0NODEID (SAMHNI0NODEID[6:0]), + .SAMHNI1NODEID (SAMHNI1NODEID[6:0]), + .SAMMNBASE (SAMMNBASE[43:24]), + .SAMMNNODEID (SAMMNNODEID[6:0]), + .SCLKEN (SCLKEN), + .SYSBARDISABLE (SYSBARDISABLE), + .TXDATLCRDV (TXDATLCRDV), + .TXLINKACTIVEACK (TXLINKACTIVEACK), + .TXREQLCRDV (TXREQLCRDV), + .TXRSPLCRDV (TXRSPLCRDV), + .WDATAS (WDATAS[127:0]), + .WLASTS (WLASTS), + .WSTRBS (WSTRBS[15:0]), + .WVALIDS (WVALIDS), + .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), + .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), + .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), + .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), + .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), + .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), + .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), + .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), + .ck_gclkfr (ck_gclkfr), + .ck_gclkl2 (ck_gclkl2), + .ck_l2_ace_inactive (ck_l2_ace_inactive), + .ck_l2_acp_inactive (ck_l2_acp_inactive), + .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_en (ds_cpu0_l2_spr_en), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_en (ds_cpu1_l2_spr_en), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_en (ds_cpu2_l2_spr_en), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_en (ds_cpu3_l2_spr_en), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), + .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), + .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), + .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), + .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), + .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), + .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), + .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), + .ic_p_rdata (ic_p_rdata[31:0]), + .ic_p_rdata_valid (ic_p_rdata_valid), + .ic_p_ready (ic_p_ready), + .l2_cpu0_dsq_rd_byte_strb_q (l2_cpu0_dsq_rd_byte_strb_q[15:0]), + .l2_cpu0_dsq_rd_data_q (l2_cpu0_dsq_rd_data_q[129:0]), + .l2_cpu0_dt_pmu_evt_en (l2_cpu0_dt_pmu_evt_en), + .l2_cpu0_early_rd_reqe4_e5_q (l2_cpu0_early_rd_reqe4_e5_q), + .l2_cpu0_ic_addr_arb_set (l2_cpu0_ic_addr_arb_set[15:0]), + .l2_cpu0_ic_arb_fast (l2_cpu0_ic_arb_fast), + .l2_cpu0_ic_data_arb_set (l2_cpu0_ic_data_arb_set[31:0]), + .l2_cpu0_ic_elem_size_arb_set (l2_cpu0_ic_elem_size_arb_set[2:0]), + .l2_cpu0_ic_excl_arb_set (l2_cpu0_ic_excl_arb_set), + .l2_cpu0_ic_id_arb_set (l2_cpu0_ic_id_arb_set[2:0]), + .l2_cpu0_ic_ns_arb_set (l2_cpu0_ic_ns_arb_set), + .l2_cpu0_ic_write_arb_set (l2_cpu0_ic_write_arb_set), + .l2_cpu0_idle_wakeup_q (l2_cpu0_idle_wakeup_q), + .l2_cpu0_if_ccb_resp (l2_cpu0_if_ccb_resp), + .l2_cpu0_if_ccb_resp_id (l2_cpu0_if_ccb_resp_id[4:0]), + .l2_cpu0_if_sync_done_q (l2_cpu0_if_sync_done_q), + .l2_cpu0_lrq_haz_clr_id_dcd_q (l2_cpu0_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu0_ls_ccb_data_wr (l2_cpu0_ls_ccb_data_wr), + .l2_cpu0_ls_ccb_resp (l2_cpu0_ls_ccb_resp), + .l2_cpu0_ls_ccb_resp_id (l2_cpu0_ls_ccb_resp_id[4:0]), + .l2_cpu0_ls_rd_haz_id_arb_q (l2_cpu0_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu0_ls_rd_haz_vld_arb_q (l2_cpu0_ls_rd_haz_vld_arb_q), + .l2_cpu0_ls_wr_ccb_id_w2a (l2_cpu0_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu0_ls_wr_data_w2a (l2_cpu0_ls_wr_data_w2a[127:0]), + .l2_cpu0_ls_wr_dirty_w2a (l2_cpu0_ls_wr_dirty_w2a), + .l2_cpu0_ls_wr_err_w2a (l2_cpu0_ls_wr_err_w2a), + .l2_cpu0_ls_wr_haz_id_arb_q (l2_cpu0_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu0_ls_wr_haz_vld_arb_q (l2_cpu0_ls_wr_haz_vld_arb_q), + .l2_cpu0_ls_wr_last_w2a (l2_cpu0_ls_wr_last_w2a), + .l2_cpu0_ls_wr_req_w2a (l2_cpu0_ls_wr_req_w2a), + .l2_cpu0_ls_wr_type_w2a (l2_cpu0_ls_wr_type_w2a[2:0]), + .l2_cpu0_rd_aarch64_arb_set (l2_cpu0_rd_aarch64_arb_set), + .l2_cpu0_rd_addr_arb_set (l2_cpu0_rd_addr_arb_set[44:0]), + .l2_cpu0_rd_arb_fast (l2_cpu0_rd_arb_fast), + .l2_cpu0_rd_asid_arb_set (l2_cpu0_rd_asid_arb_set[15:8]), + .l2_cpu0_rd_bypass_arb_set (l2_cpu0_rd_bypass_arb_set), + .l2_cpu0_rd_bypass_bufid_e5 (l2_cpu0_rd_bypass_bufid_e5[2:0]), + .l2_cpu0_rd_bypass_lrq_id_e5 (l2_cpu0_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu0_rd_bypass_req_can_e5 (l2_cpu0_rd_bypass_req_can_e5), + .l2_cpu0_rd_bypass_way_e5 (l2_cpu0_rd_bypass_way_e5), + .l2_cpu0_rd_cache_attr_arb_set (l2_cpu0_rd_cache_attr_arb_set[2:0]), + .l2_cpu0_rd_elem_size_arb_set (l2_cpu0_rd_elem_size_arb_set[2:0]), + .l2_cpu0_rd_excl_arb_set (l2_cpu0_rd_excl_arb_set), + .l2_cpu0_rd_id_arb_set (l2_cpu0_rd_id_arb_set[4:0]), + .l2_cpu0_rd_lrq_id_arb_set (l2_cpu0_rd_lrq_id_arb_set[2:0]), + .l2_cpu0_rd_page_attr_arb_set (l2_cpu0_rd_page_attr_arb_set[7:0]), + .l2_cpu0_rd_prfm_arb_set (l2_cpu0_rd_prfm_arb_set), + .l2_cpu0_rd_priv_arb_set (l2_cpu0_rd_priv_arb_set), + .l2_cpu0_rd_replayed_arb_set (l2_cpu0_rd_replayed_arb_set), + .l2_cpu0_rd_shared_arb_set (l2_cpu0_rd_shared_arb_set[1:0]), + .l2_cpu0_rd_type_arb_set (l2_cpu0_rd_type_arb_set[6:0]), + .l2_cpu0_rd_va48_arb_set (l2_cpu0_rd_va48_arb_set), + .l2_cpu0_rd_way_arb_set (l2_cpu0_rd_way_arb_set), + .l2_cpu0_tlb_sync_done_q (l2_cpu0_tlb_sync_done_q), + .l2_cpu0_tw_ccb_resp (l2_cpu0_tw_ccb_resp), + .l2_cpu0_tw_ccb_resp_id (l2_cpu0_tw_ccb_resp_id[4:0]), + .l2_cpu0_wr_1st_replayed_arb_set (l2_cpu0_wr_1st_replayed_arb_set), + .l2_cpu0_wr_addr_arb_set (l2_cpu0_wr_addr_arb_set[44:0]), + .l2_cpu0_wr_arb_fast (l2_cpu0_wr_arb_fast), + .l2_cpu0_wr_cache_attr_arb_set (l2_cpu0_wr_cache_attr_arb_set[2:0]), + .l2_cpu0_wr_cl_id_arb_set (l2_cpu0_wr_cl_id_arb_set[11:0]), + .l2_cpu0_wr_clean_evict_arb_set (l2_cpu0_wr_clean_evict_arb_set), + .l2_cpu0_wr_data (l2_cpu0_wr_data[143:0]), + .l2_cpu0_wr_data_vld_x1_q (l2_cpu0_wr_data_vld_x1_q), + .l2_cpu0_wr_dirty_arb_set (l2_cpu0_wr_dirty_arb_set), + .l2_cpu0_wr_elem_size_arb_set (l2_cpu0_wr_elem_size_arb_set[2:0]), + .l2_cpu0_wr_err_arb_set (l2_cpu0_wr_err_arb_set), + .l2_cpu0_wr_evict_x1_q (l2_cpu0_wr_evict_x1_q), + .l2_cpu0_wr_id_arb_set (l2_cpu0_wr_id_arb_set[3:0]), + .l2_cpu0_wr_last_arb_set (l2_cpu0_wr_last_arb_set), + .l2_cpu0_wr_page_attr_arb_set (l2_cpu0_wr_page_attr_arb_set[7:0]), + .l2_cpu0_wr_partial_dw_arb_set (l2_cpu0_wr_partial_dw_arb_set[3:0]), + .l2_cpu0_wr_priv_arb_set (l2_cpu0_wr_priv_arb_set), + .l2_cpu0_wr_shared_arb_set (l2_cpu0_wr_shared_arb_set[1:0]), + .l2_cpu0_wr_type_arb_set (l2_cpu0_wr_type_arb_set[2:0]), + .l2_cpu0_wr_way_arb_set (l2_cpu0_wr_way_arb_set), + .l2_cpu0_wrq_almost_full (l2_cpu0_wrq_almost_full), + .l2_cpu0_wrq_haz_clr_id_dcd_q (l2_cpu0_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu1_dsq_rd_byte_strb_q (l2_cpu1_dsq_rd_byte_strb_q[15:0]), + .l2_cpu1_dsq_rd_data_q (l2_cpu1_dsq_rd_data_q[129:0]), + .l2_cpu1_dt_pmu_evt_en (l2_cpu1_dt_pmu_evt_en), + .l2_cpu1_early_rd_reqe4_e5_q (l2_cpu1_early_rd_reqe4_e5_q), + .l2_cpu1_ic_addr_arb_set (l2_cpu1_ic_addr_arb_set[15:0]), + .l2_cpu1_ic_arb_fast (l2_cpu1_ic_arb_fast), + .l2_cpu1_ic_data_arb_set (l2_cpu1_ic_data_arb_set[31:0]), + .l2_cpu1_ic_elem_size_arb_set (l2_cpu1_ic_elem_size_arb_set[2:0]), + .l2_cpu1_ic_excl_arb_set (l2_cpu1_ic_excl_arb_set), + .l2_cpu1_ic_id_arb_set (l2_cpu1_ic_id_arb_set[2:0]), + .l2_cpu1_ic_ns_arb_set (l2_cpu1_ic_ns_arb_set), + .l2_cpu1_ic_write_arb_set (l2_cpu1_ic_write_arb_set), + .l2_cpu1_idle_wakeup_q (l2_cpu1_idle_wakeup_q), + .l2_cpu1_if_ccb_resp (l2_cpu1_if_ccb_resp), + .l2_cpu1_if_ccb_resp_id (l2_cpu1_if_ccb_resp_id[4:0]), + .l2_cpu1_if_sync_done_q (l2_cpu1_if_sync_done_q), + .l2_cpu1_lrq_haz_clr_id_dcd_q (l2_cpu1_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu1_ls_ccb_data_wr (l2_cpu1_ls_ccb_data_wr), + .l2_cpu1_ls_ccb_resp (l2_cpu1_ls_ccb_resp), + .l2_cpu1_ls_ccb_resp_id (l2_cpu1_ls_ccb_resp_id[4:0]), + .l2_cpu1_ls_rd_haz_id_arb_q (l2_cpu1_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu1_ls_rd_haz_vld_arb_q (l2_cpu1_ls_rd_haz_vld_arb_q), + .l2_cpu1_ls_wr_ccb_id_w2a (l2_cpu1_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu1_ls_wr_data_w2a (l2_cpu1_ls_wr_data_w2a[127:0]), + .l2_cpu1_ls_wr_dirty_w2a (l2_cpu1_ls_wr_dirty_w2a), + .l2_cpu1_ls_wr_err_w2a (l2_cpu1_ls_wr_err_w2a), + .l2_cpu1_ls_wr_haz_id_arb_q (l2_cpu1_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu1_ls_wr_haz_vld_arb_q (l2_cpu1_ls_wr_haz_vld_arb_q), + .l2_cpu1_ls_wr_last_w2a (l2_cpu1_ls_wr_last_w2a), + .l2_cpu1_ls_wr_req_w2a (l2_cpu1_ls_wr_req_w2a), + .l2_cpu1_ls_wr_type_w2a (l2_cpu1_ls_wr_type_w2a[2:0]), + .l2_cpu1_rd_aarch64_arb_set (l2_cpu1_rd_aarch64_arb_set), + .l2_cpu1_rd_addr_arb_set (l2_cpu1_rd_addr_arb_set[44:0]), + .l2_cpu1_rd_arb_fast (l2_cpu1_rd_arb_fast), + .l2_cpu1_rd_asid_arb_set (l2_cpu1_rd_asid_arb_set[15:8]), + .l2_cpu1_rd_bypass_arb_set (l2_cpu1_rd_bypass_arb_set), + .l2_cpu1_rd_bypass_bufid_e5 (l2_cpu1_rd_bypass_bufid_e5[2:0]), + .l2_cpu1_rd_bypass_lrq_id_e5 (l2_cpu1_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu1_rd_bypass_req_can_e5 (l2_cpu1_rd_bypass_req_can_e5), + .l2_cpu1_rd_bypass_way_e5 (l2_cpu1_rd_bypass_way_e5), + .l2_cpu1_rd_cache_attr_arb_set (l2_cpu1_rd_cache_attr_arb_set[2:0]), + .l2_cpu1_rd_elem_size_arb_set (l2_cpu1_rd_elem_size_arb_set[2:0]), + .l2_cpu1_rd_excl_arb_set (l2_cpu1_rd_excl_arb_set), + .l2_cpu1_rd_id_arb_set (l2_cpu1_rd_id_arb_set[4:0]), + .l2_cpu1_rd_lrq_id_arb_set (l2_cpu1_rd_lrq_id_arb_set[2:0]), + .l2_cpu1_rd_page_attr_arb_set (l2_cpu1_rd_page_attr_arb_set[7:0]), + .l2_cpu1_rd_prfm_arb_set (l2_cpu1_rd_prfm_arb_set), + .l2_cpu1_rd_priv_arb_set (l2_cpu1_rd_priv_arb_set), + .l2_cpu1_rd_replayed_arb_set (l2_cpu1_rd_replayed_arb_set), + .l2_cpu1_rd_shared_arb_set (l2_cpu1_rd_shared_arb_set[1:0]), + .l2_cpu1_rd_type_arb_set (l2_cpu1_rd_type_arb_set[6:0]), + .l2_cpu1_rd_va48_arb_set (l2_cpu1_rd_va48_arb_set), + .l2_cpu1_rd_way_arb_set (l2_cpu1_rd_way_arb_set), + .l2_cpu1_tlb_sync_done_q (l2_cpu1_tlb_sync_done_q), + .l2_cpu1_tw_ccb_resp (l2_cpu1_tw_ccb_resp), + .l2_cpu1_tw_ccb_resp_id (l2_cpu1_tw_ccb_resp_id[4:0]), + .l2_cpu1_wr_1st_replayed_arb_set (l2_cpu1_wr_1st_replayed_arb_set), + .l2_cpu1_wr_addr_arb_set (l2_cpu1_wr_addr_arb_set[44:0]), + .l2_cpu1_wr_arb_fast (l2_cpu1_wr_arb_fast), + .l2_cpu1_wr_cache_attr_arb_set (l2_cpu1_wr_cache_attr_arb_set[2:0]), + .l2_cpu1_wr_cl_id_arb_set (l2_cpu1_wr_cl_id_arb_set[11:0]), + .l2_cpu1_wr_clean_evict_arb_set (l2_cpu1_wr_clean_evict_arb_set), + .l2_cpu1_wr_data (l2_cpu1_wr_data[143:0]), + .l2_cpu1_wr_data_vld_x1_q (l2_cpu1_wr_data_vld_x1_q), + .l2_cpu1_wr_dirty_arb_set (l2_cpu1_wr_dirty_arb_set), + .l2_cpu1_wr_elem_size_arb_set (l2_cpu1_wr_elem_size_arb_set[2:0]), + .l2_cpu1_wr_err_arb_set (l2_cpu1_wr_err_arb_set), + .l2_cpu1_wr_evict_x1_q (l2_cpu1_wr_evict_x1_q), + .l2_cpu1_wr_id_arb_set (l2_cpu1_wr_id_arb_set[3:0]), + .l2_cpu1_wr_last_arb_set (l2_cpu1_wr_last_arb_set), + .l2_cpu1_wr_page_attr_arb_set (l2_cpu1_wr_page_attr_arb_set[7:0]), + .l2_cpu1_wr_partial_dw_arb_set (l2_cpu1_wr_partial_dw_arb_set[3:0]), + .l2_cpu1_wr_priv_arb_set (l2_cpu1_wr_priv_arb_set), + .l2_cpu1_wr_shared_arb_set (l2_cpu1_wr_shared_arb_set[1:0]), + .l2_cpu1_wr_type_arb_set (l2_cpu1_wr_type_arb_set[2:0]), + .l2_cpu1_wr_way_arb_set (l2_cpu1_wr_way_arb_set), + .l2_cpu1_wrq_almost_full (l2_cpu1_wrq_almost_full), + .l2_cpu1_wrq_haz_clr_id_dcd_q (l2_cpu1_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu2_dsq_rd_byte_strb_q (l2_cpu2_dsq_rd_byte_strb_q[15:0]), + .l2_cpu2_dsq_rd_data_q (l2_cpu2_dsq_rd_data_q[129:0]), + .l2_cpu2_dt_pmu_evt_en (l2_cpu2_dt_pmu_evt_en), + .l2_cpu2_early_rd_reqe4_e5_q (l2_cpu2_early_rd_reqe4_e5_q), + .l2_cpu2_ic_addr_arb_set (l2_cpu2_ic_addr_arb_set[15:0]), + .l2_cpu2_ic_arb_fast (l2_cpu2_ic_arb_fast), + .l2_cpu2_ic_data_arb_set (l2_cpu2_ic_data_arb_set[31:0]), + .l2_cpu2_ic_elem_size_arb_set (l2_cpu2_ic_elem_size_arb_set[2:0]), + .l2_cpu2_ic_excl_arb_set (l2_cpu2_ic_excl_arb_set), + .l2_cpu2_ic_id_arb_set (l2_cpu2_ic_id_arb_set[2:0]), + .l2_cpu2_ic_ns_arb_set (l2_cpu2_ic_ns_arb_set), + .l2_cpu2_ic_write_arb_set (l2_cpu2_ic_write_arb_set), + .l2_cpu2_idle_wakeup_q (l2_cpu2_idle_wakeup_q), + .l2_cpu2_if_ccb_resp (l2_cpu2_if_ccb_resp), + .l2_cpu2_if_ccb_resp_id (l2_cpu2_if_ccb_resp_id[4:0]), + .l2_cpu2_if_sync_done_q (l2_cpu2_if_sync_done_q), + .l2_cpu2_lrq_haz_clr_id_dcd_q (l2_cpu2_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu2_ls_ccb_data_wr (l2_cpu2_ls_ccb_data_wr), + .l2_cpu2_ls_ccb_resp (l2_cpu2_ls_ccb_resp), + .l2_cpu2_ls_ccb_resp_id (l2_cpu2_ls_ccb_resp_id[4:0]), + .l2_cpu2_ls_rd_haz_id_arb_q (l2_cpu2_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu2_ls_rd_haz_vld_arb_q (l2_cpu2_ls_rd_haz_vld_arb_q), + .l2_cpu2_ls_wr_ccb_id_w2a (l2_cpu2_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu2_ls_wr_data_w2a (l2_cpu2_ls_wr_data_w2a[127:0]), + .l2_cpu2_ls_wr_dirty_w2a (l2_cpu2_ls_wr_dirty_w2a), + .l2_cpu2_ls_wr_err_w2a (l2_cpu2_ls_wr_err_w2a), + .l2_cpu2_ls_wr_haz_id_arb_q (l2_cpu2_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu2_ls_wr_haz_vld_arb_q (l2_cpu2_ls_wr_haz_vld_arb_q), + .l2_cpu2_ls_wr_last_w2a (l2_cpu2_ls_wr_last_w2a), + .l2_cpu2_ls_wr_req_w2a (l2_cpu2_ls_wr_req_w2a), + .l2_cpu2_ls_wr_type_w2a (l2_cpu2_ls_wr_type_w2a[2:0]), + .l2_cpu2_rd_aarch64_arb_set (l2_cpu2_rd_aarch64_arb_set), + .l2_cpu2_rd_addr_arb_set (l2_cpu2_rd_addr_arb_set[44:0]), + .l2_cpu2_rd_arb_fast (l2_cpu2_rd_arb_fast), + .l2_cpu2_rd_asid_arb_set (l2_cpu2_rd_asid_arb_set[15:8]), + .l2_cpu2_rd_bypass_arb_set (l2_cpu2_rd_bypass_arb_set), + .l2_cpu2_rd_bypass_bufid_e5 (l2_cpu2_rd_bypass_bufid_e5[2:0]), + .l2_cpu2_rd_bypass_lrq_id_e5 (l2_cpu2_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu2_rd_bypass_req_can_e5 (l2_cpu2_rd_bypass_req_can_e5), + .l2_cpu2_rd_bypass_way_e5 (l2_cpu2_rd_bypass_way_e5), + .l2_cpu2_rd_cache_attr_arb_set (l2_cpu2_rd_cache_attr_arb_set[2:0]), + .l2_cpu2_rd_elem_size_arb_set (l2_cpu2_rd_elem_size_arb_set[2:0]), + .l2_cpu2_rd_excl_arb_set (l2_cpu2_rd_excl_arb_set), + .l2_cpu2_rd_id_arb_set (l2_cpu2_rd_id_arb_set[4:0]), + .l2_cpu2_rd_lrq_id_arb_set (l2_cpu2_rd_lrq_id_arb_set[2:0]), + .l2_cpu2_rd_page_attr_arb_set (l2_cpu2_rd_page_attr_arb_set[7:0]), + .l2_cpu2_rd_prfm_arb_set (l2_cpu2_rd_prfm_arb_set), + .l2_cpu2_rd_priv_arb_set (l2_cpu2_rd_priv_arb_set), + .l2_cpu2_rd_replayed_arb_set (l2_cpu2_rd_replayed_arb_set), + .l2_cpu2_rd_shared_arb_set (l2_cpu2_rd_shared_arb_set[1:0]), + .l2_cpu2_rd_type_arb_set (l2_cpu2_rd_type_arb_set[6:0]), + .l2_cpu2_rd_va48_arb_set (l2_cpu2_rd_va48_arb_set), + .l2_cpu2_rd_way_arb_set (l2_cpu2_rd_way_arb_set), + .l2_cpu2_tlb_sync_done_q (l2_cpu2_tlb_sync_done_q), + .l2_cpu2_tw_ccb_resp (l2_cpu2_tw_ccb_resp), + .l2_cpu2_tw_ccb_resp_id (l2_cpu2_tw_ccb_resp_id[4:0]), + .l2_cpu2_wr_1st_replayed_arb_set (l2_cpu2_wr_1st_replayed_arb_set), + .l2_cpu2_wr_addr_arb_set (l2_cpu2_wr_addr_arb_set[44:0]), + .l2_cpu2_wr_arb_fast (l2_cpu2_wr_arb_fast), + .l2_cpu2_wr_cache_attr_arb_set (l2_cpu2_wr_cache_attr_arb_set[2:0]), + .l2_cpu2_wr_cl_id_arb_set (l2_cpu2_wr_cl_id_arb_set[11:0]), + .l2_cpu2_wr_clean_evict_arb_set (l2_cpu2_wr_clean_evict_arb_set), + .l2_cpu2_wr_data (l2_cpu2_wr_data[143:0]), + .l2_cpu2_wr_data_vld_x1_q (l2_cpu2_wr_data_vld_x1_q), + .l2_cpu2_wr_dirty_arb_set (l2_cpu2_wr_dirty_arb_set), + .l2_cpu2_wr_elem_size_arb_set (l2_cpu2_wr_elem_size_arb_set[2:0]), + .l2_cpu2_wr_err_arb_set (l2_cpu2_wr_err_arb_set), + .l2_cpu2_wr_evict_x1_q (l2_cpu2_wr_evict_x1_q), + .l2_cpu2_wr_id_arb_set (l2_cpu2_wr_id_arb_set[3:0]), + .l2_cpu2_wr_last_arb_set (l2_cpu2_wr_last_arb_set), + .l2_cpu2_wr_page_attr_arb_set (l2_cpu2_wr_page_attr_arb_set[7:0]), + .l2_cpu2_wr_partial_dw_arb_set (l2_cpu2_wr_partial_dw_arb_set[3:0]), + .l2_cpu2_wr_priv_arb_set (l2_cpu2_wr_priv_arb_set), + .l2_cpu2_wr_shared_arb_set (l2_cpu2_wr_shared_arb_set[1:0]), + .l2_cpu2_wr_type_arb_set (l2_cpu2_wr_type_arb_set[2:0]), + .l2_cpu2_wr_way_arb_set (l2_cpu2_wr_way_arb_set), + .l2_cpu2_wrq_almost_full (l2_cpu2_wrq_almost_full), + .l2_cpu2_wrq_haz_clr_id_dcd_q (l2_cpu2_wrq_haz_clr_id_dcd_q[15:0]), + .l2_cpu3_dsq_rd_byte_strb_q (l2_cpu3_dsq_rd_byte_strb_q[15:0]), + .l2_cpu3_dsq_rd_data_q (l2_cpu3_dsq_rd_data_q[129:0]), + .l2_cpu3_dt_pmu_evt_en (l2_cpu3_dt_pmu_evt_en), + .l2_cpu3_early_rd_reqe4_e5_q (l2_cpu3_early_rd_reqe4_e5_q), + .l2_cpu3_ic_addr_arb_set (l2_cpu3_ic_addr_arb_set[15:0]), + .l2_cpu3_ic_arb_fast (l2_cpu3_ic_arb_fast), + .l2_cpu3_ic_data_arb_set (l2_cpu3_ic_data_arb_set[31:0]), + .l2_cpu3_ic_elem_size_arb_set (l2_cpu3_ic_elem_size_arb_set[2:0]), + .l2_cpu3_ic_excl_arb_set (l2_cpu3_ic_excl_arb_set), + .l2_cpu3_ic_id_arb_set (l2_cpu3_ic_id_arb_set[2:0]), + .l2_cpu3_ic_ns_arb_set (l2_cpu3_ic_ns_arb_set), + .l2_cpu3_ic_write_arb_set (l2_cpu3_ic_write_arb_set), + .l2_cpu3_idle_wakeup_q (l2_cpu3_idle_wakeup_q), + .l2_cpu3_if_ccb_resp (l2_cpu3_if_ccb_resp), + .l2_cpu3_if_ccb_resp_id (l2_cpu3_if_ccb_resp_id[4:0]), + .l2_cpu3_if_sync_done_q (l2_cpu3_if_sync_done_q), + .l2_cpu3_lrq_haz_clr_id_dcd_q (l2_cpu3_lrq_haz_clr_id_dcd_q[5:0]), + .l2_cpu3_ls_ccb_data_wr (l2_cpu3_ls_ccb_data_wr), + .l2_cpu3_ls_ccb_resp (l2_cpu3_ls_ccb_resp), + .l2_cpu3_ls_ccb_resp_id (l2_cpu3_ls_ccb_resp_id[4:0]), + .l2_cpu3_ls_rd_haz_id_arb_q (l2_cpu3_ls_rd_haz_id_arb_q[3:0]), + .l2_cpu3_ls_rd_haz_vld_arb_q (l2_cpu3_ls_rd_haz_vld_arb_q), + .l2_cpu3_ls_wr_ccb_id_w2a (l2_cpu3_ls_wr_ccb_id_w2a[4:0]), + .l2_cpu3_ls_wr_data_w2a (l2_cpu3_ls_wr_data_w2a[127:0]), + .l2_cpu3_ls_wr_dirty_w2a (l2_cpu3_ls_wr_dirty_w2a), + .l2_cpu3_ls_wr_err_w2a (l2_cpu3_ls_wr_err_w2a), + .l2_cpu3_ls_wr_haz_id_arb_q (l2_cpu3_ls_wr_haz_id_arb_q[2:0]), + .l2_cpu3_ls_wr_haz_vld_arb_q (l2_cpu3_ls_wr_haz_vld_arb_q), + .l2_cpu3_ls_wr_last_w2a (l2_cpu3_ls_wr_last_w2a), + .l2_cpu3_ls_wr_req_w2a (l2_cpu3_ls_wr_req_w2a), + .l2_cpu3_ls_wr_type_w2a (l2_cpu3_ls_wr_type_w2a[2:0]), + .l2_cpu3_rd_aarch64_arb_set (l2_cpu3_rd_aarch64_arb_set), + .l2_cpu3_rd_addr_arb_set (l2_cpu3_rd_addr_arb_set[44:0]), + .l2_cpu3_rd_arb_fast (l2_cpu3_rd_arb_fast), + .l2_cpu3_rd_asid_arb_set (l2_cpu3_rd_asid_arb_set[15:8]), + .l2_cpu3_rd_bypass_arb_set (l2_cpu3_rd_bypass_arb_set), + .l2_cpu3_rd_bypass_bufid_e5 (l2_cpu3_rd_bypass_bufid_e5[2:0]), + .l2_cpu3_rd_bypass_lrq_id_e5 (l2_cpu3_rd_bypass_lrq_id_e5[2:0]), + .l2_cpu3_rd_bypass_req_can_e5 (l2_cpu3_rd_bypass_req_can_e5), + .l2_cpu3_rd_bypass_way_e5 (l2_cpu3_rd_bypass_way_e5), + .l2_cpu3_rd_cache_attr_arb_set (l2_cpu3_rd_cache_attr_arb_set[2:0]), + .l2_cpu3_rd_elem_size_arb_set (l2_cpu3_rd_elem_size_arb_set[2:0]), + .l2_cpu3_rd_excl_arb_set (l2_cpu3_rd_excl_arb_set), + .l2_cpu3_rd_id_arb_set (l2_cpu3_rd_id_arb_set[4:0]), + .l2_cpu3_rd_lrq_id_arb_set (l2_cpu3_rd_lrq_id_arb_set[2:0]), + .l2_cpu3_rd_page_attr_arb_set (l2_cpu3_rd_page_attr_arb_set[7:0]), + .l2_cpu3_rd_prfm_arb_set (l2_cpu3_rd_prfm_arb_set), + .l2_cpu3_rd_priv_arb_set (l2_cpu3_rd_priv_arb_set), + .l2_cpu3_rd_replayed_arb_set (l2_cpu3_rd_replayed_arb_set), + .l2_cpu3_rd_shared_arb_set (l2_cpu3_rd_shared_arb_set[1:0]), + .l2_cpu3_rd_type_arb_set (l2_cpu3_rd_type_arb_set[6:0]), + .l2_cpu3_rd_va48_arb_set (l2_cpu3_rd_va48_arb_set), + .l2_cpu3_rd_way_arb_set (l2_cpu3_rd_way_arb_set), + .l2_cpu3_tlb_sync_done_q (l2_cpu3_tlb_sync_done_q), + .l2_cpu3_tw_ccb_resp (l2_cpu3_tw_ccb_resp), + .l2_cpu3_tw_ccb_resp_id (l2_cpu3_tw_ccb_resp_id[4:0]), + .l2_cpu3_wr_1st_replayed_arb_set (l2_cpu3_wr_1st_replayed_arb_set), + .l2_cpu3_wr_addr_arb_set (l2_cpu3_wr_addr_arb_set[44:0]), + .l2_cpu3_wr_arb_fast (l2_cpu3_wr_arb_fast), + .l2_cpu3_wr_cache_attr_arb_set (l2_cpu3_wr_cache_attr_arb_set[2:0]), + .l2_cpu3_wr_cl_id_arb_set (l2_cpu3_wr_cl_id_arb_set[11:0]), + .l2_cpu3_wr_clean_evict_arb_set (l2_cpu3_wr_clean_evict_arb_set), + .l2_cpu3_wr_data (l2_cpu3_wr_data[143:0]), + .l2_cpu3_wr_data_vld_x1_q (l2_cpu3_wr_data_vld_x1_q), + .l2_cpu3_wr_dirty_arb_set (l2_cpu3_wr_dirty_arb_set), + .l2_cpu3_wr_elem_size_arb_set (l2_cpu3_wr_elem_size_arb_set[2:0]), + .l2_cpu3_wr_err_arb_set (l2_cpu3_wr_err_arb_set), + .l2_cpu3_wr_evict_x1_q (l2_cpu3_wr_evict_x1_q), + .l2_cpu3_wr_id_arb_set (l2_cpu3_wr_id_arb_set[3:0]), + .l2_cpu3_wr_last_arb_set (l2_cpu3_wr_last_arb_set), + .l2_cpu3_wr_page_attr_arb_set (l2_cpu3_wr_page_attr_arb_set[7:0]), + .l2_cpu3_wr_partial_dw_arb_set (l2_cpu3_wr_partial_dw_arb_set[3:0]), + .l2_cpu3_wr_priv_arb_set (l2_cpu3_wr_priv_arb_set), + .l2_cpu3_wr_shared_arb_set (l2_cpu3_wr_shared_arb_set[1:0]), + .l2_cpu3_wr_type_arb_set (l2_cpu3_wr_type_arb_set[2:0]), + .l2_cpu3_wr_way_arb_set (l2_cpu3_wr_way_arb_set), + .l2_cpu3_wrq_almost_full (l2_cpu3_wrq_almost_full), + .l2_cpu3_wrq_haz_clr_id_dcd_q (l2_cpu3_wrq_haz_clr_id_dcd_q[15:0]), + .l2_mbist2_tbnk0_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), + .l2_mbist2_tbnk0_all_b1 (l2_mbist2_tbnk0_all_b1), + .l2_mbist2_tbnk0_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), + .l2_mbist2_tbnk0_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), + .l2_mbist2_tbnk0_en_b1 (l2_mbist2_tbnk0_en_b1), + .l2_mbist2_tbnk0_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), + .l2_mbist2_tbnk0_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), + .l2_mbist2_tbnk0_sel_b1 (l2_mbist2_tbnk0_sel_b1), + .l2_mbist2_tbnk0_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), + .l2_mbist2_tbnk0_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), + .l2_mbist2_tbnk0_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), + .l2_mbist2_tbnk0_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), + .l2_mbist2_tbnk0_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), + .l2_mbist2_tbnk1_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), + .l2_mbist2_tbnk1_all_b1 (l2_mbist2_tbnk1_all_b1), + .l2_mbist2_tbnk1_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), + .l2_mbist2_tbnk1_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), + .l2_mbist2_tbnk1_en_b1 (l2_mbist2_tbnk1_en_b1), + .l2_mbist2_tbnk1_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), + .l2_mbist2_tbnk1_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), + .l2_mbist2_tbnk1_sel_b1 (l2_mbist2_tbnk1_sel_b1), + .l2_mbist2_tbnk1_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), + .l2_mbist2_tbnk1_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), + .l2_mbist2_tbnk1_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), + .l2_mbist2_tbnk1_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), + .l2_mbist2_tbnk1_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), + .l2_tbnk0_addr44_l3_q (l2_tbnk0_addr44_l3_q), + .l2_tbnk0_addr_l6 (l2_tbnk0_addr_l6[5:2]), + .l2_tbnk0_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), + .l2_tbnk0_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), + .l2_tbnk0_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), + .l2_tbnk0_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), + .l2_tbnk0_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), + .l2_tbnk0_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), + .l2_tbnk0_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), + .l2_tbnk0_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), + .l2_tbnk0_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), + .l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), + .l2_tbnk0_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), + .l2_tbnk0_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), + .l2_tbnk0_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), + .l2_tbnk0_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), + .l2_tbnk0_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), + .l2_tbnk0_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), + .l2_tbnk0_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), + .l2_tbnk0_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), + .l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), + .l2_tbnk0_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), + .l2_tbnk0_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), + .l2_tbnk0_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), + .l2_tbnk0_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), + .l2_tbnk0_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), + .l2_tbnk0_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), + .l2_tbnk0_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), + .l2_tbnk0_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), + .l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), + .l2_tbnk0_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), + .l2_tbnk0_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk0_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), + .l2_tbnk0_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), + .l2_tbnk0_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), + .l2_tbnk0_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), + .l2_tbnk0_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), + .l2_tbnk0_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), + .l2_tbnk0_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), + .l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk0_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), + .l2_tbnk0_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), + .l2_tbnk0_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk0_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk0_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk0_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), + .l2_tbnk0_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), + .l2_tbnk0_data_l6 (l2_tbnk0_data_l6[127:0]), + .l2_tbnk0_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), + .l2_tbnk0_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk0_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk0_dirty_l3_q (l2_tbnk0_dirty_l3_q), + .l2_tbnk0_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), + .l2_tbnk0_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), + .l2_tbnk0_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), + .l2_tbnk0_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), + .l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk0_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), + .l2_tbnk0_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), + .l2_tbnk0_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), + .l2_tbnk0_excl_l4_q (l2_tbnk0_excl_l4_q), + .l2_tbnk0_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), + .l2_tbnk0_feq_clr_l4 (l2_tbnk0_feq_clr_l4), + .l2_tbnk0_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), + .l2_tbnk0_hit_l4 (l2_tbnk0_hit_l4), + .l2_tbnk0_hit_l7_q (l2_tbnk0_hit_l7_q), + .l2_tbnk0_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), + .l2_tbnk0_id_l6_q (l2_tbnk0_id_l6_q[9:0]), + .l2_tbnk0_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), + .l2_tbnk0_idle (l2_tbnk0_idle), + .l2_tbnk0_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), + .l2_tbnk0_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), + .l2_tbnk0_l2v_s_q (l2_tbnk0_l2v_s_q), + .l2_tbnk0_l2v_vld_q (l2_tbnk0_l2v_vld_q), + .l2_tbnk0_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), + .l2_tbnk0_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), + .l2_tbnk0_lock_l4 (l2_tbnk0_lock_l4[2:0]), + .l2_tbnk0_merrsr_data (l2_tbnk0_merrsr_data[32:0]), + .l2_tbnk0_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), + .l2_tbnk0_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), + .l2_tbnk0_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), + .l2_tbnk0_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), + .l2_tbnk0_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), + .l2_tbnk0_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), + .l2_tbnk0_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), + .l2_tbnk0_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), + .l2_tbnk0_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), + .l2_tbnk0_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), + .l2_tbnk0_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk0_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk0_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), + .l2_tbnk0_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), + .l2_tbnk0_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), + .l2_tbnk0_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk0_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), + .l2_tbnk0_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), + .l2_tbnk0_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), + .l2_tbnk0_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), + .l2_tbnk0_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk0_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), + .l2_tbnk0_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk0_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), + .l2_tbnk0_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), + .l2_tbnk0_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), + .l2_tbnk0_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), + .l2_tbnk0_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), + .l2_tbnk0_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), + .l2_tbnk0_size_l4_q (l2_tbnk0_size_l4_q[2:0]), + .l2_tbnk0_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), + .l2_tbnk0_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), + .l2_tbnk0_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk0_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk0_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk0_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), + .l2_tbnk0_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), + .l2_tbnk0_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk0_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), + .l2_tbnk0_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), + .l2_tbnk0_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), + .l2_tbnk0_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), + .l2_tbnk0_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), + .l2_tbnk0_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), + .l2_tbnk0_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), + .l2_tbnk0_vld_l6_q (l2_tbnk0_vld_l6_q), + .l2_tbnk0_way_l4_q (l2_tbnk0_way_l4_q), + .l2_tbnk0_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), + .l2_tbnk0_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), + .l2_tbnk0_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), + .l2_tbnk0_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), + .l2_tbnk1_addr44_l3_q (l2_tbnk1_addr44_l3_q), + .l2_tbnk1_addr_l6 (l2_tbnk1_addr_l6[5:2]), + .l2_tbnk1_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), + .l2_tbnk1_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), + .l2_tbnk1_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), + .l2_tbnk1_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), + .l2_tbnk1_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), + .l2_tbnk1_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), + .l2_tbnk1_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), + .l2_tbnk1_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), + .l2_tbnk1_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), + .l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), + .l2_tbnk1_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), + .l2_tbnk1_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), + .l2_tbnk1_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), + .l2_tbnk1_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), + .l2_tbnk1_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), + .l2_tbnk1_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), + .l2_tbnk1_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), + .l2_tbnk1_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), + .l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), + .l2_tbnk1_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), + .l2_tbnk1_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), + .l2_tbnk1_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), + .l2_tbnk1_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), + .l2_tbnk1_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), + .l2_tbnk1_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), + .l2_tbnk1_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), + .l2_tbnk1_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), + .l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), + .l2_tbnk1_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), + .l2_tbnk1_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk1_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), + .l2_tbnk1_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), + .l2_tbnk1_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), + .l2_tbnk1_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), + .l2_tbnk1_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), + .l2_tbnk1_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), + .l2_tbnk1_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), + .l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk1_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), + .l2_tbnk1_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), + .l2_tbnk1_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk1_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk1_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk1_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), + .l2_tbnk1_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), + .l2_tbnk1_data_l6 (l2_tbnk1_data_l6[127:0]), + .l2_tbnk1_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), + .l2_tbnk1_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk1_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk1_dirty_l3_q (l2_tbnk1_dirty_l3_q), + .l2_tbnk1_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), + .l2_tbnk1_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), + .l2_tbnk1_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), + .l2_tbnk1_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), + .l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk1_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), + .l2_tbnk1_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), + .l2_tbnk1_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), + .l2_tbnk1_excl_l4_q (l2_tbnk1_excl_l4_q), + .l2_tbnk1_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), + .l2_tbnk1_feq_clr_l4 (l2_tbnk1_feq_clr_l4), + .l2_tbnk1_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), + .l2_tbnk1_hit_l4 (l2_tbnk1_hit_l4), + .l2_tbnk1_hit_l7_q (l2_tbnk1_hit_l7_q), + .l2_tbnk1_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), + .l2_tbnk1_id_l6_q (l2_tbnk1_id_l6_q[9:0]), + .l2_tbnk1_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), + .l2_tbnk1_idle (l2_tbnk1_idle), + .l2_tbnk1_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), + .l2_tbnk1_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), + .l2_tbnk1_l2v_s_q (l2_tbnk1_l2v_s_q), + .l2_tbnk1_l2v_vld_q (l2_tbnk1_l2v_vld_q), + .l2_tbnk1_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), + .l2_tbnk1_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), + .l2_tbnk1_lock_l4 (l2_tbnk1_lock_l4[2:0]), + .l2_tbnk1_merrsr_data (l2_tbnk1_merrsr_data[32:0]), + .l2_tbnk1_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), + .l2_tbnk1_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), + .l2_tbnk1_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), + .l2_tbnk1_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), + .l2_tbnk1_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), + .l2_tbnk1_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), + .l2_tbnk1_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), + .l2_tbnk1_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), + .l2_tbnk1_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), + .l2_tbnk1_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), + .l2_tbnk1_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk1_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk1_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), + .l2_tbnk1_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), + .l2_tbnk1_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), + .l2_tbnk1_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk1_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), + .l2_tbnk1_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), + .l2_tbnk1_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), + .l2_tbnk1_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), + .l2_tbnk1_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk1_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), + .l2_tbnk1_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk1_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), + .l2_tbnk1_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), + .l2_tbnk1_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), + .l2_tbnk1_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), + .l2_tbnk1_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), + .l2_tbnk1_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), + .l2_tbnk1_size_l4_q (l2_tbnk1_size_l4_q[2:0]), + .l2_tbnk1_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), + .l2_tbnk1_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), + .l2_tbnk1_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk1_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk1_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk1_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), + .l2_tbnk1_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), + .l2_tbnk1_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk1_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), + .l2_tbnk1_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), + .l2_tbnk1_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), + .l2_tbnk1_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), + .l2_tbnk1_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), + .l2_tbnk1_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), + .l2_tbnk1_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), + .l2_tbnk1_vld_l6_q (l2_tbnk1_vld_l6_q), + .l2_tbnk1_way_l4_q (l2_tbnk1_way_l4_q), + .l2_tbnk1_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), + .l2_tbnk1_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), + .l2_tbnk1_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), + .l2_tbnk1_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_spr_rd_data (tm_cpu0_spr_rd_data[63:0]), + .tm_cpu1_spr_rd_data (tm_cpu1_spr_rd_data[63:0]), + .tm_cpu2_spr_rd_data (tm_cpu2_spr_rd_data[63:0]), + .tm_cpu3_spr_rd_data (tm_cpu3_spr_rd_data[63:0]), + .tm_tval_cpu0_spr_rd_data (tm_tval_cpu0_spr_rd_data[63:0]), + .tm_tval_cpu1_spr_rd_data (tm_tval_cpu1_spr_rd_data[63:0]), + .tm_tval_cpu2_spr_rd_data (tm_tval_cpu2_spr_rd_data[63:0]), + .tm_tval_cpu3_spr_rd_data (tm_tval_cpu3_spr_rd_data[63:0]) + ); // ul2_logic + + maia_l2_tbnk ul2_tbnk0( // outputs + .l2_mbist2_addr_b1 (l2_mbist2_tbnk0_addr_b1[16:0]), + .l2_mbist2_array_b1 (l2_mbist2_tbnk0_array_b1[2:0]), + .l2_mbist2_be_b1 (l2_mbist2_tbnk0_be_b1[17:0]), + .l2_mbist2_en_b1 (l2_mbist2_tbnk0_en_b1), + .l2_mbist2_indata_b1 (l2_mbist2_tbnk0_indata_b1[143:0]), + .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk0_all_b1), + .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk0_outdata_b3[143:0]), + .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk0_sel_b1), + .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk0_snp0_sel_b1), + .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk0_snp1_sel_b1), + .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk0_snp2_sel_b1), + .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk0_snp3_sel_b1), + .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk0_wr_en_b1), + .l2_tbnk_addr44_l3_q (l2_tbnk0_addr44_l3_q), + .l2_tbnk_addr_l6 (l2_tbnk0_addr_l6[5:2]), + .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk0_all_tag_incl_active_l3), + .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk0_cmo_setway_l2_inv_incl_l4), + .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk0_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk_cpu0_hit_l4 (l2_tbnk0_cpu0_hit_l4), + .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk0_cpu0_l2_inv_l4_dly2), + .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk0_cpu0_l2hit_e_l4), + .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk0_cpu0_l2hit_s_l4), + .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk0_cpu0_rd_access_l4_dly), + .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk0_cpu0_self_evict_l4_dly_q), + .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk0_cpu0_single_ecc_err_l7_q), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk0_cpu0_vld_nxt_l5), + .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk0_cpu0_wr_access_l4_dly), + .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk0_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk_cpu1_hit_l4 (l2_tbnk0_cpu1_hit_l4), + .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk0_cpu1_l2_inv_l4_dly2), + .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk0_cpu1_l2hit_e_l4), + .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk0_cpu1_l2hit_s_l4), + .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk0_cpu1_rd_access_l4_dly), + .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk0_cpu1_self_evict_l4_dly_q), + .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk0_cpu1_single_ecc_err_l7_q), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk0_cpu1_vld_nxt_l5), + .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk0_cpu1_wr_access_l4_dly), + .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk0_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk_cpu2_hit_l4 (l2_tbnk0_cpu2_hit_l4), + .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk0_cpu2_l2_inv_l4_dly2), + .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk0_cpu2_l2hit_e_l4), + .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk0_cpu2_l2hit_s_l4), + .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk0_cpu2_rd_access_l4_dly), + .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk0_cpu2_self_evict_l4_dly_q), + .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk0_cpu2_single_ecc_err_l7_q), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk0_cpu2_vld_nxt_l5), + .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk0_cpu2_wr_access_l4_dly), + .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk0_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk_cpu3_hit_l4 (l2_tbnk0_cpu3_hit_l4), + .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk0_cpu3_l2_inv_l4_dly2), + .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk0_cpu3_l2hit_e_l4), + .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk0_cpu3_l2hit_s_l4), + .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk0_cpu3_rd_access_l4_dly), + .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk0_cpu3_self_evict_l4_dly_q), + .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk0_cpu3_single_ecc_err_l7_q), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk0_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk0_cpu3_vld_nxt_l5), + .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk0_cpu3_wr_access_l4_dly), + .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk0_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk0_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk0_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk0_crit_qw_nxt_l5), + .l2_tbnk_data_corrected_l7_q (l2_tbnk0_data_corrected_l7_q[143:0]), + .l2_tbnk_data_l6 (l2_tbnk0_data_l6[127:0]), + .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk0_dbg_ram_acc_l5a), + .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk0_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk0_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk_dirty_l3_q (l2_tbnk0_dirty_l3_q), + .l2_tbnk_double_ecc_err_l7_q (l2_tbnk0_double_ecc_err_l7_q), + .l2_tbnk_early_rvalid_l4_q (l2_tbnk0_early_rvalid_l4_q), + .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk0_ecc_fixup_blk_arb), + .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk0_ecc_fixup_inprog_dly_q), + .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk0_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk0_ecc_syndrome_reg_q[31:0]), + .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk0_evict_special_hazard_l3_q), + .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk0_evict_special_hazard_rwvic_l3_q), + .l2_tbnk_excl_l4_q (l2_tbnk0_excl_l4_q), + .l2_tbnk_feq_addr_upd (l2_tbnk0_feq_addr_upd[44:6]), + .l2_tbnk_feq_clr_l4 (l2_tbnk0_feq_clr_l4), + .l2_tbnk_full_miss_l4_q (l2_tbnk0_full_miss_l4_q), + .l2_tbnk_hit_l4 (l2_tbnk0_hit_l4), + .l2_tbnk_hit_l7_q (l2_tbnk0_hit_l7_q), + .l2_tbnk_hit_way_l4_q (l2_tbnk0_hit_way_l4_q[3:0]), + .l2_tbnk_id_l6_q (l2_tbnk0_id_l6_q[9:0]), + .l2_tbnk_id_nxt_l5 (l2_tbnk0_id_nxt_l5[9:0]), + .l2_tbnk_idle (l2_tbnk0_idle), + .l2_tbnk_l2hit_e_l4 (l2_tbnk0_l2hit_e_l4), + .l2_tbnk_l2hit_s_l4 (l2_tbnk0_l2hit_s_l4), + .l2_tbnk_l2v_s_q (l2_tbnk0_l2v_s_q), + .l2_tbnk_l2v_vld_q (l2_tbnk0_l2v_vld_q), + .l2_tbnk_last_qw_l6_q (l2_tbnk0_last_qw_l6_q), + .l2_tbnk_last_qw_nxt_l5 (l2_tbnk0_last_qw_nxt_l5), + .l2_tbnk_lock_l4 (l2_tbnk0_lock_l4[2:0]), + .l2_tbnk_merrsr_data (l2_tbnk0_merrsr_data[32:0]), + .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk0_pf_cnt_dec_l4_dly), + .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk0_pf_req_sel_for_fwd_l4), + .l2_tbnk_prfm_nxt_l5 (l2_tbnk0_prfm_nxt_l5), + .l2_tbnk_prot_l4_q (l2_tbnk0_prot_l4_q[3:0]), + .l2_tbnk_qw_cnt_l3_q (l2_tbnk0_qw_cnt_l3_q[1:0]), + .l2_tbnk_raw_hit_l4_q (l2_tbnk0_raw_hit_l4_q), + .l2_tbnk_rbufid_nxt_l5 (l2_tbnk0_rbufid_nxt_l5[2:0]), + .l2_tbnk_rd_en_nxt_l5 (l2_tbnk0_rd_en_nxt_l5), + .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk0_rwvic_axi_read_err_l3_q), + .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk0_rwvic_ccb_dirty_l6_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk0_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk0_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk0_rwvic_cmo_inv_l7_q), + .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk0_rwvic_cmo_l7_q), + .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk0_rwvic_cmo_pou_l6_q), + .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk0_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk0_rwvic_ddi_l6_q), + .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk0_rwvic_l2hit_e_l3_q), + .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk0_rwvic_l2hit_e_l7_q), + .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk0_rwvic_l2v_dirty_l7_q), + .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk0_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk0_rwvic_l2v_vld_l6_q), + .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk0_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk_rwvic_owner_l7_q (l2_tbnk0_rwvic_owner_l7_q[2:0]), + .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk0_rwvic_rd_type_l6_q), + .l2_tbnk_rwvic_snp_l3_q (l2_tbnk0_rwvic_snp_l3_q), + .l2_tbnk_rwvic_snp_l6_q (l2_tbnk0_rwvic_snp_l6_q), + .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk0_rwvic_tag_wr_l0), + .l2_tbnk_rwvic_wa_l6_q (l2_tbnk0_rwvic_wa_l6_q), + .l2_tbnk_size_l4_q (l2_tbnk0_size_l4_q[2:0]), + .l2_tbnk_snp_hit_e_l4_q (l2_tbnk0_snp_hit_e_l4_q), + .l2_tbnk_snp_hit_s_l4_q (l2_tbnk0_snp_hit_s_l4_q), + .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk0_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk0_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk0_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk_special_evict_hazard_l3 (l2_tbnk0_special_evict_hazard_l3), + .l2_tbnk_special_hazard_l3_q (l2_tbnk0_special_hazard_l3_q), + .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk0_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk0_tag_ecc_err_cpu0_l4), + .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk0_tag_ecc_err_cpu1_l4), + .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk0_tag_ecc_err_cpu2_l4), + .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk0_tag_ecc_err_cpu3_l4), + .l2_tbnk_tag_ecc_err_l4 (l2_tbnk0_tag_ecc_err_l4), + .l2_tbnk_ulen_l4_q (l2_tbnk0_ulen_l4_q[1:0]), + .l2_tbnk_vld_init_l6_q (l2_tbnk0_vld_init_l6_q), + .l2_tbnk_vld_l6_q (l2_tbnk0_vld_l6_q), + .l2_tbnk_way_l4_q (l2_tbnk0_way_l4_q), + .l2_tbnk_way_nxt_l3a (l2_tbnk0_way_nxt_l3a), + .l2_tbnk_wr_data_l3 (l2_tbnk0_wr_data_l3[143:0]), + .l2_tbnk_wr_data_l4_en (l2_tbnk0_wr_data_l4_en), + .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk0_wr_non_crit_id_l4_q[11:0]), + + // inputs + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ), + .ck_areset_l2 (ck_areset_l2), + .ck_gclkl2 (ck_gclkb0), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk0_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk0_snp0_outdata_b2[79:0]), + .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk0_snp0_outdata_vld_b2), + .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk0_snp1_outdata_b2[79:0]), + .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk0_snp1_outdata_vld_b2), + .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk0_snp2_outdata_b2[79:0]), + .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk0_snp2_outdata_vld_b2), + .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk0_snp3_outdata_b2[79:0]), + .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk0_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_skyros_intf (1'b1), + .l2_tbnk_addr_l1 (l2_tbnk0_addr_l1[44:0]), + .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk0_asq_cmp_evict_l3_q), + .l2_tbnk_asq_full_flsh (l2_tbnk0_asq_full_flsh), + .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk0_asq_nc_so_dev_limit), + .l2_tbnk_cache_attr_l1 (l2_tbnk0_cache_attr_l1[2:0]), + .l2_tbnk_cfg_ecc_en (l2_tbnk0_cfg_ecc_en), + .l2_tbnk_cpu0_peq_full_q (l2_tbnk0_cpu0_peq_full_q), + .l2_tbnk_cpu0_peq_hit_q (l2_tbnk0_cpu0_peq_hit_q), + .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk0_cpu0_peq_self_evict_l3_q), + .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk0_cpu0_snp_hit_e_l3), + .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk0_cpu0_snp_hit_s_l3), + .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk0_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu1_peq_full_q (l2_tbnk0_cpu1_peq_full_q), + .l2_tbnk_cpu1_peq_hit_q (l2_tbnk0_cpu1_peq_hit_q), + .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk0_cpu1_peq_self_evict_l3_q), + .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk0_cpu1_snp_hit_e_l3), + .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk0_cpu1_snp_hit_s_l3), + .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk0_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu2_peq_full_q (l2_tbnk0_cpu2_peq_full_q), + .l2_tbnk_cpu2_peq_hit_q (l2_tbnk0_cpu2_peq_hit_q), + .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk0_cpu2_peq_self_evict_l3_q), + .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk0_cpu2_snp_hit_e_l3), + .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk0_cpu2_snp_hit_s_l3), + .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk0_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu3_peq_full_q (l2_tbnk0_cpu3_peq_full_q), + .l2_tbnk_cpu3_peq_hit_q (l2_tbnk0_cpu3_peq_hit_q), + .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk0_cpu3_peq_self_evict_l3_q), + .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk0_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk0_cpu3_snp_hit_e_l3), + .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk0_cpu3_snp_hit_s_l3), + .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk0_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk0_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk0_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_dirty_l1 (l2_tbnk0_dirty_l1), + .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk0_dis_ns_dbg_arr_acc_x2), + .l2_tbnk_excl_l1 (l2_tbnk0_excl_l1), + .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk0_feq_alloc_failed_l4), + .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk0_feq_axi_wr_vld_not_popped), + .l2_tbnk_feq_frc_incl_l3a (l2_tbnk0_feq_frc_incl_l3a[15:0]), + .l2_tbnk_feq_kill_l3 (l2_tbnk0_feq_kill_l3), + .l2_tbnk_feq_last_id_q (l2_tbnk0_feq_last_id_q[4:0]), + .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk0_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk0_feq_tbnk_id_update_or_l3), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .l2_tbnk_id_l1 (l2_tbnk0_id_l1[9:0]), + .l2_tbnk_init_req_l1 (l2_tbnk0_init_req_l1), + .l2_tbnk_kill_l2 (l2_tbnk0_kill_l2), + .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk0_l2bb_fake_wr_l1), + .l2_tbnk_l2bb_wr_l1 (l2_tbnk0_l2bb_wr_l1), + .l2_tbnk_last_qw_l1 (l2_tbnk0_last_qw_l1), + .l2_tbnk_lock_l1 (l2_tbnk0_lock_l1[2:0]), + .l2_tbnk_page_attr_l1 (l2_tbnk0_page_attr_l1[9:0]), + .l2_tbnk_partial_dw_wr_l1 (l2_tbnk0_partial_dw_wr_l1), + .l2_tbnk_pf_hazard_l3 (l2_tbnk0_pf_hazard_l3), + .l2_tbnk_prfm_l1 (l2_tbnk0_prfm_l1), + .l2_tbnk_prot_l1 (l2_tbnk0_prot_l1[3:0]), + .l2_tbnk_qw_cnt_l1 (l2_tbnk0_qw_cnt_l1[1:0]), + .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk0_rd_fail_hazchk_feq_l3), + .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk0_rwvic_axi_read_err_l1), + .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk0_rwvic_ccb_ls_xfer_l1), + .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk0_rwvic_ccb_way_l1[3:0]), + .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk0_rwvic_cmo_clean_l1), + .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk0_rwvic_cmo_inv_l1), + .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk0_rwvic_cmo_pou_l1), + .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk0_rwvic_cmo_setway_l1), + .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk0_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk0_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk0_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk0_rwvic_feq_cmp_l3_q), + .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk0_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk0_rwvic_l2hit_e_l1), + .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk0_rwvic_mesi_sh_l1), + .l2_tbnk_rwvic_owner_l1 (l2_tbnk0_rwvic_owner_l1[2:0]), + .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk0_rwvic_snp_clr_dirty_l1), + .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk0_rwvic_snp_inv_l1), + .l2_tbnk_rwvic_snp_l1 (l2_tbnk0_rwvic_snp_l1), + .l2_tbnk_rwvic_type_l1 (l2_tbnk0_rwvic_type_l1[3:0]), + .l2_tbnk_rwvic_wa_l1 (l2_tbnk0_rwvic_wa_l1), + .l2_tbnk_sel_l1 (l2_tbnk0_sel_l1[13:0]), + .l2_tbnk_size_l1 (l2_tbnk0_size_l1[2:0]), + .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk0_snp_byp_peq_haz_pending_q), + .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk0_snp_dvm_cmpl_l1), + .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk0_snp_hit_feq_evict_l4_dly), + .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk0_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk0_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_sync_l1 (l2_tbnk0_sync_l1), + .l2_tbnk_type_l1 (l2_tbnk0_type_l1[6:0]), + .l2_tbnk_ulen_l1 (l2_tbnk0_ulen_l1[1:0]), + .l2_tbnk_way_l1 (l2_tbnk0_way_l1), + .l2_tbnk_wr_data_l3a_q (l2_tbnk0_wr_data_l3a_q[127:0]), + .l2_tbnk_wr_err_l1 (l2_tbnk0_wr_err_l1), + .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk0_wr_fail_feq_full_l3), + .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk0_wr_fail_hazchk_feq_l3), + .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk0_wr_non_crit_id_l1[11:0]), + .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk0_wr_strb_mask_l3a_q[15:0]) + ); // ul2_tbnk0 + + maia_l2_tbnk ul2_tbnk1( // outputs + .l2_mbist2_addr_b1 (l2_mbist2_tbnk1_addr_b1[16:0]), + .l2_mbist2_array_b1 (l2_mbist2_tbnk1_array_b1[2:0]), + .l2_mbist2_be_b1 (l2_mbist2_tbnk1_be_b1[17:0]), + .l2_mbist2_en_b1 (l2_mbist2_tbnk1_en_b1), + .l2_mbist2_indata_b1 (l2_mbist2_tbnk1_indata_b1[143:0]), + .l2_mbist2_tbnk_all_b1 (l2_mbist2_tbnk1_all_b1), + .l2_mbist2_tbnk_outdata_b3 (l2_mbist2_tbnk1_outdata_b3[143:0]), + .l2_mbist2_tbnk_sel_b1 (l2_mbist2_tbnk1_sel_b1), + .l2_mbist2_tbnk_snp0_sel_b1 (l2_mbist2_tbnk1_snp0_sel_b1), + .l2_mbist2_tbnk_snp1_sel_b1 (l2_mbist2_tbnk1_snp1_sel_b1), + .l2_mbist2_tbnk_snp2_sel_b1 (l2_mbist2_tbnk1_snp2_sel_b1), + .l2_mbist2_tbnk_snp3_sel_b1 (l2_mbist2_tbnk1_snp3_sel_b1), + .l2_mbist2_wr_en_b1 (l2_mbist2_tbnk1_wr_en_b1), + .l2_tbnk_addr44_l3_q (l2_tbnk1_addr44_l3_q), + .l2_tbnk_addr_l6 (l2_tbnk1_addr_l6[5:2]), + .l2_tbnk_all_tag_incl_active_l3 (l2_tbnk1_all_tag_incl_active_l3), + .l2_tbnk_cmo_setway_l2_inv_incl_l4 (l2_tbnk1_cmo_setway_l2_inv_incl_l4), + .l2_tbnk_cpu0_ccb_xfer_l4_dly2 (l2_tbnk1_cpu0_ccb_xfer_l4_dly2), + .l2_tbnk_cpu0_hit_l4 (l2_tbnk1_cpu0_hit_l4), + .l2_tbnk_cpu0_l2_inv_l4_dly2 (l2_tbnk1_cpu0_l2_inv_l4_dly2), + .l2_tbnk_cpu0_l2hit_e_l4 (l2_tbnk1_cpu0_l2hit_e_l4), + .l2_tbnk_cpu0_l2hit_s_l4 (l2_tbnk1_cpu0_l2hit_s_l4), + .l2_tbnk_cpu0_rd_access_l4_dly (l2_tbnk1_cpu0_rd_access_l4_dly), + .l2_tbnk_cpu0_self_evict_l4_dly_q (l2_tbnk1_cpu0_self_evict_l4_dly_q), + .l2_tbnk_cpu0_single_ecc_err_l7_q (l2_tbnk1_cpu0_single_ecc_err_l7_q), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu0_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu0_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu0_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu0_vld_nxt_l5 (l2_tbnk1_cpu0_vld_nxt_l5), + .l2_tbnk_cpu0_wr_access_l4_dly (l2_tbnk1_cpu0_wr_access_l4_dly), + .l2_tbnk_cpu1_ccb_xfer_l4_dly2 (l2_tbnk1_cpu1_ccb_xfer_l4_dly2), + .l2_tbnk_cpu1_hit_l4 (l2_tbnk1_cpu1_hit_l4), + .l2_tbnk_cpu1_l2_inv_l4_dly2 (l2_tbnk1_cpu1_l2_inv_l4_dly2), + .l2_tbnk_cpu1_l2hit_e_l4 (l2_tbnk1_cpu1_l2hit_e_l4), + .l2_tbnk_cpu1_l2hit_s_l4 (l2_tbnk1_cpu1_l2hit_s_l4), + .l2_tbnk_cpu1_rd_access_l4_dly (l2_tbnk1_cpu1_rd_access_l4_dly), + .l2_tbnk_cpu1_self_evict_l4_dly_q (l2_tbnk1_cpu1_self_evict_l4_dly_q), + .l2_tbnk_cpu1_single_ecc_err_l7_q (l2_tbnk1_cpu1_single_ecc_err_l7_q), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu1_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu1_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu1_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu1_vld_nxt_l5 (l2_tbnk1_cpu1_vld_nxt_l5), + .l2_tbnk_cpu1_wr_access_l4_dly (l2_tbnk1_cpu1_wr_access_l4_dly), + .l2_tbnk_cpu2_ccb_xfer_l4_dly2 (l2_tbnk1_cpu2_ccb_xfer_l4_dly2), + .l2_tbnk_cpu2_hit_l4 (l2_tbnk1_cpu2_hit_l4), + .l2_tbnk_cpu2_l2_inv_l4_dly2 (l2_tbnk1_cpu2_l2_inv_l4_dly2), + .l2_tbnk_cpu2_l2hit_e_l4 (l2_tbnk1_cpu2_l2hit_e_l4), + .l2_tbnk_cpu2_l2hit_s_l4 (l2_tbnk1_cpu2_l2hit_s_l4), + .l2_tbnk_cpu2_rd_access_l4_dly (l2_tbnk1_cpu2_rd_access_l4_dly), + .l2_tbnk_cpu2_self_evict_l4_dly_q (l2_tbnk1_cpu2_self_evict_l4_dly_q), + .l2_tbnk_cpu2_single_ecc_err_l7_q (l2_tbnk1_cpu2_single_ecc_err_l7_q), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu2_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu2_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu2_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu2_vld_nxt_l5 (l2_tbnk1_cpu2_vld_nxt_l5), + .l2_tbnk_cpu2_wr_access_l4_dly (l2_tbnk1_cpu2_wr_access_l4_dly), + .l2_tbnk_cpu3_ccb_xfer_l4_dly2 (l2_tbnk1_cpu3_ccb_xfer_l4_dly2), + .l2_tbnk_cpu3_hit_l4 (l2_tbnk1_cpu3_hit_l4), + .l2_tbnk_cpu3_l2_inv_l4_dly2 (l2_tbnk1_cpu3_l2_inv_l4_dly2), + .l2_tbnk_cpu3_l2hit_e_l4 (l2_tbnk1_cpu3_l2hit_e_l4), + .l2_tbnk_cpu3_l2hit_s_l4 (l2_tbnk1_cpu3_l2hit_s_l4), + .l2_tbnk_cpu3_rd_access_l4_dly (l2_tbnk1_cpu3_rd_access_l4_dly), + .l2_tbnk_cpu3_self_evict_l4_dly_q (l2_tbnk1_cpu3_self_evict_l4_dly_q), + .l2_tbnk_cpu3_single_ecc_err_l7_q (l2_tbnk1_cpu3_single_ecc_err_l7_q), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_rd_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_rd_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_ecc_rmw_wr_l0 (l2_tbnk1_cpu3_snp_tag_ecc_rmw_wr_l0[1:0]), + .l2_tbnk_cpu3_snp_tag_wr_evict_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_early_l4_dly), + .l2_tbnk_cpu3_snp_tag_wr_l2_hit_early_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_l2_hit_early_l4_dly), + .l2_tbnk_cpu3_vld_nxt_l5 (l2_tbnk1_cpu3_vld_nxt_l5), + .l2_tbnk_cpu3_wr_access_l4_dly (l2_tbnk1_cpu3_wr_access_l4_dly), + .l2_tbnk_cpu_rvalid_init_nxt_l5 (l2_tbnk1_cpu_rvalid_init_nxt_l5[3:0]), + .l2_tbnk_cpu_rvalid_nxt_l5 (l2_tbnk1_cpu_rvalid_nxt_l5[3:0]), + .l2_tbnk_cpu_snp_hit_e_l4_q (l2_tbnk1_cpu_snp_hit_e_l4_q[3:0]), + .l2_tbnk_crit_qw_nxt_l5 (l2_tbnk1_crit_qw_nxt_l5), + .l2_tbnk_data_corrected_l7_q (l2_tbnk1_data_corrected_l7_q[143:0]), + .l2_tbnk_data_l6 (l2_tbnk1_data_l6[127:0]), + .l2_tbnk_dbg_ram_acc_l5a (l2_tbnk1_dbg_ram_acc_l5a), + .l2_tbnk_dbg_ram_acc_unit_nxt (l2_tbnk1_dbg_ram_acc_unit_nxt[2:0]), + .l2_tbnk_dbg_ram_id_nxt_l5 (l2_tbnk1_dbg_ram_id_nxt_l5[7:0]), + .l2_tbnk_dirty_l3_q (l2_tbnk1_dirty_l3_q), + .l2_tbnk_double_ecc_err_l7_q (l2_tbnk1_double_ecc_err_l7_q), + .l2_tbnk_early_rvalid_l4_q (l2_tbnk1_early_rvalid_l4_q), + .l2_tbnk_ecc_fixup_blk_arb (l2_tbnk1_ecc_fixup_blk_arb), + .l2_tbnk_ecc_fixup_inprog_dly_q (l2_tbnk1_ecc_fixup_inprog_dly_q), + .l2_tbnk_ecc_rmw_snp_tag_rd_l3_q (l2_tbnk1_ecc_rmw_snp_tag_rd_l3_q), + .l2_tbnk_ecc_syndrome_reg_q (l2_tbnk1_ecc_syndrome_reg_q[31:0]), + .l2_tbnk_evict_special_hazard_l3_q (l2_tbnk1_evict_special_hazard_l3_q), + .l2_tbnk_evict_special_hazard_rwvic_l3_q (l2_tbnk1_evict_special_hazard_rwvic_l3_q), + .l2_tbnk_excl_l4_q (l2_tbnk1_excl_l4_q), + .l2_tbnk_feq_addr_upd (l2_tbnk1_feq_addr_upd[44:6]), + .l2_tbnk_feq_clr_l4 (l2_tbnk1_feq_clr_l4), + .l2_tbnk_full_miss_l4_q (l2_tbnk1_full_miss_l4_q), + .l2_tbnk_hit_l4 (l2_tbnk1_hit_l4), + .l2_tbnk_hit_l7_q (l2_tbnk1_hit_l7_q), + .l2_tbnk_hit_way_l4_q (l2_tbnk1_hit_way_l4_q[3:0]), + .l2_tbnk_id_l6_q (l2_tbnk1_id_l6_q[9:0]), + .l2_tbnk_id_nxt_l5 (l2_tbnk1_id_nxt_l5[9:0]), + .l2_tbnk_idle (l2_tbnk1_idle), + .l2_tbnk_l2hit_e_l4 (l2_tbnk1_l2hit_e_l4), + .l2_tbnk_l2hit_s_l4 (l2_tbnk1_l2hit_s_l4), + .l2_tbnk_l2v_s_q (l2_tbnk1_l2v_s_q), + .l2_tbnk_l2v_vld_q (l2_tbnk1_l2v_vld_q), + .l2_tbnk_last_qw_l6_q (l2_tbnk1_last_qw_l6_q), + .l2_tbnk_last_qw_nxt_l5 (l2_tbnk1_last_qw_nxt_l5), + .l2_tbnk_lock_l4 (l2_tbnk1_lock_l4[2:0]), + .l2_tbnk_merrsr_data (l2_tbnk1_merrsr_data[32:0]), + .l2_tbnk_pf_cnt_dec_l4_dly (l2_tbnk1_pf_cnt_dec_l4_dly), + .l2_tbnk_pf_req_sel_for_fwd_l4 (l2_tbnk1_pf_req_sel_for_fwd_l4), + .l2_tbnk_prfm_nxt_l5 (l2_tbnk1_prfm_nxt_l5), + .l2_tbnk_prot_l4_q (l2_tbnk1_prot_l4_q[3:0]), + .l2_tbnk_qw_cnt_l3_q (l2_tbnk1_qw_cnt_l3_q[1:0]), + .l2_tbnk_raw_hit_l4_q (l2_tbnk1_raw_hit_l4_q), + .l2_tbnk_rbufid_nxt_l5 (l2_tbnk1_rbufid_nxt_l5[2:0]), + .l2_tbnk_rd_en_nxt_l5 (l2_tbnk1_rd_en_nxt_l5), + .l2_tbnk_rwvic_axi_read_err_l3_q (l2_tbnk1_rwvic_axi_read_err_l3_q), + .l2_tbnk_rwvic_ccb_dirty_l6_q (l2_tbnk1_rwvic_ccb_dirty_l6_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l3_q (l2_tbnk1_rwvic_ccb_ls_xfer_l3_q), + .l2_tbnk_rwvic_ccb_ls_xfer_l6_q (l2_tbnk1_rwvic_ccb_ls_xfer_l6_q), + .l2_tbnk_rwvic_cmo_inv_l7_q (l2_tbnk1_rwvic_cmo_inv_l7_q), + .l2_tbnk_rwvic_cmo_l7_q (l2_tbnk1_rwvic_cmo_l7_q), + .l2_tbnk_rwvic_cmo_pou_l6_q (l2_tbnk1_rwvic_cmo_pou_l6_q), + .l2_tbnk_rwvic_cmo_setway_ls_l6_q (l2_tbnk1_rwvic_cmo_setway_ls_l6_q), + .l2_tbnk_rwvic_ddi_l6_q (l2_tbnk1_rwvic_ddi_l6_q), + .l2_tbnk_rwvic_l2hit_e_l3_q (l2_tbnk1_rwvic_l2hit_e_l3_q), + .l2_tbnk_rwvic_l2hit_e_l7_q (l2_tbnk1_rwvic_l2hit_e_l7_q), + .l2_tbnk_rwvic_l2v_dirty_l7_q (l2_tbnk1_rwvic_l2v_dirty_l7_q), + .l2_tbnk_rwvic_l2v_page_attr_l7_q (l2_tbnk1_rwvic_l2v_page_attr_l7_q[3:0]), + .l2_tbnk_rwvic_l2v_vld_l6_q (l2_tbnk1_rwvic_l2v_vld_l6_q), + .l2_tbnk_rwvic_non_snp_fail_hazchk_l3 (l2_tbnk1_rwvic_non_snp_fail_hazchk_l3), + .l2_tbnk_rwvic_owner_l7_q (l2_tbnk1_rwvic_owner_l7_q[2:0]), + .l2_tbnk_rwvic_rd_type_l6_q (l2_tbnk1_rwvic_rd_type_l6_q), + .l2_tbnk_rwvic_snp_l3_q (l2_tbnk1_rwvic_snp_l3_q), + .l2_tbnk_rwvic_snp_l6_q (l2_tbnk1_rwvic_snp_l6_q), + .l2_tbnk_rwvic_tag_wr_l0 (l2_tbnk1_rwvic_tag_wr_l0), + .l2_tbnk_rwvic_wa_l6_q (l2_tbnk1_rwvic_wa_l6_q), + .l2_tbnk_size_l4_q (l2_tbnk1_size_l4_q[2:0]), + .l2_tbnk_snp_hit_e_l4_q (l2_tbnk1_snp_hit_e_l4_q), + .l2_tbnk_snp_hit_s_l4_q (l2_tbnk1_snp_hit_s_l4_q), + .l2_tbnk_snp_tag_wr_l2_hit_addr_l1 (l2_tbnk1_snp_tag_wr_l2_hit_addr_l1[44:7]), + .l2_tbnk_snp_tag_wr_l2_hit_state_l1 (l2_tbnk1_snp_tag_wr_l2_hit_state_l1[1:0]), + .l2_tbnk_snp_tag_wr_l2_hit_way_l1 (l2_tbnk1_snp_tag_wr_l2_hit_way_l1), + .l2_tbnk_special_evict_hazard_l3 (l2_tbnk1_special_evict_hazard_l3), + .l2_tbnk_special_hazard_l3_q (l2_tbnk1_special_hazard_l3_q), + .l2_tbnk_tag_ecc_dbl_rmw_wr_l1 (l2_tbnk1_tag_ecc_dbl_rmw_wr_l1), + .l2_tbnk_tag_ecc_err_cpu0_l4 (l2_tbnk1_tag_ecc_err_cpu0_l4), + .l2_tbnk_tag_ecc_err_cpu1_l4 (l2_tbnk1_tag_ecc_err_cpu1_l4), + .l2_tbnk_tag_ecc_err_cpu2_l4 (l2_tbnk1_tag_ecc_err_cpu2_l4), + .l2_tbnk_tag_ecc_err_cpu3_l4 (l2_tbnk1_tag_ecc_err_cpu3_l4), + .l2_tbnk_tag_ecc_err_l4 (l2_tbnk1_tag_ecc_err_l4), + .l2_tbnk_ulen_l4_q (l2_tbnk1_ulen_l4_q[1:0]), + .l2_tbnk_vld_init_l6_q (l2_tbnk1_vld_init_l6_q), + .l2_tbnk_vld_l6_q (l2_tbnk1_vld_l6_q), + .l2_tbnk_way_l4_q (l2_tbnk1_way_l4_q), + .l2_tbnk_way_nxt_l3a (l2_tbnk1_way_nxt_l3a), + .l2_tbnk_wr_data_l3 (l2_tbnk1_wr_data_l3[143:0]), + .l2_tbnk_wr_data_l4_en (l2_tbnk1_wr_data_l4_en), + .l2_tbnk_wr_non_crit_id_l4_q (l2_tbnk1_wr_non_crit_id_l4_q[11:0]), + + // inputs + .DFTCLKBYPASS (DFTCLKBYPASS), + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRAMHOLD (DFTRAMHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ), + .ck_areset_l2 (ck_areset_l2), + .ck_gclkl2 (ck_gclkb1), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .l2_acp_flsh_rd_cnt_active_glb_l2_dly (l2_acp_flsh_rd_cnt_active_glb_l2_dly), + .l2_acp_flsh_wr_cnt_active_glb_l2_dly (l2_acp_flsh_wr_cnt_active_glb_l2_dly), + .l2_acp_rd_haz_vld_l2_dly_q (l2_acp_rd_haz_vld_l2_dly_q), + .l2_acp_wr_haz_vld_l2_dly_q (l2_acp_wr_haz_vld_l2_dly_q), + .l2_actlr_disable_b2b_setway_hzd_opt_x2_ns (l2_actlr_disable_b2b_setway_hzd_opt_x2_ns), + .l2_actlr_disable_setway_opt (l2_actlr_disable_setway_opt), + .l2_actlr_plru_dynamic (l2_actlr_plru_dynamic), + .l2_actlr_plru_en (l2_actlr_plru_en), + .l2_actlr_plru_mode (l2_actlr_plru_mode[1:0]), + .l2_actlr_writeunique_disable (l2_actlr_writeunique_disable), + .l2_cfg_broadcastinner (l2_cfg_broadcastinner), + .l2_cfg_broadcastouter (l2_cfg_broadcastouter), + .l2_cpu0_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu0_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu0_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu0_ls_rd_haz_vld_l2_dly_q (l2_cpu0_ls_rd_haz_vld_l2_dly_q), + .l2_cpu0_ls_wr_haz_vld_l2_dly_q (l2_cpu0_ls_wr_haz_vld_l2_dly_q), + .l2_cpu1_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu1_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu1_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu1_ls_rd_haz_vld_l2_dly_q (l2_cpu1_ls_rd_haz_vld_l2_dly_q), + .l2_cpu1_ls_wr_haz_vld_l2_dly_q (l2_cpu1_ls_wr_haz_vld_l2_dly_q), + .l2_cpu2_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu2_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu2_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu2_ls_rd_haz_vld_l2_dly_q (l2_cpu2_ls_rd_haz_vld_l2_dly_q), + .l2_cpu2_ls_wr_haz_vld_l2_dly_q (l2_cpu2_ls_wr_haz_vld_l2_dly_q), + .l2_cpu3_flsh_ls_rd_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_rd_cnt_active_glb_l2_dly), + .l2_cpu3_flsh_ls_wr_cnt_active_glb_l2_dly (l2_cpu3_tbnk1_flsh_ls_wr_cnt_active_glb_l2_dly), + .l2_cpu3_ls_rd_haz_vld_l2_dly_q (l2_cpu3_ls_rd_haz_vld_l2_dly_q), + .l2_cpu3_ls_wr_haz_vld_l2_dly_q (l2_cpu3_ls_wr_haz_vld_l2_dly_q), + .l2_ctlr_x1_wr_q (l2_ctlr_x1_wr_q), + .l2_ctlr_x2_ns (l2_ctlr_x2_ns[9:0]), + .l2_mbist2_snp0_outdata_b2 (l2_mbist2_tbnk1_snp0_outdata_b2[79:0]), + .l2_mbist2_snp0_outdata_vld_b2 (l2_mbist2_tbnk1_snp0_outdata_vld_b2), + .l2_mbist2_snp1_outdata_b2 (l2_mbist2_tbnk1_snp1_outdata_b2[79:0]), + .l2_mbist2_snp1_outdata_vld_b2 (l2_mbist2_tbnk1_snp1_outdata_vld_b2), + .l2_mbist2_snp2_outdata_b2 (l2_mbist2_tbnk1_snp2_outdata_b2[79:0]), + .l2_mbist2_snp2_outdata_vld_b2 (l2_mbist2_tbnk1_snp2_outdata_vld_b2), + .l2_mbist2_snp3_outdata_b2 (l2_mbist2_tbnk1_snp3_outdata_b2[79:0]), + .l2_mbist2_snp3_outdata_vld_b2 (l2_mbist2_tbnk1_snp3_outdata_vld_b2), + .l2_no_ram_acc_nxt_cycle (l2_no_ram_acc_nxt_cycle), + .l2_rstdisable_x1_q (l2_rstdisable_x1_q), + .l2_skyros_intf (1'b1), + .l2_tbnk_addr_l1 (l2_tbnk1_addr_l1[44:0]), + .l2_tbnk_asq_cmp_evict_l3_q (l2_tbnk1_asq_cmp_evict_l3_q), + .l2_tbnk_asq_full_flsh (l2_tbnk1_asq_full_flsh), + .l2_tbnk_asq_nc_so_dev_limit (l2_tbnk1_asq_nc_so_dev_limit), + .l2_tbnk_cache_attr_l1 (l2_tbnk1_cache_attr_l1[2:0]), + .l2_tbnk_cfg_ecc_en (l2_tbnk1_cfg_ecc_en), + .l2_tbnk_cpu0_peq_full_q (l2_tbnk1_cpu0_peq_full_q), + .l2_tbnk_cpu0_peq_hit_q (l2_tbnk1_cpu0_peq_hit_q), + .l2_tbnk_cpu0_peq_self_evict_l3_q (l2_tbnk1_cpu0_peq_self_evict_l3_q), + .l2_tbnk_cpu0_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu0_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu0_snp_hit_e_l3 (l2_tbnk1_cpu0_snp_hit_e_l3), + .l2_tbnk_cpu0_snp_hit_s_l3 (l2_tbnk1_cpu0_snp_hit_s_l3), + .l2_tbnk_cpu0_snp_setway_addr_l3 (l2_tbnk1_cpu0_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu0_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu0_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu0_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu0_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu1_peq_full_q (l2_tbnk1_cpu1_peq_full_q), + .l2_tbnk_cpu1_peq_hit_q (l2_tbnk1_cpu1_peq_hit_q), + .l2_tbnk_cpu1_peq_self_evict_l3_q (l2_tbnk1_cpu1_peq_self_evict_l3_q), + .l2_tbnk_cpu1_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu1_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu1_snp_hit_e_l3 (l2_tbnk1_cpu1_snp_hit_e_l3), + .l2_tbnk_cpu1_snp_hit_s_l3 (l2_tbnk1_cpu1_snp_hit_s_l3), + .l2_tbnk_cpu1_snp_setway_addr_l3 (l2_tbnk1_cpu1_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu1_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu1_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu1_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu1_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu2_peq_full_q (l2_tbnk1_cpu2_peq_full_q), + .l2_tbnk_cpu2_peq_hit_q (l2_tbnk1_cpu2_peq_hit_q), + .l2_tbnk_cpu2_peq_self_evict_l3_q (l2_tbnk1_cpu2_peq_self_evict_l3_q), + .l2_tbnk_cpu2_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu2_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu2_snp_hit_e_l3 (l2_tbnk1_cpu2_snp_hit_e_l3), + .l2_tbnk_cpu2_snp_hit_s_l3 (l2_tbnk1_cpu2_snp_hit_s_l3), + .l2_tbnk_cpu2_snp_setway_addr_l3 (l2_tbnk1_cpu2_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu2_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu2_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu2_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu2_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_cpu3_peq_full_q (l2_tbnk1_cpu3_peq_full_q), + .l2_tbnk_cpu3_peq_hit_q (l2_tbnk1_cpu3_peq_hit_q), + .l2_tbnk_cpu3_peq_self_evict_l3_q (l2_tbnk1_cpu3_peq_self_evict_l3_q), + .l2_tbnk_cpu3_peq_self_evict_wbna_l3_q (l2_tbnk1_cpu3_peq_self_evict_wbna_l3_q), + .l2_tbnk_cpu3_snp_hit_e_l3 (l2_tbnk1_cpu3_snp_hit_e_l3), + .l2_tbnk_cpu3_snp_hit_s_l3 (l2_tbnk1_cpu3_snp_hit_s_l3), + .l2_tbnk_cpu3_snp_setway_addr_l3 (l2_tbnk1_cpu3_snp_setway_addr_l3[44:14]), + .l2_tbnk_cpu3_snp_tag_ecc_err_tp_l4_q (l2_tbnk1_cpu3_snp_tag_ecc_err_tp_l4_q), + .l2_tbnk_cpu3_snp_tag_wr_evict_qual_l4_dly (l2_tbnk1_cpu3_snp_tag_wr_evict_qual_l4_dly), + .l2_tbnk_dirty_l1 (l2_tbnk1_dirty_l1), + .l2_tbnk_dis_ns_dbg_arr_acc_x2 (l2_tbnk1_dis_ns_dbg_arr_acc_x2), + .l2_tbnk_excl_l1 (l2_tbnk1_excl_l1), + .l2_tbnk_feq_alloc_failed_l4 (l2_tbnk1_feq_alloc_failed_l4), + .l2_tbnk_feq_axi_wr_vld_not_popped (l2_tbnk1_feq_axi_wr_vld_not_popped), + .l2_tbnk_feq_frc_incl_l3a (l2_tbnk1_feq_frc_incl_l3a[15:0]), + .l2_tbnk_feq_kill_l3 (l2_tbnk1_feq_kill_l3), + .l2_tbnk_feq_last_id_q (l2_tbnk1_feq_last_id_q[4:0]), + .l2_tbnk_feq_tbnk_id_update_hit_prfm_or_l3 (l2_tbnk1_feq_tbnk_id_update_hit_prfm_or_l3), + .l2_tbnk_feq_tbnk_id_update_or_l3 (l2_tbnk1_feq_tbnk_id_update_or_l3), + .l2_tbnk_hwrst_done_x2 (l2_tbnk_hwrst_done_x2), + .l2_tbnk_hwrst_idx_x1_q (l2_tbnk_hwrst_idx_x1_q[13:0]), + .l2_tbnk_id_l1 (l2_tbnk1_id_l1[9:0]), + .l2_tbnk_init_req_l1 (l2_tbnk1_init_req_l1), + .l2_tbnk_kill_l2 (l2_tbnk1_kill_l2), + .l2_tbnk_l2bb_fake_wr_l1 (l2_tbnk1_l2bb_fake_wr_l1), + .l2_tbnk_l2bb_wr_l1 (l2_tbnk1_l2bb_wr_l1), + .l2_tbnk_last_qw_l1 (l2_tbnk1_last_qw_l1), + .l2_tbnk_lock_l1 (l2_tbnk1_lock_l1[2:0]), + .l2_tbnk_page_attr_l1 (l2_tbnk1_page_attr_l1[9:0]), + .l2_tbnk_partial_dw_wr_l1 (l2_tbnk1_partial_dw_wr_l1), + .l2_tbnk_pf_hazard_l3 (l2_tbnk1_pf_hazard_l3), + .l2_tbnk_prfm_l1 (l2_tbnk1_prfm_l1), + .l2_tbnk_prot_l1 (l2_tbnk1_prot_l1[3:0]), + .l2_tbnk_qw_cnt_l1 (l2_tbnk1_qw_cnt_l1[1:0]), + .l2_tbnk_rd_fail_hazchk_feq_l3 (l2_tbnk1_rd_fail_hazchk_feq_l3), + .l2_tbnk_rwvic_axi_read_err_l1 (l2_tbnk1_rwvic_axi_read_err_l1), + .l2_tbnk_rwvic_ccb_ls_xfer_l1 (l2_tbnk1_rwvic_ccb_ls_xfer_l1), + .l2_tbnk_rwvic_ccb_way_l1 (l2_tbnk1_rwvic_ccb_way_l1[3:0]), + .l2_tbnk_rwvic_cmo_clean_l1 (l2_tbnk1_rwvic_cmo_clean_l1), + .l2_tbnk_rwvic_cmo_inv_l1 (l2_tbnk1_rwvic_cmo_inv_l1), + .l2_tbnk_rwvic_cmo_pou_l1 (l2_tbnk1_rwvic_cmo_pou_l1), + .l2_tbnk_rwvic_cmo_setway_l1 (l2_tbnk1_rwvic_cmo_setway_l1), + .l2_tbnk_rwvic_cmo_setway_ls_full_miss_l1 (l2_tbnk1_rwvic_cmo_setway_ls_full_miss_l1), + .l2_tbnk_rwvic_cpu_fb_id_l1 (l2_tbnk1_rwvic_cpu_fb_id_l1[2:0]), + .l2_tbnk_rwvic_cpu_id_dcd_l1 (l2_tbnk1_rwvic_cpu_id_dcd_l1[3:0]), + .l2_tbnk_rwvic_feq_cmp_l3_q (l2_tbnk1_rwvic_feq_cmp_l3_q), + .l2_tbnk_rwvic_frc_l2hit_fwd_l1 (l2_tbnk1_rwvic_frc_l2hit_fwd_l1), + .l2_tbnk_rwvic_l2hit_e_l1 (l2_tbnk1_rwvic_l2hit_e_l1), + .l2_tbnk_rwvic_mesi_sh_l1 (l2_tbnk1_rwvic_mesi_sh_l1), + .l2_tbnk_rwvic_owner_l1 (l2_tbnk1_rwvic_owner_l1[2:0]), + .l2_tbnk_rwvic_snp_clr_dirty_l1 (l2_tbnk1_rwvic_snp_clr_dirty_l1), + .l2_tbnk_rwvic_snp_inv_l1 (l2_tbnk1_rwvic_snp_inv_l1), + .l2_tbnk_rwvic_snp_l1 (l2_tbnk1_rwvic_snp_l1), + .l2_tbnk_rwvic_type_l1 (l2_tbnk1_rwvic_type_l1[3:0]), + .l2_tbnk_rwvic_wa_l1 (l2_tbnk1_rwvic_wa_l1), + .l2_tbnk_sel_l1 (l2_tbnk1_sel_l1[13:0]), + .l2_tbnk_size_l1 (l2_tbnk1_size_l1[2:0]), + .l2_tbnk_snp_byp_peq_haz_pending_q (l2_tbnk1_snp_byp_peq_haz_pending_q), + .l2_tbnk_snp_dvm_cmpl_l1 (l2_tbnk1_snp_dvm_cmpl_l1), + .l2_tbnk_snp_hit_feq_evict_l4_dly (l2_tbnk1_snp_hit_feq_evict_l4_dly), + .l2_tbnk_snp_rd_feq_id_cmp_l4_dly_q (l2_tbnk1_snp_rd_feq_id_cmp_l4_dly_q[4:0]), + .l2_tbnk_snp_tag_double_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_double_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_snp_tag_single_ecc_err_l4_dly_q (l2_tbnk1_snp_tag_single_ecc_err_l4_dly_q[7:0]), + .l2_tbnk_sync_l1 (l2_tbnk1_sync_l1), + .l2_tbnk_type_l1 (l2_tbnk1_type_l1[6:0]), + .l2_tbnk_ulen_l1 (l2_tbnk1_ulen_l1[1:0]), + .l2_tbnk_way_l1 (l2_tbnk1_way_l1), + .l2_tbnk_wr_data_l3a_q (l2_tbnk1_wr_data_l3a_q[127:0]), + .l2_tbnk_wr_err_l1 (l2_tbnk1_wr_err_l1), + .l2_tbnk_wr_fail_feq_full_l3 (l2_tbnk1_wr_fail_feq_full_l3), + .l2_tbnk_wr_fail_hazchk_feq_l3 (l2_tbnk1_wr_fail_hazchk_feq_l3), + .l2_tbnk_wr_non_crit_id_l1 (l2_tbnk1_wr_non_crit_id_l1[11:0]), + .l2_tbnk_wr_strb_mask_l3a_q (l2_tbnk1_wr_strb_mask_l3a_q[15:0]) + ); // ul2_tbnk1 + + maia_dt_pclk udt_pclk( // outputs + .CTICHINACK (CTICHINACK[3:0]), + .CTICHOUT (CTICHOUT[3:0]), + .CTIIRQ (CTIIRQ[`MAIA_CN:0]), + .DBGPWRUPREQ (DBGPWRUPREQ[`MAIA_CN:0]), + .PMUSNAPSHOTACK (PMUSNAPSHOTACK[`MAIA_CN:0]), + .PRDATADBG (PRDATADBG[31:0]), + .PREADYDBG (PREADYDBG), + .PSLVERRDBG (PSLVERRDBG), + .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), + .dt_cpu0_cti_triginack_1to0_pclk (dt_cpu0_cti_triginack_1to0_pclk[1:0]), + .dt_cpu0_cti_triginack_7to4_pclk (dt_cpu0_cti_triginack_7to4_pclk[3:0]), + .dt_cpu0_cti_trigout_1to0_pclk (dt_cpu0_cti_trigout_1to0_pclk[1:0]), + .dt_cpu0_cti_trigout_7to4_pclk (dt_cpu0_cti_trigout_7to4_pclk[3:0]), + .dt_cpu0_dbif_addr_pclk (dt_cpu0_dbif_addr_pclk[14:2]), + .dt_cpu0_dbif_locked_pclk (dt_cpu0_dbif_locked_pclk), + .dt_cpu0_dbif_req_pclk (dt_cpu0_dbif_req_pclk), + .dt_cpu0_dbif_wrdata_pclk (dt_cpu0_dbif_wrdata_pclk[31:0]), + .dt_cpu0_dbif_write_pclk (dt_cpu0_dbif_write_pclk), + .dt_cpu0_edacr_frc_idleack_pclk (dt_cpu0_edacr_frc_idleack_pclk), + .dt_cpu0_edbgrq_pclk (dt_cpu0_edbgrq_pclk), + .dt_cpu0_edecr_osuce_pclk (dt_cpu0_edecr_osuce_pclk), + .dt_cpu0_edecr_rce_pclk (dt_cpu0_edecr_rce_pclk), + .dt_cpu0_edecr_ss_pclk (dt_cpu0_edecr_ss_pclk), + .dt_cpu0_edprcr_corepurq_pclk (dt_cpu0_edprcr_corepurq_pclk), + .dt_cpu0_noclkstop_pclk (dt_cpu0_noclkstop_pclk), + .dt_cpu0_pmusnapshot_req_pclk (dt_cpu0_pmusnapshot_req_pclk), + .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), + .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), + .dt_cpu1_cti_triginack_1to0_pclk (dt_cpu1_cti_triginack_1to0_pclk[1:0]), + .dt_cpu1_cti_triginack_7to4_pclk (dt_cpu1_cti_triginack_7to4_pclk[3:0]), + .dt_cpu1_cti_trigout_1to0_pclk (dt_cpu1_cti_trigout_1to0_pclk[1:0]), + .dt_cpu1_cti_trigout_7to4_pclk (dt_cpu1_cti_trigout_7to4_pclk[3:0]), + .dt_cpu1_dbif_addr_pclk (dt_cpu1_dbif_addr_pclk[14:2]), + .dt_cpu1_dbif_locked_pclk (dt_cpu1_dbif_locked_pclk), + .dt_cpu1_dbif_req_pclk (dt_cpu1_dbif_req_pclk), + .dt_cpu1_dbif_wrdata_pclk (dt_cpu1_dbif_wrdata_pclk[31:0]), + .dt_cpu1_dbif_write_pclk (dt_cpu1_dbif_write_pclk), + .dt_cpu1_edacr_frc_idleack_pclk (dt_cpu1_edacr_frc_idleack_pclk), + .dt_cpu1_edbgrq_pclk (dt_cpu1_edbgrq_pclk), + .dt_cpu1_edecr_osuce_pclk (dt_cpu1_edecr_osuce_pclk), + .dt_cpu1_edecr_rce_pclk (dt_cpu1_edecr_rce_pclk), + .dt_cpu1_edecr_ss_pclk (dt_cpu1_edecr_ss_pclk), + .dt_cpu1_edprcr_corepurq_pclk (dt_cpu1_edprcr_corepurq_pclk), + .dt_cpu1_noclkstop_pclk (dt_cpu1_noclkstop_pclk), + .dt_cpu1_pmusnapshot_req_pclk (dt_cpu1_pmusnapshot_req_pclk), + .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), + .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), + .dt_cpu2_cti_triginack_1to0_pclk (dt_cpu2_cti_triginack_1to0_pclk[1:0]), + .dt_cpu2_cti_triginack_7to4_pclk (dt_cpu2_cti_triginack_7to4_pclk[3:0]), + .dt_cpu2_cti_trigout_1to0_pclk (dt_cpu2_cti_trigout_1to0_pclk[1:0]), + .dt_cpu2_cti_trigout_7to4_pclk (dt_cpu2_cti_trigout_7to4_pclk[3:0]), + .dt_cpu2_dbif_addr_pclk (dt_cpu2_dbif_addr_pclk[14:2]), + .dt_cpu2_dbif_locked_pclk (dt_cpu2_dbif_locked_pclk), + .dt_cpu2_dbif_req_pclk (dt_cpu2_dbif_req_pclk), + .dt_cpu2_dbif_wrdata_pclk (dt_cpu2_dbif_wrdata_pclk[31:0]), + .dt_cpu2_dbif_write_pclk (dt_cpu2_dbif_write_pclk), + .dt_cpu2_edacr_frc_idleack_pclk (dt_cpu2_edacr_frc_idleack_pclk), + .dt_cpu2_edbgrq_pclk (dt_cpu2_edbgrq_pclk), + .dt_cpu2_edecr_osuce_pclk (dt_cpu2_edecr_osuce_pclk), + .dt_cpu2_edecr_rce_pclk (dt_cpu2_edecr_rce_pclk), + .dt_cpu2_edecr_ss_pclk (dt_cpu2_edecr_ss_pclk), + .dt_cpu2_edprcr_corepurq_pclk (dt_cpu2_edprcr_corepurq_pclk), + .dt_cpu2_noclkstop_pclk (dt_cpu2_noclkstop_pclk), + .dt_cpu2_pmusnapshot_req_pclk (dt_cpu2_pmusnapshot_req_pclk), + .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), + .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), + .dt_cpu3_cti_triginack_1to0_pclk (dt_cpu3_cti_triginack_1to0_pclk[1:0]), + .dt_cpu3_cti_triginack_7to4_pclk (dt_cpu3_cti_triginack_7to4_pclk[3:0]), + .dt_cpu3_cti_trigout_1to0_pclk (dt_cpu3_cti_trigout_1to0_pclk[1:0]), + .dt_cpu3_cti_trigout_7to4_pclk (dt_cpu3_cti_trigout_7to4_pclk[3:0]), + .dt_cpu3_dbif_addr_pclk (dt_cpu3_dbif_addr_pclk[14:2]), + .dt_cpu3_dbif_locked_pclk (dt_cpu3_dbif_locked_pclk), + .dt_cpu3_dbif_req_pclk (dt_cpu3_dbif_req_pclk), + .dt_cpu3_dbif_wrdata_pclk (dt_cpu3_dbif_wrdata_pclk[31:0]), + .dt_cpu3_dbif_write_pclk (dt_cpu3_dbif_write_pclk), + .dt_cpu3_edacr_frc_idleack_pclk (dt_cpu3_edacr_frc_idleack_pclk), + .dt_cpu3_edbgrq_pclk (dt_cpu3_edbgrq_pclk), + .dt_cpu3_edecr_osuce_pclk (dt_cpu3_edecr_osuce_pclk), + .dt_cpu3_edecr_rce_pclk (dt_cpu3_edecr_rce_pclk), + .dt_cpu3_edecr_ss_pclk (dt_cpu3_edecr_ss_pclk), + .dt_cpu3_edprcr_corepurq_pclk (dt_cpu3_edprcr_corepurq_pclk), + .dt_cpu3_noclkstop_pclk (dt_cpu3_noclkstop_pclk), + .dt_cpu3_pmusnapshot_req_pclk (dt_cpu3_pmusnapshot_req_pclk), + .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), + .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + + // inputs + .CIHSBYPASS (CIHSBYPASS[3:0]), + .CISBYPASS (CISBYPASS), + .CLUSTERIDAFF1 (CLUSTERIDAFF1[7:0]), + .CLUSTERIDAFF2 (CLUSTERIDAFF2[7:0]), + .CRYPTODISABLE (CRYPTODISABLE[`MAIA_CN:0]), + .CTICHIN (CTICHIN[3:0]), + .CTICHOUTACK (CTICHOUTACK[3:0]), + .CTIIRQACK (CTIIRQACK[`MAIA_CN:0]), + .DBGEN (DBGEN[`MAIA_CN:0]), + .DBGPWRDUP (DBGPWRDUP[`MAIA_CN:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .EDBGRQ (EDBGRQ[`MAIA_CN:0]), + .GICCDISABLE (GICCDISABLE), + .NIDEN (NIDEN[`MAIA_CN:0]), + .PADDRDBG (PADDRDBG[21:2]), + .PADDRDBG31 (PADDRDBG31), + .PCLKDBG (PCLKDBG), + .PCLKENDBG (PCLKENDBG), + .PENABLEDBG (PENABLEDBG), + .PMUSNAPSHOTREQ (PMUSNAPSHOTREQ[`MAIA_CN:0]), + .PSELDBG (PSELDBG), + .PWDATADBG (PWDATADBG[31:0]), + .PWRITEDBG (PWRITEDBG), + .SPIDEN (SPIDEN[`MAIA_CN:0]), + .SPNIDEN (SPNIDEN[`MAIA_CN:0]), + .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), + .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), + .ck_cpu0_poreset_status (ck_cpu0_poreset_status), + .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), + .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), + .ck_cpu1_poreset_status (ck_cpu1_poreset_status), + .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), + .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), + .ck_cpu2_poreset_status (ck_cpu2_poreset_status), + .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), + .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), + .ck_cpu3_poreset_status (ck_cpu3_poreset_status), + .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), + .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), + .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), + .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), + .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), + .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), + .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), + .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), + .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), + .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), + .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), + .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), + .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), + .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), + .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), + .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), + .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), + .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), + .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), + .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), + .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), + .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), + .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), + .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), + .dt_cpu0_cti_trigin_7to4_gclk (dt_cpu0_cti_trigin_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_7to4_gclk (dt_cpu0_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu0_cti_trigoutack_bit1_gclk (dt_cpu0_cti_trigoutack_bit1_gclk), + .dt_cpu0_dbif_ack_gclk (dt_cpu0_dbif_ack_gclk), + .dt_cpu0_dbif_err_gclk (dt_cpu0_dbif_err_gclk), + .dt_cpu0_dbif_rddata_gclk (dt_cpu0_dbif_rddata_gclk[31:0]), + .dt_cpu0_halt_ack_gclk (dt_cpu0_halt_ack_gclk), + .dt_cpu1_cti_trigin_7to4_gclk (dt_cpu1_cti_trigin_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_7to4_gclk (dt_cpu1_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu1_cti_trigoutack_bit1_gclk (dt_cpu1_cti_trigoutack_bit1_gclk), + .dt_cpu1_dbif_ack_gclk (dt_cpu1_dbif_ack_gclk), + .dt_cpu1_dbif_err_gclk (dt_cpu1_dbif_err_gclk), + .dt_cpu1_dbif_rddata_gclk (dt_cpu1_dbif_rddata_gclk[31:0]), + .dt_cpu1_halt_ack_gclk (dt_cpu1_halt_ack_gclk), + .dt_cpu2_cti_trigin_7to4_gclk (dt_cpu2_cti_trigin_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_7to4_gclk (dt_cpu2_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu2_cti_trigoutack_bit1_gclk (dt_cpu2_cti_trigoutack_bit1_gclk), + .dt_cpu2_dbif_ack_gclk (dt_cpu2_dbif_ack_gclk), + .dt_cpu2_dbif_err_gclk (dt_cpu2_dbif_err_gclk), + .dt_cpu2_dbif_rddata_gclk (dt_cpu2_dbif_rddata_gclk[31:0]), + .dt_cpu2_halt_ack_gclk (dt_cpu2_halt_ack_gclk), + .dt_cpu3_cti_trigin_7to4_gclk (dt_cpu3_cti_trigin_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_7to4_gclk (dt_cpu3_cti_trigoutack_7to4_gclk[3:0]), + .dt_cpu3_cti_trigoutack_bit1_gclk (dt_cpu3_cti_trigoutack_bit1_gclk), + .dt_cpu3_dbif_ack_gclk (dt_cpu3_dbif_ack_gclk), + .dt_cpu3_dbif_err_gclk (dt_cpu3_dbif_err_gclk), + .dt_cpu3_dbif_rddata_gclk (dt_cpu3_dbif_rddata_gclk[31:0]), + .dt_cpu3_halt_ack_gclk (dt_cpu3_halt_ack_gclk), + .nPRESETDBG (nPRESETDBG) + ); // udt_pclk + + maia_intctrl uic( // outputs + .ICCTDATA (ICCTDATA[15:0]), + .ICCTID (ICCTID[1:0]), + .ICCTLAST (ICCTLAST), + .ICCTVALID (ICCTVALID), + .ICDTREADY (ICDTREADY), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), + .ic_cpu0_l2_dsb_block (ic_cpu0_l2_dsb_block), + .ic_cpu0_spr_rd_data (ic_cpu0_spr_rd_data[63:0]), + .ic_cpu1_l2_dsb_block (ic_cpu1_l2_dsb_block), + .ic_cpu1_spr_rd_data (ic_cpu1_spr_rd_data[63:0]), + .ic_cpu2_l2_dsb_block (ic_cpu2_l2_dsb_block), + .ic_cpu2_spr_rd_data (ic_cpu2_spr_rd_data[63:0]), + .ic_cpu3_l2_dsb_block (ic_cpu3_l2_dsb_block), + .ic_cpu3_spr_rd_data (ic_cpu3_spr_rd_data[63:0]), + .ic_el_change_complete_o (ic_el_change_complete_o[`MAIA_CN:0]), + .ic_hcr_change_complete_o (ic_hcr_change_complete_o[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .ic_p_rdata (ic_p_rdata[31:0]), + .ic_p_rdata_valid (ic_p_rdata_valid), + .ic_p_ready (ic_p_ready), + .ic_p_valid (ic_p_valid[`MAIA_CN:0]), + .ic_sample_spr_o (ic_sample_spr_o[`MAIA_CN:0]), + .ic_scr_change_complete_o (ic_scr_change_complete_o[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]), + .nVCPUMNTIRQ (nVCPUMNTIRQ[`MAIA_CN:0]), + + // inputs + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .GICCDISABLE (GICCDISABLE), + .ICCTREADY (ICCTREADY), + .ICDTDATA (ICDTDATA[15:0]), + .ICDTDEST (ICDTDEST[1:0]), + .ICDTLAST (ICDTLAST), + .ICDTVALID (ICDTVALID), + .ck_areset_l2 (ck_areset_l2), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_aa64naa32_i (ds_cpu0_ic_aa64naa32_i), + .ds_cpu0_cpsr_mode_i (ds_cpu0_ic_cpsr_mode_i[4:0]), + .ds_cpu0_hcr_change_i (ds_cpu0_ic_hcr_change_i), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_l2_spr_addr (ds_cpu0_l2_spr_addr[8:0]), + .ds_cpu0_l2_spr_dw (ds_cpu0_l2_spr_dw), + .ds_cpu0_l2_spr_rd (ds_cpu0_l2_spr_rd), + .ds_cpu0_l2_spr_wr (ds_cpu0_l2_spr_wr), + .ds_cpu0_l2_spr_wr_data (ds_cpu0_l2_spr_wr_data[63:0]), + .ds_cpu0_sample_spr_i (ds_cpu0_ic_sample_spr_i), + .ds_cpu0_scr_change_i (ds_cpu0_ic_scr_change_i), + .ds_cpu1_aa64naa32_i (ds_cpu1_ic_aa64naa32_i), + .ds_cpu1_cpsr_mode_i (ds_cpu1_ic_cpsr_mode_i[4:0]), + .ds_cpu1_hcr_change_i (ds_cpu1_ic_hcr_change_i), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_l2_spr_addr (ds_cpu1_l2_spr_addr[8:0]), + .ds_cpu1_l2_spr_dw (ds_cpu1_l2_spr_dw), + .ds_cpu1_l2_spr_rd (ds_cpu1_l2_spr_rd), + .ds_cpu1_l2_spr_wr (ds_cpu1_l2_spr_wr), + .ds_cpu1_l2_spr_wr_data (ds_cpu1_l2_spr_wr_data[63:0]), + .ds_cpu1_sample_spr_i (ds_cpu1_ic_sample_spr_i), + .ds_cpu1_scr_change_i (ds_cpu1_ic_scr_change_i), + .ds_cpu2_aa64naa32_i (ds_cpu2_ic_aa64naa32_i), + .ds_cpu2_cpsr_mode_i (ds_cpu2_ic_cpsr_mode_i[4:0]), + .ds_cpu2_hcr_change_i (ds_cpu2_ic_hcr_change_i), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_l2_spr_addr (ds_cpu2_l2_spr_addr[8:0]), + .ds_cpu2_l2_spr_dw (ds_cpu2_l2_spr_dw), + .ds_cpu2_l2_spr_rd (ds_cpu2_l2_spr_rd), + .ds_cpu2_l2_spr_wr (ds_cpu2_l2_spr_wr), + .ds_cpu2_l2_spr_wr_data (ds_cpu2_l2_spr_wr_data[63:0]), + .ds_cpu2_sample_spr_i (ds_cpu2_ic_sample_spr_i), + .ds_cpu2_scr_change_i (ds_cpu2_ic_scr_change_i), + .ds_cpu3_aa64naa32_i (ds_cpu3_ic_aa64naa32_i), + .ds_cpu3_cpsr_mode_i (ds_cpu3_ic_cpsr_mode_i[4:0]), + .ds_cpu3_hcr_change_i (ds_cpu3_ic_hcr_change_i), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_l2_spr_addr (ds_cpu3_l2_spr_addr[8:0]), + .ds_cpu3_l2_spr_dw (ds_cpu3_l2_spr_dw), + .ds_cpu3_l2_spr_rd (ds_cpu3_l2_spr_rd), + .ds_cpu3_l2_spr_wr (ds_cpu3_l2_spr_wr), + .ds_cpu3_l2_spr_wr_data (ds_cpu3_l2_spr_wr_data[63:0]), + .ds_cpu3_sample_spr_i (ds_cpu3_ic_sample_spr_i), + .ds_cpu3_scr_change_i (ds_cpu3_ic_scr_change_i), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_cpu0_wr_decerr_i (l2_cpu0_wr_decerr_q), + .l2_cpu0_wr_slverr_i (l2_cpu0_wr_slverr_q), + .l2_cpu1_wr_decerr_i (l2_cpu1_wr_decerr_q), + .l2_cpu1_wr_slverr_i (l2_cpu1_wr_slverr_q), + .l2_cpu2_wr_decerr_i (l2_cpu2_wr_decerr_q), + .l2_cpu2_wr_slverr_i (l2_cpu2_wr_slverr_q), + .l2_cpu3_wr_decerr_i (l2_cpu3_wr_decerr_q), + .l2_cpu3_wr_slverr_i (l2_cpu3_wr_slverr_q), + .l2_p_addr (l2_p_addr[13:0]), + .l2_p_cpu (l2_p_cpu[1:0]), + .l2_p_nsecure (l2_p_nsecure), + .l2_p_sel (l2_p_sel[2:0]), + .l2_p_wdata (l2_p_wdata[31:0]), + .l2_p_write (l2_p_write), + .ls_cpu0_imp_abort_containable (ls_cpu0_imp_abort_containable), + .ls_cpu0_imp_abort_dec (ls_cpu0_imp_abort_dec), + .ls_cpu0_imp_abort_ecc (ls_cpu0_imp_abort_ecc), + .ls_cpu0_imp_abort_slv (ls_cpu0_imp_abort_slv), + .ls_cpu0_raw_eae_nonsec (ls_cpu0_raw_eae_nonsec), + .ls_cpu0_raw_eae_secure (ls_cpu0_raw_eae_secure), + .ls_cpu1_imp_abort_containable (ls_cpu1_imp_abort_containable), + .ls_cpu1_imp_abort_dec (ls_cpu1_imp_abort_dec), + .ls_cpu1_imp_abort_ecc (ls_cpu1_imp_abort_ecc), + .ls_cpu1_imp_abort_slv (ls_cpu1_imp_abort_slv), + .ls_cpu1_raw_eae_nonsec (ls_cpu1_raw_eae_nonsec), + .ls_cpu1_raw_eae_secure (ls_cpu1_raw_eae_secure), + .ls_cpu2_imp_abort_containable (ls_cpu2_imp_abort_containable), + .ls_cpu2_imp_abort_dec (ls_cpu2_imp_abort_dec), + .ls_cpu2_imp_abort_ecc (ls_cpu2_imp_abort_ecc), + .ls_cpu2_imp_abort_slv (ls_cpu2_imp_abort_slv), + .ls_cpu2_raw_eae_nonsec (ls_cpu2_raw_eae_nonsec), + .ls_cpu2_raw_eae_secure (ls_cpu2_raw_eae_secure), + .ls_cpu3_imp_abort_containable (ls_cpu3_imp_abort_containable), + .ls_cpu3_imp_abort_dec (ls_cpu3_imp_abort_dec), + .ls_cpu3_imp_abort_ecc (ls_cpu3_imp_abort_ecc), + .ls_cpu3_imp_abort_slv (ls_cpu3_imp_abort_slv), + .ls_cpu3_raw_eae_nonsec (ls_cpu3_raw_eae_nonsec), + .ls_cpu3_raw_eae_secure (ls_cpu3_raw_eae_secure), + .nFIQ (nFIQ[`MAIA_CN:0]), + .nIRQ (nIRQ[`MAIA_CN:0]), + .nREI (nREI[`MAIA_CN:0]), + .nSEI (nSEI[`MAIA_CN:0]), + .nVFIQ (nVFIQ[`MAIA_CN:0]), + .nVIRQ (nVIRQ[`MAIA_CN:0]), + .nVSEI (nVSEI[`MAIA_CN:0]) + ); // uic + + maia_ck_l2 uck_l2( // outputs + .ck_gclkb0 (ck_gclkb0), + .ck_gclkb1 (ck_gclkb1), + .ck_gclkfr (ck_gclkfr), + .ck_gclkl2 (ck_gclkl2), + + // inputs + .DFTL2CLKDISABLE (DFTL2CLKDISABLE), + .DFTSE (DFTSE), + .ck_gclktl2 (ck_gclktl2), + .ck_l2_logic_clk_en (ck_l2_logic_clk_en), + .ck_l2_tbnk0_clk_en (ck_l2_tbnk0_clk_en), + .ck_l2_tbnk1_clk_en (ck_l2_tbnk1_clk_en), + .l2_reset3 (l2_reset3) + ); // uck_l2 + + maia_ck_top uck_top( // outputs + .ck_gclkt (ck_gclkt[`MAIA_CN:0]), + .ck_gclktl2 (ck_gclktl2), + + // inputs + .CLK (CLK), + .CLKEN (CLKEN), + .DFTSE (DFTSE), + .MBISTREQ (MBISTREQ) + ); // uck_top + + maia_ck_logic uck_logic( // outputs + .CPUQACCEPTn (CPUQACCEPTn[`MAIA_CN:0]), + .CPUQACTIVE (CPUQACTIVE[`MAIA_CN:0]), + .CPUQDENY (CPUQDENY[`MAIA_CN:0]), + .STANDBYWFE (STANDBYWFE[`MAIA_CN:0]), + .STANDBYWFI (STANDBYWFI[`MAIA_CN:0]), + .STANDBYWFIL2 (STANDBYWFIL2), + .WARMRSTREQ (WARMRSTREQ[`MAIA_CN:0]), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), + .ck_cpu0_commrx (ck_cpu0_commrx), + .ck_cpu0_commtx (ck_cpu0_commtx), + .ck_cpu0_crcx_clk_en_n (ck_cpu0_crcx_clk_en_n), + .ck_cpu0_crcx_clk_en_n_ic (ck_cpu0_crcx_clk_en_n_ic), + .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), + .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), + .ck_cpu0_dt_standbywfx (ck_cpu0_dt_standbywfx), + .ck_cpu0_dt_wfx_ack (ck_cpu0_dt_wfx_ack), + .ck_cpu0_event_reg (ck_cpu0_event_reg), + .ck_cpu0_l2_standbywfi (ck_cpu0_l2_standbywfi), + .ck_cpu0_l2_standbywfx (ck_cpu0_l2_standbywfx), + .ck_cpu0_ncommirq (ck_cpu0_ncommirq), + .ck_cpu0_npmuirq (ck_cpu0_npmuirq), + .ck_cpu0_poreset_status (ck_cpu0_poreset_status), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), + .ck_cpu0_wfe_ack (ck_cpu0_wfe_ack), + .ck_cpu0_wfi_ack (ck_cpu0_wfi_ack), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), + .ck_cpu1_commrx (ck_cpu1_commrx), + .ck_cpu1_commtx (ck_cpu1_commtx), + .ck_cpu1_crcx_clk_en_n (ck_cpu1_crcx_clk_en_n), + .ck_cpu1_crcx_clk_en_n_ic (ck_cpu1_crcx_clk_en_n_ic), + .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), + .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), + .ck_cpu1_dt_standbywfx (ck_cpu1_dt_standbywfx), + .ck_cpu1_dt_wfx_ack (ck_cpu1_dt_wfx_ack), + .ck_cpu1_event_reg (ck_cpu1_event_reg), + .ck_cpu1_l2_standbywfi (ck_cpu1_l2_standbywfi), + .ck_cpu1_l2_standbywfx (ck_cpu1_l2_standbywfx), + .ck_cpu1_ncommirq (ck_cpu1_ncommirq), + .ck_cpu1_npmuirq (ck_cpu1_npmuirq), + .ck_cpu1_poreset_status (ck_cpu1_poreset_status), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), + .ck_cpu1_wfe_ack (ck_cpu1_wfe_ack), + .ck_cpu1_wfi_ack (ck_cpu1_wfi_ack), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), + .ck_cpu2_commrx (ck_cpu2_commrx), + .ck_cpu2_commtx (ck_cpu2_commtx), + .ck_cpu2_crcx_clk_en_n (ck_cpu2_crcx_clk_en_n), + .ck_cpu2_crcx_clk_en_n_ic (ck_cpu2_crcx_clk_en_n_ic), + .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), + .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), + .ck_cpu2_dt_standbywfx (ck_cpu2_dt_standbywfx), + .ck_cpu2_dt_wfx_ack (ck_cpu2_dt_wfx_ack), + .ck_cpu2_event_reg (ck_cpu2_event_reg), + .ck_cpu2_l2_standbywfi (ck_cpu2_l2_standbywfi), + .ck_cpu2_l2_standbywfx (ck_cpu2_l2_standbywfx), + .ck_cpu2_ncommirq (ck_cpu2_ncommirq), + .ck_cpu2_npmuirq (ck_cpu2_npmuirq), + .ck_cpu2_poreset_status (ck_cpu2_poreset_status), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), + .ck_cpu2_wfe_ack (ck_cpu2_wfe_ack), + .ck_cpu2_wfi_ack (ck_cpu2_wfi_ack), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), + .ck_cpu3_commrx (ck_cpu3_commrx), + .ck_cpu3_commtx (ck_cpu3_commtx), + .ck_cpu3_crcx_clk_en_n (ck_cpu3_crcx_clk_en_n), + .ck_cpu3_crcx_clk_en_n_ic (ck_cpu3_crcx_clk_en_n_ic), + .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), + .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), + .ck_cpu3_dt_standbywfx (ck_cpu3_dt_standbywfx), + .ck_cpu3_dt_wfx_ack (ck_cpu3_dt_wfx_ack), + .ck_cpu3_event_reg (ck_cpu3_event_reg), + .ck_cpu3_l2_standbywfi (ck_cpu3_l2_standbywfi), + .ck_cpu3_l2_standbywfx (ck_cpu3_l2_standbywfx), + .ck_cpu3_ncommirq (ck_cpu3_ncommirq), + .ck_cpu3_npmuirq (ck_cpu3_npmuirq), + .ck_cpu3_poreset_status (ck_cpu3_poreset_status), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), + .ck_cpu3_wfe_ack (ck_cpu3_wfe_ack), + .ck_cpu3_wfi_ack (ck_cpu3_wfi_ack), + .ck_dt_cpu0_coredbg_in_reset_gclk (ck_dt_cpu0_coredbg_in_reset_gclk), + .ck_dt_cpu0_cti_trigin_1to0_gclk (ck_dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu0_et_oslock_gclk (ck_dt_cpu0_et_oslock_gclk), + .ck_dt_cpu0_hlt_dbgevt_ok_gclk (ck_dt_cpu0_hlt_dbgevt_ok_gclk), + .ck_dt_cpu0_os_double_lock_gclk (ck_dt_cpu0_os_double_lock_gclk), + .ck_dt_cpu0_pmusnapshot_ack_gclk (ck_dt_cpu0_pmusnapshot_ack_gclk), + .ck_dt_cpu0_wfx_dbg_req_gclk (ck_dt_cpu0_wfx_dbg_req_gclk), + .ck_dt_cpu1_coredbg_in_reset_gclk (ck_dt_cpu1_coredbg_in_reset_gclk), + .ck_dt_cpu1_cti_trigin_1to0_gclk (ck_dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu1_et_oslock_gclk (ck_dt_cpu1_et_oslock_gclk), + .ck_dt_cpu1_hlt_dbgevt_ok_gclk (ck_dt_cpu1_hlt_dbgevt_ok_gclk), + .ck_dt_cpu1_os_double_lock_gclk (ck_dt_cpu1_os_double_lock_gclk), + .ck_dt_cpu1_pmusnapshot_ack_gclk (ck_dt_cpu1_pmusnapshot_ack_gclk), + .ck_dt_cpu1_wfx_dbg_req_gclk (ck_dt_cpu1_wfx_dbg_req_gclk), + .ck_dt_cpu2_coredbg_in_reset_gclk (ck_dt_cpu2_coredbg_in_reset_gclk), + .ck_dt_cpu2_cti_trigin_1to0_gclk (ck_dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu2_et_oslock_gclk (ck_dt_cpu2_et_oslock_gclk), + .ck_dt_cpu2_hlt_dbgevt_ok_gclk (ck_dt_cpu2_hlt_dbgevt_ok_gclk), + .ck_dt_cpu2_os_double_lock_gclk (ck_dt_cpu2_os_double_lock_gclk), + .ck_dt_cpu2_pmusnapshot_ack_gclk (ck_dt_cpu2_pmusnapshot_ack_gclk), + .ck_dt_cpu2_wfx_dbg_req_gclk (ck_dt_cpu2_wfx_dbg_req_gclk), + .ck_dt_cpu3_coredbg_in_reset_gclk (ck_dt_cpu3_coredbg_in_reset_gclk), + .ck_dt_cpu3_cti_trigin_1to0_gclk (ck_dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .ck_dt_cpu3_et_oslock_gclk (ck_dt_cpu3_et_oslock_gclk), + .ck_dt_cpu3_hlt_dbgevt_ok_gclk (ck_dt_cpu3_hlt_dbgevt_ok_gclk), + .ck_dt_cpu3_os_double_lock_gclk (ck_dt_cpu3_os_double_lock_gclk), + .ck_dt_cpu3_pmusnapshot_ack_gclk (ck_dt_cpu3_pmusnapshot_ack_gclk), + .ck_dt_cpu3_wfx_dbg_req_gclk (ck_dt_cpu3_wfx_dbg_req_gclk), + .ck_l2_ace_inactive (ck_l2_ace_inactive), + .ck_l2_acp_inactive (ck_l2_acp_inactive), + .ck_l2_sky_link_deactivate (ck_l2_sky_link_deactivate), + + // inputs + .ACINACTM (SINACT), + .AINACTS (AINACTS), + .CPUQREQn (CPUQREQn[`MAIA_CN:0]), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .ck_gclkfr (ck_gclkfr), + .clrexmon_c1 (clrexmon_c1), + .commrx_cpu0_i (commrx_cpu0_i), + .commrx_cpu1_i (commrx_cpu1_i), + .commrx_cpu2_i (commrx_cpu2_i), + .commrx_cpu3_i (commrx_cpu3_i), + .commtx_cpu0_i (commtx_cpu0_i), + .commtx_cpu1_i (commtx_cpu1_i), + .commtx_cpu2_i (commtx_cpu2_i), + .commtx_cpu3_i (commtx_cpu3_i), + .dbgnopwrdwn_cpu0_i (dbgnopwrdwn_cpu0_i), + .dbgnopwrdwn_cpu1_i (dbgnopwrdwn_cpu1_i), + .dbgnopwrdwn_cpu2_i (dbgnopwrdwn_cpu2_i), + .dbgnopwrdwn_cpu3_i (dbgnopwrdwn_cpu3_i), + .dbgrstreq_cpu0_i (dbgrstreq_cpu0_i), + .dbgrstreq_cpu1_i (dbgrstreq_cpu1_i), + .dbgrstreq_cpu2_i (dbgrstreq_cpu2_i), + .dbgrstreq_cpu3_i (dbgrstreq_cpu3_i), + .ds_cpu0_cpuectlr_ret (ds_cpu0_cpuectlr_ret[2:0]), + .ds_cpu0_fiq_wfe_qual (ds_cpu0_fiq_wfe_qual), + .ds_cpu0_fiq_wfi_qual (ds_cpu0_fiq_wfi_qual), + .ds_cpu0_flush (ds_cpu0_flush), + .ds_cpu0_flush_type (ds_cpu0_flush_type[5:0]), + .ds_cpu0_hcr_va (ds_cpu0_hcr_va), + .ds_cpu0_hcr_vf (ds_cpu0_hcr_vf), + .ds_cpu0_hcr_vi (ds_cpu0_hcr_vi), + .ds_cpu0_imp_abrt_wfe_qual (ds_cpu0_imp_abrt_wfe_qual), + .ds_cpu0_imp_abrt_wfi_qual (ds_cpu0_imp_abrt_wfi_qual), + .ds_cpu0_irq_wfe_qual (ds_cpu0_irq_wfe_qual), + .ds_cpu0_irq_wfi_qual (ds_cpu0_irq_wfi_qual), + .ds_cpu0_reset_req (ds_cpu0_reset_req), + .ds_cpu0_sevl_req (ds_cpu0_sevl_req), + .ds_cpu0_vfiq_wfe_qual (ds_cpu0_vfiq_wfe_qual), + .ds_cpu0_vfiq_wfi_qual (ds_cpu0_vfiq_wfi_qual), + .ds_cpu0_vimp_abrt_wfe_qual (ds_cpu0_vimp_abrt_wfe_qual), + .ds_cpu0_vimp_abrt_wfi_qual (ds_cpu0_vimp_abrt_wfi_qual), + .ds_cpu0_virq_wfe_qual (ds_cpu0_virq_wfe_qual), + .ds_cpu0_virq_wfi_qual (ds_cpu0_virq_wfi_qual), + .ds_cpu0_wfe_req (ds_cpu0_wfe_req), + .ds_cpu0_wfi_req (ds_cpu0_wfi_req), + .ds_cpu1_cpuectlr_ret (ds_cpu1_cpuectlr_ret[2:0]), + .ds_cpu1_fiq_wfe_qual (ds_cpu1_fiq_wfe_qual), + .ds_cpu1_fiq_wfi_qual (ds_cpu1_fiq_wfi_qual), + .ds_cpu1_flush (ds_cpu1_flush), + .ds_cpu1_flush_type (ds_cpu1_flush_type[5:0]), + .ds_cpu1_hcr_va (ds_cpu1_hcr_va), + .ds_cpu1_hcr_vf (ds_cpu1_hcr_vf), + .ds_cpu1_hcr_vi (ds_cpu1_hcr_vi), + .ds_cpu1_imp_abrt_wfe_qual (ds_cpu1_imp_abrt_wfe_qual), + .ds_cpu1_imp_abrt_wfi_qual (ds_cpu1_imp_abrt_wfi_qual), + .ds_cpu1_irq_wfe_qual (ds_cpu1_irq_wfe_qual), + .ds_cpu1_irq_wfi_qual (ds_cpu1_irq_wfi_qual), + .ds_cpu1_reset_req (ds_cpu1_reset_req), + .ds_cpu1_sevl_req (ds_cpu1_sevl_req), + .ds_cpu1_vfiq_wfe_qual (ds_cpu1_vfiq_wfe_qual), + .ds_cpu1_vfiq_wfi_qual (ds_cpu1_vfiq_wfi_qual), + .ds_cpu1_vimp_abrt_wfe_qual (ds_cpu1_vimp_abrt_wfe_qual), + .ds_cpu1_vimp_abrt_wfi_qual (ds_cpu1_vimp_abrt_wfi_qual), + .ds_cpu1_virq_wfe_qual (ds_cpu1_virq_wfe_qual), + .ds_cpu1_virq_wfi_qual (ds_cpu1_virq_wfi_qual), + .ds_cpu1_wfe_req (ds_cpu1_wfe_req), + .ds_cpu1_wfi_req (ds_cpu1_wfi_req), + .ds_cpu2_cpuectlr_ret (ds_cpu2_cpuectlr_ret[2:0]), + .ds_cpu2_fiq_wfe_qual (ds_cpu2_fiq_wfe_qual), + .ds_cpu2_fiq_wfi_qual (ds_cpu2_fiq_wfi_qual), + .ds_cpu2_flush (ds_cpu2_flush), + .ds_cpu2_flush_type (ds_cpu2_flush_type[5:0]), + .ds_cpu2_hcr_va (ds_cpu2_hcr_va), + .ds_cpu2_hcr_vf (ds_cpu2_hcr_vf), + .ds_cpu2_hcr_vi (ds_cpu2_hcr_vi), + .ds_cpu2_imp_abrt_wfe_qual (ds_cpu2_imp_abrt_wfe_qual), + .ds_cpu2_imp_abrt_wfi_qual (ds_cpu2_imp_abrt_wfi_qual), + .ds_cpu2_irq_wfe_qual (ds_cpu2_irq_wfe_qual), + .ds_cpu2_irq_wfi_qual (ds_cpu2_irq_wfi_qual), + .ds_cpu2_reset_req (ds_cpu2_reset_req), + .ds_cpu2_sevl_req (ds_cpu2_sevl_req), + .ds_cpu2_vfiq_wfe_qual (ds_cpu2_vfiq_wfe_qual), + .ds_cpu2_vfiq_wfi_qual (ds_cpu2_vfiq_wfi_qual), + .ds_cpu2_vimp_abrt_wfe_qual (ds_cpu2_vimp_abrt_wfe_qual), + .ds_cpu2_vimp_abrt_wfi_qual (ds_cpu2_vimp_abrt_wfi_qual), + .ds_cpu2_virq_wfe_qual (ds_cpu2_virq_wfe_qual), + .ds_cpu2_virq_wfi_qual (ds_cpu2_virq_wfi_qual), + .ds_cpu2_wfe_req (ds_cpu2_wfe_req), + .ds_cpu2_wfi_req (ds_cpu2_wfi_req), + .ds_cpu3_cpuectlr_ret (ds_cpu3_cpuectlr_ret[2:0]), + .ds_cpu3_fiq_wfe_qual (ds_cpu3_fiq_wfe_qual), + .ds_cpu3_fiq_wfi_qual (ds_cpu3_fiq_wfi_qual), + .ds_cpu3_flush (ds_cpu3_flush), + .ds_cpu3_flush_type (ds_cpu3_flush_type[5:0]), + .ds_cpu3_hcr_va (ds_cpu3_hcr_va), + .ds_cpu3_hcr_vf (ds_cpu3_hcr_vf), + .ds_cpu3_hcr_vi (ds_cpu3_hcr_vi), + .ds_cpu3_imp_abrt_wfe_qual (ds_cpu3_imp_abrt_wfe_qual), + .ds_cpu3_imp_abrt_wfi_qual (ds_cpu3_imp_abrt_wfi_qual), + .ds_cpu3_irq_wfe_qual (ds_cpu3_irq_wfe_qual), + .ds_cpu3_irq_wfi_qual (ds_cpu3_irq_wfi_qual), + .ds_cpu3_reset_req (ds_cpu3_reset_req), + .ds_cpu3_sevl_req (ds_cpu3_sevl_req), + .ds_cpu3_vfiq_wfe_qual (ds_cpu3_vfiq_wfe_qual), + .ds_cpu3_vfiq_wfi_qual (ds_cpu3_vfiq_wfi_qual), + .ds_cpu3_vimp_abrt_wfe_qual (ds_cpu3_vimp_abrt_wfe_qual), + .ds_cpu3_vimp_abrt_wfi_qual (ds_cpu3_vimp_abrt_wfi_qual), + .ds_cpu3_virq_wfe_qual (ds_cpu3_virq_wfe_qual), + .ds_cpu3_virq_wfi_qual (ds_cpu3_virq_wfi_qual), + .ds_cpu3_wfe_req (ds_cpu3_wfe_req), + .ds_cpu3_wfi_req (ds_cpu3_wfi_req), + .dt_cpu0_apb_active_pclk (dt_cpu0_apb_active_pclk), + .dt_cpu0_coredbg_in_reset_gclk (dt_cpu0_coredbg_in_reset_gclk), + .dt_cpu0_cti_trigin_1to0_gclk (dt_cpu0_cti_trigin_1to0_gclk[1:0]), + .dt_cpu0_et_oslock_gclk (dt_cpu0_et_oslock_gclk), + .dt_cpu0_hlt_dbgevt_ok_gclk (dt_cpu0_hlt_dbgevt_ok_gclk), + .dt_cpu0_os_double_lock_gclk (dt_cpu0_os_double_lock_gclk), + .dt_cpu0_pmusnapshot_ack_gclk (dt_cpu0_pmusnapshot_ack_gclk), + .dt_cpu0_poreset_status_ack_pclk (dt_cpu0_poreset_status_ack_pclk), + .dt_cpu0_wfx_dbg_req_gclk (dt_cpu0_wfx_dbg_req_gclk), + .dt_cpu0_wfx_wakeup_pclk (dt_cpu0_wfx_wakeup_pclk), + .dt_cpu1_apb_active_pclk (dt_cpu1_apb_active_pclk), + .dt_cpu1_coredbg_in_reset_gclk (dt_cpu1_coredbg_in_reset_gclk), + .dt_cpu1_cti_trigin_1to0_gclk (dt_cpu1_cti_trigin_1to0_gclk[1:0]), + .dt_cpu1_et_oslock_gclk (dt_cpu1_et_oslock_gclk), + .dt_cpu1_hlt_dbgevt_ok_gclk (dt_cpu1_hlt_dbgevt_ok_gclk), + .dt_cpu1_os_double_lock_gclk (dt_cpu1_os_double_lock_gclk), + .dt_cpu1_pmusnapshot_ack_gclk (dt_cpu1_pmusnapshot_ack_gclk), + .dt_cpu1_poreset_status_ack_pclk (dt_cpu1_poreset_status_ack_pclk), + .dt_cpu1_wfx_dbg_req_gclk (dt_cpu1_wfx_dbg_req_gclk), + .dt_cpu1_wfx_wakeup_pclk (dt_cpu1_wfx_wakeup_pclk), + .dt_cpu2_apb_active_pclk (dt_cpu2_apb_active_pclk), + .dt_cpu2_coredbg_in_reset_gclk (dt_cpu2_coredbg_in_reset_gclk), + .dt_cpu2_cti_trigin_1to0_gclk (dt_cpu2_cti_trigin_1to0_gclk[1:0]), + .dt_cpu2_et_oslock_gclk (dt_cpu2_et_oslock_gclk), + .dt_cpu2_hlt_dbgevt_ok_gclk (dt_cpu2_hlt_dbgevt_ok_gclk), + .dt_cpu2_os_double_lock_gclk (dt_cpu2_os_double_lock_gclk), + .dt_cpu2_pmusnapshot_ack_gclk (dt_cpu2_pmusnapshot_ack_gclk), + .dt_cpu2_poreset_status_ack_pclk (dt_cpu2_poreset_status_ack_pclk), + .dt_cpu2_wfx_dbg_req_gclk (dt_cpu2_wfx_dbg_req_gclk), + .dt_cpu2_wfx_wakeup_pclk (dt_cpu2_wfx_wakeup_pclk), + .dt_cpu3_apb_active_pclk (dt_cpu3_apb_active_pclk), + .dt_cpu3_coredbg_in_reset_gclk (dt_cpu3_coredbg_in_reset_gclk), + .dt_cpu3_cti_trigin_1to0_gclk (dt_cpu3_cti_trigin_1to0_gclk[1:0]), + .dt_cpu3_et_oslock_gclk (dt_cpu3_et_oslock_gclk), + .dt_cpu3_hlt_dbgevt_ok_gclk (dt_cpu3_hlt_dbgevt_ok_gclk), + .dt_cpu3_os_double_lock_gclk (dt_cpu3_os_double_lock_gclk), + .dt_cpu3_pmusnapshot_ack_gclk (dt_cpu3_pmusnapshot_ack_gclk), + .dt_cpu3_poreset_status_ack_pclk (dt_cpu3_poreset_status_ack_pclk), + .dt_cpu3_wfx_dbg_req_gclk (dt_cpu3_wfx_dbg_req_gclk), + .dt_cpu3_wfx_wakeup_pclk (dt_cpu3_wfx_wakeup_pclk), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .l2_actlr_ncpu_rcg_enable (l2_actlr_ncpu_rcg_enable), + .l2_cpu0_snp_active (l2_cpu0_snp_active), + .l2_cpu1_snp_active (l2_cpu1_snp_active), + .l2_cpu2_snp_active (l2_cpu2_snp_active), + .l2_cpu3_snp_active (l2_cpu3_snp_active), + .l2_idle (l2_idle), + .l2_mbist1_en_b1 (l2_mbist1_en_b1[`MAIA_CN:0]), + .l2_reset3 (l2_reset3), + .l2_sky_link_stopped (l2_sky_link_stopped), + .ls_cpu0_clrexmon (ls_cpu0_clrexmon), + .ls_cpu1_clrexmon (ls_cpu1_clrexmon), + .ls_cpu2_clrexmon (ls_cpu2_clrexmon), + .ls_cpu3_clrexmon (ls_cpu3_clrexmon), + .nCORERESET (nCORERESET[`MAIA_CN:0]), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nL2RESET (nL2RESET), + .nMBISTRESET (nMBISTRESET), + .ncommirq_cpu0_i (ncommirq_cpu0_i), + .ncommirq_cpu1_i (ncommirq_cpu1_i), + .ncommirq_cpu2_i (ncommirq_cpu2_i), + .ncommirq_cpu3_i (ncommirq_cpu3_i), + .npmuirq_cpu0_i (npmuirq_cpu0_i), + .npmuirq_cpu1_i (npmuirq_cpu1_i), + .npmuirq_cpu2_i (npmuirq_cpu2_i), + .npmuirq_cpu3_i (npmuirq_cpu3_i), + .tm_cntpct_q (tm_cntpct_q[8:0]), + .tm_cpu0_event_sev (tm_cpu0_event_sev), + .tm_cpu1_event_sev (tm_cpu1_event_sev), + .tm_cpu2_event_sev (tm_cpu2_event_sev), + .tm_cpu3_event_sev (tm_cpu3_event_sev) + ); // uck_logic + + maia_cpu_io ucpu_io( // outputs + .aa64naa32_cpu0_o (aa64naa32_cpu0_o), + .aa64naa32_cpu1_o (aa64naa32_cpu1_o), + .aa64naa32_cpu2_o (aa64naa32_cpu2_o), + .aa64naa32_cpu3_o (aa64naa32_cpu3_o), + .cfgend_cpu0_o (cfgend_cpu0_o), + .cfgend_cpu1_o (cfgend_cpu1_o), + .cfgend_cpu2_o (cfgend_cpu2_o), + .cfgend_cpu3_o (cfgend_cpu3_o), + .cfgte_cpu0_o (cfgte_cpu0_o), + .cfgte_cpu1_o (cfgte_cpu1_o), + .cfgte_cpu2_o (cfgte_cpu2_o), + .cfgte_cpu3_o (cfgte_cpu3_o), + .clrexmon_c1 (clrexmon_c1), + .clrexmonack_o (CLREXMONACK), + .clusteridaff1_cpu0_o (clusteridaff1_cpu0_o[7:0]), + .clusteridaff1_cpu1_o (clusteridaff1_cpu1_o[7:0]), + .clusteridaff1_cpu2_o (clusteridaff1_cpu2_o[7:0]), + .clusteridaff1_cpu3_o (clusteridaff1_cpu3_o[7:0]), + .clusteridaff2_cpu0_o (clusteridaff2_cpu0_o[7:0]), + .clusteridaff2_cpu1_o (clusteridaff2_cpu1_o[7:0]), + .clusteridaff2_cpu2_o (clusteridaff2_cpu2_o[7:0]), + .clusteridaff2_cpu3_o (clusteridaff2_cpu3_o[7:0]), + .commrx_o (COMMRX[`MAIA_CN:0]), + .commtx_o (COMMTX[`MAIA_CN:0]), + .cp15sdisable_cpu0_o (cp15sdisable_cpu0_o), + .cp15sdisable_cpu1_o (cp15sdisable_cpu1_o), + .cp15sdisable_cpu2_o (cp15sdisable_cpu2_o), + .cp15sdisable_cpu3_o (cp15sdisable_cpu3_o), + .cpuid_cpu0_o (cpuid_cpu0_o[1:0]), + .cpuid_cpu1_o (cpuid_cpu1_o[1:0]), + .cpuid_cpu2_o (cpuid_cpu2_o[1:0]), + .cpuid_cpu3_o (cpuid_cpu3_o[1:0]), + .cryptodisable_cpu0_o (cryptodisable_cpu0_o), + .cryptodisable_cpu1_o (cryptodisable_cpu1_o), + .cryptodisable_cpu2_o (cryptodisable_cpu2_o), + .cryptodisable_cpu3_o (cryptodisable_cpu3_o), + .dbgack_o (DBGACK[`MAIA_CN:0]), + .dbgen_cpu0_o (dbgen_cpu0_o), + .dbgen_cpu1_o (dbgen_cpu1_o), + .dbgen_cpu2_o (dbgen_cpu2_o), + .dbgen_cpu3_o (dbgen_cpu3_o), + .dbgl1rstdisable_cpu0_o (dbgl1rstdisable_cpu0_o), + .dbgl1rstdisable_cpu1_o (dbgl1rstdisable_cpu1_o), + .dbgl1rstdisable_cpu2_o (dbgl1rstdisable_cpu2_o), + .dbgl1rstdisable_cpu3_o (dbgl1rstdisable_cpu3_o), + .dbgnopwrdwn_o (DBGNOPWRDWN[`MAIA_CN:0]), + .dbgromaddr_cpu0_o (dbgromaddr_cpu0_o[43:12]), + .dbgromaddr_cpu1_o (dbgromaddr_cpu1_o[43:12]), + .dbgromaddr_cpu2_o (dbgromaddr_cpu2_o[43:12]), + .dbgromaddr_cpu3_o (dbgromaddr_cpu3_o[43:12]), + .dbgromaddrv_cpu0_o (dbgromaddrv_cpu0_o), + .dbgromaddrv_cpu1_o (dbgromaddrv_cpu1_o), + .dbgromaddrv_cpu2_o (dbgromaddrv_cpu2_o), + .dbgromaddrv_cpu3_o (dbgromaddrv_cpu3_o), + .dbgrstreq_o (DBGRSTREQ[`MAIA_CN:0]), + .dftcrclkdisable_cpu0_o (dftcrclkdisable_cpu0_o), + .dftcrclkdisable_cpu1_o (dftcrclkdisable_cpu1_o), + .dftcrclkdisable_cpu2_o (dftcrclkdisable_cpu2_o), + .dftcrclkdisable_cpu3_o (dftcrclkdisable_cpu3_o), + .dftramhold_cpu0_o (dftramhold_cpu0_o), + .dftramhold_cpu1_o (dftramhold_cpu1_o), + .dftramhold_cpu2_o (dftramhold_cpu2_o), + .dftramhold_cpu3_o (dftramhold_cpu3_o), + .dftrstdisable_cpu0_o (dftrstdisable_cpu0_o), + .dftrstdisable_cpu1_o (dftrstdisable_cpu1_o), + .dftrstdisable_cpu2_o (dftrstdisable_cpu2_o), + .dftrstdisable_cpu3_o (dftrstdisable_cpu3_o), + .dftse_cpu0_o (dftse_cpu0_o), + .dftse_cpu1_o (dftse_cpu1_o), + .dftse_cpu2_o (dftse_cpu2_o), + .dftse_cpu3_o (dftse_cpu3_o), + .eventi_sev (eventi_sev), + .evento_o (EVENTO), + .giccdisable_cpu0_o (giccdisable_cpu0_o), + .giccdisable_cpu1_o (giccdisable_cpu1_o), + .giccdisable_cpu2_o (giccdisable_cpu2_o), + .giccdisable_cpu3_o (giccdisable_cpu3_o), + .ncommirq_o (nCOMMIRQ[`MAIA_CN:0]), + .ncorereset_cpu0_o (ncorereset_cpu0_o), + .ncorereset_cpu1_o (ncorereset_cpu1_o), + .ncorereset_cpu2_o (ncorereset_cpu2_o), + .ncorereset_cpu3_o (ncorereset_cpu3_o), + .ncpuporeset_cpu0_o (ncpuporeset_cpu0_o), + .ncpuporeset_cpu1_o (ncpuporeset_cpu1_o), + .ncpuporeset_cpu2_o (ncpuporeset_cpu2_o), + .ncpuporeset_cpu3_o (ncpuporeset_cpu3_o), + .niden_cpu0_o (niden_cpu0_o), + .niden_cpu1_o (niden_cpu1_o), + .niden_cpu2_o (niden_cpu2_o), + .niden_cpu3_o (niden_cpu3_o), + .nmbistreset_cpu0_o (nmbistreset_cpu0_o), + .nmbistreset_cpu1_o (nmbistreset_cpu1_o), + .nmbistreset_cpu2_o (nmbistreset_cpu2_o), + .nmbistreset_cpu3_o (nmbistreset_cpu3_o), + .npmuirq_o (nPMUIRQ[`MAIA_CN:0]), + .pmuevent0_o (PMUEVENT0[24:0]), + .pmuevent1_o (PMUEVENT1[24:0]), + .pmuevent2_o (PMUEVENT2[24:0]), + .pmuevent3_o (PMUEVENT3[24:0]), + .rvbaraddr_cpu0_o (rvbaraddr_cpu0_o[43:2]), + .rvbaraddr_cpu1_o (rvbaraddr_cpu1_o[43:2]), + .rvbaraddr_cpu2_o (rvbaraddr_cpu2_o[43:2]), + .rvbaraddr_cpu3_o (rvbaraddr_cpu3_o[43:2]), + .smpen_o (SMPEN[`MAIA_CN:0]), + .spiden_cpu0_o (spiden_cpu0_o), + .spiden_cpu1_o (spiden_cpu1_o), + .spiden_cpu2_o (spiden_cpu2_o), + .spiden_cpu3_o (spiden_cpu3_o), + .spniden_cpu0_o (spniden_cpu0_o), + .spniden_cpu1_o (spniden_cpu1_o), + .spniden_cpu2_o (spniden_cpu2_o), + .spniden_cpu3_o (spniden_cpu3_o), + .vinithi_cpu0_o (vinithi_cpu0_o), + .vinithi_cpu1_o (vinithi_cpu1_o), + .vinithi_cpu2_o (vinithi_cpu2_o), + .vinithi_cpu3_o (vinithi_cpu3_o), + + // inputs + .aa64naa32_i (AA64nAA32[`MAIA_CN:0]), + .cfgend_i (CFGEND[`MAIA_CN:0]), + .cfgte_i (CFGTE[`MAIA_CN:0]), + .ck_cpu0_areset_l2cpu (ck_cpu0_areset_l2cpu), + .ck_cpu0_areset_l2dt (ck_cpu0_areset_l2dt), + .ck_cpu0_commrx (ck_cpu0_commrx), + .ck_cpu0_commtx (ck_cpu0_commtx), + .ck_cpu0_dbgnopwrdwn (ck_cpu0_dbgnopwrdwn), + .ck_cpu0_dbgrstreq (ck_cpu0_dbgrstreq), + .ck_cpu0_ncommirq (ck_cpu0_ncommirq), + .ck_cpu0_npmuirq (ck_cpu0_npmuirq), + .ck_cpu0_reset1_n_l2cpu (ck_cpu0_reset1_n_l2cpu), + .ck_cpu0_reset1_n_l2dt (ck_cpu0_reset1_n_l2dt), + .ck_cpu1_areset_l2cpu (ck_cpu1_areset_l2cpu), + .ck_cpu1_areset_l2dt (ck_cpu1_areset_l2dt), + .ck_cpu1_commrx (ck_cpu1_commrx), + .ck_cpu1_commtx (ck_cpu1_commtx), + .ck_cpu1_dbgnopwrdwn (ck_cpu1_dbgnopwrdwn), + .ck_cpu1_dbgrstreq (ck_cpu1_dbgrstreq), + .ck_cpu1_ncommirq (ck_cpu1_ncommirq), + .ck_cpu1_npmuirq (ck_cpu1_npmuirq), + .ck_cpu1_reset1_n_l2cpu (ck_cpu1_reset1_n_l2cpu), + .ck_cpu1_reset1_n_l2dt (ck_cpu1_reset1_n_l2dt), + .ck_cpu2_areset_l2cpu (ck_cpu2_areset_l2cpu), + .ck_cpu2_areset_l2dt (ck_cpu2_areset_l2dt), + .ck_cpu2_commrx (ck_cpu2_commrx), + .ck_cpu2_commtx (ck_cpu2_commtx), + .ck_cpu2_dbgnopwrdwn (ck_cpu2_dbgnopwrdwn), + .ck_cpu2_dbgrstreq (ck_cpu2_dbgrstreq), + .ck_cpu2_ncommirq (ck_cpu2_ncommirq), + .ck_cpu2_npmuirq (ck_cpu2_npmuirq), + .ck_cpu2_reset1_n_l2cpu (ck_cpu2_reset1_n_l2cpu), + .ck_cpu2_reset1_n_l2dt (ck_cpu2_reset1_n_l2dt), + .ck_cpu3_areset_l2cpu (ck_cpu3_areset_l2cpu), + .ck_cpu3_areset_l2dt (ck_cpu3_areset_l2dt), + .ck_cpu3_commrx (ck_cpu3_commrx), + .ck_cpu3_commtx (ck_cpu3_commtx), + .ck_cpu3_dbgnopwrdwn (ck_cpu3_dbgnopwrdwn), + .ck_cpu3_dbgrstreq (ck_cpu3_dbgrstreq), + .ck_cpu3_ncommirq (ck_cpu3_ncommirq), + .ck_cpu3_npmuirq (ck_cpu3_npmuirq), + .ck_cpu3_reset1_n_l2cpu (ck_cpu3_reset1_n_l2cpu), + .ck_cpu3_reset1_n_l2dt (ck_cpu3_reset1_n_l2dt), + .ck_gclkfr (ck_gclkfr), + .clrexmonreq_i (CLREXMONREQ), + .clusteridaff1_i (CLUSTERIDAFF1[7:0]), + .clusteridaff2_i (CLUSTERIDAFF2[7:0]), + .cp15sdisable_i (CP15SDISABLE[`MAIA_CN:0]), + .cryptodisable_i (CRYPTODISABLE[`MAIA_CN:0]), + .dbgack_cpu0_i (dbgack_cpu0_i), + .dbgack_cpu1_i (dbgack_cpu1_i), + .dbgack_cpu2_i (dbgack_cpu2_i), + .dbgack_cpu3_i (dbgack_cpu3_i), + .dbgen_i (DBGEN[`MAIA_CN:0]), + .dbgl1rstdisable_i (DBGL1RSTDISABLE), + .dbgromaddr_i (DBGROMADDR[43:12]), + .dbgromaddrv_i (DBGROMADDRV), + .dftcrclkdisable_i (DFTCRCLKDISABLE[`MAIA_CN:0]), + .dftramhold_i (DFTRAMHOLD), + .dftrstdisable_i (DFTRSTDISABLE), + .dftse_i (DFTSE), + .ds_cpu0_cpuectlr_smp (ds_cpu0_cpuectlr_smp), + .ds_cpu0_sev_req (ds_cpu0_sev_req), + .ds_cpu1_cpuectlr_smp (ds_cpu1_cpuectlr_smp), + .ds_cpu1_sev_req (ds_cpu1_sev_req), + .ds_cpu2_cpuectlr_smp (ds_cpu2_cpuectlr_smp), + .ds_cpu2_sev_req (ds_cpu2_sev_req), + .ds_cpu3_cpuectlr_smp (ds_cpu3_cpuectlr_smp), + .ds_cpu3_sev_req (ds_cpu3_sev_req), + .eventi_i (EVENTI), + .giccdisable_i (GICCDISABLE), + .l2_reset3 (l2_reset3), + .ncorereset_i (nCORERESET[`MAIA_CN:0]), + .ncpuporeset_i (nCPUPORESET[`MAIA_CN:0]), + .niden_i (NIDEN[`MAIA_CN:0]), + .nmbistreset_i (nMBISTRESET), + .pm_export_cpu0_i (pm_export_cpu0_i), + .pm_export_cpu1_i (pm_export_cpu1_i), + .pm_export_cpu2_i (pm_export_cpu2_i), + .pm_export_cpu3_i (pm_export_cpu3_i), + .pmuevent_cpu0_i (pmuevent_cpu0_i[24:0]), + .pmuevent_cpu1_i (pmuevent_cpu1_i[24:0]), + .pmuevent_cpu2_i (pmuevent_cpu2_i[24:0]), + .pmuevent_cpu3_i (pmuevent_cpu3_i[24:0]), + .rvbaraddr0_i (RVBARADDR0[43:2]), + .rvbaraddr1_i (RVBARADDR1[43:2]), + .rvbaraddr2_i (RVBARADDR2[43:2]), + .rvbaraddr3_i (RVBARADDR3[43:2]), + .spiden_i (SPIDEN[`MAIA_CN:0]), + .spniden_i (SPNIDEN[`MAIA_CN:0]), + .vinithi_i (VINITHI[`MAIA_CN:0]) + ); // ucpu_io + + maia_dt_sb udt_sb( // outputs + .afreadym0_o (AFREADYM0), + .afreadym1_o (AFREADYM1), + .afreadym2_o (AFREADYM2), + .afreadym3_o (AFREADYM3), + .afvalidm_cpu0_o (afvalidm_cpu0_o), + .afvalidm_cpu1_o (afvalidm_cpu1_o), + .afvalidm_cpu2_o (afvalidm_cpu2_o), + .afvalidm_cpu3_o (afvalidm_cpu3_o), + .atbytesm0_o (ATBYTESM0[1:0]), + .atbytesm1_o (ATBYTESM1[1:0]), + .atbytesm2_o (ATBYTESM2[1:0]), + .atbytesm3_o (ATBYTESM3[1:0]), + .atclken_cpu0_o (atclken_cpu0_o), + .atclken_cpu1_o (atclken_cpu1_o), + .atclken_cpu2_o (atclken_cpu2_o), + .atclken_cpu3_o (atclken_cpu3_o), + .atdatam0_o (ATDATAM0[31:0]), + .atdatam1_o (ATDATAM1[31:0]), + .atdatam2_o (ATDATAM2[31:0]), + .atdatam3_o (ATDATAM3[31:0]), + .atidm0_o (ATIDM0[6:0]), + .atidm1_o (ATIDM1[6:0]), + .atidm2_o (ATIDM2[6:0]), + .atidm3_o (ATIDM3[6:0]), + .atreadym_cpu0_o (atreadym_cpu0_o), + .atreadym_cpu1_o (atreadym_cpu1_o), + .atreadym_cpu2_o (atreadym_cpu2_o), + .atreadym_cpu3_o (atreadym_cpu3_o), + .atvalidm0_o (ATVALIDM0), + .atvalidm1_o (ATVALIDM1), + .atvalidm2_o (ATVALIDM2), + .atvalidm3_o (ATVALIDM3), + .syncreqm_cpu0_o (syncreqm_cpu0_o), + .syncreqm_cpu1_o (syncreqm_cpu1_o), + .syncreqm_cpu2_o (syncreqm_cpu2_o), + .syncreqm_cpu3_o (syncreqm_cpu3_o), + .tsvalueb_cpu0_o (tsvalueb_cpu0_o[63:0]), + .tsvalueb_cpu1_o (tsvalueb_cpu1_o[63:0]), + .tsvalueb_cpu2_o (tsvalueb_cpu2_o[63:0]), + .tsvalueb_cpu3_o (tsvalueb_cpu3_o[63:0]), + + // inputs + .DFTMCPHOLD (DFTMCPHOLD), + .DFTRSTDISABLE (DFTRSTDISABLE), + .DFTSE (DFTSE), + .TSVALUEB (TSVALUEB[63:0]), + .afreadym_cpu0_i (afreadym_cpu0_i), + .afreadym_cpu1_i (afreadym_cpu1_i), + .afreadym_cpu2_i (afreadym_cpu2_i), + .afreadym_cpu3_i (afreadym_cpu3_i), + .afvalidm0_i (AFVALIDM0), + .afvalidm1_i (AFVALIDM1), + .afvalidm2_i (AFVALIDM2), + .afvalidm3_i (AFVALIDM3), + .atbytesm_cpu0_i (atbytesm_cpu0_i[1:0]), + .atbytesm_cpu1_i (atbytesm_cpu1_i[1:0]), + .atbytesm_cpu2_i (atbytesm_cpu2_i[1:0]), + .atbytesm_cpu3_i (atbytesm_cpu3_i[1:0]), + .atclken_i (ATCLKEN), + .atdatam_cpu0_i (atdatam_cpu0_i[31:0]), + .atdatam_cpu1_i (atdatam_cpu1_i[31:0]), + .atdatam_cpu2_i (atdatam_cpu2_i[31:0]), + .atdatam_cpu3_i (atdatam_cpu3_i[31:0]), + .atidm_cpu0_i (atidm_cpu0_i[6:0]), + .atidm_cpu1_i (atidm_cpu1_i[6:0]), + .atidm_cpu2_i (atidm_cpu2_i[6:0]), + .atidm_cpu3_i (atidm_cpu3_i[6:0]), + .atreadym0_i (ATREADYM0), + .atreadym1_i (ATREADYM1), + .atreadym2_i (ATREADYM2), + .atreadym3_i (ATREADYM3), + .atvalidm_cpu0_i (atvalidm_cpu0_i), + .atvalidm_cpu1_i (atvalidm_cpu1_i), + .atvalidm_cpu2_i (atvalidm_cpu2_i), + .atvalidm_cpu3_i (atvalidm_cpu3_i), + .ck_gclkfr (ck_gclkfr), + .dt_cpu0_trcauxctlr_sb_rcg_disable_pclk (dt_cpu0_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu1_trcauxctlr_sb_rcg_disable_pclk (dt_cpu1_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu2_trcauxctlr_sb_rcg_disable_pclk (dt_cpu2_trcauxctlr_sb_rcg_disable_pclk), + .dt_cpu3_trcauxctlr_sb_rcg_disable_pclk (dt_cpu3_trcauxctlr_sb_rcg_disable_pclk), + .etclken_cpu0_i (etclken_cpu0_i), + .etclken_cpu1_i (etclken_cpu1_i), + .etclken_cpu2_i (etclken_cpu2_i), + .etclken_cpu3_i (etclken_cpu3_i), + .nCPUPORESET (nCPUPORESET[`MAIA_CN:0]), + .nMBISTRESET (nMBISTRESET), + .syncreqm0_i (SYNCREQM0), + .syncreqm1_i (SYNCREQM1), + .syncreqm2_i (SYNCREQM2), + .syncreqm3_i (SYNCREQM3) + ); // udt_sb + + maia_ncpu_reg_rep uncpu_reg_rep( // outputs + .ds_cpu0_ic_aa64naa32_reg_o (ds_cpu0_ic_aa64naa32_i), + .ds_cpu0_ic_cpsr_mode_reg_o (ds_cpu0_ic_cpsr_mode_i[4:0]), + .ds_cpu0_ic_hcr_change_reg_o (ds_cpu0_ic_hcr_change_i), + .ds_cpu0_ic_sample_spr_reg_o (ds_cpu0_ic_sample_spr_i), + .ds_cpu0_ic_scr_change_reg_o (ds_cpu0_ic_scr_change_i), + .ds_cpu1_ic_aa64naa32_reg_o (ds_cpu1_ic_aa64naa32_i), + .ds_cpu1_ic_cpsr_mode_reg_o (ds_cpu1_ic_cpsr_mode_i[4:0]), + .ds_cpu1_ic_hcr_change_reg_o (ds_cpu1_ic_hcr_change_i), + .ds_cpu1_ic_sample_spr_reg_o (ds_cpu1_ic_sample_spr_i), + .ds_cpu1_ic_scr_change_reg_o (ds_cpu1_ic_scr_change_i), + .ds_cpu2_ic_aa64naa32_reg_o (ds_cpu2_ic_aa64naa32_i), + .ds_cpu2_ic_cpsr_mode_reg_o (ds_cpu2_ic_cpsr_mode_i[4:0]), + .ds_cpu2_ic_hcr_change_reg_o (ds_cpu2_ic_hcr_change_i), + .ds_cpu2_ic_sample_spr_reg_o (ds_cpu2_ic_sample_spr_i), + .ds_cpu2_ic_scr_change_reg_o (ds_cpu2_ic_scr_change_i), + .ds_cpu3_ic_aa64naa32_reg_o (ds_cpu3_ic_aa64naa32_i), + .ds_cpu3_ic_cpsr_mode_reg_o (ds_cpu3_ic_cpsr_mode_i[4:0]), + .ds_cpu3_ic_hcr_change_reg_o (ds_cpu3_ic_hcr_change_i), + .ds_cpu3_ic_sample_spr_reg_o (ds_cpu3_ic_sample_spr_i), + .ds_cpu3_ic_scr_change_reg_o (ds_cpu3_ic_scr_change_i), + .ic_block_eoi_sgi_wr_reg_o (ic_block_eoi_sgi_wr[`MAIA_CN:0]), + .ic_el_change_complete_reg_o (ic_el_change_complete[`MAIA_CN:0]), + .ic_hcr_change_complete_reg_o (ic_hcr_change_complete[`MAIA_CN:0]), + .ic_ich_el2_tall0_reg_o (ic_ich_el2_tall0[`MAIA_CN:0]), + .ic_ich_el2_tall1_reg_o (ic_ich_el2_tall1[`MAIA_CN:0]), + .ic_ich_el2_tc_reg_o (ic_ich_el2_tc[`MAIA_CN:0]), + .ic_nfiq_reg_o (ic_nfiq[`MAIA_CN:0]), + .ic_nirq_reg_o (ic_nirq[`MAIA_CN:0]), + .ic_nsei_reg_o (ic_nsei[`MAIA_CN:0]), + .ic_nvfiq_reg_o (ic_nvfiq[`MAIA_CN:0]), + .ic_nvirq_reg_o (ic_nvirq[`MAIA_CN:0]), + .ic_nvsei_reg_o (ic_nvsei[`MAIA_CN:0]), + .ic_sample_spr_reg_o (ic_sample_spr[`MAIA_CN:0]), + .ic_scr_change_complete_reg_o (ic_scr_change_complete[`MAIA_CN:0]), + .ic_sra_el1ns_en_reg_o (ic_sra_el1ns_en[`MAIA_CN:0]), + .ic_sra_el1s_en_reg_o (ic_sra_el1s_en[`MAIA_CN:0]), + .ic_sra_el2_en_reg_o (ic_sra_el2_en[`MAIA_CN:0]), + .ic_sra_el3_en_reg_o (ic_sra_el3_en[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap_reg_o (ic_sre_el1ns_hyp_trap[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap_reg_o (ic_sre_el1ns_mon_trap[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap_reg_o (ic_sre_el1s_mon_trap[`MAIA_CN:0]), + .ic_sre_el2_mon_trap_reg_o (ic_sre_el2_mon_trap[`MAIA_CN:0]), + + // inputs + .ck_gclkfr (ck_gclkfr), + .ck_reset1_n_l2 (ck_reset1_n_l2), + .ds_cpu0_ic_aa64naa32 (ds_cpu0_ic_aa64naa32), + .ds_cpu0_ic_cpsr_mode (ds_cpu0_ic_cpsr_mode[4:0]), + .ds_cpu0_ic_hcr_change (ds_cpu0_ic_hcr_change), + .ds_cpu0_ic_sample_spr (ds_cpu0_ic_sample_spr), + .ds_cpu0_ic_scr_change (ds_cpu0_ic_scr_change), + .ds_cpu1_ic_aa64naa32 (ds_cpu1_ic_aa64naa32), + .ds_cpu1_ic_cpsr_mode (ds_cpu1_ic_cpsr_mode[4:0]), + .ds_cpu1_ic_hcr_change (ds_cpu1_ic_hcr_change), + .ds_cpu1_ic_sample_spr (ds_cpu1_ic_sample_spr), + .ds_cpu1_ic_scr_change (ds_cpu1_ic_scr_change), + .ds_cpu2_ic_aa64naa32 (ds_cpu2_ic_aa64naa32), + .ds_cpu2_ic_cpsr_mode (ds_cpu2_ic_cpsr_mode[4:0]), + .ds_cpu2_ic_hcr_change (ds_cpu2_ic_hcr_change), + .ds_cpu2_ic_sample_spr (ds_cpu2_ic_sample_spr), + .ds_cpu2_ic_scr_change (ds_cpu2_ic_scr_change), + .ds_cpu3_ic_aa64naa32 (ds_cpu3_ic_aa64naa32), + .ds_cpu3_ic_cpsr_mode (ds_cpu3_ic_cpsr_mode[4:0]), + .ds_cpu3_ic_hcr_change (ds_cpu3_ic_hcr_change), + .ds_cpu3_ic_sample_spr (ds_cpu3_ic_sample_spr), + .ds_cpu3_ic_scr_change (ds_cpu3_ic_scr_change), + .ic_block_eoi_sgi_wr (ic_block_eoi_sgi_wr_o[`MAIA_CN:0]), + .ic_el_change_complete (ic_el_change_complete_o[`MAIA_CN:0]), + .ic_hcr_change_complete (ic_hcr_change_complete_o[`MAIA_CN:0]), + .ic_ich_el2_tall0 (ic_ich_el2_tall0_o[`MAIA_CN:0]), + .ic_ich_el2_tall1 (ic_ich_el2_tall1_o[`MAIA_CN:0]), + .ic_ich_el2_tc (ic_ich_el2_tc_o[`MAIA_CN:0]), + .ic_nfiq (ic_nfiq_o[`MAIA_CN:0]), + .ic_nirq (ic_nirq_o[`MAIA_CN:0]), + .ic_nsei (ic_nsei_o[`MAIA_CN:0]), + .ic_nvfiq (ic_nvfiq_o[`MAIA_CN:0]), + .ic_nvirq (ic_nvirq_o[`MAIA_CN:0]), + .ic_nvsei (ic_nvsei_o[`MAIA_CN:0]), + .ic_sample_spr (ic_sample_spr_o[`MAIA_CN:0]), + .ic_scr_change_complete (ic_scr_change_complete_o[`MAIA_CN:0]), + .ic_sra_el1ns_en (ic_sra_el1ns_en_o[`MAIA_CN:0]), + .ic_sra_el1s_en (ic_sra_el1s_en_o[`MAIA_CN:0]), + .ic_sra_el2_en (ic_sra_el2_en_o[`MAIA_CN:0]), + .ic_sra_el3_en (ic_sra_el3_en_o[`MAIA_CN:0]), + .ic_sre_el1ns_hyp_trap (ic_sre_el1ns_hyp_trap_o[`MAIA_CN:0]), + .ic_sre_el1ns_mon_trap (ic_sre_el1ns_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el1s_mon_trap (ic_sre_el1s_mon_trap_o[`MAIA_CN:0]), + .ic_sre_el2_mon_trap (ic_sre_el2_mon_trap_o[`MAIA_CN:0]) + ); // uncpu_reg_rep + +//----------------------------------------------------------------------------- +// OVL Assertions +//----------------------------------------------------------------------------- +`ifdef ARM_ASSERT_ON + `include "maia_noncpu_s_val.v" +`endif + +endmodule // maia_noncpu_s + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia_complex/verilog/maia_complex.v b/Security Algo Accelerator/logical/maia_complex/verilog/maia_complex.v new file mode 100644 index 0000000000..496b1e1872 --- /dev/null +++ b/Security Algo Accelerator/logical/maia_complex/verilog/maia_complex.v @@ -0,0 +1,2816 @@ + +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: maia_complex.v $ +// Checked In : $Date: 2014-08-29 00:16:46 -0500 (Fri, 29 Aug 2014) $ +// Revision : $Revision: 70482 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- +//# +//# Overview +//# ======== +//# +//# This is top-level interconnect layer for the Complex Execute unit. +//# + +`include "maia_header.v" + +module maia_complex( // outputs + cx_active, + cx_credit_j, + cx_credit_k, + cx_dstp_tag_ke1, + cx_dstp_tag_vld_ke1, + cx_resp_data_w1, + cx_resp_qfbit_gid_w1, + cx_resp_qfbit_vld_w1, + cx_resp_qfbit_w2, + cx_resp_tag_vld_w0, + cx_resp_tag_w0, + cx_resx_data_w2, + cx_resx_dw_w1, + cx_resx_qfbit_gid_w1, + cx_resx_qfbit_vld_w1, + cx_resx_qfbit_w2, + cx_resx_tag_vld_w1, + cx_resx_tag_w1, + cx_resy_data_w2, + cx_resy_dw_w1, + cx_resy_qfbit_gid_w1, + cx_resy_qfbit_vld_w1, + cx_resy_qfbit_w2, + cx_resy_tag_vld_w1, + cx_resy_tag_w1, + cx_resz_data_w2, + cx_resz_dw_w1, + cx_resz_qfbit_gid_w1, + cx_resz_qfbit_vld_w1, + cx_resz_qfbit_w2, + cx_resz_tag_vld_w1, + cx_resz_tag_w1, + + // inputs + ck_areset, + ck_gclkcx, + ck_reset1_n_cx, + dftrstdisable_cpu, + dftse_cpu, + ds_cx_aarch32_state, + ds_cx_aarch64_state, + ds_cx_cpuactlr_frc_cpu_rcg_active, + ds_cx_dstp_tag_jp2, + ds_cx_dstp_tag_kp2, + ds_cx_dstp_tag_vld_jp2, + ds_cx_dstp_tag_vld_kp2, + ds_cx_dstx_dw_jp2, + ds_cx_dstx_dw_kp2, + ds_cx_dstx_tag_jp2, + ds_cx_dstx_tag_kp2, + ds_cx_dstx_tag_vld_jp2, + ds_cx_dstx_tag_vld_kp2, + ds_cx_dsty_dw_jp2, + ds_cx_dsty_dw_kp2, + ds_cx_dsty_tag_jp2, + ds_cx_dsty_tag_kp2, + ds_cx_dsty_tag_vld_jp2, + ds_cx_dsty_tag_vld_kp2, + ds_cx_flush_gid, + ds_cx_flush_seq, + ds_cx_flush_u1, + ds_cx_fpscr_ahp, + ds_cx_fpscr_dn, + ds_cx_fpscr_fz, + ds_cx_fpscr_rmode, + ds_cx_gid_jp2, + ds_cx_gid_kp2, + ds_cx_prt_sel_jp1, + ds_cx_prt_sel_kp1, + ds_cx_srca_data_jp2, + ds_cx_srca_data_kp2, + ds_cx_srca_data_vld_jp2, + ds_cx_srca_data_vld_kp2, + ds_cx_srcb_data_jp2, + ds_cx_srcb_data_kp2, + ds_cx_srcb_data_vld_jp2, + ds_cx_srcb_data_vld_kp2, + ds_cx_srcc_data_jp2, + ds_cx_srcc_data_kp2, + ds_cx_srcc_data_vld_jp2, + ds_cx_srcc_data_vld_kp2, + ds_cx_srcd_data_jp2, + ds_cx_srcd_data_kp2, + ds_cx_srcd_data_vld_jp2, + ds_cx_srcd_data_vld_kp2, + ds_cx_srcp_data_jp2, + ds_cx_srcp_data_kp2, + ds_cx_srcp_data_vld_jp2, + ds_cx_srcp_data_vld_kp2, + ds_cx_swdw_nuke_jp2, + ds_cx_swdw_nuke_kp2, + ds_cx_uop_ctl_jp2, + ds_cx_uop_ctl_kp2, + ds_cx_uop_vld_jp2, + ds_cx_uop_vld_kp2, + ds_srca_dw_0p1, + ds_srca_dw_1p1, + ds_srca_dw_2p1, + ds_srca_prdcr_dw_0p1, + ds_srca_prdcr_dw_1p1, + ds_srca_prdcr_dw_2p1, + ds_srca_tag_0p1, + ds_srca_tag_1p1, + ds_srca_tag_2p1, + ds_srca_tag_vld_0p1, + ds_srca_tag_vld_1p1, + ds_srca_tag_vld_2p1, + ds_srcb_dw_0p1, + ds_srcb_dw_1p1, + ds_srcb_dw_2p1, + ds_srcb_prdcr_dw_0p1, + ds_srcb_prdcr_dw_1p1, + ds_srcb_prdcr_dw_2p1, + ds_srcb_tag_0p1, + ds_srcb_tag_1p1, + ds_srcb_tag_2p1, + ds_srcb_tag_vld_0p1, + ds_srcb_tag_vld_1p1, + ds_srcb_tag_vld_2p1, + ds_srcc_dw_0p1, + ds_srcc_dw_1p1, + ds_srcc_dw_2p1, + ds_srcc_prdcr_dw_0p1, + ds_srcc_prdcr_dw_1p1, + ds_srcc_prdcr_dw_2p1, + ds_srcc_tag_0p1, + ds_srcc_tag_1p1, + ds_srcc_tag_2p1, + ds_srcc_tag_vld_0p1, + ds_srcc_tag_vld_1p1, + ds_srcc_tag_vld_2p1, + ds_srcd_dw_0p1, + ds_srcd_dw_1p1, + ds_srcd_dw_2p1, + ds_srcd_prdcr_dw_0p1, + ds_srcd_prdcr_dw_1p1, + ds_srcd_prdcr_dw_2p1, + ds_srcd_tag_0p1, + ds_srcd_tag_1p1, + ds_srcd_tag_2p1, + ds_srcd_tag_vld_0p1, + ds_srcd_tag_vld_1p1, + ds_srcd_tag_vld_2p1, + ds_srcp_tag_0p1, + ds_srcp_tag_1p1, + ds_srcp_tag_2p1, + ds_srcp_tag_vld_0p1, + ds_srcp_tag_vld_1p1, + ds_srcp_tag_vld_2p1, + ls_resx_data_cancel_w1, + ls_resx_data_cancel_w2, + ls_resx_data_w2, + ls_resx_dw_w0, + ls_resx_dw_w1, + ls_resx_tag_vld_w0, + ls_resx_tag_vld_w1, + ls_resx_tag_w0, + ls_resx_tag_w1, + ls_resy_data_cancel_w1, + ls_resy_data_cancel_w2, + ls_resy_data_w2, + ls_resy_dw_w0, + ls_resy_dw_w1, + ls_resy_tag_vld_w0, + ls_resy_tag_vld_w1, + ls_resy_tag_w0, + ls_resy_tag_w1, + mx_resp_data_w2, + mx_resp_tag_vld_w0, + mx_resp_tag_vld_w1, + mx_resp_tag_w0, + mx_resp_tag_w1, + sx_ldxcancel_sel_jw0, + sx_ldxcancel_sel_jw1, + sx_ldxcancel_sel_kw0, + sx_ldxcancel_sel_kw1, + sx_resp_data_jw2, + sx_resp_data_kw2, + sx_resp_tag_jw0, + sx_resp_tag_jw1, + sx_resp_tag_kw0, + sx_resp_tag_kw1, + sx_resp_tag_vld_jw0, + sx_resp_tag_vld_jw1, + sx_resp_tag_vld_kw0, + sx_resp_tag_vld_kw1, + sx_uop_vld_jw0, + sx_uop_vld_kw0 + ); + +wire [3:0] unused1; + + // outputs + output cx_active; + output [2:0] cx_credit_j; + output [2:0] cx_credit_k; + output [4:0] cx_dstp_tag_ke1; + output cx_dstp_tag_vld_ke1; + output [3:0] cx_resp_data_w1; + output [5:0] cx_resp_qfbit_gid_w1; + output cx_resp_qfbit_vld_w1; + output [6:0] cx_resp_qfbit_w2; + output cx_resp_tag_vld_w0; + output [4:0] cx_resp_tag_w0; + output [63:0] cx_resx_data_w2; + output cx_resx_dw_w1; + output [5:0] cx_resx_qfbit_gid_w1; + output cx_resx_qfbit_vld_w1; + output [6:0] cx_resx_qfbit_w2; + output cx_resx_tag_vld_w1; + output [6:0] cx_resx_tag_w1; + output [63:0] cx_resy_data_w2; + output cx_resy_dw_w1; + output [5:0] cx_resy_qfbit_gid_w1; + output cx_resy_qfbit_vld_w1; + output [6:0] cx_resy_qfbit_w2; + output cx_resy_tag_vld_w1; + output [6:0] cx_resy_tag_w1; + output [63:0] cx_resz_data_w2; + output cx_resz_dw_w1; + output [5:0] cx_resz_qfbit_gid_w1; + output cx_resz_qfbit_vld_w1; + output [6:0] cx_resz_qfbit_w2; + output cx_resz_tag_vld_w1; + output [6:0] cx_resz_tag_w1; + + // inputs + input ck_areset; + input ck_gclkcx; + input ck_reset1_n_cx; + input dftrstdisable_cpu; + input dftse_cpu; + input ds_cx_aarch32_state; + input ds_cx_aarch64_state; + input ds_cx_cpuactlr_frc_cpu_rcg_active; + input [4:0] ds_cx_dstp_tag_jp2; + input [4:0] ds_cx_dstp_tag_kp2; + input ds_cx_dstp_tag_vld_jp2; + input ds_cx_dstp_tag_vld_kp2; + input ds_cx_dstx_dw_jp2; + input ds_cx_dstx_dw_kp2; + input [6:0] ds_cx_dstx_tag_jp2; + input [6:0] ds_cx_dstx_tag_kp2; + input ds_cx_dstx_tag_vld_jp2; + input ds_cx_dstx_tag_vld_kp2; + input ds_cx_dsty_dw_jp2; + input ds_cx_dsty_dw_kp2; + input [6:0] ds_cx_dsty_tag_jp2; + input [6:0] ds_cx_dsty_tag_kp2; + input ds_cx_dsty_tag_vld_jp2; + input ds_cx_dsty_tag_vld_kp2; + input [6:0] ds_cx_flush_gid; + input ds_cx_flush_seq; + input ds_cx_flush_u1; + input ds_cx_fpscr_ahp; + input ds_cx_fpscr_dn; + input ds_cx_fpscr_fz; + input [1:0] ds_cx_fpscr_rmode; + input [6:0] ds_cx_gid_jp2; + input [6:0] ds_cx_gid_kp2; + input [2:0] ds_cx_prt_sel_jp1; + input [2:0] ds_cx_prt_sel_kp1; + input [63:0] ds_cx_srca_data_jp2; + input [63:0] ds_cx_srca_data_kp2; + input [1:0] ds_cx_srca_data_vld_jp2; + input [1:0] ds_cx_srca_data_vld_kp2; + input [63:0] ds_cx_srcb_data_jp2; + input [63:0] ds_cx_srcb_data_kp2; + input [1:0] ds_cx_srcb_data_vld_jp2; + input [1:0] ds_cx_srcb_data_vld_kp2; + input [63:0] ds_cx_srcc_data_jp2; + input [63:0] ds_cx_srcc_data_kp2; + input [1:0] ds_cx_srcc_data_vld_jp2; + input [1:0] ds_cx_srcc_data_vld_kp2; + input [63:0] ds_cx_srcd_data_jp2; + input [63:0] ds_cx_srcd_data_kp2; + input [1:0] ds_cx_srcd_data_vld_jp2; + input [1:0] ds_cx_srcd_data_vld_kp2; + input [3:0] ds_cx_srcp_data_jp2; + input [3:0] ds_cx_srcp_data_kp2; + input ds_cx_srcp_data_vld_jp2; + input ds_cx_srcp_data_vld_kp2; + input ds_cx_swdw_nuke_jp2; + input ds_cx_swdw_nuke_kp2; + input [58:0] ds_cx_uop_ctl_jp2; + input [58:0] ds_cx_uop_ctl_kp2; + input ds_cx_uop_vld_jp2; + input ds_cx_uop_vld_kp2; + input ds_srca_dw_0p1; + input ds_srca_dw_1p1; + input ds_srca_dw_2p1; + input ds_srca_prdcr_dw_0p1; + input ds_srca_prdcr_dw_1p1; + input ds_srca_prdcr_dw_2p1; + input [6:0] ds_srca_tag_0p1; + input [6:0] ds_srca_tag_1p1; + input [6:0] ds_srca_tag_2p1; + input ds_srca_tag_vld_0p1; + input ds_srca_tag_vld_1p1; + input ds_srca_tag_vld_2p1; + input ds_srcb_dw_0p1; + input ds_srcb_dw_1p1; + input ds_srcb_dw_2p1; + input ds_srcb_prdcr_dw_0p1; + input ds_srcb_prdcr_dw_1p1; + input ds_srcb_prdcr_dw_2p1; + input [6:0] ds_srcb_tag_0p1; + input [6:0] ds_srcb_tag_1p1; + input [6:0] ds_srcb_tag_2p1; + input ds_srcb_tag_vld_0p1; + input ds_srcb_tag_vld_1p1; + input ds_srcb_tag_vld_2p1; + input ds_srcc_dw_0p1; + input ds_srcc_dw_1p1; + input ds_srcc_dw_2p1; + input ds_srcc_prdcr_dw_0p1; + input ds_srcc_prdcr_dw_1p1; + input ds_srcc_prdcr_dw_2p1; + input [6:0] ds_srcc_tag_0p1; + input [6:0] ds_srcc_tag_1p1; + input [6:0] ds_srcc_tag_2p1; + input ds_srcc_tag_vld_0p1; + input ds_srcc_tag_vld_1p1; + input ds_srcc_tag_vld_2p1; + input ds_srcd_dw_0p1; + input ds_srcd_dw_1p1; + input ds_srcd_dw_2p1; + input ds_srcd_prdcr_dw_0p1; + input ds_srcd_prdcr_dw_1p1; + input ds_srcd_prdcr_dw_2p1; + input [6:0] ds_srcd_tag_0p1; + input [6:0] ds_srcd_tag_1p1; + input [6:0] ds_srcd_tag_2p1; + input ds_srcd_tag_vld_0p1; + input ds_srcd_tag_vld_1p1; + input ds_srcd_tag_vld_2p1; + input [4:0] ds_srcp_tag_0p1; + input [4:0] ds_srcp_tag_1p1; + input [4:0] ds_srcp_tag_2p1; + input ds_srcp_tag_vld_0p1; + input ds_srcp_tag_vld_1p1; + input ds_srcp_tag_vld_2p1; + input ls_resx_data_cancel_w1; + input ls_resx_data_cancel_w2; + input [63:0] ls_resx_data_w2; + input ls_resx_dw_w0; + input ls_resx_dw_w1; + input ls_resx_tag_vld_w0; + input ls_resx_tag_vld_w1; + input [6:0] ls_resx_tag_w0; + input [6:0] ls_resx_tag_w1; + input ls_resy_data_cancel_w1; + input ls_resy_data_cancel_w2; + input [63:0] ls_resy_data_w2; + input ls_resy_dw_w0; + input ls_resy_dw_w1; + input ls_resy_tag_vld_w0; + input ls_resy_tag_vld_w1; + input [6:0] ls_resy_tag_w0; + input [6:0] ls_resy_tag_w1; + input [3:0] mx_resp_data_w2; + input mx_resp_tag_vld_w0; + input mx_resp_tag_vld_w1; + input [4:0] mx_resp_tag_w0; + input [4:0] mx_resp_tag_w1; + input sx_ldxcancel_sel_jw0; + input sx_ldxcancel_sel_jw1; + input sx_ldxcancel_sel_kw0; + input sx_ldxcancel_sel_kw1; + input [3:0] sx_resp_data_jw2; + input [3:0] sx_resp_data_kw2; + input [4:0] sx_resp_tag_jw0; + input [4:0] sx_resp_tag_jw1; + input [4:0] sx_resp_tag_kw0; + input [4:0] sx_resp_tag_kw1; + input sx_resp_tag_vld_jw0; + input sx_resp_tag_vld_jw1; + input sx_resp_tag_vld_kw0; + input sx_resp_tag_vld_kw1; + input sx_uop_vld_jw0; + input sx_uop_vld_kw0; + + // wires + wire acc_size_eq64_e3_q; + wire acc_size_ge32_e3_q; + wire acc_size_ne08_e3_q; + wire addj_active; + wire addk_active; + wire aesd_e1; + wire aesdimc_e1; + wire aese_e1; + wire aesemc_e1; + wire aesimc_e1; + wire aesmc_e1; + wire ahp_mode_e1_q; + wire [3:0] c00_x_sel_e1; + wire c00_y_sel_e1; + wire [5:0] c01_x_sel_e1; + wire [2:0] c01_y_sel_e1; + wire [5:0] c02_x_sel_e1; + wire [2:0] c02_y_sel_e1; + wire [6:0] c03_x_sel_e1; + wire [4:0] c03_y_sel_e1; + wire [5:0] c04_x_sel_e1; + wire [2:0] c04_y_sel_e1; + wire [7:0] c05_x_sel_e1; + wire [4:0] c05_y_sel_e1; + wire [5:0] c06_x_sel_e1; + wire [4:0] c06_y_sel_e1; + wire [6:0] c07_x_sel_e1; + wire [4:0] c07_y_sel_e1; + wire [6:0] c08_x_sel_e1; + wire [2:0] c08_y_sel_e1; + wire [8:0] c09_x_sel_e1; + wire [5:0] c09_y_sel_e1; + wire [8:0] c10_x_sel_e1; + wire [5:0] c10_y_sel_e1; + wire [9:0] c11_x_sel_e1; + wire [7:0] c11_y_sel_e1; + wire [7:0] c12_x_sel_e1; + wire [5:0] c12_y_sel_e1; + wire [9:0] c13_x_sel_e1; + wire [6:0] c13_y_sel_e1; + wire [7:0] c14_x_sel_e1; + wire [6:0] c14_y_sel_e1; + wire [7:0] c15_x_sel_e1; + wire [6:0] c15_y_sel_e1; + wire ccpass_ke2; + wire ck_gclkcx_crypt; + wire ck_gclkcx_floatj; + wire ck_gclkcx_floatk; + wire ck_gclkcx_intj; + wire ck_gclkcx_intk; + wire crp3_vld_je1; + wire crypt2_active; + wire [127:0] crypt2_out_e3_q; + wire crypt2_vld_e1; + wire crypt3_active; + wire [127:0] crypt3_out_e6_q; + wire crypt3_vld0_e1; + wire crypt3_vld1_e1; + wire cvtj_active; + wire [3:0] cx_acc_type_je1; + wire [3:1] cx_acc_type_je2; + wire [3:0] cx_acc_type_ke1; + wire [3:1] cx_acc_type_ke2; + wire cx_ccpass_je1; + wire cx_ccpass_ke1; + wire cx_ctl_dp_fp_valid_ji1; + wire cx_ctl_dp_fp_valid_ki1; + wire cx_ctl_dp_int_valid_ji1; + wire cx_ctl_dp_int_valid_ki1; + wire [4:0] cx_dst_sel_je1; + wire [4:0] cx_dst_sel_ke1; + wire [4:0] cx_dstp_tag_je1; + wire [4:0] cx_dstp_tag_ke1; + wire cx_dstp_tag_vld_je1; + wire cx_dstp_tag_vld_ke1; + wire cx_dstx_dw_je1; + wire cx_dstx_dw_ke1; + wire [6:0] cx_dstx_tag_je1; + wire [6:0] cx_dstx_tag_je2; + wire [6:0] cx_dstx_tag_ke1; + wire [6:0] cx_dstx_tag_ke2; + wire cx_dstx_tag_vld_je1; + wire cx_dstx_tag_vld_ke1; + wire cx_dsty_dw_je1; + wire cx_dsty_dw_ke1; + wire [6:0] cx_dsty_tag_je1; + wire [6:0] cx_dsty_tag_ke1; + wire cx_dsty_tag_vld_je1; + wire cx_dsty_tag_vld_ke1; + wire [63:0] cx_fadd_srca_fp_data32_je1; + wire [63:0] cx_fadd_srca_fp_data32_ke1; + wire [63:0] cx_fadd_srca_fp_data64_je1; + wire [63:0] cx_fadd_srca_fp_data64_ke1; + wire [55:0] cx_fadd_srcb_fp_data32_h_je1; + wire [55:0] cx_fadd_srcb_fp_data32_h_ke1; + wire [55:0] cx_fadd_srcb_fp_data32_l_je1; + wire [55:0] cx_fadd_srcb_fp_data32_l_ke1; + wire [116:0] cx_fadd_srcb_fp_data64_je1; + wire [116:0] cx_fadd_srcb_fp_data64_ke1; + wire [63:0] cx_fadd_srcc_fp_data32_je1; + wire [63:0] cx_fadd_srcc_fp_data32_ke1; + wire [31:0] cx_fadd_srcc_fp_data64_je1; + wire [31:0] cx_fadd_srcc_fp_data64_ke1; + wire [31:0] cx_fadd_srcd_fp_data64_je1; + wire [31:0] cx_fadd_srcd_fp_data64_ke1; + wire [63:0] cx_fmul_srca_fp_data32_je1; + wire [63:0] cx_fmul_srca_fp_data32_ke1; + wire [63:0] cx_fmul_srcb_fp_data32_je1; + wire [63:0] cx_fmul_srcb_fp_data32_ke1; + wire [6:0] cx_gid_je1; + wire [6:0] cx_gid_ke1; + wire [12:0] cx_imac_cmd_e1; + wire cx_imac_vld_e1; + wire cx_ls_resx_data_cancel_w2; + wire cx_ls_resx_data_cancel_w3; + wire cx_ls_resx_dw_w1; + wire cx_ls_resx_dw_w2; + wire cx_ls_resx_tag_vld_w1; + wire cx_ls_resx_tag_vld_w2; + wire [6:0] cx_ls_resx_tag_w1; + wire [6:0] cx_ls_resx_tag_w2; + wire cx_ls_resy_data_cancel_w2; + wire cx_ls_resy_data_cancel_w3; + wire cx_ls_resy_dw_w1; + wire cx_ls_resy_dw_w2; + wire cx_ls_resy_tag_vld_w1; + wire cx_ls_resy_tag_vld_w2; + wire [6:0] cx_ls_resy_tag_w1; + wire [6:0] cx_ls_resy_tag_w2; + wire [4:0] cx_mla_fwd_sel_je1; + wire [4:0] cx_mla_fwd_sel_je2; + wire [4:0] cx_mla_fwd_sel_je3; + wire [4:0] cx_mla_fwd_sel_ke1; + wire [4:0] cx_mla_fwd_sel_ke2; + wire [4:0] cx_mla_fwd_sel_ke3; + wire cx_mx_resp_tag_vld_w1; + wire cx_mx_resp_tag_vld_w2; + wire [4:0] cx_mx_resp_tag_w1; + wire [4:0] cx_mx_resp_tag_w2; + wire [2:0] cx_region_je1; + wire [2:0] cx_region_ke1; + wire cx_res128_je1; + wire cx_res128_ke1; + wire cx_reset3; + wire [3:0] cx_resp_data_w1; + wire [3:0] cx_resp_data_w2; + wire cx_resp_tag_vld_w0; + wire cx_resp_tag_vld_w1; + wire cx_resp_tag_vld_w2; + wire [4:0] cx_resp_tag_w0; + wire [4:0] cx_resp_tag_w1; + wire [4:0] cx_resp_tag_w2; + wire [63:0] cx_resx_data_w2; + wire cx_resx_dw_w0; + wire cx_resx_dw_w0m1; + wire cx_resx_dw_w1; + wire cx_resx_dw_w2; + wire [2:0] cx_resx_region_w0m1; + wire [49:32] cx_resx_sel_dec_jw0; + wire [13:0] cx_resx_sel_dec_kw0; + wire cx_resx_selj_w0; + wire cx_resx_tag_vld_w0; + wire cx_resx_tag_vld_w0m1; + wire cx_resx_tag_vld_w1; + wire cx_resx_tag_vld_w2; + wire [6:0] cx_resx_tag_w0; + wire [6:0] cx_resx_tag_w0m1; + wire [6:0] cx_resx_tag_w1; + wire [6:0] cx_resx_tag_w2; + wire [63:0] cx_resy_data_w2; + wire cx_resy_dw_w0; + wire cx_resy_dw_w0m1; + wire cx_resy_dw_w1; + wire cx_resy_dw_w2; + wire [2:0] cx_resy_region_w0m1; + wire [49:32] cx_resy_sel_dec_jw0; + wire [13:0] cx_resy_sel_dec_kw0; + wire cx_resy_selj_w0; + wire cx_resy_tag_vld_w0; + wire cx_resy_tag_vld_w0m1; + wire cx_resy_tag_vld_w1; + wire cx_resy_tag_vld_w2; + wire [6:0] cx_resy_tag_w0; + wire [6:0] cx_resy_tag_w0m1; + wire [6:0] cx_resy_tag_w1; + wire [6:0] cx_resy_tag_w2; + wire [63:0] cx_resz_data_w2; + wire cx_resz_dw_w0; + wire cx_resz_dw_w0m1; + wire cx_resz_dw_w1; + wire cx_resz_dw_w2; + wire [2:0] cx_resz_region_w0m1; + wire [49:32] cx_resz_sel_dec_jw0; + wire [13:0] cx_resz_sel_dec_kw0; + wire cx_resz_selj_w0; + wire cx_resz_tag_vld_w0; + wire cx_resz_tag_vld_w0m1; + wire cx_resz_tag_vld_w1; + wire cx_resz_tag_vld_w2; + wire [6:0] cx_resz_tag_w0; + wire [6:0] cx_resz_tag_w0m1; + wire [6:0] cx_resz_tag_w1; + wire [6:0] cx_resz_tag_w2; + wire [63:0] cx_srca_crypt_data_je1; + wire [63:0] cx_srca_data_ji1; + wire [63:0] cx_srca_data_ki1; + wire cx_srca_en_je1; + wire cx_srca_en_ke1; + wire [63:0] cx_srca_fp_data32_je1; + wire [63:0] cx_srca_fp_data32_ke1; + wire [63:0] cx_srca_fp_data64_je1; + wire [63:0] cx_srca_fp_data64_ke1; + wire cx_srca_fp_h_en_ji1; + wire cx_srca_fp_h_en_ki1; + wire cx_srca_fp_l_en_ji1; + wire cx_srca_fp_l_en_ki1; + wire [63:0] cx_srca_int_data_je1; + wire [63:0] cx_srca_int_data_ke1; + wire cx_srca_int_h_en_ji1; + wire cx_srca_int_h_en_ki1; + wire cx_srca_int_l_en_ji1; + wire cx_srca_int_l_en_ki1; + wire [63:0] cx_srcb_crypt_data_je1; + wire [63:0] cx_srcb_data_ji1; + wire [63:0] cx_srcb_data_ki1; + wire cx_srcb_en_je1; + wire cx_srcb_en_ke1; + wire [63:0] cx_srcb_fp_data32_je1; + wire [63:0] cx_srcb_fp_data64_je1; + wire [63:0] cx_srcb_fp_data64_ke1; + wire cx_srcb_fp_h_en_ji1; + wire cx_srcb_fp_h_en_ki1; + wire cx_srcb_fp_l_en_ji1; + wire cx_srcb_fp_l_en_ki1; + wire [63:0] cx_srcb_int_data_je1; + wire [63:0] cx_srcb_int_data_ke1; + wire cx_srcb_int_h_en_ji1; + wire cx_srcb_int_h_en_ki1; + wire cx_srcb_int_l_en_ji1; + wire cx_srcb_int_l_en_ki1; + wire [63:0] cx_srcc_crypt_data_je1; + wire [63:0] cx_srcc_data_ji1; + wire [63:0] cx_srcc_data_ke3; + wire [63:0] cx_srcc_data_ki1; + wire cx_srcc_en_je1; + wire cx_srcc_en_ke1; + wire [63:0] cx_srcc_fp_data32_je1; + wire [63:0] cx_srcc_fp_data32_ke1; + wire cx_srcc_fp_h_en_ji1; + wire cx_srcc_fp_h_en_ki1; + wire cx_srcc_fp_l_en_ji1; + wire cx_srcc_fp_l_en_ki1; + wire [63:0] cx_srcc_int_data_je1; + wire [63:0] cx_srcc_int_data_ke1; + wire cx_srcc_int_h_en_ji1; + wire cx_srcc_int_h_en_ki1; + wire cx_srcc_int_l_en_ji1; + wire cx_srcc_int_l_en_ki1; + wire [63:0] cx_srcd_crypt_data_je1; + wire [63:0] cx_srcd_data_ji1; + wire [63:0] cx_srcd_data_ke3; + wire [63:0] cx_srcd_data_ki1; + wire cx_srcd_en_je1; + wire cx_srcd_en_ke1; + wire [31:0] cx_srcd_fp_data32_je1; + wire [31:0] cx_srcd_fp_data32_ke1; + wire cx_srcd_fp_h_en_ji1; + wire cx_srcd_fp_h_en_ki1; + wire cx_srcd_fp_l_en_ji1; + wire cx_srcd_fp_l_en_ki1; + wire [63:0] cx_srcd_int_data_je1; + wire [63:0] cx_srcd_int_data_ke1; + wire cx_srcd_int_h_en_ji1; + wire cx_srcd_int_h_en_ki1; + wire cx_srcd_int_l_en_ji1; + wire cx_srcd_int_l_en_ki1; + wire [3:0] cx_srcp_data_je1; + wire [3:0] cx_srcp_data_ke1; + wire cx_sx_ldxcancel_sel_jw1; + wire cx_sx_ldxcancel_sel_kw1; + wire [4:0] cx_sx_resp_tag_jw1; + wire [4:0] cx_sx_resp_tag_jw2; + wire [4:0] cx_sx_resp_tag_kw1; + wire [4:0] cx_sx_resp_tag_kw2; + wire cx_sx_resp_tag_vld_jw1; + wire cx_sx_resp_tag_vld_jw2; + wire cx_sx_resp_tag_vld_kw1; + wire cx_sx_resp_tag_vld_kw2; + wire [58:0] cx_uop_ctl_ji1; + wire [58:0] cx_uop_ctl_ki1; + wire [2:0] cx_uop_res_latency_je1; + wire [2:0] cx_uop_res_latency_ke1; + wire cx_uop_vld_je1; + wire cx_uop_vld_ji1; + wire cx_uop_vld_ke1; + wire cx_uop_vld_ki1; + wire dn_fadd_je1; + wire dn_fadd_ke1; + wire dn_je1; + wire dn_ke1; + wire dn_raw_e1_q; + wire [39:0] dstx_bytesel_je; + wire [39:0] dstx_bytesel_ke; + wire [39:0] dsty_bytesel_je; + wire [39:0] dsty_bytesel_ke; + wire [5:0] fadd32_ex_h_je4; + wire [5:0] fadd32_ex_h_ke4; + wire [5:0] fadd32_ex_l_je4; + wire [5:0] fadd32_ex_l_ke4; + wire [5:0] fadd64_ex_je4; + wire [5:0] fadd64_ex_ke4; + wire fadd_absin_je1; + wire fadd_absin_ke1; + wire fadd_absout_je1; + wire fadd_absout_ke1; + wire fadd_ccpass_je1; + wire fadd_ccpass_ke1; + wire fadd_hazard1_j; + wire fadd_hazard1_k; + wire [2:0] fadd_srca_sel_h_je1; + wire [2:0] fadd_srca_sel_h_ke1; + wire fadd_srca_sel_l_je1; + wire fadd_srca_sel_l_ke1; + wire [2:0] fadd_srcb_sel_h_je1; + wire [2:0] fadd_srcb_sel_h_ke1; + wire [2:0] fadd_srcb_sel_l_je1; + wire [2:0] fadd_srcb_sel_l_ke1; + wire fadd_sub_je1; + wire fadd_sub_ke1; + wire [2:0] fadd_vld_je1; + wire [2:0] fadd_vld_je4; + wire [2:0] fadd_vld_ke1; + wire [2:0] fadd_vld_ke4; + wire [31:0] faddout32_h_je4; + wire [31:0] faddout32_h_ke4; + wire [31:0] faddout32_l_je4; + wire [31:0] faddout32_l_ke4; + wire [63:0] faddout64_je4; + wire [63:0] faddout64_ke4; + wire fcvt_cvt_f_to_f_je1; + wire fcvt_cvt_f_to_i_je1; + wire fcvt_cvt_i_to_f_je1; + wire fcvt_cvts_je1; + wire [5:0] fcvt_ex_h_e3; + wire [5:0] fcvt_ex_l_e3; + wire fcvt_frint_je1; + wire fcvt_hp_sel_top_je1; + wire fcvt_imm_je1; + wire [5:0] fcvt_immv_je1; + wire [1:0] fcvt_isize_je1; + wire fcvt_noixc_je1; + wire [1:0] fcvt_osize_je1; + wire fcvt_recpe_je1; + wire fcvt_recpx_je1; + wire fcvt_restf_je1; + wire fcvt_rsqrte_je1; + wire fcvt_scalar_je1; + wire [1:0] fcvt_vld_je1; + wire [1:0] fcvt_vld_je3; + wire [127:0] fcvtout_e3; + wire fdiv_active; + wire [1:0] fdiv_busy_q; + wire [2:0] fdiv_cmd_e1; + wire [1:0] fdiv_done; + wire [1:0] fdiv_done_ack; + wire [1:0] fdiv_done_hold; + wire [1:0] fdiv_flush; + wire [1:0] fdiv_scalar; + wire fdiv_scalar_je1; + wire [1:0] fdiv_uop_vld_je1; + wire [5:0] fdivexc32_q; + wire [5:0] fdivexc64_q; + wire [31:0] fdivout32_q; + wire [63:0] fdivout64_q; + wire [63:0] fmla_acc_je4; + wire [63:0] fmla_acc_ke4; + wire fmla_fused_je1; + wire fmla_fused_je4; + wire fmla_fused_ke1; + wire fmla_fused_ke4; + wire [1:0] fmla_fwd_je3; + wire [1:0] fmla_fwd_je4; + wire [1:0] fmla_fwd_ke3; + wire [1:0] fmla_fwd_ke4; + wire fmla_je1; + wire fmla_je2; + wire fmla_je3; + wire fmla_je4; + wire fmla_ke1; + wire fmla_ke2; + wire fmla_ke3; + wire fmla_ke4; + wire fmla_negopa_je4; + wire fmla_negopa_ke4; + wire [4:0] fmul32_ex_h_je4; + wire [4:0] fmul32_ex_h_ke4; + wire [4:0] fmul32_ex_l_je4; + wire [4:0] fmul32_ex_l_ke4; + wire [4:0] fmul64_ex_je4; + wire [4:0] fmul64_ex_ke4; + wire fmul_c_on_d_je1; + wire fmul_c_on_d_ke1; + wire fmul_div_je4; + wire fmul_div_ke4; + wire fmul_ext_je1; + wire fmul_ext_ke1; + wire fmul_f_exp_ovfl_h_je4; + wire fmul_f_exp_ovfl_h_ke4; + wire fmul_f_exp_ovfl_je4; + wire fmul_f_exp_ovfl_ke4; + wire fmul_f_exp_ovfl_l_je4; + wire fmul_f_exp_ovfl_l_ke4; + wire fmul_f_infnanzero_h_je4; + wire fmul_f_infnanzero_h_ke4; + wire fmul_f_infnanzero_je4; + wire fmul_f_infnanzero_ke4; + wire fmul_f_infnanzero_l_je4; + wire fmul_f_infnanzero_l_ke4; + wire fmul_f_prod_inf_zero_h_je4; + wire fmul_f_prod_inf_zero_h_ke4; + wire fmul_f_prod_inf_zero_je4; + wire fmul_f_prod_inf_zero_ke4; + wire fmul_f_prod_inf_zero_l_je4; + wire fmul_f_prod_inf_zero_l_ke4; + wire fmul_negmul_je1; + wire fmul_negmul_ke1; + wire fmul_srca_sel_l_je1; + wire fmul_srca_sel_l_ke1; + wire fmul_srcb_sel_h_je1; + wire fmul_srcb_sel_h_ke1; + wire fmul_srcb_sel_l_je1; + wire fmul_srcb_sel_l_ke1; + wire fmul_step_je1; + wire fmul_step_ke1; + wire [2:0] fmul_vld_je1; + wire [2:0] fmul_vld_je2; + wire [2:0] fmul_vld_je3; + wire [2:0] fmul_vld_je4; + wire [2:0] fmul_vld_ke1; + wire [2:0] fmul_vld_ke2; + wire [2:0] fmul_vld_ke3; + wire [2:0] fmul_vld_ke4; + wire fmulj_active; + wire fmulk_active; + wire [55:0] fmulout32_h_je4; + wire [55:0] fmulout32_h_ke4; + wire [55:0] fmulout32_l_je4; + wire [55:0] fmulout32_l_ke4; + wire [116:0] fmulout64_je4; + wire [116:0] fmulout64_ke4; + wire fsqrt_active; + wire [1:0] fsqrt_busy_q; + wire [2:0] fsqrt_cmd_e1; + wire [1:0] fsqrt_done; + wire [1:0] fsqrt_done_ack; + wire [1:0] fsqrt_done_hold; + wire [1:0] fsqrt_flush; + wire [1:0] fsqrt_scalar; + wire fsqrt_scalar_ke1; + wire [1:0] fsqrt_uop_vld_ke1; + wire [5:0] fsqrtexc32_q; + wire [5:0] fsqrtexc64_q; + wire [31:0] fsqrtout32_q; + wire [63:0] fsqrtout64_q; + wire fz_fadd_je1; + wire fz_fadd_ke1; + wire fz_je1; + wire fz_ke1; + wire fz_raw_e1_q; + wire [7:1] iacc_cin_sel_e3_q; + wire iacc_en_e1; + wire iacc_en_e2; + wire iacc_en_e4; + wire iacc_shfsel_e2; + wire iacce4_fwd_e2; + wire ialu_acc_en_ke1; + wire [21:0] ialu_ctl_je1; + wire [21:0] ialu_ctl_ke1; + wire ialu_en_je1; + wire ialu_en_ke1; + wire ialu_en_ke3; + wire [1:0] ialu_esize_je1; + wire [1:0] ialu_esize_ke1; + wire ialu_fp_dn_je1; + wire ialu_fp_dn_ke1; + wire ialu_fp_fz_je1; + wire ialu_fp_fz_ke1; + wire [4:0] ialu_fpex_je3_q; + wire [4:0] ialu_fpex_ke3_q; + wire [3:0] ialu_nzcv_ke3_q; + wire ialu_qc_je3_q; + wire ialu_qc_ke3_q; + wire ialu_qc_vld_je2; + wire ialu_qc_vld_ke2; + wire ialu_res128_je1_q; + wire ialu_res128_ke1_q; + wire ialuj_active; + wire ialuk_active; + wire [127:0] ialuout_je3_q; + wire [127:0] ialuout_ke3_q; + wire imac_active; + wire imac_qc_e4_q; + wire imac_qc_vld_e3; + wire [6:0] iqj_flush_gid; + wire iqj_flush_u2; + wire [6:0] iqk_flush_gid; + wire iqk_flush_u2; + wire [1:0] ired_esize_ke1; + wire ired_long_ke1; + wire ired_opb_en_ke1; + wire ired_seladd_ke1; + wire ired_selmax_ke1; + wire ired_selmin_ke1; + wire ired_selusgn_ke1; + wire ired_vrop_ke1; + wire iredk_active; + wire [63:0] iredout_ke2; + wire ishf3_iss_e2; + wire ishf3_iss_e3; + wire ishf3_uiss_e2; + wire ishf_active; + wire ishf_imm_e1; + wire [7:0] ishf_immv_e1; + wire ishf_insert_e1; + wire ishf_iss_e1; + wire ishf_iss_e2; + wire ishf_left_e1; + wire ishf_narrow_e1; + wire ishf_qc_e4_q; + wire ishf_qc_vld_e3; + wire ishf_round_e1; + wire [2:0] ishf_s1_sel_e1; + wire [2:0] ishf_s2_sel_e1; + wire [3:0] ishf_s3_sel_e1; + wire [2:0] ishf_s4_sel_e1; + wire [3:0] ishf_s5_sel_e1; + wire [3:0] ishf_s6_sel_e1; + wire [4:0] ishf_s7_sel_e1; + wire ishf_saturate_e1; + wire ishf_scalar_e1; + wire ishf_sel16_e1; + wire ishf_sel32_e1; + wire ishf_sel64_e1; + wire ishf_sel8_e1; + wire ishf_selqsat_e3; + wire ishf_signed_e1; + wire ishf_stous_e1; + wire ishf_uiss_e2; + wire ishf_widen_e1; + wire [127:0] ishfaccout_e4_q; + wire [127:0] ishfout_e3_q; + wire issq_active; + wire issq_crypt_active; + wire issq_floatj_active; + wire issq_floatk_active; + wire issq_intj_active; + wire issq_intk_active; + wire [127:0] iwbout_e4_q; + wire [127:0] lspout_je3_q; + wire [127:0] lspout_ke3_q; + wire perm_en_je1; + wire perm_en_je2; + wire perm_en_ke1; + wire perm_en_ke2; + wire perm_opa_en_je1; + wire perm_opa_en_ke1; + wire perm_opb_en_je1; + wire perm_opb_en_ke1; + wire perm_opc_en_je1; + wire perm_opc_en_ke1; + wire perm_opd_en_je1; + wire perm_opd_en_ke1; + wire [2:0] perm_sign_sel0_je1; + wire [2:0] perm_sign_sel0_ke1; + wire [2:0] perm_sign_sel1_je1; + wire [2:0] perm_sign_sel1_ke1; + wire [2:0] perm_sign_sel2_je1; + wire [2:0] perm_sign_sel2_ke1; + wire [2:0] perm_sign_sel3_je1; + wire [2:0] perm_sign_sel3_ke1; + wire perm_uen_je1; + wire perm_uen_je2; + wire perm_uen_ke1; + wire perm_uen_ke2; + wire pmull_e1; + wire res128_e2; + wire [1:0] rmode_fadd_je1; + wire [1:0] rmode_fadd_ke1; + wire [2:0] rmode_fcvt_je1; + wire [1:0] rmode_fpscr_e1_q; + wire [1:0] rmode_je1; + wire [1:0] rmode_ke1; + wire selusgn_je1_q; + wire selusgn_ke1_q; + wire sha1c_e1; + wire sha1h_e1; + wire sha1m_e1; + wire sha1p_e1; + wire sha1su1_e1; + wire sha256h2_e1; + wire sha256h_e1; + wire sha256su0_e1; + wire sha256su1_e1; + wire shf_size_eq64_e3_q; + wire shf_size_ge32_e3_q; + wire shf_size_ne08_e3_q; + wire [11:1] srca_dec_hi_sel_ji1; + wire [11:1] srca_dec_hi_sel_ki1; + wire [11:1] srca_dec_sel_ji1; + wire [11:1] srca_dec_sel_ki1; + wire srca_hi_sel_ji1; + wire srca_hi_sel_ki1; + wire [11:1] srcb_dec_hi_sel_ji1; + wire [11:1] srcb_dec_hi_sel_ki1; + wire [11:1] srcb_dec_sel_ji1; + wire [11:1] srcb_dec_sel_ki1; + wire srcb_hi_sel_ji1; + wire srcb_hi_sel_ki1; + wire [11:1] srcc_dec_hi_sel_ji1; + wire [11:1] srcc_dec_hi_sel_ki1; + wire [11:1] srcc_dec_sel_ji1; + wire [11:1] srcc_dec_sel_ki1; + wire srcc_hi_sel_ji1; + wire srcc_hi_sel_ki1; + wire [11:1] srcd_dec_hi_sel_ji1; + wire [11:1] srcd_dec_hi_sel_ki1; + wire [11:1] srcd_dec_sel_ji1; + wire [11:1] srcd_dec_sel_ki1; + wire srcd_hi_sel_ji1; + wire srcd_hi_sel_ki1; + wire tbl_inst_je; + wire tbl_inst_ke; + wire tbltbx_qdest_je; + wire tbltbx_qdest_ke; + wire [3:0] tbltbx_reg_bitmask_je; + wire [3:0] tbltbx_reg_bitmask_ke; + wire tbx_inst_je; + wire tbx_inst_ke; + wire [2:0] uopnum_je; + wire [2:0] uopnum_ke; + wire vcmp_inst_je; + wire vcmp_inst_ke; + + maia_cx_rb urb( // outputs + .ahp_mode_e1_q (ahp_mode_e1_q), + .ck_gclkcx_crypt (ck_gclkcx_crypt), + .ck_gclkcx_floatj (ck_gclkcx_floatj), + .ck_gclkcx_floatk (ck_gclkcx_floatk), + .ck_gclkcx_intj (ck_gclkcx_intj), + .ck_gclkcx_intk (ck_gclkcx_intk), + .cx_acc_type_je2 (cx_acc_type_je2[3:1]), + .cx_acc_type_ke2 (cx_acc_type_ke2[3:1]), + .cx_active (cx_active), + .cx_dstx_tag_je2 (cx_dstx_tag_je2[6:0]), + .cx_dstx_tag_ke2 (cx_dstx_tag_ke2[6:0]), + .cx_ls_resx_data_cancel_w2 (cx_ls_resx_data_cancel_w2), + .cx_ls_resx_data_cancel_w3 (cx_ls_resx_data_cancel_w3), + .cx_ls_resx_dw_w1 (cx_ls_resx_dw_w1), + .cx_ls_resx_dw_w2 (cx_ls_resx_dw_w2), + .cx_ls_resx_tag_vld_w1 (cx_ls_resx_tag_vld_w1), + .cx_ls_resx_tag_vld_w2 (cx_ls_resx_tag_vld_w2), + .cx_ls_resx_tag_w1 (cx_ls_resx_tag_w1[6:0]), + .cx_ls_resx_tag_w2 (cx_ls_resx_tag_w2[6:0]), + .cx_ls_resy_data_cancel_w2 (cx_ls_resy_data_cancel_w2), + .cx_ls_resy_data_cancel_w3 (cx_ls_resy_data_cancel_w3), + .cx_ls_resy_dw_w1 (cx_ls_resy_dw_w1), + .cx_ls_resy_dw_w2 (cx_ls_resy_dw_w2), + .cx_ls_resy_tag_vld_w1 (cx_ls_resy_tag_vld_w1), + .cx_ls_resy_tag_vld_w2 (cx_ls_resy_tag_vld_w2), + .cx_ls_resy_tag_w1 (cx_ls_resy_tag_w1[6:0]), + .cx_ls_resy_tag_w2 (cx_ls_resy_tag_w2[6:0]), + .cx_mx_resp_tag_vld_w1 (cx_mx_resp_tag_vld_w1), + .cx_mx_resp_tag_vld_w2 (cx_mx_resp_tag_vld_w2), + .cx_mx_resp_tag_w1 (cx_mx_resp_tag_w1[4:0]), + .cx_mx_resp_tag_w2 (cx_mx_resp_tag_w2[4:0]), + .cx_reset3 (cx_reset3), + .cx_resp_data_w1 (cx_resp_data_w1[3:0]), + .cx_resp_data_w2 (cx_resp_data_w2[3:0]), + .cx_resp_qfbit_gid_w1 (cx_resp_qfbit_gid_w1[5:0]), + .cx_resp_qfbit_vld_w1 (cx_resp_qfbit_vld_w1), + .cx_resp_qfbit_w2 (cx_resp_qfbit_w2[6:0]), + .cx_resp_tag_vld_w0 (cx_resp_tag_vld_w0), + .cx_resp_tag_vld_w1 (cx_resp_tag_vld_w1), + .cx_resp_tag_vld_w2 (cx_resp_tag_vld_w2), + .cx_resp_tag_w0 (cx_resp_tag_w0[4:0]), + .cx_resp_tag_w1 (cx_resp_tag_w1[4:0]), + .cx_resp_tag_w2 (cx_resp_tag_w2[4:0]), + .cx_resx_dw_w0 (cx_resx_dw_w0), + .cx_resx_dw_w0m1 (cx_resx_dw_w0m1), + .cx_resx_dw_w1 (cx_resx_dw_w1), + .cx_resx_dw_w2 (cx_resx_dw_w2), + .cx_resx_qfbit_gid_w1 (cx_resx_qfbit_gid_w1[5:0]), + .cx_resx_qfbit_vld_w1 (cx_resx_qfbit_vld_w1), + .cx_resx_qfbit_w2 (cx_resx_qfbit_w2[6:0]), + .cx_resx_region_w0m1 (cx_resx_region_w0m1[2:0]), + .cx_resx_sel_dec_jw0 (cx_resx_sel_dec_jw0[49:32]), + .cx_resx_sel_dec_kw0 (cx_resx_sel_dec_kw0[13:0]), + .cx_resx_selj_w0 (cx_resx_selj_w0), + .cx_resx_tag_vld_w0 (cx_resx_tag_vld_w0), + .cx_resx_tag_vld_w0m1 (cx_resx_tag_vld_w0m1), + .cx_resx_tag_vld_w1 (cx_resx_tag_vld_w1), + .cx_resx_tag_vld_w2 (cx_resx_tag_vld_w2), + .cx_resx_tag_w0 (cx_resx_tag_w0[6:0]), + .cx_resx_tag_w0m1 (cx_resx_tag_w0m1[6:0]), + .cx_resx_tag_w1 (cx_resx_tag_w1[6:0]), + .cx_resx_tag_w2 (cx_resx_tag_w2[6:0]), + .cx_resy_dw_w0 (cx_resy_dw_w0), + .cx_resy_dw_w0m1 (cx_resy_dw_w0m1), + .cx_resy_dw_w1 (cx_resy_dw_w1), + .cx_resy_dw_w2 (cx_resy_dw_w2), + .cx_resy_qfbit_gid_w1 (cx_resy_qfbit_gid_w1[5:0]), + .cx_resy_qfbit_vld_w1 (cx_resy_qfbit_vld_w1), + .cx_resy_qfbit_w2 (cx_resy_qfbit_w2[6:0]), + .cx_resy_region_w0m1 (cx_resy_region_w0m1[2:0]), + .cx_resy_sel_dec_jw0 (cx_resy_sel_dec_jw0[49:32]), + .cx_resy_sel_dec_kw0 (cx_resy_sel_dec_kw0[13:0]), + .cx_resy_selj_w0 (cx_resy_selj_w0), + .cx_resy_tag_vld_w0 (cx_resy_tag_vld_w0), + .cx_resy_tag_vld_w0m1 (cx_resy_tag_vld_w0m1), + .cx_resy_tag_vld_w1 (cx_resy_tag_vld_w1), + .cx_resy_tag_vld_w2 (cx_resy_tag_vld_w2), + .cx_resy_tag_w0 (cx_resy_tag_w0[6:0]), + .cx_resy_tag_w0m1 (cx_resy_tag_w0m1[6:0]), + .cx_resy_tag_w1 (cx_resy_tag_w1[6:0]), + .cx_resy_tag_w2 (cx_resy_tag_w2[6:0]), + .cx_resz_dw_w0 (cx_resz_dw_w0), + .cx_resz_dw_w0m1 (cx_resz_dw_w0m1), + .cx_resz_dw_w1 (cx_resz_dw_w1), + .cx_resz_dw_w2 (cx_resz_dw_w2), + .cx_resz_qfbit_gid_w1 (cx_resz_qfbit_gid_w1[5:0]), + .cx_resz_qfbit_vld_w1 (cx_resz_qfbit_vld_w1), + .cx_resz_qfbit_w2 (cx_resz_qfbit_w2[6:0]), + .cx_resz_region_w0m1 (cx_resz_region_w0m1[2:0]), + .cx_resz_sel_dec_jw0 (cx_resz_sel_dec_jw0[49:32]), + .cx_resz_sel_dec_kw0 (cx_resz_sel_dec_kw0[13:0]), + .cx_resz_selj_w0 (cx_resz_selj_w0), + .cx_resz_tag_vld_w0 (cx_resz_tag_vld_w0), + .cx_resz_tag_vld_w0m1 (cx_resz_tag_vld_w0m1), + .cx_resz_tag_vld_w1 (cx_resz_tag_vld_w1), + .cx_resz_tag_vld_w2 (cx_resz_tag_vld_w2), + .cx_resz_tag_w0 (cx_resz_tag_w0[6:0]), + .cx_resz_tag_w0m1 (cx_resz_tag_w0m1[6:0]), + .cx_resz_tag_w1 (cx_resz_tag_w1[6:0]), + .cx_resz_tag_w2 (cx_resz_tag_w2[6:0]), + .cx_sx_ldxcancel_sel_jw1 (cx_sx_ldxcancel_sel_jw1), + .cx_sx_ldxcancel_sel_kw1 (cx_sx_ldxcancel_sel_kw1), + .cx_sx_resp_tag_jw1 (cx_sx_resp_tag_jw1[4:0]), + .cx_sx_resp_tag_jw2 (cx_sx_resp_tag_jw2[4:0]), + .cx_sx_resp_tag_kw1 (cx_sx_resp_tag_kw1[4:0]), + .cx_sx_resp_tag_kw2 (cx_sx_resp_tag_kw2[4:0]), + .cx_sx_resp_tag_vld_jw1 (cx_sx_resp_tag_vld_jw1), + .cx_sx_resp_tag_vld_jw2 (cx_sx_resp_tag_vld_jw2), + .cx_sx_resp_tag_vld_kw1 (cx_sx_resp_tag_vld_kw1), + .cx_sx_resp_tag_vld_kw2 (cx_sx_resp_tag_vld_kw2), + .dn_raw_e1_q (dn_raw_e1_q), + .fdiv_busy_q (fdiv_busy_q[1:0]), + .fdiv_done_hold (fdiv_done_hold[1:0]), + .fdiv_flush (fdiv_flush[1:0]), + .fdiv_scalar (fdiv_scalar[1:0]), + .fsqrt_busy_q (fsqrt_busy_q[1:0]), + .fsqrt_done_hold (fsqrt_done_hold[1:0]), + .fsqrt_flush (fsqrt_flush[1:0]), + .fsqrt_scalar (fsqrt_scalar[1:0]), + .fz_raw_e1_q (fz_raw_e1_q), + .iqj_flush_gid (iqj_flush_gid[6:0]), + .iqj_flush_u2 (iqj_flush_u2), + .iqk_flush_gid (iqk_flush_gid[6:0]), + .iqk_flush_u2 (iqk_flush_u2), + .rmode_fpscr_e1_q (rmode_fpscr_e1_q[1:0]), + + // inputs + .ccpass_ke2 (ccpass_ke2), + .ck_areset (ck_areset), + .ck_gclkcx (ck_gclkcx), + .ck_reset1_n_cx (ck_reset1_n_cx), + .crypt2_active (crypt2_active), + .crypt3_active (crypt3_active), + .cx_acc_type_je1 (cx_acc_type_je1[3:0]), + .cx_acc_type_ke1 (cx_acc_type_ke1[3:0]), + .cx_ccpass_je1 (cx_ccpass_je1), + .cx_ccpass_ke1 (cx_ccpass_ke1), + .cx_dst_sel_je1 (cx_dst_sel_je1[4:0]), + .cx_dst_sel_ke1 (cx_dst_sel_ke1[4:0]), + .cx_dstp_tag_je1 (cx_dstp_tag_je1[4:0]), + .cx_dstp_tag_ke1 (cx_dstp_tag_ke1[4:0]), + .cx_dstp_tag_vld_je1 (cx_dstp_tag_vld_je1), + .cx_dstp_tag_vld_ke1 (cx_dstp_tag_vld_ke1), + .cx_dstx_dw_je1 (cx_dstx_dw_je1), + .cx_dstx_dw_ke1 (cx_dstx_dw_ke1), + .cx_dstx_tag_je1 (cx_dstx_tag_je1[6:0]), + .cx_dstx_tag_ke1 (cx_dstx_tag_ke1[6:0]), + .cx_dstx_tag_vld_je1 (cx_dstx_tag_vld_je1), + .cx_dstx_tag_vld_ke1 (cx_dstx_tag_vld_ke1), + .cx_dsty_dw_je1 (cx_dsty_dw_je1), + .cx_dsty_dw_ke1 (cx_dsty_dw_ke1), + .cx_dsty_tag_je1 (cx_dsty_tag_je1[6:0]), + .cx_dsty_tag_ke1 (cx_dsty_tag_ke1[6:0]), + .cx_dsty_tag_vld_je1 (cx_dsty_tag_vld_je1), + .cx_dsty_tag_vld_ke1 (cx_dsty_tag_vld_ke1), + .cx_gid_je1 (cx_gid_je1[6:0]), + .cx_gid_ke1 (cx_gid_ke1[6:0]), + .cx_region_je1 (cx_region_je1[2:0]), + .cx_region_ke1 (cx_region_ke1[2:0]), + .cx_uop_res_latency_je1 (cx_uop_res_latency_je1[2:0]), + .cx_uop_res_latency_ke1 (cx_uop_res_latency_ke1[2:0]), + .dftrstdisable_cpu (dftrstdisable_cpu), + .dftse_cpu (dftse_cpu), + .ds_cx_cpuactlr_frc_cpu_rcg_active (ds_cx_cpuactlr_frc_cpu_rcg_active), + .ds_cx_flush_gid (ds_cx_flush_gid[6:0]), + .ds_cx_flush_seq (ds_cx_flush_seq), + .ds_cx_flush_u1 (ds_cx_flush_u1), + .ds_cx_fpscr_ahp (ds_cx_fpscr_ahp), + .ds_cx_fpscr_dn (ds_cx_fpscr_dn), + .ds_cx_fpscr_fz (ds_cx_fpscr_fz), + .ds_cx_fpscr_rmode (ds_cx_fpscr_rmode[1:0]), + .fadd32_ex_h_je4 (fadd32_ex_h_je4[5:0]), + .fadd32_ex_h_ke4 (fadd32_ex_h_ke4[5:0]), + .fadd32_ex_l_je4 (fadd32_ex_l_je4[5:0]), + .fadd32_ex_l_ke4 (fadd32_ex_l_ke4[5:0]), + .fadd64_ex_je4 (fadd64_ex_je4[5:0]), + .fadd64_ex_ke4 (fadd64_ex_ke4[5:0]), + .fadd_vld_je4 (fadd_vld_je4[2:0]), + .fadd_vld_ke4 (fadd_vld_ke4[2:0]), + .faddj_active (addj_active), + .faddk_active (addk_active), + .fcvt_ex_h_je3 (fcvt_ex_h_e3[5:0]), + .fcvt_ex_l_je3 (fcvt_ex_l_e3[5:0]), + .fcvt_vld_je3 (fcvt_vld_je3[1:0]), + .fcvtj_active (cvtj_active), + .fdiv_done (fdiv_done[1:0]), + .fdiv_done_ack (fdiv_done_ack[1:0]), + .fdiv_scalar_je1 (fdiv_scalar_je1), + .fdiv_uop_vld_je1 (fdiv_uop_vld_je1[1:0]), + .fdivexc32_q (fdivexc32_q[5:0]), + .fdivexc64_q (fdivexc64_q[5:0]), + .fdivj_active (fdiv_active), + .fmul32_ex_h_je4 (fmul32_ex_h_je4[4:0]), + .fmul32_ex_h_ke4 (fmul32_ex_h_ke4[4:0]), + .fmul32_ex_l_je4 (fmul32_ex_l_je4[4:0]), + .fmul32_ex_l_ke4 (fmul32_ex_l_ke4[4:0]), + .fmul64_ex_je4 (fmul64_ex_je4[4:0]), + .fmul64_ex_ke4 (fmul64_ex_ke4[4:0]), + .fmul_vld_je4 (fmul_vld_je4[2:0]), + .fmul_vld_ke4 (fmul_vld_ke4[2:0]), + .fmulj_active (fmulj_active), + .fmulk_active (fmulk_active), + .fsqrt_done (fsqrt_done[1:0]), + .fsqrt_done_ack (fsqrt_done_ack[1:0]), + .fsqrt_scalar_ke1 (fsqrt_scalar_ke1), + .fsqrt_uop_vld_ke1 (fsqrt_uop_vld_ke1[1:0]), + .fsqrtexc32_q (fsqrtexc32_q[5:0]), + .fsqrtexc64_q (fsqrtexc64_q[5:0]), + .fsqrtk_active (fsqrt_active), + .ialu_fpex_je3_q (ialu_fpex_je3_q[4:0]), + .ialu_fpex_ke3_q (ialu_fpex_ke3_q[4:0]), + .ialu_nzcv_ke3_q (ialu_nzcv_ke3_q[3:0]), + .ialu_qc_je3_q (ialu_qc_je3_q), + .ialu_qc_ke3_q (ialu_qc_ke3_q), + .ialu_qc_vld_je2 (ialu_qc_vld_je2), + .ialu_qc_vld_ke2 (ialu_qc_vld_ke2), + .ialuj_active (ialuj_active), + .ialuk_active (ialuk_active), + .imac_qc_e4_q (imac_qc_e4_q), + .imac_qc_vld_e3 (imac_qc_vld_e3), + .imacj_active (imac_active), + .iredk_active (iredk_active), + .ishf_qc_e4_q (ishf_qc_e4_q), + .ishf_qc_vld_e3 (ishf_qc_vld_e3), + .ishfk_active (ishf_active), + .issq_active (issq_active), + .issq_crypt_active (issq_crypt_active), + .issq_floatj_active (issq_floatj_active), + .issq_floatk_active (issq_floatk_active), + .issq_intj_active (issq_intj_active), + .issq_intk_active (issq_intk_active), + .ls_resx_data_cancel_w1 (ls_resx_data_cancel_w1), + .ls_resx_data_cancel_w2 (ls_resx_data_cancel_w2), + .ls_resx_dw_w0 (ls_resx_dw_w0), + .ls_resx_dw_w1 (ls_resx_dw_w1), + .ls_resx_tag_vld_w0 (ls_resx_tag_vld_w0), + .ls_resx_tag_vld_w1 (ls_resx_tag_vld_w1), + .ls_resx_tag_w0 (ls_resx_tag_w0[6:0]), + .ls_resx_tag_w1 (ls_resx_tag_w1[6:0]), + .ls_resy_data_cancel_w1 (ls_resy_data_cancel_w1), + .ls_resy_data_cancel_w2 (ls_resy_data_cancel_w2), + .ls_resy_dw_w0 (ls_resy_dw_w0), + .ls_resy_dw_w1 (ls_resy_dw_w1), + .ls_resy_tag_vld_w0 (ls_resy_tag_vld_w0), + .ls_resy_tag_vld_w1 (ls_resy_tag_vld_w1), + .ls_resy_tag_w0 (ls_resy_tag_w0[6:0]), + .ls_resy_tag_w1 (ls_resy_tag_w1[6:0]), + .mx_resp_tag_vld_w0 (mx_resp_tag_vld_w0), + .mx_resp_tag_vld_w1 (mx_resp_tag_vld_w1), + .mx_resp_tag_w0 (mx_resp_tag_w0[4:0]), + .mx_resp_tag_w1 (mx_resp_tag_w1[4:0]), + .sx_ldxcancel_sel_jw0 (sx_ldxcancel_sel_jw0), + .sx_ldxcancel_sel_jw1 (sx_ldxcancel_sel_jw1), + .sx_ldxcancel_sel_kw0 (sx_ldxcancel_sel_kw0), + .sx_ldxcancel_sel_kw1 (sx_ldxcancel_sel_kw1), + .sx_resp_tag_jw0 (sx_resp_tag_jw0[4:0]), + .sx_resp_tag_jw1 (sx_resp_tag_jw1[4:0]), + .sx_resp_tag_kw0 (sx_resp_tag_kw0[4:0]), + .sx_resp_tag_kw1 (sx_resp_tag_kw1[4:0]), + .sx_resp_tag_vld_jw0 (sx_resp_tag_vld_jw0), + .sx_resp_tag_vld_jw1 (sx_resp_tag_vld_jw1), + .sx_resp_tag_vld_kw0 (sx_resp_tag_vld_kw0), + .sx_resp_tag_vld_kw1 (sx_resp_tag_vld_kw1), + .sx_uop_vld_jw0 (sx_uop_vld_jw0), + .sx_uop_vld_kw0 (sx_uop_vld_kw0) + ); // urb + + maia_cx_rb_dp urb_dp( // outputs + .cx_fadd_srca_fp_data32_je1 (cx_fadd_srca_fp_data32_je1[63:0]), + .cx_fadd_srca_fp_data32_ke1 (cx_fadd_srca_fp_data32_ke1[63:0]), + .cx_fadd_srca_fp_data64_je1 (cx_fadd_srca_fp_data64_je1[63:0]), + .cx_fadd_srca_fp_data64_ke1 (cx_fadd_srca_fp_data64_ke1[63:0]), + .cx_fadd_srcb_fp_data32_h_je1 (cx_fadd_srcb_fp_data32_h_je1[55:0]), + .cx_fadd_srcb_fp_data32_h_ke1 (cx_fadd_srcb_fp_data32_h_ke1[55:0]), + .cx_fadd_srcb_fp_data32_l_je1 (cx_fadd_srcb_fp_data32_l_je1[55:0]), + .cx_fadd_srcb_fp_data32_l_ke1 (cx_fadd_srcb_fp_data32_l_ke1[55:0]), + .cx_fadd_srcb_fp_data64_je1 (cx_fadd_srcb_fp_data64_je1[116:0]), + .cx_fadd_srcb_fp_data64_ke1 (cx_fadd_srcb_fp_data64_ke1[116:0]), + .cx_fadd_srcc_fp_data32_je1 (cx_fadd_srcc_fp_data32_je1[63:0]), + .cx_fadd_srcc_fp_data32_ke1 (cx_fadd_srcc_fp_data32_ke1[63:0]), + .cx_fadd_srcc_fp_data64_je1 (cx_fadd_srcc_fp_data64_je1[31:0]), + .cx_fadd_srcc_fp_data64_ke1 (cx_fadd_srcc_fp_data64_ke1[31:0]), + .cx_fadd_srcd_fp_data64_je1 (cx_fadd_srcd_fp_data64_je1[31:0]), + .cx_fadd_srcd_fp_data64_ke1 (cx_fadd_srcd_fp_data64_ke1[31:0]), + .cx_fmul_srca_fp_data32_je1 (cx_fmul_srca_fp_data32_je1[63:0]), + .cx_fmul_srca_fp_data32_ke1 (cx_fmul_srca_fp_data32_ke1[63:0]), + .cx_fmul_srcb_fp_data32_je1 (cx_fmul_srcb_fp_data32_je1[63:0]), + .cx_fmul_srcb_fp_data32_ke1 (cx_fmul_srcb_fp_data32_ke1[63:0]), + .cx_resx_data_w2 (cx_resx_data_w2[63:0]), + .cx_resy_data_w2 (cx_resy_data_w2[63:0]), + .cx_resz_data_w2 (cx_resz_data_w2[63:0]), + .cx_srca_crypt_data_je1 (cx_srca_crypt_data_je1[63:0]), + .cx_srca_fp_data32_je1 (cx_srca_fp_data32_je1[63:0]), + .cx_srca_fp_data32_ke1 (cx_srca_fp_data32_ke1[63:0]), + .cx_srca_fp_data64_je1 (cx_srca_fp_data64_je1[63:0]), + .cx_srca_fp_data64_ke1 (cx_srca_fp_data64_ke1[63:0]), + .cx_srca_int_data_je1 (cx_srca_int_data_je1[63:0]), + .cx_srca_int_data_ke1 (cx_srca_int_data_ke1[63:0]), + .cx_srcb_crypt_data_je1 (cx_srcb_crypt_data_je1[63:0]), + .cx_srcb_fp_data32_je1 (cx_srcb_fp_data32_je1[63:0]), + .cx_srcb_fp_data64_je1 (cx_srcb_fp_data64_je1[63:0]), + .cx_srcb_fp_data64_ke1 (cx_srcb_fp_data64_ke1[63:0]), + .cx_srcb_int_data_je1 (cx_srcb_int_data_je1[63:0]), + .cx_srcb_int_data_ke1 (cx_srcb_int_data_ke1[63:0]), + .cx_srcc_crypt_data_je1 (cx_srcc_crypt_data_je1[63:0]), + .cx_srcc_fp_data32_je1 (cx_srcc_fp_data32_je1[63:0]), + .cx_srcc_fp_data32_ke1 (cx_srcc_fp_data32_ke1[63:0]), + .cx_srcc_int_data_je1 (cx_srcc_int_data_je1[63:0]), + .cx_srcc_int_data_ke1 (cx_srcc_int_data_ke1[63:0]), + .cx_srcd_crypt_data_je1 (cx_srcd_crypt_data_je1[63:0]), + .cx_srcd_fp_data32_je1 (cx_srcd_fp_data32_je1[31:0]), + .cx_srcd_fp_data32_ke1 (cx_srcd_fp_data32_ke1[31:0]), + .cx_srcd_int_data_je1 (cx_srcd_int_data_je1[63:0]), + .cx_srcd_int_data_ke1 (cx_srcd_int_data_ke1[63:0]), + + // inputs + .ck_gclkcx (ck_gclkcx), + .crypt2_out_e3_q (crypt2_out_e3_q[127:0]), + .crypt3_out_e6_q (crypt3_out_e6_q[127:0]), + .cx_ctl_dp_fp_valid_ji1 (cx_ctl_dp_fp_valid_ji1), + .cx_ctl_dp_fp_valid_ki1 (cx_ctl_dp_fp_valid_ki1), + .cx_ctl_dp_int_valid_ji1 (cx_ctl_dp_int_valid_ji1), + .cx_ctl_dp_int_valid_ki1 (cx_ctl_dp_int_valid_ki1), + .cx_reset3 (cx_reset3), + .cx_resx_dw_w1 (cx_resx_dw_w1), + .cx_resx_sel_dec_jw0 (cx_resx_sel_dec_jw0[49:32]), + .cx_resx_sel_dec_kw0 (cx_resx_sel_dec_kw0[13:0]), + .cx_resx_selj_w0 (cx_resx_selj_w0), + .cx_resx_tag_vld_w0 (cx_resx_tag_vld_w0), + .cx_resx_tag_vld_w1 (cx_resx_tag_vld_w1), + .cx_resy_dw_w1 (cx_resy_dw_w1), + .cx_resy_sel_dec_jw0 (cx_resy_sel_dec_jw0[49:32]), + .cx_resy_sel_dec_kw0 (cx_resy_sel_dec_kw0[13:0]), + .cx_resy_selj_w0 (cx_resy_selj_w0), + .cx_resy_tag_vld_w0 (cx_resy_tag_vld_w0), + .cx_resy_tag_vld_w1 (cx_resy_tag_vld_w1), + .cx_resz_dw_w1 (cx_resz_dw_w1), + .cx_resz_sel_dec_jw0 (cx_resz_sel_dec_jw0[49:32]), + .cx_resz_sel_dec_kw0 (cx_resz_sel_dec_kw0[13:0]), + .cx_resz_selj_w0 (cx_resz_selj_w0), + .cx_resz_tag_vld_w0 (cx_resz_tag_vld_w0), + .cx_resz_tag_vld_w1 (cx_resz_tag_vld_w1), + .cx_srca_data_ji1 (cx_srca_data_ji1[63:0]), + .cx_srca_data_ki1 (cx_srca_data_ki1[63:0]), + .cx_srca_fp_h_en_ji1 (cx_srca_fp_h_en_ji1), + .cx_srca_fp_h_en_ki1 (cx_srca_fp_h_en_ki1), + .cx_srca_fp_l_en_ji1 (cx_srca_fp_l_en_ji1), + .cx_srca_fp_l_en_ki1 (cx_srca_fp_l_en_ki1), + .cx_srca_int_h_en_ji1 (cx_srca_int_h_en_ji1), + .cx_srca_int_h_en_ki1 (cx_srca_int_h_en_ki1), + .cx_srca_int_l_en_ji1 (cx_srca_int_l_en_ji1), + .cx_srca_int_l_en_ki1 (cx_srca_int_l_en_ki1), + .cx_srcb_data_ji1 (cx_srcb_data_ji1[63:0]), + .cx_srcb_data_ki1 (cx_srcb_data_ki1[63:0]), + .cx_srcb_fp_h_en_ji1 (cx_srcb_fp_h_en_ji1), + .cx_srcb_fp_h_en_ki1 (cx_srcb_fp_h_en_ki1), + .cx_srcb_fp_l_en_ji1 (cx_srcb_fp_l_en_ji1), + .cx_srcb_fp_l_en_ki1 (cx_srcb_fp_l_en_ki1), + .cx_srcb_int_h_en_ji1 (cx_srcb_int_h_en_ji1), + .cx_srcb_int_h_en_ki1 (cx_srcb_int_h_en_ki1), + .cx_srcb_int_l_en_ji1 (cx_srcb_int_l_en_ji1), + .cx_srcb_int_l_en_ki1 (cx_srcb_int_l_en_ki1), + .cx_srcc_data_ji1 (cx_srcc_data_ji1[63:0]), + .cx_srcc_data_ki1 (cx_srcc_data_ki1[63:0]), + .cx_srcc_fp_h_en_ji1 (cx_srcc_fp_h_en_ji1), + .cx_srcc_fp_h_en_ki1 (cx_srcc_fp_h_en_ki1), + .cx_srcc_fp_l_en_ji1 (cx_srcc_fp_l_en_ji1), + .cx_srcc_fp_l_en_ki1 (cx_srcc_fp_l_en_ki1), + .cx_srcc_int_h_en_ji1 (cx_srcc_int_h_en_ji1), + .cx_srcc_int_h_en_ki1 (cx_srcc_int_h_en_ki1), + .cx_srcc_int_l_en_ji1 (cx_srcc_int_l_en_ji1), + .cx_srcc_int_l_en_ki1 (cx_srcc_int_l_en_ki1), + .cx_srcd_data_ji1 (cx_srcd_data_ji1[63:0]), + .cx_srcd_data_ki1 (cx_srcd_data_ki1[63:0]), + .cx_srcd_fp_h_en_ji1 (cx_srcd_fp_h_en_ji1), + .cx_srcd_fp_h_en_ki1 (cx_srcd_fp_h_en_ki1), + .cx_srcd_fp_l_en_ji1 (cx_srcd_fp_l_en_ji1), + .cx_srcd_fp_l_en_ki1 (cx_srcd_fp_l_en_ki1), + .cx_srcd_int_h_en_ji1 (cx_srcd_int_h_en_ji1), + .cx_srcd_int_h_en_ki1 (cx_srcd_int_h_en_ki1), + .cx_srcd_int_l_en_ji1 (cx_srcd_int_l_en_ji1), + .cx_srcd_int_l_en_ki1 (cx_srcd_int_l_en_ki1), + .cx_uop_vld_ji1 (cx_uop_vld_ji1), + .cx_uop_vld_ki1 (cx_uop_vld_ki1), + .fadd_srca_sel_h_je1 (fadd_srca_sel_h_je1[2:0]), + .fadd_srca_sel_h_ke1 (fadd_srca_sel_h_ke1[2:0]), + .fadd_srca_sel_l_je1 (fadd_srca_sel_l_je1), + .fadd_srca_sel_l_ke1 (fadd_srca_sel_l_ke1), + .fadd_srcb_sel_h_je1 (fadd_srcb_sel_h_je1[2:0]), + .fadd_srcb_sel_h_ke1 (fadd_srcb_sel_h_ke1[2:0]), + .fadd_srcb_sel_l_je1 (fadd_srcb_sel_l_je1[2:0]), + .fadd_srcb_sel_l_ke1 (fadd_srcb_sel_l_ke1[2:0]), + .fadd_vld_je4 (fadd_vld_je4[0]), + .fadd_vld_ke4 (fadd_vld_ke4[0]), + .faddout32_h_je4 (faddout32_h_je4[31:0]), + .faddout32_h_ke4 (faddout32_h_ke4[31:0]), + .faddout32_l_je4 (faddout32_l_je4[31:0]), + .faddout32_l_ke4 (faddout32_l_ke4[31:0]), + .faddout64_je4 (faddout64_je4[63:0]), + .faddout64_ke4 (faddout64_ke4[63:0]), + .fcvtout_je3 (fcvtout_e3[127:0]), + .fdivout32_q (fdivout32_q[31:0]), + .fdivout64_q (fdivout64_q[63:0]), + .fmla_acc_je4 (fmla_acc_je4[63:0]), + .fmla_acc_ke4 (fmla_acc_ke4[63:0]), + .fmla_fwd_je3 (fmla_fwd_je3[1:0]), + .fmla_fwd_je4 (fmla_fwd_je4[1:0]), + .fmla_fwd_ke3 (fmla_fwd_ke3[1:0]), + .fmla_fwd_ke4 (fmla_fwd_ke4[1:0]), + .fmla_je3 (fmla_je3), + .fmla_je4 (fmla_je4), + .fmla_ke3 (fmla_ke3), + .fmla_ke4 (fmla_ke4), + .fmul_srca_sel_l_je1 (fmul_srca_sel_l_je1), + .fmul_srca_sel_l_ke1 (fmul_srca_sel_l_ke1), + .fmul_srcb_sel_h_je1 (fmul_srcb_sel_h_je1), + .fmul_srcb_sel_h_ke1 (fmul_srcb_sel_h_ke1), + .fmul_srcb_sel_l_je1 (fmul_srcb_sel_l_je1), + .fmul_srcb_sel_l_ke1 (fmul_srcb_sel_l_ke1), + .fmul_vld_je4 (fmul_vld_je4[0]), + .fmul_vld_ke4 (fmul_vld_ke4[0]), + .fmulout32_h_je4 (fmulout32_h_je4[55:0]), + .fmulout32_h_ke4 (fmulout32_h_ke4[55:0]), + .fmulout32_l_je4 (fmulout32_l_je4[55:0]), + .fmulout32_l_ke4 (fmulout32_l_ke4[55:0]), + .fmulout64_je4 (fmulout64_je4[116:0]), + .fmulout64_ke4 (fmulout64_ke4[116:0]), + .fsqrtout32_q (fsqrtout32_q[31:0]), + .fsqrtout64_q (fsqrtout64_q[63:0]), + .ialuout_je3_q (ialuout_je3_q[127:0]), + .ialuout_ke3_q (ialuout_ke3_q[127:0]), + .iredout_ke3_q (iredout_ke2[63:0]), + .ishfaccout_e4_q (ishfaccout_e4_q[127:0]), + .ishfout_e3_q (ishfout_e3_q[127:0]), + .iwbout_e4_q (iwbout_e4_q[127:0]), + .ls_resx_data_w2 (ls_resx_data_w2[63:0]), + .ls_resy_data_w2 (ls_resy_data_w2[63:0]), + .lspout_je3_q (lspout_je3_q[127:0]), + .lspout_ke3_q (lspout_ke3_q[127:0]), + .srca_dec_hi_sel_ji1 (srca_dec_hi_sel_ji1[11:1]), + .srca_dec_hi_sel_ki1 (srca_dec_hi_sel_ki1[11:1]), + .srca_dec_sel_ji1 (srca_dec_sel_ji1[11:1]), + .srca_dec_sel_ki1 (srca_dec_sel_ki1[11:1]), + .srca_hi_sel_ji1 (srca_hi_sel_ji1), + .srca_hi_sel_ki1 (srca_hi_sel_ki1), + .srcb_dec_hi_sel_ji1 (srcb_dec_hi_sel_ji1[11:1]), + .srcb_dec_hi_sel_ki1 (srcb_dec_hi_sel_ki1[11:1]), + .srcb_dec_sel_ji1 (srcb_dec_sel_ji1[11:1]), + .srcb_dec_sel_ki1 (srcb_dec_sel_ki1[11:1]), + .srcb_hi_sel_ji1 (srcb_hi_sel_ji1), + .srcb_hi_sel_ki1 (srcb_hi_sel_ki1), + .srcc_dec_hi_sel_ji1 (srcc_dec_hi_sel_ji1[11:1]), + .srcc_dec_hi_sel_ki1 (srcc_dec_hi_sel_ki1[11:1]), + .srcc_dec_sel_ji1 (srcc_dec_sel_ji1[11:1]), + .srcc_dec_sel_ki1 (srcc_dec_sel_ki1[11:1]), + .srcc_hi_sel_ji1 (srcc_hi_sel_ji1), + .srcc_hi_sel_ki1 (srcc_hi_sel_ki1), + .srcd_dec_hi_sel_ji1 (srcd_dec_hi_sel_ji1[11:1]), + .srcd_dec_hi_sel_ki1 (srcd_dec_hi_sel_ki1[11:1]), + .srcd_dec_sel_ji1 (srcd_dec_sel_ji1[11:1]), + .srcd_dec_sel_ki1 (srcd_dec_sel_ki1[11:1]), + .srcd_hi_sel_ji1 (srcd_hi_sel_ji1), + .srcd_hi_sel_ki1 (srcd_hi_sel_ki1) + ); // urb_dp + + maia_cx_issq_top uissq_top( // outputs + .cx_acc_type_je1 (cx_acc_type_je1[3:0]), + .cx_acc_type_ke1 (cx_acc_type_ke1[3:0]), + .cx_credit_j (cx_credit_j[2:0]), + .cx_credit_k (cx_credit_k[2:0]), + .cx_ctl_dp_fp_valid_ji1 (cx_ctl_dp_fp_valid_ji1), + .cx_ctl_dp_fp_valid_ki1 (cx_ctl_dp_fp_valid_ki1), + .cx_ctl_dp_int_valid_ji1 (cx_ctl_dp_int_valid_ji1), + .cx_ctl_dp_int_valid_ki1 (cx_ctl_dp_int_valid_ki1), + .cx_dstp_tag_je1 (cx_dstp_tag_je1[4:0]), + .cx_dstp_tag_ke1 (cx_dstp_tag_ke1[4:0]), + .cx_dstp_tag_vld_je1 (cx_dstp_tag_vld_je1), + .cx_dstp_tag_vld_ke1 (cx_dstp_tag_vld_ke1), + .cx_dstx_dw_je1 (cx_dstx_dw_je1), + .cx_dstx_dw_ke1 (cx_dstx_dw_ke1), + .cx_dstx_tag_je1 (cx_dstx_tag_je1[6:0]), + .cx_dstx_tag_ke1 (cx_dstx_tag_ke1[6:0]), + .cx_dstx_tag_vld_je1 (cx_dstx_tag_vld_je1), + .cx_dstx_tag_vld_ke1 (cx_dstx_tag_vld_ke1), + .cx_dsty_dw_je1 (cx_dsty_dw_je1), + .cx_dsty_dw_ke1 (cx_dsty_dw_ke1), + .cx_dsty_tag_je1 (cx_dsty_tag_je1[6:0]), + .cx_dsty_tag_ke1 (cx_dsty_tag_ke1[6:0]), + .cx_dsty_tag_vld_je1 (cx_dsty_tag_vld_je1), + .cx_dsty_tag_vld_ke1 (cx_dsty_tag_vld_ke1), + .cx_gid_je1 (cx_gid_je1[6:0]), + .cx_gid_ke1 (cx_gid_ke1[6:0]), + .cx_mla_fwd_sel_je1 (cx_mla_fwd_sel_je1[4:0]), + .cx_mla_fwd_sel_ke1 (cx_mla_fwd_sel_ke1[4:0]), + .cx_region_je1 (cx_region_je1[2:0]), + .cx_region_ke1 (cx_region_ke1[2:0]), + .cx_res128_je1 (cx_res128_je1), + .cx_res128_ke1 (cx_res128_ke1), + .cx_srca_data_ji1 (cx_srca_data_ji1[63:0]), + .cx_srca_data_ki1 (cx_srca_data_ki1[63:0]), + .cx_srca_en_je1 (cx_srca_en_je1), + .cx_srca_en_ke1 (cx_srca_en_ke1), + .cx_srca_fp_h_en_ji1 (cx_srca_fp_h_en_ji1), + .cx_srca_fp_h_en_ki1 (cx_srca_fp_h_en_ki1), + .cx_srca_fp_l_en_ji1 (cx_srca_fp_l_en_ji1), + .cx_srca_fp_l_en_ki1 (cx_srca_fp_l_en_ki1), + .cx_srca_int_h_en_ji1 (cx_srca_int_h_en_ji1), + .cx_srca_int_h_en_ki1 (cx_srca_int_h_en_ki1), + .cx_srca_int_l_en_ji1 (cx_srca_int_l_en_ji1), + .cx_srca_int_l_en_ki1 (cx_srca_int_l_en_ki1), + .cx_srcb_data_ji1 (cx_srcb_data_ji1[63:0]), + .cx_srcb_data_ki1 (cx_srcb_data_ki1[63:0]), + .cx_srcb_en_je1 (cx_srcb_en_je1), + .cx_srcb_en_ke1 (cx_srcb_en_ke1), + .cx_srcb_fp_h_en_ji1 (cx_srcb_fp_h_en_ji1), + .cx_srcb_fp_h_en_ki1 (cx_srcb_fp_h_en_ki1), + .cx_srcb_fp_l_en_ji1 (cx_srcb_fp_l_en_ji1), + .cx_srcb_fp_l_en_ki1 (cx_srcb_fp_l_en_ki1), + .cx_srcb_int_h_en_ji1 (cx_srcb_int_h_en_ji1), + .cx_srcb_int_h_en_ki1 (cx_srcb_int_h_en_ki1), + .cx_srcb_int_l_en_ji1 (cx_srcb_int_l_en_ji1), + .cx_srcb_int_l_en_ki1 (cx_srcb_int_l_en_ki1), + .cx_srcc_data_ji1 (cx_srcc_data_ji1[63:0]), + .cx_srcc_data_ki1 (cx_srcc_data_ki1[63:0]), + .cx_srcc_en_je1 (cx_srcc_en_je1), + .cx_srcc_en_ke1 (cx_srcc_en_ke1), + .cx_srcc_fp_h_en_ji1 (cx_srcc_fp_h_en_ji1), + .cx_srcc_fp_h_en_ki1 (cx_srcc_fp_h_en_ki1), + .cx_srcc_fp_l_en_ji1 (cx_srcc_fp_l_en_ji1), + .cx_srcc_fp_l_en_ki1 (cx_srcc_fp_l_en_ki1), + .cx_srcc_int_h_en_ji1 (cx_srcc_int_h_en_ji1), + .cx_srcc_int_h_en_ki1 (cx_srcc_int_h_en_ki1), + .cx_srcc_int_l_en_ji1 (cx_srcc_int_l_en_ji1), + .cx_srcc_int_l_en_ki1 (cx_srcc_int_l_en_ki1), + .cx_srcd_data_ji1 (cx_srcd_data_ji1[63:0]), + .cx_srcd_data_ki1 (cx_srcd_data_ki1[63:0]), + .cx_srcd_en_je1 (cx_srcd_en_je1), + .cx_srcd_en_ke1 (cx_srcd_en_ke1), + .cx_srcd_fp_h_en_ji1 (cx_srcd_fp_h_en_ji1), + .cx_srcd_fp_h_en_ki1 (cx_srcd_fp_h_en_ki1), + .cx_srcd_fp_l_en_ji1 (cx_srcd_fp_l_en_ji1), + .cx_srcd_fp_l_en_ki1 (cx_srcd_fp_l_en_ki1), + .cx_srcd_int_h_en_ji1 (cx_srcd_int_h_en_ji1), + .cx_srcd_int_h_en_ki1 (cx_srcd_int_h_en_ki1), + .cx_srcd_int_l_en_ji1 (cx_srcd_int_l_en_ji1), + .cx_srcd_int_l_en_ki1 (cx_srcd_int_l_en_ki1), + .cx_srcp_data_je1 (cx_srcp_data_je1[3:0]), + .cx_srcp_data_ke1 (cx_srcp_data_ke1[3:0]), + .cx_uop_ctl_ji1 (cx_uop_ctl_ji1[58:0]), + .cx_uop_ctl_ki1 (cx_uop_ctl_ki1[58:0]), + .cx_uop_vld_je1 (cx_uop_vld_je1), + .cx_uop_vld_ji1 (cx_uop_vld_ji1), + .cx_uop_vld_ke1 (cx_uop_vld_ke1), + .cx_uop_vld_ki1 (cx_uop_vld_ki1), + .fdiv_done_ack (fdiv_done_ack[1:0]), + .fdiv_uop_vld_je1 (fdiv_uop_vld_je1[1:0]), + .fsqrt_done_ack (fsqrt_done_ack[1:0]), + .fsqrt_uop_vld_ke1 (fsqrt_uop_vld_ke1[1:0]), + .issq_active (issq_active), + .issq_crypt_active (issq_crypt_active), + .issq_floatj_active (issq_floatj_active), + .issq_floatk_active (issq_floatk_active), + .issq_intj_active (issq_intj_active), + .issq_intk_active (issq_intk_active), + .srca_dec_hi_sel_ji1 (srca_dec_hi_sel_ji1[11:1]), + .srca_dec_hi_sel_ki1 (srca_dec_hi_sel_ki1[11:1]), + .srca_dec_sel_ji1 (srca_dec_sel_ji1[11:1]), + .srca_dec_sel_ki1 (srca_dec_sel_ki1[11:1]), + .srca_hi_sel_ji1 (srca_hi_sel_ji1), + .srca_hi_sel_ki1 (srca_hi_sel_ki1), + .srcb_dec_hi_sel_ji1 (srcb_dec_hi_sel_ji1[11:1]), + .srcb_dec_hi_sel_ki1 (srcb_dec_hi_sel_ki1[11:1]), + .srcb_dec_sel_ji1 (srcb_dec_sel_ji1[11:1]), + .srcb_dec_sel_ki1 (srcb_dec_sel_ki1[11:1]), + .srcb_hi_sel_ji1 (srcb_hi_sel_ji1), + .srcb_hi_sel_ki1 (srcb_hi_sel_ki1), + .srcc_dec_hi_sel_ji1 (srcc_dec_hi_sel_ji1[11:1]), + .srcc_dec_hi_sel_ki1 (srcc_dec_hi_sel_ki1[11:1]), + .srcc_dec_sel_ji1 (srcc_dec_sel_ji1[11:1]), + .srcc_dec_sel_ki1 (srcc_dec_sel_ki1[11:1]), + .srcc_hi_sel_ji1 (srcc_hi_sel_ji1), + .srcc_hi_sel_ki1 (srcc_hi_sel_ki1), + .srcd_dec_hi_sel_ji1 (srcd_dec_hi_sel_ji1[11:1]), + .srcd_dec_hi_sel_ki1 (srcd_dec_hi_sel_ki1[11:1]), + .srcd_dec_sel_ji1 (srcd_dec_sel_ji1[11:1]), + .srcd_dec_sel_ki1 (srcd_dec_sel_ki1[11:1]), + .srcd_hi_sel_ji1 (srcd_hi_sel_ji1), + .srcd_hi_sel_ki1 (srcd_hi_sel_ki1), + + // inputs + .ck_gclkcx (ck_gclkcx), + .crp3_vld_je1 (crp3_vld_je1), + .cx_acc_type_je2 (cx_acc_type_je2[3:1]), + .cx_acc_type_ke2 (cx_acc_type_ke2[3:1]), + .cx_dstx_tag_je2 (cx_dstx_tag_je2[6:0]), + .cx_dstx_tag_ke2 (cx_dstx_tag_ke2[6:0]), + .cx_ls_resx_data_cancel_w2 (cx_ls_resx_data_cancel_w2), + .cx_ls_resx_data_cancel_w3 (cx_ls_resx_data_cancel_w3), + .cx_ls_resx_dw_w1 (cx_ls_resx_dw_w1), + .cx_ls_resx_dw_w2 (cx_ls_resx_dw_w2), + .cx_ls_resx_tag_vld_w1 (cx_ls_resx_tag_vld_w1), + .cx_ls_resx_tag_vld_w2 (cx_ls_resx_tag_vld_w2), + .cx_ls_resx_tag_w1 (cx_ls_resx_tag_w1[6:0]), + .cx_ls_resx_tag_w2 (cx_ls_resx_tag_w2[6:0]), + .cx_ls_resy_data_cancel_w2 (cx_ls_resy_data_cancel_w2), + .cx_ls_resy_data_cancel_w3 (cx_ls_resy_data_cancel_w3), + .cx_ls_resy_dw_w1 (cx_ls_resy_dw_w1), + .cx_ls_resy_dw_w2 (cx_ls_resy_dw_w2), + .cx_ls_resy_tag_vld_w1 (cx_ls_resy_tag_vld_w1), + .cx_ls_resy_tag_vld_w2 (cx_ls_resy_tag_vld_w2), + .cx_ls_resy_tag_w1 (cx_ls_resy_tag_w1[6:0]), + .cx_ls_resy_tag_w2 (cx_ls_resy_tag_w2[6:0]), + .cx_mx_resp_tag_vld_w1 (cx_mx_resp_tag_vld_w1), + .cx_mx_resp_tag_vld_w2 (cx_mx_resp_tag_vld_w2), + .cx_mx_resp_tag_w1 (cx_mx_resp_tag_w1[4:0]), + .cx_mx_resp_tag_w2 (cx_mx_resp_tag_w2[4:0]), + .cx_reset3 (cx_reset3), + .cx_resp_data_w1 (cx_resp_data_w1[3:0]), + .cx_resp_data_w2 (cx_resp_data_w2[3:0]), + .cx_resp_tag_vld_w0 (cx_resp_tag_vld_w0), + .cx_resp_tag_vld_w1 (cx_resp_tag_vld_w1), + .cx_resp_tag_vld_w2 (cx_resp_tag_vld_w2), + .cx_resp_tag_w0 (cx_resp_tag_w0[4:0]), + .cx_resp_tag_w1 (cx_resp_tag_w1[4:0]), + .cx_resp_tag_w2 (cx_resp_tag_w2[4:0]), + .cx_resx_data_w2 (cx_resx_data_w2[63:0]), + .cx_resx_dw_w0 (cx_resx_dw_w0), + .cx_resx_dw_w0m1 (cx_resx_dw_w0m1), + .cx_resx_dw_w1 (cx_resx_dw_w1), + .cx_resx_dw_w2 (cx_resx_dw_w2), + .cx_resx_region_w0m1 (cx_resx_region_w0m1[2:0]), + .cx_resx_tag_vld_w0 (cx_resx_tag_vld_w0), + .cx_resx_tag_vld_w0m1 (cx_resx_tag_vld_w0m1), + .cx_resx_tag_vld_w1 (cx_resx_tag_vld_w1), + .cx_resx_tag_vld_w2 (cx_resx_tag_vld_w2), + .cx_resx_tag_w0 (cx_resx_tag_w0[6:0]), + .cx_resx_tag_w0m1 (cx_resx_tag_w0m1[6:0]), + .cx_resx_tag_w1 (cx_resx_tag_w1[6:0]), + .cx_resx_tag_w2 (cx_resx_tag_w2[6:0]), + .cx_resy_data_w2 (cx_resy_data_w2[63:0]), + .cx_resy_dw_w0 (cx_resy_dw_w0), + .cx_resy_dw_w0m1 (cx_resy_dw_w0m1), + .cx_resy_dw_w1 (cx_resy_dw_w1), + .cx_resy_dw_w2 (cx_resy_dw_w2), + .cx_resy_region_w0m1 (cx_resy_region_w0m1[2:0]), + .cx_resy_tag_vld_w0 (cx_resy_tag_vld_w0), + .cx_resy_tag_vld_w0m1 (cx_resy_tag_vld_w0m1), + .cx_resy_tag_vld_w1 (cx_resy_tag_vld_w1), + .cx_resy_tag_vld_w2 (cx_resy_tag_vld_w2), + .cx_resy_tag_w0 (cx_resy_tag_w0[6:0]), + .cx_resy_tag_w0m1 (cx_resy_tag_w0m1[6:0]), + .cx_resy_tag_w1 (cx_resy_tag_w1[6:0]), + .cx_resy_tag_w2 (cx_resy_tag_w2[6:0]), + .cx_resz_data_w2 (cx_resz_data_w2[63:0]), + .cx_resz_dw_w0 (cx_resz_dw_w0), + .cx_resz_dw_w0m1 (cx_resz_dw_w0m1), + .cx_resz_dw_w1 (cx_resz_dw_w1), + .cx_resz_dw_w2 (cx_resz_dw_w2), + .cx_resz_region_w0m1 (cx_resz_region_w0m1[2:0]), + .cx_resz_tag_vld_w0 (cx_resz_tag_vld_w0), + .cx_resz_tag_vld_w0m1 (cx_resz_tag_vld_w0m1), + .cx_resz_tag_vld_w1 (cx_resz_tag_vld_w1), + .cx_resz_tag_vld_w2 (cx_resz_tag_vld_w2), + .cx_resz_tag_w0 (cx_resz_tag_w0[6:0]), + .cx_resz_tag_w0m1 (cx_resz_tag_w0m1[6:0]), + .cx_resz_tag_w1 (cx_resz_tag_w1[6:0]), + .cx_resz_tag_w2 (cx_resz_tag_w2[6:0]), + .cx_sx_ldxcancel_sel_jw1 (cx_sx_ldxcancel_sel_jw1), + .cx_sx_ldxcancel_sel_kw1 (cx_sx_ldxcancel_sel_kw1), + .cx_sx_resp_tag_jw1 (cx_sx_resp_tag_jw1[4:0]), + .cx_sx_resp_tag_jw2 (cx_sx_resp_tag_jw2[4:0]), + .cx_sx_resp_tag_kw1 (cx_sx_resp_tag_kw1[4:0]), + .cx_sx_resp_tag_kw2 (cx_sx_resp_tag_kw2[4:0]), + .cx_sx_resp_tag_vld_jw1 (cx_sx_resp_tag_vld_jw1), + .cx_sx_resp_tag_vld_jw2 (cx_sx_resp_tag_vld_jw2), + .cx_sx_resp_tag_vld_kw1 (cx_sx_resp_tag_vld_kw1), + .cx_sx_resp_tag_vld_kw2 (cx_sx_resp_tag_vld_kw2), + .ds_cx_dstp_tag_jp2 (ds_cx_dstp_tag_jp2[4:0]), + .ds_cx_dstp_tag_kp2 (ds_cx_dstp_tag_kp2[4:0]), + .ds_cx_dstp_tag_vld_jp2 (ds_cx_dstp_tag_vld_jp2), + .ds_cx_dstp_tag_vld_kp2 (ds_cx_dstp_tag_vld_kp2), + .ds_cx_dstx_dw_jp2 (ds_cx_dstx_dw_jp2), + .ds_cx_dstx_dw_kp2 (ds_cx_dstx_dw_kp2), + .ds_cx_dstx_tag_jp2 (ds_cx_dstx_tag_jp2[6:0]), + .ds_cx_dstx_tag_kp2 (ds_cx_dstx_tag_kp2[6:0]), + .ds_cx_dstx_tag_vld_jp2 (ds_cx_dstx_tag_vld_jp2), + .ds_cx_dstx_tag_vld_kp2 (ds_cx_dstx_tag_vld_kp2), + .ds_cx_dsty_dw_jp2 (ds_cx_dsty_dw_jp2), + .ds_cx_dsty_dw_kp2 (ds_cx_dsty_dw_kp2), + .ds_cx_dsty_tag_jp2 (ds_cx_dsty_tag_jp2[6:0]), + .ds_cx_dsty_tag_kp2 (ds_cx_dsty_tag_kp2[6:0]), + .ds_cx_dsty_tag_vld_jp2 (ds_cx_dsty_tag_vld_jp2), + .ds_cx_dsty_tag_vld_kp2 (ds_cx_dsty_tag_vld_kp2), + .ds_cx_gid_jp2 (ds_cx_gid_jp2[6:0]), + .ds_cx_gid_kp2 (ds_cx_gid_kp2[6:0]), + .ds_cx_prt_sel_jp1 (ds_cx_prt_sel_jp1[2:0]), + .ds_cx_prt_sel_kp1 (ds_cx_prt_sel_kp1[2:0]), + .ds_cx_srca_data_jp2 (ds_cx_srca_data_jp2[63:0]), + .ds_cx_srca_data_kp2 (ds_cx_srca_data_kp2[63:0]), + .ds_cx_srca_data_vld_jp2 (ds_cx_srca_data_vld_jp2[1:0]), + .ds_cx_srca_data_vld_kp2 (ds_cx_srca_data_vld_kp2[1:0]), + .ds_cx_srcb_data_jp2 (ds_cx_srcb_data_jp2[63:0]), + .ds_cx_srcb_data_kp2 (ds_cx_srcb_data_kp2[63:0]), + .ds_cx_srcb_data_vld_jp2 (ds_cx_srcb_data_vld_jp2[1:0]), + .ds_cx_srcb_data_vld_kp2 (ds_cx_srcb_data_vld_kp2[1:0]), + .ds_cx_srcc_data_jp2 (ds_cx_srcc_data_jp2[63:0]), + .ds_cx_srcc_data_kp2 (ds_cx_srcc_data_kp2[63:0]), + .ds_cx_srcc_data_vld_jp2 (ds_cx_srcc_data_vld_jp2[1:0]), + .ds_cx_srcc_data_vld_kp2 (ds_cx_srcc_data_vld_kp2[1:0]), + .ds_cx_srcd_data_jp2 (ds_cx_srcd_data_jp2[63:0]), + .ds_cx_srcd_data_kp2 (ds_cx_srcd_data_kp2[63:0]), + .ds_cx_srcd_data_vld_jp2 (ds_cx_srcd_data_vld_jp2[1:0]), + .ds_cx_srcd_data_vld_kp2 (ds_cx_srcd_data_vld_kp2[1:0]), + .ds_cx_srcp_data_jp2 (ds_cx_srcp_data_jp2[3:0]), + .ds_cx_srcp_data_kp2 (ds_cx_srcp_data_kp2[3:0]), + .ds_cx_srcp_data_vld_jp2 (ds_cx_srcp_data_vld_jp2), + .ds_cx_srcp_data_vld_kp2 (ds_cx_srcp_data_vld_kp2), + .ds_cx_swdw_nuke_jp2 (ds_cx_swdw_nuke_jp2), + .ds_cx_swdw_nuke_kp2 (ds_cx_swdw_nuke_kp2), + .ds_cx_uop_ctl_jp2 (ds_cx_uop_ctl_jp2[58:0]), + .ds_cx_uop_ctl_kp2 (ds_cx_uop_ctl_kp2[58:0]), + .ds_cx_uop_vld_jp2 (ds_cx_uop_vld_jp2), + .ds_cx_uop_vld_kp2 (ds_cx_uop_vld_kp2), + .ds_srca_dw_0p1 (ds_srca_dw_0p1), + .ds_srca_dw_1p1 (ds_srca_dw_1p1), + .ds_srca_dw_2p1 (ds_srca_dw_2p1), + .ds_srca_prdcr_dw_0p1 (ds_srca_prdcr_dw_0p1), + .ds_srca_prdcr_dw_1p1 (ds_srca_prdcr_dw_1p1), + .ds_srca_prdcr_dw_2p1 (ds_srca_prdcr_dw_2p1), + .ds_srca_tag_0p1 (ds_srca_tag_0p1[6:0]), + .ds_srca_tag_1p1 (ds_srca_tag_1p1[6:0]), + .ds_srca_tag_2p1 (ds_srca_tag_2p1[6:0]), + .ds_srca_tag_vld_0p1 (ds_srca_tag_vld_0p1), + .ds_srca_tag_vld_1p1 (ds_srca_tag_vld_1p1), + .ds_srca_tag_vld_2p1 (ds_srca_tag_vld_2p1), + .ds_srcb_dw_0p1 (ds_srcb_dw_0p1), + .ds_srcb_dw_1p1 (ds_srcb_dw_1p1), + .ds_srcb_dw_2p1 (ds_srcb_dw_2p1), + .ds_srcb_prdcr_dw_0p1 (ds_srcb_prdcr_dw_0p1), + .ds_srcb_prdcr_dw_1p1 (ds_srcb_prdcr_dw_1p1), + .ds_srcb_prdcr_dw_2p1 (ds_srcb_prdcr_dw_2p1), + .ds_srcb_tag_0p1 (ds_srcb_tag_0p1[6:0]), + .ds_srcb_tag_1p1 (ds_srcb_tag_1p1[6:0]), + .ds_srcb_tag_2p1 (ds_srcb_tag_2p1[6:0]), + .ds_srcb_tag_vld_0p1 (ds_srcb_tag_vld_0p1), + .ds_srcb_tag_vld_1p1 (ds_srcb_tag_vld_1p1), + .ds_srcb_tag_vld_2p1 (ds_srcb_tag_vld_2p1), + .ds_srcc_dw_0p1 (ds_srcc_dw_0p1), + .ds_srcc_dw_1p1 (ds_srcc_dw_1p1), + .ds_srcc_dw_2p1 (ds_srcc_dw_2p1), + .ds_srcc_prdcr_dw_0p1 (ds_srcc_prdcr_dw_0p1), + .ds_srcc_prdcr_dw_1p1 (ds_srcc_prdcr_dw_1p1), + .ds_srcc_prdcr_dw_2p1 (ds_srcc_prdcr_dw_2p1), + .ds_srcc_tag_0p1 (ds_srcc_tag_0p1[6:0]), + .ds_srcc_tag_1p1 (ds_srcc_tag_1p1[6:0]), + .ds_srcc_tag_2p1 (ds_srcc_tag_2p1[6:0]), + .ds_srcc_tag_vld_0p1 (ds_srcc_tag_vld_0p1), + .ds_srcc_tag_vld_1p1 (ds_srcc_tag_vld_1p1), + .ds_srcc_tag_vld_2p1 (ds_srcc_tag_vld_2p1), + .ds_srcd_dw_0p1 (ds_srcd_dw_0p1), + .ds_srcd_dw_1p1 (ds_srcd_dw_1p1), + .ds_srcd_dw_2p1 (ds_srcd_dw_2p1), + .ds_srcd_prdcr_dw_0p1 (ds_srcd_prdcr_dw_0p1), + .ds_srcd_prdcr_dw_1p1 (ds_srcd_prdcr_dw_1p1), + .ds_srcd_prdcr_dw_2p1 (ds_srcd_prdcr_dw_2p1), + .ds_srcd_tag_0p1 (ds_srcd_tag_0p1[6:0]), + .ds_srcd_tag_1p1 (ds_srcd_tag_1p1[6:0]), + .ds_srcd_tag_2p1 (ds_srcd_tag_2p1[6:0]), + .ds_srcd_tag_vld_0p1 (ds_srcd_tag_vld_0p1), + .ds_srcd_tag_vld_1p1 (ds_srcd_tag_vld_1p1), + .ds_srcd_tag_vld_2p1 (ds_srcd_tag_vld_2p1), + .ds_srcp_tag_0p1 (ds_srcp_tag_0p1[4:0]), + .ds_srcp_tag_1p1 (ds_srcp_tag_1p1[4:0]), + .ds_srcp_tag_2p1 (ds_srcp_tag_2p1[4:0]), + .ds_srcp_tag_vld_0p1 (ds_srcp_tag_vld_0p1), + .ds_srcp_tag_vld_1p1 (ds_srcp_tag_vld_1p1), + .ds_srcp_tag_vld_2p1 (ds_srcp_tag_vld_2p1), + .fadd_hazard1_j (fadd_hazard1_j), + .fadd_hazard1_k (fadd_hazard1_k), + .fdiv_busy_q (fdiv_busy_q[1:0]), + .fdiv_done (fdiv_done[1:0]), + .fdiv_done_hold (fdiv_done_hold[1:0]), + .fdiv_flush (fdiv_flush[1:0]), + .fdiv_scalar (fdiv_scalar[1:0]), + .fmla_je2 (fmla_je2), + .fmla_ke2 (fmla_ke2), + .fsqrt_busy_q (fsqrt_busy_q[1:0]), + .fsqrt_done (fsqrt_done[1:0]), + .fsqrt_done_hold (fsqrt_done_hold[1:0]), + .fsqrt_flush (fsqrt_flush[1:0]), + .fsqrt_scalar (fsqrt_scalar[1:0]), + .iqj_flush_gid (iqj_flush_gid[6:0]), + .iqj_flush_u2 (iqj_flush_u2), + .iqk_flush_gid (iqk_flush_gid[6:0]), + .iqk_flush_u2 (iqk_flush_u2), + .ls_resx_data_w2 (ls_resx_data_w2[63:0]), + .ls_resy_data_w2 (ls_resy_data_w2[63:0]), + .mx_resp_data_w2 (mx_resp_data_w2[3:0]), + .sx_resp_data_jw2 (sx_resp_data_jw2[3:0]), + .sx_resp_data_kw2 (sx_resp_data_kw2[3:0]) + ); // uissq_top + + maia_cx_dpj_ctl udpj_ctl( // outputs + .aesd_e1 (aesd_e1), + .aesdimc_e1 (aesdimc_e1), + .aese_e1 (aese_e1), + .aesemc_e1 (aesemc_e1), + .aesimc_e1 (aesimc_e1), + .aesmc_e1 (aesmc_e1), + .crp3_vld_je1 (crp3_vld_je1), + .crypt2_vld_e1 (crypt2_vld_e1), + .crypt3_vld0_e1 (crypt3_vld0_e1), + .crypt3_vld1_e1 (crypt3_vld1_e1), + .cx_ccpass_je1 (cx_ccpass_je1), + .cx_dst_sel_je1 (cx_dst_sel_je1[4:0]), + .cx_imac_cmd_e1 (cx_imac_cmd_e1[12:0]), + .cx_imac_vld_e1 (cx_imac_vld_e1), + .cx_mla_fwd_sel_je2 (cx_mla_fwd_sel_je2[4:0]), + .cx_mla_fwd_sel_je3 (cx_mla_fwd_sel_je3[4:0]), + .cx_uop_res_latency_je1 (cx_uop_res_latency_je1[2:0]), + .dn_fadd_je1 (dn_fadd_je1), + .dn_je1 (dn_je1), + .dstx_bytesel_je1 (dstx_bytesel_je[39:0]), + .dsty_bytesel_je1 (dsty_bytesel_je[39:0]), + .fadd_absin_je1 (fadd_absin_je1), + .fadd_absout_je1 (fadd_absout_je1), + .fadd_ccpass_je1 (fadd_ccpass_je1), + .fadd_hazard1_j (fadd_hazard1_j), + .fadd_srca_sel_h_je1 (fadd_srca_sel_h_je1[2:0]), + .fadd_srca_sel_l_je1 (fadd_srca_sel_l_je1), + .fadd_srcb_sel_h_je1 (fadd_srcb_sel_h_je1[2:0]), + .fadd_srcb_sel_l_je1 (fadd_srcb_sel_l_je1[2:0]), + .fadd_sub_je1 (fadd_sub_je1), + .fadd_vld_je1 (fadd_vld_je1[2:0]), + .fadd_vld_je4 (fadd_vld_je4[2:0]), + .fcvt_cvt_f_to_f_je1 (fcvt_cvt_f_to_f_je1), + .fcvt_cvt_f_to_i_je1 (fcvt_cvt_f_to_i_je1), + .fcvt_cvt_i_to_f_je1 (fcvt_cvt_i_to_f_je1), + .fcvt_cvts_je1 (fcvt_cvts_je1), + .fcvt_frint_je1 (fcvt_frint_je1), + .fcvt_hp_sel_top_je1 (fcvt_hp_sel_top_je1), + .fcvt_imm_je1 (fcvt_imm_je1), + .fcvt_immv_je1 (fcvt_immv_je1[5:0]), + .fcvt_isize_je1 (fcvt_isize_je1[1:0]), + .fcvt_noixc_je1 (fcvt_noixc_je1), + .fcvt_osize_je1 (fcvt_osize_je1[1:0]), + .fcvt_recpe_je1 (fcvt_recpe_je1), + .fcvt_recpx_je1 (fcvt_recpx_je1), + .fcvt_restf_je1 (fcvt_restf_je1), + .fcvt_rsqrte_je1 (fcvt_rsqrte_je1), + .fcvt_scalar_je1 (fcvt_scalar_je1), + .fcvt_vld_je1 (fcvt_vld_je1[1:0]), + .fcvt_vld_je3 (fcvt_vld_je3[1:0]), + .fdiv_cmd_e1 (fdiv_cmd_e1[2:0]), + .fdiv_scalar_je1 (fdiv_scalar_je1), + .fmla_fused_je1 (fmla_fused_je1), + .fmla_fused_je4 (fmla_fused_je4), + .fmla_fwd_je3 (fmla_fwd_je3[1:0]), + .fmla_fwd_je4 (fmla_fwd_je4[1:0]), + .fmla_je1 (fmla_je1), + .fmla_je2 (fmla_je2), + .fmla_je3 (fmla_je3), + .fmla_je4 (fmla_je4), + .fmla_negopa_je4 (fmla_negopa_je4), + .fmul_c_on_d_je1 (fmul_c_on_d_je1), + .fmul_div_je4 (fmul_div_je4), + .fmul_ext_je1 (fmul_ext_je1), + .fmul_negmul_je1 (fmul_negmul_je1), + .fmul_srca_sel_l_je1 (fmul_srca_sel_l_je1), + .fmul_srcb_sel_h_je1 (fmul_srcb_sel_h_je1), + .fmul_srcb_sel_l_je1 (fmul_srcb_sel_l_je1), + .fmul_step_je1 (fmul_step_je1), + .fmul_vld_je1 (fmul_vld_je1[2:0]), + .fmul_vld_je2 (fmul_vld_je2[2:0]), + .fmul_vld_je3 (fmul_vld_je3[2:0]), + .fmul_vld_je4 (fmul_vld_je4[2:0]), + .fz_fadd_je1 (fz_fadd_je1), + .fz_je1 (fz_je1), + .ialu_ctl_je1 (ialu_ctl_je1[21:0]), + .ialu_en_je1 (ialu_en_je1), + .ialu_esize_je1 (ialu_esize_je1[1:0]), + .ialu_fp_dn_je1 (ialu_fp_dn_je1), + .ialu_fp_fz_je1 (ialu_fp_fz_je1), + .ialu_res128_je1 (ialu_res128_je1_q), + .ialu_selusgn_je1 (selusgn_je1_q), + .perm_en_je1 (perm_en_je1), + .perm_en_je2 (perm_en_je2), + .perm_opa_en_je1 (perm_opa_en_je1), + .perm_opb_en_je1 (perm_opb_en_je1), + .perm_opc_en_je1 (perm_opc_en_je1), + .perm_opd_en_je1 (perm_opd_en_je1), + .perm_sign_sel0_je1 (perm_sign_sel0_je1[2:0]), + .perm_sign_sel1_je1 (perm_sign_sel1_je1[2:0]), + .perm_sign_sel2_je1 (perm_sign_sel2_je1[2:0]), + .perm_sign_sel3_je1 (perm_sign_sel3_je1[2:0]), + .perm_uen_je1 (perm_uen_je1), + .perm_uen_je2 (perm_uen_je2), + .pmull_e1 (pmull_e1), + .rmode_fadd_je1 (rmode_fadd_je1[1:0]), + .rmode_fcvt_je1 (rmode_fcvt_je1[2:0]), + .rmode_je1 (rmode_je1[1:0]), + .sha1c_e1 (sha1c_e1), + .sha1h_e1 (sha1h_e1), + .sha1m_e1 (sha1m_e1), + .sha1p_e1 (sha1p_e1), + .sha1su1_e1 (sha1su1_e1), + .sha256h2_e1 (sha256h2_e1), + .sha256h_e1 (sha256h_e1), + .sha256su0_e1 (sha256su0_e1), + .sha256su1_e1 (sha256su1_e1), + .tbl_inst_je1 (tbl_inst_je), + .tbltbx_qdest_je1 (tbltbx_qdest_je), + .tbltbx_reg_bitmask_je1 (tbltbx_reg_bitmask_je[3:0]), + .tbx_inst_je1 (tbx_inst_je), + .uopnum_je1 (uopnum_je[2:0]), + .vcmp_inst_je1 (vcmp_inst_je), + + // inputs + .ck_gclkcx (ck_gclkcx), + .cx_mla_fwd_sel_je1 (cx_mla_fwd_sel_je1[4:0]), + .cx_res128_je1 (cx_res128_je1), + .cx_reset3 (cx_reset3), + .cx_srca_en_je1 (cx_srca_en_je1), + .cx_srcb_en_je1 (cx_srcb_en_je1), + .cx_srcc_en_je1 (cx_srcc_en_je1), + .cx_srcd_en_je1 (cx_srcd_en_je1), + .cx_srcp_data_je1 (cx_srcp_data_je1[3:0]), + .cx_uop_ctl_ji1 (cx_uop_ctl_ji1[58:0]), + .cx_uop_vld_je1 (cx_uop_vld_je1), + .cx_uop_vld_ji1 (cx_uop_vld_ji1), + .dn_raw_e1_q (dn_raw_e1_q), + .ds_cx_aarch32_state (ds_cx_aarch32_state), + .ds_cx_aarch64_state (ds_cx_aarch64_state), + .fz_raw_e1_q (fz_raw_e1_q), + .rmode_fpscr_e1_q (rmode_fpscr_e1_q[1:0]), + .srca_hi_sel_ji1 (srca_hi_sel_ji1), + .srcb_hi_sel_ji1 (srcb_hi_sel_ji1) + ); // udpj_ctl + + maia_cx_dpk_ctl udpk_ctl( // outputs + .acc_size_eq64_e3_q (acc_size_eq64_e3_q), + .acc_size_ge32_e3_q (acc_size_ge32_e3_q), + .acc_size_ne08_e3_q (acc_size_ne08_e3_q), + .c00_x_sel_e1 (c00_x_sel_e1[3:0]), + .c00_y_sel_e1 (c00_y_sel_e1), + .c01_x_sel_e1 (c01_x_sel_e1[5:0]), + .c01_y_sel_e1 (c01_y_sel_e1[2:0]), + .c02_x_sel_e1 (c02_x_sel_e1[5:0]), + .c02_y_sel_e1 (c02_y_sel_e1[2:0]), + .c03_x_sel_e1 (c03_x_sel_e1[6:0]), + .c03_y_sel_e1 (c03_y_sel_e1[4:0]), + .c04_x_sel_e1 (c04_x_sel_e1[5:0]), + .c04_y_sel_e1 (c04_y_sel_e1[2:0]), + .c05_x_sel_e1 (c05_x_sel_e1[7:0]), + .c05_y_sel_e1 (c05_y_sel_e1[4:0]), + .c06_x_sel_e1 (c06_x_sel_e1[5:0]), + .c06_y_sel_e1 (c06_y_sel_e1[4:0]), + .c07_x_sel_e1 (c07_x_sel_e1[6:0]), + .c07_y_sel_e1 (c07_y_sel_e1[4:0]), + .c08_x_sel_e1 (c08_x_sel_e1[6:0]), + .c08_y_sel_e1 (c08_y_sel_e1[2:0]), + .c09_x_sel_e1 (c09_x_sel_e1[8:0]), + .c09_y_sel_e1 (c09_y_sel_e1[5:0]), + .c10_x_sel_e1 (c10_x_sel_e1[8:0]), + .c10_y_sel_e1 (c10_y_sel_e1[5:0]), + .c11_x_sel_e1 (c11_x_sel_e1[9:0]), + .c11_y_sel_e1 (c11_y_sel_e1[7:0]), + .c12_x_sel_e1 (c12_x_sel_e1[7:0]), + .c12_y_sel_e1 (c12_y_sel_e1[5:0]), + .c13_x_sel_e1 (c13_x_sel_e1[9:0]), + .c13_y_sel_e1 (c13_y_sel_e1[6:0]), + .c14_x_sel_e1 (c14_x_sel_e1[7:0]), + .c14_y_sel_e1 (c14_y_sel_e1[6:0]), + .c15_x_sel_e1 (c15_x_sel_e1[7:0]), + .c15_y_sel_e1 (c15_y_sel_e1[6:0]), + .ccpass_ke2 (ccpass_ke2), + .cx_ccpass_ke1 (cx_ccpass_ke1), + .cx_dst_sel_ke1 (cx_dst_sel_ke1[4:0]), + .cx_mla_fwd_sel_ke2 (cx_mla_fwd_sel_ke2[4:0]), + .cx_mla_fwd_sel_ke3 (cx_mla_fwd_sel_ke3[4:0]), + .cx_uop_res_latency_ke1 (cx_uop_res_latency_ke1[2:0]), + .dn_fadd_ke1 (dn_fadd_ke1), + .dn_ke1 (dn_ke1), + .dstx_bytesel_ke1 (dstx_bytesel_ke[39:0]), + .dsty_bytesel_ke1 (dsty_bytesel_ke[39:0]), + .fadd_absin_ke1 (fadd_absin_ke1), + .fadd_absout_ke1 (fadd_absout_ke1), + .fadd_ccpass_ke1 (fadd_ccpass_ke1), + .fadd_hazard1_k (fadd_hazard1_k), + .fadd_srca_sel_h_ke1 (fadd_srca_sel_h_ke1[2:0]), + .fadd_srca_sel_l_ke1 (fadd_srca_sel_l_ke1), + .fadd_srcb_sel_h_ke1 (fadd_srcb_sel_h_ke1[2:0]), + .fadd_srcb_sel_l_ke1 (fadd_srcb_sel_l_ke1[2:0]), + .fadd_sub_ke1 (fadd_sub_ke1), + .fadd_vld_ke1 (fadd_vld_ke1[2:0]), + .fadd_vld_ke4 (fadd_vld_ke4[2:0]), + .fmla_fused_ke1 (fmla_fused_ke1), + .fmla_fused_ke4 (fmla_fused_ke4), + .fmla_fwd_ke3 (fmla_fwd_ke3[1:0]), + .fmla_fwd_ke4 (fmla_fwd_ke4[1:0]), + .fmla_ke1 (fmla_ke1), + .fmla_ke2 (fmla_ke2), + .fmla_ke3 (fmla_ke3), + .fmla_ke4 (fmla_ke4), + .fmla_negopa_ke4 (fmla_negopa_ke4), + .fmul_c_on_d_ke1 (fmul_c_on_d_ke1), + .fmul_div_ke4 (fmul_div_ke4), + .fmul_ext_ke1 (fmul_ext_ke1), + .fmul_negmul_ke1 (fmul_negmul_ke1), + .fmul_srca_sel_l_ke1 (fmul_srca_sel_l_ke1), + .fmul_srcb_sel_h_ke1 (fmul_srcb_sel_h_ke1), + .fmul_srcb_sel_l_ke1 (fmul_srcb_sel_l_ke1), + .fmul_step_ke1 (fmul_step_ke1), + .fmul_vld_ke1 (fmul_vld_ke1[2:0]), + .fmul_vld_ke2 (fmul_vld_ke2[2:0]), + .fmul_vld_ke3 (fmul_vld_ke3[2:0]), + .fmul_vld_ke4 (fmul_vld_ke4[2:0]), + .fsqrt_cmd_e1 (fsqrt_cmd_e1[2:0]), + .fsqrt_scalar_ke1 (fsqrt_scalar_ke1), + .fz_fadd_ke1 (fz_fadd_ke1), + .fz_ke1 (fz_ke1), + .iacc_cin_sel_e3_q (iacc_cin_sel_e3_q[7:1]), + .iacc_en_e1 (iacc_en_e1), + .iacc_en_e2 (iacc_en_e2), + .iacc_en_e4 (iacc_en_e4), + .iacc_shfsel_e2 (iacc_shfsel_e2), + .iacce4_fwd_e2 (iacce4_fwd_e2), + .ialu_acc_en_ke1 (ialu_acc_en_ke1), + .ialu_ctl_ke1 (ialu_ctl_ke1[21:0]), + .ialu_en_ke1 (ialu_en_ke1), + .ialu_en_ke3 (ialu_en_ke3), + .ialu_esize_ke1 (ialu_esize_ke1[1:0]), + .ialu_fp_dn_ke1 (ialu_fp_dn_ke1), + .ialu_fp_fz_ke1 (ialu_fp_fz_ke1), + .ialu_res128_ke1 (ialu_res128_ke1_q), + .ialu_selusgn_ke1 (selusgn_ke1_q), + .ired_esize_ke1 (ired_esize_ke1[1:0]), + .ired_long_ke1 (ired_long_ke1), + .ired_opb_en_ke1 (ired_opb_en_ke1), + .ired_seladd_ke1 (ired_seladd_ke1), + .ired_selmax_ke1 (ired_selmax_ke1), + .ired_selmin_ke1 (ired_selmin_ke1), + .ired_selusgn_ke1 (ired_selusgn_ke1), + .ired_vrop_ke1 (ired_vrop_ke1), + .ishf3_iss_e2 (ishf3_iss_e2), + .ishf3_iss_e3 (ishf3_iss_e3), + .ishf3_uiss_e2 (ishf3_uiss_e2), + .ishf_imm_e1 (ishf_imm_e1), + .ishf_immv_e1 (ishf_immv_e1[7:0]), + .ishf_insert_e1 (ishf_insert_e1), + .ishf_iss_e1 (ishf_iss_e1), + .ishf_iss_e2 (ishf_iss_e2), + .ishf_left_e1 (ishf_left_e1), + .ishf_narrow_e1 (ishf_narrow_e1), + .ishf_qc_vld_e3 (ishf_qc_vld_e3), + .ishf_round_e1 (ishf_round_e1), + .ishf_s1_sel_e1 (ishf_s1_sel_e1[2:0]), + .ishf_s2_sel_e1 (ishf_s2_sel_e1[2:0]), + .ishf_s3_sel_e1 (ishf_s3_sel_e1[3:0]), + .ishf_s4_sel_e1 (ishf_s4_sel_e1[2:0]), + .ishf_s5_sel_e1 (ishf_s5_sel_e1[3:0]), + .ishf_s6_sel_e1 (ishf_s6_sel_e1[3:0]), + .ishf_s7_sel_e1 (ishf_s7_sel_e1[4:0]), + .ishf_saturate_e1 (ishf_saturate_e1), + .ishf_scalar_e1 (ishf_scalar_e1), + .ishf_sel16_e1 (ishf_sel16_e1), + .ishf_sel32_e1 (ishf_sel32_e1), + .ishf_sel64_e1 (ishf_sel64_e1), + .ishf_sel8_e1 (ishf_sel8_e1), + .ishf_selqsat_e3 (ishf_selqsat_e3), + .ishf_signed_e1 (ishf_signed_e1), + .ishf_stous_e1 (ishf_stous_e1), + .ishf_uiss_e2 (ishf_uiss_e2), + .ishf_widen_e1 (ishf_widen_e1), + .perm_en_ke1 (perm_en_ke1), + .perm_en_ke2 (perm_en_ke2), + .perm_opa_en_ke1 (perm_opa_en_ke1), + .perm_opb_en_ke1 (perm_opb_en_ke1), + .perm_opc_en_ke1 (perm_opc_en_ke1), + .perm_opd_en_ke1 (perm_opd_en_ke1), + .perm_sign_sel0_ke1 (perm_sign_sel0_ke1[2:0]), + .perm_sign_sel1_ke1 (perm_sign_sel1_ke1[2:0]), + .perm_sign_sel2_ke1 (perm_sign_sel2_ke1[2:0]), + .perm_sign_sel3_ke1 (perm_sign_sel3_ke1[2:0]), + .perm_uen_ke1 (perm_uen_ke1), + .perm_uen_ke2 (perm_uen_ke2), + .res128_e2 (res128_e2), + .rmode_fadd_ke1 (rmode_fadd_ke1[1:0]), + .rmode_ke1 (rmode_ke1[1:0]), + .shf_size_eq64_e3_q (shf_size_eq64_e3_q), + .shf_size_ge32_e3_q (shf_size_ge32_e3_q), + .shf_size_ne08_e3_q (shf_size_ne08_e3_q), + .tbl_inst_ke1 (tbl_inst_ke), + .tbltbx_qdest_ke1 (tbltbx_qdest_ke), + .tbltbx_reg_bitmask_ke1 (tbltbx_reg_bitmask_ke[3:0]), + .tbx_inst_ke1 (tbx_inst_ke), + .uopnum_ke1 (uopnum_ke[2:0]), + .vcmp_inst_ke1 (vcmp_inst_ke), + + // inputs + .ck_gclkcx (ck_gclkcx), + .cx_mla_fwd_sel_ke1 (cx_mla_fwd_sel_ke1[4:0]), + .cx_res128_ke1 (cx_res128_ke1), + .cx_reset3 (cx_reset3), + .cx_srca_en_ke1 (cx_srca_en_ke1), + .cx_srcb_en_ke1 (cx_srcb_en_ke1), + .cx_srcc_en_ke1 (cx_srcc_en_ke1), + .cx_srcd_en_ke1 (cx_srcd_en_ke1), + .cx_srcp_data_ke1 (cx_srcp_data_ke1[3:0]), + .cx_uop_ctl_ki1 (cx_uop_ctl_ki1[58:0]), + .cx_uop_vld_ke1 (cx_uop_vld_ke1), + .cx_uop_vld_ki1 (cx_uop_vld_ki1), + .dn_raw_e1_q (dn_raw_e1_q), + .ds_cx_aarch32_state (ds_cx_aarch32_state), + .ds_cx_aarch64_state (ds_cx_aarch64_state), + .fz_raw_e1_q (fz_raw_e1_q), + .rmode_fpscr_e1_q (rmode_fpscr_e1_q[1:0]), + .srca_hi_sel_ki1 (srca_hi_sel_ki1), + .srcb_hi_sel_ki1 (srcb_hi_sel_ki1) + ); // udpk_ctl + + maia_cx_iacc_ff uiacck_ff( // outputs + .cx_srcc_data_e3_q (cx_srcc_data_ke3[63:0]), + .cx_srcd_data_e3_q (cx_srcd_data_ke3[63:0]), + + // inputs + .ck_gclkcx_int (ck_gclkcx_intk), + .cx_mla_fwd_sel_e1 (cx_mla_fwd_sel_ke1[1:0]), + .cx_mla_fwd_sel_e2 (cx_mla_fwd_sel_ke2[1:0]), + .cx_reset3 (cx_reset3), + .cx_srcc_data_e1 (cx_srcc_int_data_ke1[63:0]), + .cx_srcc_en_e1 (cx_srcc_en_ke1), + .cx_srcd_data_e1 (cx_srcd_int_data_ke1[63:0]), + .iacc_en_e1 (iacc_en_e1), + .iacc_en_e4 (iacc_en_e4), + .ialu_en_ke3 (ialu_en_ke3), + .ialuout_e3_q (ialuout_ke3_q[127:0]), + .ishf3_iss_e3 (ishf3_iss_e3), + .ishfaccout_e4_q (ishfaccout_e4_q[127:0]), + .ishfout_e3_q (ishfout_e3_q[127:0]), + .res128_e1 (cx_res128_ke1), + .res128_e2 (res128_e2) + ); // uiacck_ff + + maia_cx_fmla_ff ufmlaj_ff( // outputs + .fmla_acc_e4 (fmla_acc_je4[63:0]), + + // inputs + .ck_gclkcx_float (ck_gclkcx_floatj), + .cx_mla_fwd_sel_e1 (cx_mla_fwd_sel_je1[4:0]), + .cx_mla_fwd_sel_e2 (cx_mla_fwd_sel_je2[4:0]), + .cx_mla_fwd_sel_e3 (cx_mla_fwd_sel_je3[4:0]), + .cx_reset3 (cx_reset3), + .cx_srcc_en_e1 (cx_srcc_en_je1), + .cx_srcc_fp_data_e1 (cx_srcc_fp_data32_je1[63:0]), + .cx_srcd_fp_data_e1 (cx_srcd_fp_data32_je1[31:0]), + .faddout32_h_e4 (faddout32_h_je4[31:0]), + .faddout32_h_oe4 (faddout32_h_ke4[31:0]), + .faddout32_l_e4 (faddout32_l_je4[31:0]), + .faddout32_l_oe4 (faddout32_l_ke4[31:0]), + .faddout64_e4 (faddout64_je4[63:0]), + .faddout64_oe4 (faddout64_ke4[63:0]), + .fmla_e1 (fmla_je1), + .fmla_e2 (fmla_je2), + .fmla_e3 (fmla_je3), + .fmul_c_on_d_e1 (fmul_c_on_d_je1), + .fmul_vld_e1 (fmul_vld_je1[2:0]), + .fmul_vld_e2 (fmul_vld_je2[2:0]), + .fmul_vld_e3 (fmul_vld_je3[2:0]), + .fmulout32_h_e4 (fmulout32_h_je4[55:24]), + .fmulout32_h_oe4 (fmulout32_h_ke4[55:24]), + .fmulout32_l_e4 (fmulout32_l_je4[55:24]), + .fmulout32_l_oe4 (fmulout32_l_ke4[55:24]), + .fmulout64_e4 (fmulout64_je4[116:53]), + .fmulout64_oe4 (fmulout64_ke4[116:53]) + ); // ufmlaj_ff + + maia_cx_fmla_ff ufmlak_ff( // outputs + .fmla_acc_e4 (fmla_acc_ke4[63:0]), + + // inputs + .ck_gclkcx_float (ck_gclkcx_floatk), + .cx_mla_fwd_sel_e1 (cx_mla_fwd_sel_ke1[4:0]), + .cx_mla_fwd_sel_e2 (cx_mla_fwd_sel_ke2[4:0]), + .cx_mla_fwd_sel_e3 (cx_mla_fwd_sel_ke3[4:0]), + .cx_reset3 (cx_reset3), + .cx_srcc_en_e1 (cx_srcc_en_ke1), + .cx_srcc_fp_data_e1 (cx_srcc_fp_data32_ke1[63:0]), + .cx_srcd_fp_data_e1 (cx_srcd_fp_data32_ke1[31:0]), + .faddout32_h_e4 (faddout32_h_ke4[31:0]), + .faddout32_h_oe4 (faddout32_h_je4[31:0]), + .faddout32_l_e4 (faddout32_l_ke4[31:0]), + .faddout32_l_oe4 (faddout32_l_je4[31:0]), + .faddout64_e4 (faddout64_ke4[63:0]), + .faddout64_oe4 (faddout64_je4[63:0]), + .fmla_e1 (fmla_ke1), + .fmla_e2 (fmla_ke2), + .fmla_e3 (fmla_ke3), + .fmul_c_on_d_e1 (fmul_c_on_d_ke1), + .fmul_vld_e1 (fmul_vld_ke1[2:0]), + .fmul_vld_e2 (fmul_vld_ke2[2:0]), + .fmul_vld_e3 (fmul_vld_ke3[2:0]), + .fmulout32_h_e4 (fmulout32_h_ke4[55:24]), + .fmulout32_h_oe4 (fmulout32_h_je4[55:24]), + .fmulout32_l_e4 (fmulout32_l_ke4[55:24]), + .fmulout32_l_oe4 (fmulout32_l_je4[55:24]), + .fmulout64_e4 (fmulout64_ke4[116:53]), + .fmulout64_oe4 (fmulout64_je4[116:53]) + ); // ufmlak_ff + + maia_cx_fmul ufmulj( // outputs + .fmul32_ex_h_e4 (fmul32_ex_h_je4[4:0]), + .fmul32_ex_l_e4 (fmul32_ex_l_je4[4:0]), + .fmul64_ex_e4 (fmul64_ex_je4[4:0]), + .fmul_active (fmulj_active), + .fmul_f_exp_ovfl_e4 (fmul_f_exp_ovfl_je4), + .fmul_f_exp_ovfl_h_e4 (fmul_f_exp_ovfl_h_je4), + .fmul_f_exp_ovfl_l_e4 (fmul_f_exp_ovfl_l_je4), + .fmul_f_infnanzero_e4 (fmul_f_infnanzero_je4), + .fmul_f_infnanzero_h_e4 (fmul_f_infnanzero_h_je4), + .fmul_f_infnanzero_l_e4 (fmul_f_infnanzero_l_je4), + .fmul_f_prod_inf_zero_e4 (fmul_f_prod_inf_zero_je4), + .fmul_f_prod_inf_zero_h_e4 (fmul_f_prod_inf_zero_h_je4), + .fmul_f_prod_inf_zero_l_e4 (fmul_f_prod_inf_zero_l_je4), + .fmulout32_h_e4 (fmulout32_h_je4[55:0]), + .fmulout32_l_e4 (fmulout32_l_je4[55:0]), + .fmulout64_e4 (fmulout64_je4[116:0]), + + // inputs + .ck_gclkcx_float (ck_gclkcx_floatj), + .cx_ccpass_e1 (cx_ccpass_je1), + .cx_reset3 (cx_reset3), + .cx_srca_fp_data32_e1 (cx_fmul_srca_fp_data32_je1[63:0]), + .cx_srca_fp_data64_e1 (cx_srca_fp_data64_je1[63:0]), + .cx_srcb_fp_data32_e1 (cx_fmul_srcb_fp_data32_je1[63:0]), + .cx_srcb_fp_data64_e1 (cx_srcb_fp_data64_je1[63:0]), + .cx_srcc_fp_data32_e1 (cx_srcc_fp_data32_je1[63:0]), + .cx_srcc_fp_data64_e1 (cx_srcc_fp_data32_je1[31:0]), + .cx_srcd_fp_data64_e1 (cx_srcd_fp_data32_je1[31:0]), + .dn_e1 (dn_je1), + .fmla_fused_e1_q (fmla_fused_je1), + .fmul_ext_e1 (fmul_ext_je1), + .fmul_negmul_e1_q (fmul_negmul_je1), + .fmul_step_e1_q (fmul_step_je1), + .fmul_vld_e1 (fmul_vld_je1[2:0]), + .fz_e1 (fz_je1), + .rmode_e1_q (rmode_je1[1:0]) + ); // ufmulj + + maia_cx_fadd ufaddj( // outputs + .fadd32_ex_h_e4 (fadd32_ex_h_je4[5:0]), + .fadd32_ex_l_e4 (fadd32_ex_l_je4[5:0]), + .fadd64_ex_e4 (fadd64_ex_je4[5:0]), + .fadd_active (addj_active), + .faddout32_h_e4 (faddout32_h_je4[31:0]), + .faddout32_l_e4 (faddout32_l_je4[31:0]), + .faddout64_e4 (faddout64_je4[63:0]), + + // inputs + .ck_gclkcx_float (ck_gclkcx_floatj), + .cx_reset3 (cx_reset3), + .cx_srca_fp_data32_e1 (cx_fadd_srca_fp_data32_je1[63:0]), + .cx_srca_fp_data64_e1 (cx_fadd_srca_fp_data64_je1[63:0]), + .cx_srcb_fp_data32_h_e1 (cx_fadd_srcb_fp_data32_h_je1[55:0]), + .cx_srcb_fp_data32_l_e1 (cx_fadd_srcb_fp_data32_l_je1[55:0]), + .cx_srcb_fp_data64_e1 (cx_fadd_srcb_fp_data64_je1[116:0]), + .cx_srcc_fp_data32_e1 (cx_fadd_srcc_fp_data32_je1[63:0]), + .cx_srcc_fp_data64_e1 (cx_fadd_srcc_fp_data64_je1[31:0]), + .cx_srcd_fp_data64_e1 (cx_fadd_srcd_fp_data64_je1[31:0]), + .dn_e1 (dn_fadd_je1), + .fadd_absin_e1_q (fadd_absin_je1), + .fadd_absout_e1_q (fadd_absout_je1), + .fadd_ccpass_e1 (fadd_ccpass_je1), + .fadd_sub_e1_q (fadd_sub_je1), + .fadd_vld_e1 (fadd_vld_je1[2:0]), + .fmla_e4_q (fmla_je4), + .fmla_fused_e4_q (fmla_fused_je4), + .fmla_negopa_e4_q (fmla_negopa_je4), + .fmul32_ex_h_e4 (fmul32_ex_h_je4[4:0]), + .fmul32_ex_l_e4 (fmul32_ex_l_je4[4:0]), + .fmul64_ex_e4 (fmul64_ex_je4[4:0]), + .fmul_div_e4_q (fmul_div_je4), + .fmul_f_exp_ovfl_e4 (fmul_f_exp_ovfl_je4), + .fmul_f_exp_ovfl_h_e4 (fmul_f_exp_ovfl_h_je4), + .fmul_f_exp_ovfl_l_e4 (fmul_f_exp_ovfl_l_je4), + .fmul_f_infnanzero_e4 (fmul_f_infnanzero_je4), + .fmul_f_infnanzero_h_e4 (fmul_f_infnanzero_h_je4), + .fmul_f_infnanzero_l_e4 (fmul_f_infnanzero_l_je4), + .fmul_f_prod_inf_zero_e4 (fmul_f_prod_inf_zero_je4), + .fmul_f_prod_inf_zero_h_e4 (fmul_f_prod_inf_zero_h_je4), + .fmul_f_prod_inf_zero_l_e4 (fmul_f_prod_inf_zero_l_je4), + .fz_e1 (fz_fadd_je1), + .rmode_e1_q (rmode_fadd_je1[1:0]) + ); // ufaddj + + maia_cx_ialu uialuj( // outputs + .ialu_active (ialuj_active), + .ialu_fpex_e3_q (ialu_fpex_je3_q[4:0]), + .ialu_nzcv_e3_q (unused1[3:0]), + .ialu_qc_e3_q (ialu_qc_je3_q), + .ialu_qc_vld_e2 (ialu_qc_vld_je2), + .ialuout_e3_q (ialuout_je3_q[127:0]), + + // inputs + .ck_gclkcx_int (ck_gclkcx_intj), + .cx_reset3 (cx_reset3), + .esize_e1 (ialu_esize_je1[1:0]), + .ialu_acc_en_e1 (1'b0), + .ialu_ccpass_e1 (1'b1), + .ialu_ctl_e1 (ialu_ctl_je1[21:0]), + .ialu_en_e1 (ialu_en_je1), + .ialu_fp_dn_e1 (ialu_fp_dn_je1), + .ialu_fp_fz_e1 (ialu_fp_fz_je1), + .ialu_nzcv_e1 (4'b0000), + .opa_e1_q (cx_srca_int_data_je1[63:0]), + .opb_e1_q (cx_srcb_int_data_je1[63:0]), + .opc_e1_q (cx_srcc_int_data_je1[63:0]), + .opd_e1_q (cx_srcd_int_data_je1[63:0]), + .res128_e1 (ialu_res128_je1_q), + .unsigned_e1 (selusgn_je1_q) + ); // uialuj + + maia_cx_perm upermj( // outputs + .lspout_e3_q (lspout_je3_q[127:0]), + + // inputs + .ck_gclkcx (ck_gclkcx), + .ds_cx_aarch64_state (ds_cx_aarch64_state), + .dstx_bytesel_e1 (dstx_bytesel_je[39:0]), + .dsty_bytesel_e1 (dsty_bytesel_je[39:0]), + .fpscr_e1_q (cx_srcp_data_je1[3:0]), + .opa_e1_q (cx_srca_int_data_je1[63:0]), + .opb_e1_q (cx_srcb_int_data_je1[63:0]), + .opc_e1_q (cx_srcc_int_data_je1[63:0]), + .opd_e1_q (cx_srcd_int_data_je1[63:0]), + .perm_en_e1 (perm_en_je1), + .perm_en_e2 (perm_en_je2), + .perm_opa_en_e1 (perm_opa_en_je1), + .perm_opb_en_e1 (perm_opb_en_je1), + .perm_opc_en_e1 (perm_opc_en_je1), + .perm_opd_en_e1 (perm_opd_en_je1), + .perm_sign_sel0_e1 (perm_sign_sel0_je1[2:0]), + .perm_sign_sel1_e1 (perm_sign_sel1_je1[2:0]), + .perm_sign_sel2_e1 (perm_sign_sel2_je1[2:0]), + .perm_sign_sel3_e1 (perm_sign_sel3_je1[2:0]), + .perm_uen_e1 (perm_uen_je1), + .perm_uen_e2 (perm_uen_je2), + .tbl_inst_e1 (tbl_inst_je), + .tbltbx_qdest_e1 (tbltbx_qdest_je), + .tbltbx_reg_bitmask_e1 (tbltbx_reg_bitmask_je[3:0]), + .tbx_inst_e1 (tbx_inst_je), + .uopnum_e1 (uopnum_je[2:0]), + .vcmp_inst_e1 (vcmp_inst_je) + ); // upermj + + maia_cx_imac uimacj( // outputs + .imac_active (imac_active), + .imac_qc_e4_q (imac_qc_e4_q), + .imac_qc_vld_e3 (imac_qc_vld_e3), + .iwbout_e4_q (iwbout_e4_q[127:0]), + + // inputs + .ck_gclkcx_int (ck_gclkcx_intj), + .cx_imac_cmd_e1_q (cx_imac_cmd_e1[12:0]), + .cx_imac_fwd_sel_e1_q (cx_mla_fwd_sel_je1[2:0]), + .cx_imac_vld_e1_q (cx_imac_vld_e1), + .cx_reset3 (cx_reset3), + .opa_e1_q (cx_srca_int_data_je1[63:0]), + .opb_e1_q (cx_srcb_int_data_je1[63:0]), + .opc_e1_q (cx_srcc_int_data_je1[63:0]), + .opd_e1_q (cx_srcd_int_data_je1[63:0]) + ); // uimacj + + maia_cx_fdiv ufdivj( // outputs + .fdiv_active (fdiv_active), + .fdiv_done (fdiv_done[1:0]), + .fdivexc32_q (fdivexc32_q[5:0]), + .fdivexc64_q (fdivexc64_q[5:0]), + .fdivout32_q (fdivout32_q[31:0]), + .fdivout64_q (fdivout64_q[63:0]), + + // inputs + .ck_gclkcx_float (ck_gclkcx_floatj), + .cx_reset3 (cx_reset3), + .dn_e1_q (dn_je1), + .fdiv_ccpass_e1 (cx_ccpass_je1), + .fdiv_cmd_e1_q (fdiv_cmd_e1[2:0]), + .fdiv_flush (fdiv_flush[1:0]), + .fdiv_vld_e1 (fdiv_uop_vld_je1[1:0]), + .fz_e1_q (fz_je1), + .opa_e1_q (cx_srca_fp_data32_je1[63:0]), + .opb_e1_q (cx_srcb_fp_data32_je1[63:0]), + .opc_e1_q (cx_srcc_fp_data32_je1[31:0]), + .opd_e1_q (cx_srcd_fp_data32_je1[31:0]), + .rmode_e1_q (rmode_je1[1:0]) + ); // ufdivj + + maia_cx_fcvt ufcvtj( // outputs + .fcvt_active (cvtj_active), + .fcvt_ex_h_e3 (fcvt_ex_h_e3[5:0]), + .fcvt_ex_l_e3 (fcvt_ex_l_e3[5:0]), + .fcvtout_e3 (fcvtout_e3[127:0]), + + // inputs + .ahp_mode_e1_q (ahp_mode_e1_q), + .ccpass_e1 (cx_ccpass_je1), + .ck_gclkcx_float (ck_gclkcx_floatj), + .cx_reset3 (cx_reset3), + .cx_srca_fp_data_e1 (cx_srca_fp_data32_je1[63:0]), + .cx_srcb_fp_data_e1 (cx_srcb_fp_data32_je1[63:0]), + .cx_srcc_fp_data_e1 (cx_srcc_fp_data32_je1[31:0]), + .cx_srcd_fp_data_e1 (cx_srcd_fp_data32_je1[31:0]), + .dn_e1_q (dn_je1), + .fcvt_cvt_f_to_f_e1 (fcvt_cvt_f_to_f_je1), + .fcvt_cvt_f_to_i_e1 (fcvt_cvt_f_to_i_je1), + .fcvt_cvt_i_to_f_e1 (fcvt_cvt_i_to_f_je1), + .fcvt_cvts_e1 (fcvt_cvts_je1), + .fcvt_frint_e1 (fcvt_frint_je1), + .fcvt_hp_sel_top_e1 (fcvt_hp_sel_top_je1), + .fcvt_imm_e1 (fcvt_imm_je1), + .fcvt_immv_e1 (fcvt_immv_je1[5:0]), + .fcvt_isize_e1 (fcvt_isize_je1[1:0]), + .fcvt_noixc_e1 (fcvt_noixc_je1), + .fcvt_osize_e1 (fcvt_osize_je1[1:0]), + .fcvt_recpe_e1 (fcvt_recpe_je1), + .fcvt_recpx_e1 (fcvt_recpx_je1), + .fcvt_restf_e1 (fcvt_restf_je1), + .fcvt_rsqrte_e1 (fcvt_rsqrte_je1), + .fcvt_scalar_e1 (fcvt_scalar_je1), + .fcvt_vld_e1 (fcvt_vld_je1[1:0]), + .fz_e1_q (fz_je1), + .rmode_e1_q (rmode_fcvt_je1[2:0]) + ); // ufcvtj + + maia_cx_fmul ufmulk( // outputs + .fmul32_ex_h_e4 (fmul32_ex_h_ke4[4:0]), + .fmul32_ex_l_e4 (fmul32_ex_l_ke4[4:0]), + .fmul64_ex_e4 (fmul64_ex_ke4[4:0]), + .fmul_active (fmulk_active), + .fmul_f_exp_ovfl_e4 (fmul_f_exp_ovfl_ke4), + .fmul_f_exp_ovfl_h_e4 (fmul_f_exp_ovfl_h_ke4), + .fmul_f_exp_ovfl_l_e4 (fmul_f_exp_ovfl_l_ke4), + .fmul_f_infnanzero_e4 (fmul_f_infnanzero_ke4), + .fmul_f_infnanzero_h_e4 (fmul_f_infnanzero_h_ke4), + .fmul_f_infnanzero_l_e4 (fmul_f_infnanzero_l_ke4), + .fmul_f_prod_inf_zero_e4 (fmul_f_prod_inf_zero_ke4), + .fmul_f_prod_inf_zero_h_e4 (fmul_f_prod_inf_zero_h_ke4), + .fmul_f_prod_inf_zero_l_e4 (fmul_f_prod_inf_zero_l_ke4), + .fmulout32_h_e4 (fmulout32_h_ke4[55:0]), + .fmulout32_l_e4 (fmulout32_l_ke4[55:0]), + .fmulout64_e4 (fmulout64_ke4[116:0]), + + // inputs + .ck_gclkcx_float (ck_gclkcx_floatk), + .cx_ccpass_e1 (cx_ccpass_ke1), + .cx_reset3 (cx_reset3), + .cx_srca_fp_data32_e1 (cx_fmul_srca_fp_data32_ke1[63:0]), + .cx_srca_fp_data64_e1 (cx_srca_fp_data64_ke1[63:0]), + .cx_srcb_fp_data32_e1 (cx_fmul_srcb_fp_data32_ke1[63:0]), + .cx_srcb_fp_data64_e1 (cx_srcb_fp_data64_ke1[63:0]), + .cx_srcc_fp_data32_e1 (cx_srcc_fp_data32_ke1[63:0]), + .cx_srcc_fp_data64_e1 (cx_srcc_fp_data32_ke1[31:0]), + .cx_srcd_fp_data64_e1 (cx_srcd_fp_data32_ke1[31:0]), + .dn_e1 (dn_ke1), + .fmla_fused_e1_q (fmla_fused_ke1), + .fmul_ext_e1 (fmul_ext_ke1), + .fmul_negmul_e1_q (fmul_negmul_ke1), + .fmul_step_e1_q (fmul_step_ke1), + .fmul_vld_e1 (fmul_vld_ke1[2:0]), + .fz_e1 (fz_ke1), + .rmode_e1_q (rmode_ke1[1:0]) + ); // ufmulk + + maia_cx_fadd ufaddk( // outputs + .fadd32_ex_h_e4 (fadd32_ex_h_ke4[5:0]), + .fadd32_ex_l_e4 (fadd32_ex_l_ke4[5:0]), + .fadd64_ex_e4 (fadd64_ex_ke4[5:0]), + .fadd_active (addk_active), + .faddout32_h_e4 (faddout32_h_ke4[31:0]), + .faddout32_l_e4 (faddout32_l_ke4[31:0]), + .faddout64_e4 (faddout64_ke4[63:0]), + + // inputs + .ck_gclkcx_float (ck_gclkcx_floatk), + .cx_reset3 (cx_reset3), + .cx_srca_fp_data32_e1 (cx_fadd_srca_fp_data32_ke1[63:0]), + .cx_srca_fp_data64_e1 (cx_fadd_srca_fp_data64_ke1[63:0]), + .cx_srcb_fp_data32_h_e1 (cx_fadd_srcb_fp_data32_h_ke1[55:0]), + .cx_srcb_fp_data32_l_e1 (cx_fadd_srcb_fp_data32_l_ke1[55:0]), + .cx_srcb_fp_data64_e1 (cx_fadd_srcb_fp_data64_ke1[116:0]), + .cx_srcc_fp_data32_e1 (cx_fadd_srcc_fp_data32_ke1[63:0]), + .cx_srcc_fp_data64_e1 (cx_fadd_srcc_fp_data64_ke1[31:0]), + .cx_srcd_fp_data64_e1 (cx_fadd_srcd_fp_data64_ke1[31:0]), + .dn_e1 (dn_fadd_ke1), + .fadd_absin_e1_q (fadd_absin_ke1), + .fadd_absout_e1_q (fadd_absout_ke1), + .fadd_ccpass_e1 (fadd_ccpass_ke1), + .fadd_sub_e1_q (fadd_sub_ke1), + .fadd_vld_e1 (fadd_vld_ke1[2:0]), + .fmla_e4_q (fmla_ke4), + .fmla_fused_e4_q (fmla_fused_ke4), + .fmla_negopa_e4_q (fmla_negopa_ke4), + .fmul32_ex_h_e4 (fmul32_ex_h_ke4[4:0]), + .fmul32_ex_l_e4 (fmul32_ex_l_ke4[4:0]), + .fmul64_ex_e4 (fmul64_ex_ke4[4:0]), + .fmul_div_e4_q (fmul_div_ke4), + .fmul_f_exp_ovfl_e4 (fmul_f_exp_ovfl_ke4), + .fmul_f_exp_ovfl_h_e4 (fmul_f_exp_ovfl_h_ke4), + .fmul_f_exp_ovfl_l_e4 (fmul_f_exp_ovfl_l_ke4), + .fmul_f_infnanzero_e4 (fmul_f_infnanzero_ke4), + .fmul_f_infnanzero_h_e4 (fmul_f_infnanzero_h_ke4), + .fmul_f_infnanzero_l_e4 (fmul_f_infnanzero_l_ke4), + .fmul_f_prod_inf_zero_e4 (fmul_f_prod_inf_zero_ke4), + .fmul_f_prod_inf_zero_h_e4 (fmul_f_prod_inf_zero_h_ke4), + .fmul_f_prod_inf_zero_l_e4 (fmul_f_prod_inf_zero_l_ke4), + .fz_e1 (fz_fadd_ke1), + .rmode_e1_q (rmode_fadd_ke1[1:0]) + ); // ufaddk + + maia_cx_ialu uialuk( // outputs + .ialu_active (ialuk_active), + .ialu_fpex_e3_q (ialu_fpex_ke3_q[4:0]), + .ialu_nzcv_e3_q (ialu_nzcv_ke3_q[3:0]), + .ialu_qc_e3_q (ialu_qc_ke3_q), + .ialu_qc_vld_e2 (ialu_qc_vld_ke2), + .ialuout_e3_q (ialuout_ke3_q[127:0]), + + // inputs + .ck_gclkcx_int (ck_gclkcx_intk), + .cx_reset3 (cx_reset3), + .esize_e1 (ialu_esize_ke1[1:0]), + .ialu_acc_en_e1 (ialu_acc_en_ke1), + .ialu_ccpass_e1 (cx_ccpass_ke1), + .ialu_ctl_e1 (ialu_ctl_ke1[21:0]), + .ialu_en_e1 (ialu_en_ke1), + .ialu_fp_dn_e1 (ialu_fp_dn_ke1), + .ialu_fp_fz_e1 (ialu_fp_fz_ke1), + .ialu_nzcv_e1 (cx_srcp_data_ke1[3:0]), + .opa_e1_q (cx_srca_int_data_ke1[63:0]), + .opb_e1_q (cx_srcb_int_data_ke1[63:0]), + .opc_e1_q (cx_srcc_int_data_ke1[63:0]), + .opd_e1_q (cx_srcd_int_data_ke1[63:0]), + .res128_e1 (ialu_res128_ke1_q), + .unsigned_e1 (selusgn_ke1_q) + ); // uialuk + + maia_cx_ired uiredk( // outputs + .ired_active (iredk_active), + .iredout_e3_q (iredout_ke2[63:0]), + + // inputs + .ck_gclkcx_int (ck_gclkcx_intk), + .cx_reset3 (cx_reset3), + .esize_e1 (ired_esize_ke1[1:0]), + .long_e1 (ired_long_ke1), + .opa_e1_q (cx_srca_int_data_ke1[63:0]), + .opb_e1_q (cx_srcb_int_data_ke1[63:0]), + .opb_en_e1 (ired_opb_en_ke1), + .seladd_e1 (ired_seladd_ke1), + .selmax_e1 (ired_selmax_ke1), + .selmin_e1 (ired_selmin_ke1), + .unsigned_e1 (ired_selusgn_ke1), + .vrop_e1 (ired_vrop_ke1) + ); // uiredk + + maia_cx_perm upermk( // outputs + .lspout_e3_q (lspout_ke3_q[127:0]), + + // inputs + .ck_gclkcx (ck_gclkcx), + .ds_cx_aarch64_state (ds_cx_aarch64_state), + .dstx_bytesel_e1 (dstx_bytesel_ke[39:0]), + .dsty_bytesel_e1 (dsty_bytesel_ke[39:0]), + .fpscr_e1_q (cx_srcp_data_ke1[3:0]), + .opa_e1_q (cx_srca_int_data_ke1[63:0]), + .opb_e1_q (cx_srcb_int_data_ke1[63:0]), + .opc_e1_q (cx_srcc_int_data_ke1[63:0]), + .opd_e1_q (cx_srcd_int_data_ke1[63:0]), + .perm_en_e1 (perm_en_ke1), + .perm_en_e2 (perm_en_ke2), + .perm_opa_en_e1 (perm_opa_en_ke1), + .perm_opb_en_e1 (perm_opb_en_ke1), + .perm_opc_en_e1 (perm_opc_en_ke1), + .perm_opd_en_e1 (perm_opd_en_ke1), + .perm_sign_sel0_e1 (perm_sign_sel0_ke1[2:0]), + .perm_sign_sel1_e1 (perm_sign_sel1_ke1[2:0]), + .perm_sign_sel2_e1 (perm_sign_sel2_ke1[2:0]), + .perm_sign_sel3_e1 (perm_sign_sel3_ke1[2:0]), + .perm_uen_e1 (perm_uen_ke1), + .perm_uen_e2 (perm_uen_ke2), + .tbl_inst_e1 (tbl_inst_ke), + .tbltbx_qdest_e1 (tbltbx_qdest_ke), + .tbltbx_reg_bitmask_e1 (tbltbx_reg_bitmask_ke[3:0]), + .tbx_inst_e1 (tbx_inst_ke), + .uopnum_e1 (uopnum_ke[2:0]), + .vcmp_inst_e1 (vcmp_inst_ke) + ); // upermk + + maia_cx_ishf uishfk( // outputs + .ishf_active (ishf_active), + .ishf_qc_e4_q (ishf_qc_e4_q), + .ishfaccout_e4_q (ishfaccout_e4_q[127:0]), + .ishfout_e3_q (ishfout_e3_q[127:0]), + + // inputs + .acc_size_eq64_e3_q (acc_size_eq64_e3_q), + .acc_size_ge32_e3_q (acc_size_ge32_e3_q), + .acc_size_ne08_e3_q (acc_size_ne08_e3_q), + .c00_x_sel_e1_q (c00_x_sel_e1[3:0]), + .c00_y_sel_e1_q (c00_y_sel_e1), + .c01_x_sel_e1_q (c01_x_sel_e1[5:0]), + .c01_y_sel_e1_q (c01_y_sel_e1[2:0]), + .c02_x_sel_e1_q (c02_x_sel_e1[5:0]), + .c02_y_sel_e1_q (c02_y_sel_e1[2:0]), + .c03_x_sel_e1_q (c03_x_sel_e1[6:0]), + .c03_y_sel_e1_q (c03_y_sel_e1[4:0]), + .c04_x_sel_e1_q (c04_x_sel_e1[5:0]), + .c04_y_sel_e1_q (c04_y_sel_e1[2:0]), + .c05_x_sel_e1_q (c05_x_sel_e1[7:0]), + .c05_y_sel_e1_q (c05_y_sel_e1[4:0]), + .c06_x_sel_e1_q (c06_x_sel_e1[5:0]), + .c06_y_sel_e1_q (c06_y_sel_e1[4:0]), + .c07_x_sel_e1_q (c07_x_sel_e1[6:0]), + .c07_y_sel_e1_q (c07_y_sel_e1[4:0]), + .c08_x_sel_e1_q (c08_x_sel_e1[6:0]), + .c08_y_sel_e1_q (c08_y_sel_e1[2:0]), + .c09_x_sel_e1_q (c09_x_sel_e1[8:0]), + .c09_y_sel_e1_q (c09_y_sel_e1[5:0]), + .c10_x_sel_e1_q (c10_x_sel_e1[8:0]), + .c10_y_sel_e1_q (c10_y_sel_e1[5:0]), + .c11_x_sel_e1_q (c11_x_sel_e1[9:0]), + .c11_y_sel_e1_q (c11_y_sel_e1[7:0]), + .c12_x_sel_e1_q (c12_x_sel_e1[7:0]), + .c12_y_sel_e1_q (c12_y_sel_e1[5:0]), + .c13_x_sel_e1_q (c13_x_sel_e1[9:0]), + .c13_y_sel_e1_q (c13_y_sel_e1[6:0]), + .c14_x_sel_e1_q (c14_x_sel_e1[7:0]), + .c14_y_sel_e1_q (c14_y_sel_e1[6:0]), + .c15_x_sel_e1_q (c15_x_sel_e1[7:0]), + .c15_y_sel_e1_q (c15_y_sel_e1[6:0]), + .ck_gclkcx_int (ck_gclkcx_intk), + .cx_reset3 (cx_reset3), + .iacc_cin_sel_e3_q (iacc_cin_sel_e3_q[7:1]), + .iacc_en_e2 (iacc_en_e2), + .iacc_shfsel_e2 (iacc_shfsel_e2), + .iacce4_fwd_e2 (iacce4_fwd_e2), + .ialuout_e3_q (ialuout_ke3_q[127:0]), + .ishf3_iss_e2_q (ishf3_iss_e2), + .ishf3_iss_e3_q (ishf3_iss_e3), + .ishf3_uiss_e2_q (ishf3_uiss_e2), + .ishf_imm_e1_q (ishf_imm_e1), + .ishf_immv_e1_q (ishf_immv_e1[7:0]), + .ishf_insert_e1_q (ishf_insert_e1), + .ishf_iss_e1_q (ishf_iss_e1), + .ishf_iss_e2_q (ishf_iss_e2), + .ishf_left_e1_q (ishf_left_e1), + .ishf_narrow_e1_q (ishf_narrow_e1), + .ishf_round_e1_q (ishf_round_e1), + .ishf_s1_sel_e1_q (ishf_s1_sel_e1[2:0]), + .ishf_s2_sel_e1_q (ishf_s2_sel_e1[2:0]), + .ishf_s3_sel_e1_q (ishf_s3_sel_e1[3:0]), + .ishf_s4_sel_e1_q (ishf_s4_sel_e1[2:0]), + .ishf_s5_sel_e1_q (ishf_s5_sel_e1[3:0]), + .ishf_s6_sel_e1_q (ishf_s6_sel_e1[3:0]), + .ishf_s7_sel_e1_q (ishf_s7_sel_e1[4:0]), + .ishf_saturate_e1_q (ishf_saturate_e1), + .ishf_scalar_e1 (ishf_scalar_e1), + .ishf_sel16_e1_q (ishf_sel16_e1), + .ishf_sel32_e1_q (ishf_sel32_e1), + .ishf_sel64_e1_q (ishf_sel64_e1), + .ishf_sel8_e1_q (ishf_sel8_e1), + .ishf_selqsat_e3_q (ishf_selqsat_e3), + .ishf_signed_e1_q (ishf_signed_e1), + .ishf_stous_e1_q (ishf_stous_e1), + .ishf_uiss_e2_q (ishf_uiss_e2), + .ishf_widen_e1_q (ishf_widen_e1), + .opa_e1_q (cx_srca_int_data_ke1[63:0]), + .opb_e1_q (cx_srcb_int_data_ke1[63:0]), + .opc_e3_q (cx_srcc_data_ke3[63:0]), + .opd_e3_q (cx_srcd_data_ke3[63:0]), + .shf_size_eq64_e3_q (shf_size_eq64_e3_q), + .shf_size_ge32_e3_q (shf_size_ge32_e3_q), + .shf_size_ne08_e3_q (shf_size_ne08_e3_q) + ); // uishfk + + maia_cx_crypt2 ucrypt2( // outputs + .crypt2_active (crypt2_active), + .crypt2_out_e3_q (crypt2_out_e3_q[127:0]), + + // inputs + .aesd_e1_q (aesd_e1), + .aesdimc_e1_q (aesdimc_e1), + .aese_e1_q (aese_e1), + .aesemc_e1_q (aesemc_e1), + .aesimc_e1_q (aesimc_e1), + .aesmc_e1_q (aesmc_e1), + .ck_gclkcx_crypt (ck_gclkcx_crypt), + .cx_reset3 (cx_reset3), + .ival_e1_q (crypt2_vld_e1), + .pmull_e1_q (pmull_e1), + .qd ({cx_srcd_crypt_data_je1[63:0], cx_srcc_crypt_data_je1[63:0]}), + .qn ({cx_srcb_crypt_data_je1[63:0], cx_srca_crypt_data_je1[63:0]}), + .sha1h_e1_q (sha1h_e1), + .sha1su1_e1_q (sha1su1_e1), + .sha256su0_e1_q (sha256su0_e1) + ); // ucrypt2 + + maia_cx_crypt3 ucrypt3( // outputs + .crypt3_active (crypt3_active), + .crypt3_out_e6_q (crypt3_out_e6_q[127:0]), + + // inputs + .ck_gclkcx_crypt (ck_gclkcx_crypt), + .cx_reset3 (cx_reset3), + .ival_e1_q (crypt3_vld0_e1), + .ival_e2_q (crypt3_vld1_e1), + .qd_e2_q ({cx_srcb_crypt_data_je1[63:0], cx_srca_crypt_data_je1[63:0]}), + .qm_e1_q ({cx_srcd_crypt_data_je1[63:0], cx_srcc_crypt_data_je1[63:0]}), + .qn_e1_q ({cx_srcb_crypt_data_je1[63:0], cx_srca_crypt_data_je1[63:0]}), + .sha1c_e1_q (sha1c_e1), + .sha1m_e1_q (sha1m_e1), + .sha1p_e1_q (sha1p_e1), + .sha256h2_e1_q (sha256h2_e1), + .sha256h_e1_q (sha256h_e1), + .sha256su1_e1_q (sha256su1_e1) + ); // ucrypt3 + + maia_cx_fsqrt ufsqrtk( // outputs + .fsqrt_active (fsqrt_active), + .fsqrt_done (fsqrt_done[1:0]), + .fsqrtexc32_q (fsqrtexc32_q[5:0]), + .fsqrtexc64_q (fsqrtexc64_q[5:0]), + .fsqrtout32_q (fsqrtout32_q[31:0]), + .fsqrtout64_q (fsqrtout64_q[63:0]), + + // inputs + .ck_gclkcx_float (ck_gclkcx_floatk), + .cx_reset3 (cx_reset3), + .dn_e1_q (dn_ke1), + .fsqrt_ccpass_e1 (cx_ccpass_ke1), + .fsqrt_cmd_e1_q (fsqrt_cmd_e1[2:0]), + .fsqrt_flush (fsqrt_flush[1:0]), + .fsqrt_vld_e1 (fsqrt_uop_vld_ke1[1:0]), + .fz_e1_q (fz_ke1), + .opa_e1_q (cx_srca_fp_data32_ke1[63:0]), + .opc_e1_q (cx_srcc_fp_data32_ke1[31:0]), + .opd_e1_q (cx_srcd_fp_data32_ke1[31:0]), + .rmode_e1_q (rmode_ke1[1:0]) + ); // ufsqrtk +endmodule // maia_complex + + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt2.v b/Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt2.v new file mode 100644 index 0000000000..6c292397b2 --- /dev/null +++ b/Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt2.v @@ -0,0 +1,351 @@ + +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: maia_cx_crypt2.v $ +// Checked In : $Date: 2014-08-29 00:16:46 -0500 (Fri, 29 Aug 2014) $ +// Revision : $Revision: 70482 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// This block does the following operations: +// - AES encrypt and decrypt operations: aesd, aese, aesmc, aesimc +// - SHA single-cycle operations: sha1h, sha1su1, sha256su0 + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +module maia_cx_crypt2 ( + +//# +//# Interface Signals +//# ================= +//# + +// Global inputs + ck_gclkcx_crypt, + cx_reset3, + +// Control inputs + ival_e1_q, + aesd_e1_q, + aese_e1_q, + aesmc_e1_q, + aesimc_e1_q, + aesdimc_e1_q, + aesemc_e1_q, + pmull_e1_q, + sha1h_e1_q, + sha1su1_e1_q, + sha256su0_e1_q, + + +// Data inputs + qd, + qn, + + +// Outputs + crypt2_out_e3_q, + crypt2_active +); + + +//# +//# Interface Signals +//# ================= +//# + +// Global inputs + input ck_gclkcx_crypt; + input cx_reset3; + +// Control inputs + input ival_e1_q; + input aesd_e1_q; // aes encode + input aese_e1_q; // aes decode + input aesmc_e1_q; // ae smix columns + input aesimc_e1_q; // aes inverse mix columns + input aesdimc_e1_q; // aes decode superop + input aesemc_e1_q; // aes encode superop + input pmull_e1_q; // polynomial multiplication + input sha1h_e1_q; // sha1 fixed rotate + input sha1su1_e1_q; // sha1 schedule update 1 + input sha256su0_e1_q; // sha256 schedule update 0 + + +// Data inputs + input [127:0] qd; + input [127:0] qn; + + +// Outputs + output [127:0] crypt2_out_e3_q; + output crypt2_active; + +//# +//# Internal Signals - Automatic Declarations +//# ========================================= +//# + wire [ 15: 0] aes_shf_e1; + reg [ 15: 0] aes_shf_e2_q; + wire [127: 0] aesd_e1; + reg aesd_e2_q; + wire aesd_or_e_e1; + wire [127: 0] aesd_out; + wire [ 15: 0] aesd_shf_e1; + reg aesdimc_e2_q; + wire [127: 0] aesdimc_out; + wire [127: 0] aese_e1; + reg aese_e2_q; + wire [127: 0] aese_out; + wire [ 15: 0] aese_shf_e1; + reg aesemc_e2_q; + wire [127: 0] aesemc_out; + reg aesimc_e2_q; + wire [127: 0] aesimc_in; + wire [127: 0] aesimc_out; + reg aesmc_e2_q; + wire [127: 0] aesmc_in; + wire [127: 0] aesmc_out; + wire [127: 0] crypt2_d_e1; + reg [127: 0] crypt2_d_e2_q; + wire [127: 0] crypt2_out_e2; + reg [127: 0] crypt2_out_e3_q; + reg ival_e2_q; + reg pmull_e2_q; + wire [127: 0] pmull_out; + wire [127: 0] qx_e1; + wire [ 31: 0] sha1h_in_e1; + wire [ 31: 0] sha1h_out_e1; + wire [127: 0] sha1su1_out_e1; + wire [127: 0] sha1su1_qdin_e1; + wire [127: 0] sha1su1_qnin_e1; + wire [127: 0] sha256su0_out_e1; + wire sha_inst_e1; + reg sha_inst_e2_q; + +//# +//# Main Code +//# ========= +//# +// + +// aes functions are all in the same block because of limited result bus bandwidth. +// Mais CX has 3x64-bit result buses, and each of these instructions produces +// a 128-bit result. Two instructions could be issued in a cycle, but there is +// no value in doing this because they could not both write results. +// +// The single-cycle 2-input SHA instructions are in the same block because they have the same inputs +// and latency as the aes instructions. +// +// Originally, all functions in this block had single-cycle latency, but CX is unable to make use +// of single-cycle latency. To reduce area, functionality is spread across E1 and E2 +// In particular, the AES SBOX and ISBOX functions are split into LUT(mult inverse) -> affine transform +// & affine inverse transform -> LUT(mult inverse), so that they can share the same LUT. + +// E1 +// 38% of this cycle is used up to drive qd and qn from the issq block. Therefore, the relatively +// shallow SHA operations are performed in this cycle, along with some preliminary processing for AESE and AESD + +assign qx_e1[127:0] = {128{aesd_or_e_e1}} & (qd[127:0] ^ qn[127:0]); + + maia_cx_aese1 uaese1( + .q (qx_e1[127:0]), + .aese_out (aese_e1[127:0]), + .aese_shf (aese_shf_e1[15:0]) +); + + maia_cx_aesd1 uaesd1( + .q (qx_e1[127:0]), + .aesd_out (aesd_e1[127:0]), + .aesd_shf (aesd_shf_e1[15:0]) +); + +assign aesd_or_e_e1 = aesd_e1_q | aese_e1_q; + +// Perform sha functions in E1 to save pipeline flops +// and reduce complexity of multiplexer in E2 + +assign sha1h_in_e1[31:0] = {32{sha1h_e1_q}} & qn[31:0]; + + maia_cx_sha1h usha1h( + .qn (sha1h_in_e1[31:0]), + .d (sha1h_out_e1[31:0]) +); + +assign sha1su1_qdin_e1[127:0] = {128{sha1su1_e1_q}} & qd[127:0]; +assign sha1su1_qnin_e1[127:0] = {128{sha1su1_e1_q}} & qn[127:0]; + + maia_cx_sha1su1 usha1su1( + .qd (sha1su1_qdin_e1[127:0]), + .qn (sha1su1_qnin_e1[127:0]), + .d (sha1su1_out_e1[127:0]) +); + + + maia_cx_sha256su0 usha256su0( + .qd (qd[127:0]), + .qn (qn[127:0]), + .d (sha256su0_out_e1[127:0]) +); + +assign sha_inst_e1 = sha1h_e1_q | sha1su1_e1_q | sha256su0_e1_q; + +assign crypt2_d_e1[127:0] = ({128{sha1h_e1_q}} & {{96{1'b0}}, sha1h_out_e1[31:0]}) + | ({128{sha1su1_e1_q}} & sha1su1_out_e1[127:0]) + | ({128{sha256su0_e1_q}} & sha256su0_out_e1[127:0]) + | ({128{aese_e1_q}} & aese_e1[127:0]) + | ({128{aesd_e1_q}} & aesd_e1[127:0]) + | ({128{~(aesd_or_e_e1 | sha_inst_e1)}} & qn[127:0]); + +assign aes_shf_e1[15:0] = {16{aese_e1_q}} & aese_shf_e1[15:0] | + {16{aesd_e1_q}} & aesd_shf_e1[15:0]; + +// reset flop(s) since feeds into active signal used for RCG + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt or posedge cx_reset3) + begin: uival_e2_q + if (cx_reset3 == 1'b1) + ival_e2_q <= `MAIA_DFF_DELAY {1{1'b0}}; +`ifdef MAIA_XPROP_FLOP + else if (cx_reset3==1'b0) + ival_e2_q <= `MAIA_DFF_DELAY ival_e1_q; + else + ival_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; +`else + else + ival_e2_q <= `MAIA_DFF_DELAY ival_e1_q; +`endif + end + // verilint flop_checks on + // end of Macro DFF + + + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt) + begin: ucrypt2_e2 + if (ival_e1_q==1'b1) begin + crypt2_d_e2_q[127:0] <= `MAIA_DFF_DELAY crypt2_d_e1[127:0]; + aes_shf_e2_q[15:0] <= `MAIA_DFF_DELAY aes_shf_e1[15:0]; + aesd_e2_q <= `MAIA_DFF_DELAY aesd_e1_q; + aese_e2_q <= `MAIA_DFF_DELAY aese_e1_q; + aesmc_e2_q <= `MAIA_DFF_DELAY aesmc_e1_q; + aesimc_e2_q <= `MAIA_DFF_DELAY aesimc_e1_q; + aesemc_e2_q <= `MAIA_DFF_DELAY aesemc_e1_q; + aesdimc_e2_q <= `MAIA_DFF_DELAY aesdimc_e1_q; + pmull_e2_q <= `MAIA_DFF_DELAY pmull_e1_q; + sha_inst_e2_q <= `MAIA_DFF_DELAY sha_inst_e1; + end +`ifdef MAIA_XPROP_FLOP + else if ((ival_e1_q==1'b0)); + else begin + crypt2_d_e2_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; + aes_shf_e2_q[15:0] <= `MAIA_DFF_DELAY {16{1'bx}}; + aesd_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + aese_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + aesmc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + aesimc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + aesemc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + aesdimc_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + pmull_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha_inst_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + end +`endif + end + // verilint flop_checks on + // end of Macro DFF + +// Enable data inputs for selected operation (glitch suppression in unused datapaths) + assign aesmc_in[127:0] = {128{aesmc_e2_q }} & crypt2_d_e2_q[127:0]; + assign aesimc_in[127:0] = {128{aesimc_e2_q}} & crypt2_d_e2_q[127:0]; + + maia_cx_aesed2 uaesed2( + .aes_din (crypt2_d_e2_q[127:0]), + .aes_shf (aes_shf_e2_q[15:0]), + .aesd_out (aesd_out[127:0]), + .aese_out (aese_out[127:0]), + .aesemc_out (aesemc_out[127:0]), + .aesdimc_out (aesdimc_out[127:0]) +); + + maia_cx_aesmc uaesmc( + .d_in (aesmc_in[127:0]), + .mc (aesmc_out[127:0]) +); + + maia_cx_aesimc uaesimc( + .d_in (aesimc_in[127:0]), + .imc (aesimc_out[127:0]) +); + + maia_cx_pmull upmull( + .a_in (crypt2_d_e2_q[63:0]), + .b_in (crypt2_d_e2_q[127:64]), + .p_out (pmull_out[127:0]) +); + +assign crypt2_out_e2[127:0] = ({128{aesd_e2_q & ~aesdimc_e2_q}} & aesd_out[127:0]) + | ({128{aese_e2_q & ~aesemc_e2_q}} & aese_out[127:0]) + | ({128{aesmc_e2_q}} & aesmc_out[127:0]) + | ({128{aesemc_e2_q}} & aesemc_out[127:0]) + | ({128{aesimc_e2_q}} & aesimc_out[127:0]) + | ({128{aesdimc_e2_q}} & aesdimc_out[127:0]) + | ({128{sha_inst_e2_q}} & crypt2_d_e2_q[127:0]) + | ({128{pmull_e2_q}} & pmull_out[127:0]); + + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt) + begin: ucrypt2_e3 + if (ival_e2_q==1'b1) begin + crypt2_out_e3_q[127:0] <= `MAIA_DFF_DELAY crypt2_out_e2[127:0]; + end +`ifdef MAIA_XPROP_FLOP + else if ((ival_e2_q==1'b0)); + else begin + crypt2_out_e3_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; + end +`endif + end + // verilint flop_checks on + // end of Macro DFF + +//----------------------------------------------------------------------------- +// regional clock gating (RCG) terms +//----------------------------------------------------------------------------- + +assign crypt2_active = (ival_e1_q | ival_e2_q); + + +endmodule + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt3.v b/Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt3.v new file mode 100644 index 0000000000..3654c6017b --- /dev/null +++ b/Security Algo Accelerator/logical/maia_complex/verilog/maia_cx_crypt3.v @@ -0,0 +1,713 @@ + +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2013-2014 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// Filename : $RCSfile: maia_cx_crypt3.v $ +// Checked In : $Date: 2014-08-29 00:16:46 -0500 (Fri, 29 Aug 2014) $ +// Revision : $Revision: 70482 $ +// Release Information : Cortex-A72-r1p0-00rel0 +// +//----------------------------------------------------------------------------- +// Verilog-2001 (IEEE Std 1364-2001) +//----------------------------------------------------------------------------- + +//# +//# Overview +//# ======== +//# + +// This block does the following operations: +// - SHA 3-input operations: sha1cpm, sha1su0, sha256h, sha256h2, sha256su1 + +//# +//# Module Declaration +//# ================== +//# + +`include "maia_header.v" + +module maia_cx_crypt3 ( + +//# +//# Interface Signals +//# ================= +//# + +// Global inputs + ck_gclkcx_crypt, + cx_reset3, + +// Control inputs +// +// This block has 3x128-bit inputs for each instruction, so it requires two cycles just to +// get its operands. In E1, we receive two of the operands (qn and qm) and ival_e1_q, +// which allows the operands to be stored in flops. We also get inputs indicating which +// instruction is to be computed. +// +// At some later cycle, we receive the 3rd operand, qd, and ival_e2_q, indicating that +// we should begin the computation. +// +// There are 4 execution stages, E2-E5. + ival_e1_q, + sha1c_e1_q, + sha1p_e1_q, + sha1m_e1_q, + sha256h_e1_q, + sha256h2_e1_q, + sha256su1_e1_q, + ival_e2_q, +// Data inputs + qn_e1_q, + qm_e1_q, + qd_e2_q, +// Outputs + crypt3_out_e6_q, + crypt3_active +); + + +//# +//# Interface Signals +//# ================= +//# + +// Global inputs + input ck_gclkcx_crypt; + input cx_reset3; + +// Control inputs +// +// This block has 3x128-bit inputs for each instruction, so it requires two cycles just to +// get its operands. In E1, we receive two of the operands (qn and qm) and ival_e1_q, +// which allows the operands to be stored in flops. We also get inputs indicating which +// instruction is to be computed. +// +// At some later cycle, we receive the 3rd operand, qd, and ival_e2_q, indicating that +// we should begin the computation. +// +// There are 4 execution stages, E2-E5. + input ival_e1_q; + input sha1c_e1_q; // sha hash update (choose) + input sha1p_e1_q; // sha hash update (parity) + input sha1m_e1_q; // sha hash update (majority) + input sha256h_e1_q; // sha256 hash update + input sha256h2_e1_q; // sha256 hash update 2 + input sha256su1_e1_q; // sha256 schedule update 1 + input ival_e2_q; +// Data inputs + input [127:0] qn_e1_q; // qn arrives with first uop on {srcb,srca} + input [127:0] qm_e1_q; // qm arrives with first uop on {srcd,srcc} + input [127:0] qd_e2_q; // qd arrives with second uop on {srcb,srca} +// Outputs + output [127:0] crypt3_out_e6_q; + output crypt3_active; + +//# +//# Internal Signals - Automatic Declarations +//# ========================================= +//# + wire [127: 0] crypt3_out_e5; + reg [127: 0] crypt3_out_e6_q; + wire firstop_recvd_e1; + reg firstop_recvd_e2_q; + reg ival_e3_q; + reg ival_e4_q; + reg ival_e5_q; + wire [127: 0] newx_e2; + wire [127: 0] newx_e3; + wire [127: 0] newx_e4; + wire [127: 0] newy_e2; + wire [127: 0] newy_e3; + wire [127: 0] newy_e4; + reg [127: 0] qm_e2_q; + reg [127: 0] qn_e2_q; + wire [127: 0] sha1_xin_e2; + wire [ 31: 0] sha1_yin_e2; + wire [ 31: 0] sha1_zin_e2; + wire sha1c_e2; + reg sha1c_e2_q; + reg sha1c_e3_q; + reg sha1c_e4_q; + reg sha1c_e5_q; + wire sha1cpm_e2; + wire sha1cpm_e3; + wire sha1cpm_e4; + wire sha1cpm_e5; + wire [127: 0] sha1cpm_x_e2; + wire [127: 0] sha1cpm_x_e3; + wire [127: 0] sha1cpm_x_e4; + wire [127: 0] sha1cpm_x_e5; + wire [127: 0] sha1cpm_y_e2; + wire [127: 0] sha1cpm_y_e3; + wire [127: 0] sha1cpm_y_e4; +// verilint unused_sigs off + wire [ 31: 0] sha1cpm_y_e5; +// verilint unused_sigs on + wire sha1m_e2; + reg sha1m_e2_q; + reg sha1m_e3_q; + reg sha1m_e4_q; + reg sha1m_e5_q; + wire sha1p_e2; + reg sha1p_e2_q; + reg sha1p_e3_q; + reg sha1p_e4_q; + reg sha1p_e5_q; + wire [127: 0] sha256_xin_e2; + wire [127: 0] sha256_yin_e2; + wire [ 31: 0] sha256_zin_e2; + wire sha256h2_e2; + reg sha256h2_e2_q; + reg sha256h2_e3_q; + reg sha256h2_e4_q; + reg sha256h2_e5_q; + wire sha256h_e2; + reg sha256h_e2_q; + reg sha256h_e3_q; + reg sha256h_e4_q; + reg sha256h_e5_q; + wire [127: 0] sha256h_x_e2; + wire [127: 0] sha256h_x_e3; + wire [127: 0] sha256h_x_e4; + wire [127: 0] sha256h_x_e5; + wire [127: 0] sha256h_y_e2; + wire [127: 0] sha256h_y_e3; + wire [127: 0] sha256h_y_e4; + wire [127: 0] sha256h_y_e5; + wire sha256hh2_e2; + wire sha256hh2_e3; + wire sha256hh2_e4; + wire sha256su1_e2; + reg sha256su1_e2_q; + reg sha256su1_e3_q; + reg sha256su1_e4_q; + reg sha256su1_e5_q; + wire [ 63: 0] sha256su1_x_e3; + wire [ 63: 0] sha256su1_x_e4; + wire [127: 0] x_e2; + wire [127: 0] x_e3; + reg [127: 0] x_e3_q; + wire [127: 0] x_e4; + reg [127: 0] x_e4_q; + wire [127: 0] x_e5; + reg [127: 0] x_e5_q; + wire [127: 0] y_e2; + wire [127: 0] y_e3; + reg [127: 0] y_e3_q; + wire [127: 0] y_e4; + reg [127: 0] y_e4_q; + wire [127: 0] y_e5; + reg [127: 0] y_e5_q; + wire [127: 0] z_e2; + wire [ 95: 0] z_e3; + reg [ 95: 0] z_e3_q; + wire [ 63: 0] z_e4; + reg [ 63: 0] z_e4_q; + wire [ 31: 0] z_e5; + reg [ 31: 0] z_e5_q; + +//# +//# Main Code +//# ========= +//# +// + +// set when ival_e1_q first received, and held until the 2nd uop (ival_e2_q) is received +assign firstop_recvd_e1 = (ival_e1_q | (firstop_recvd_e2_q & ~ival_e2_q)); + +// ival and instruction flops + +// reset flop since 1st uop of crypto pair can be flushed due to SWDW nuke, thus might +// have received ival_e2_q without ever receiving ival_e1_q (since it was flushed). thus +// want firstop_recvd_e2_q to be 0 (not X) to stop X-prop + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt or posedge cx_reset3) + begin: ufirstop_recvd_e2_q + if (cx_reset3 == 1'b1) + firstop_recvd_e2_q <= `MAIA_DFF_DELAY {1{1'b0}}; +`ifdef MAIA_XPROP_FLOP + else if (cx_reset3==1'b0) + firstop_recvd_e2_q <= `MAIA_DFF_DELAY firstop_recvd_e1; + else + firstop_recvd_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; +`else + else + firstop_recvd_e2_q <= `MAIA_DFF_DELAY firstop_recvd_e1; +`endif + end + // verilint flop_checks on + // end of Macro DFF + +// reset flop(s) since feeds into active signal used for RCG + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt or posedge cx_reset3) + begin: uival_e3_q + if (cx_reset3 == 1'b1) + ival_e3_q <= `MAIA_DFF_DELAY {1{1'b0}}; +`ifdef MAIA_XPROP_FLOP + else if (cx_reset3==1'b0) + ival_e3_q <= `MAIA_DFF_DELAY ival_e2_q; + else + ival_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; +`else + else + ival_e3_q <= `MAIA_DFF_DELAY ival_e2_q; +`endif + end + // verilint flop_checks on + // end of Macro DFF + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt or posedge cx_reset3) + begin: uival_e4_q + if (cx_reset3 == 1'b1) + ival_e4_q <= `MAIA_DFF_DELAY {1{1'b0}}; +`ifdef MAIA_XPROP_FLOP + else if (cx_reset3==1'b0) + ival_e4_q <= `MAIA_DFF_DELAY ival_e3_q; + else + ival_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; +`else + else + ival_e4_q <= `MAIA_DFF_DELAY ival_e3_q; +`endif + end + // verilint flop_checks on + // end of Macro DFF + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt or posedge cx_reset3) + begin: uival_e5_q + if (cx_reset3 == 1'b1) + ival_e5_q <= `MAIA_DFF_DELAY {1{1'b0}}; +`ifdef MAIA_XPROP_FLOP + else if (cx_reset3==1'b0) + ival_e5_q <= `MAIA_DFF_DELAY ival_e4_q; + else + ival_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; +`else + else + ival_e5_q <= `MAIA_DFF_DELAY ival_e4_q; +`endif + end + // verilint flop_checks on + // end of Macro DFF + + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt) + begin: uinst_e2 + if (ival_e1_q==1'b1) begin + sha1c_e2_q <= `MAIA_DFF_DELAY sha1c_e1_q; + sha1p_e2_q <= `MAIA_DFF_DELAY sha1p_e1_q; + sha1m_e2_q <= `MAIA_DFF_DELAY sha1m_e1_q; + sha256h_e2_q <= `MAIA_DFF_DELAY sha256h_e1_q; + sha256h2_e2_q <= `MAIA_DFF_DELAY sha256h2_e1_q; + sha256su1_e2_q <= `MAIA_DFF_DELAY sha256su1_e1_q; + end +`ifdef MAIA_XPROP_FLOP + else if ((ival_e1_q==1'b0)); + else begin + sha1c_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha1p_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha1m_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha256h_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha256h2_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha256su1_e2_q <= `MAIA_DFF_DELAY {1{1'bx}}; + end +`endif + end + // verilint flop_checks on + // end of Macro DFF + +// stop X-prop if 1st uop was nuked due to swdw_nuke and 2nd was issued + +assign sha1c_e2 = firstop_recvd_e2_q & sha1c_e2_q; +assign sha1p_e2 = firstop_recvd_e2_q & sha1p_e2_q; +assign sha1m_e2 = firstop_recvd_e2_q & sha1m_e2_q; +assign sha256h_e2 = firstop_recvd_e2_q & sha256h_e2_q; +assign sha256h2_e2 = firstop_recvd_e2_q & sha256h2_e2_q; +assign sha256su1_e2 = firstop_recvd_e2_q & sha256su1_e2_q; + + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt) + begin: uinst_e3 + if (ival_e2_q==1'b1) begin + sha1c_e3_q <= `MAIA_DFF_DELAY sha1c_e2; + sha1p_e3_q <= `MAIA_DFF_DELAY sha1p_e2; + sha1m_e3_q <= `MAIA_DFF_DELAY sha1m_e2; + sha256h_e3_q <= `MAIA_DFF_DELAY sha256h_e2; + sha256h2_e3_q <= `MAIA_DFF_DELAY sha256h2_e2; + sha256su1_e3_q <= `MAIA_DFF_DELAY sha256su1_e2; + end +`ifdef MAIA_XPROP_FLOP + else if ((ival_e2_q==1'b0)); + else begin + sha1c_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha1p_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha1m_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha256h_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha256h2_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha256su1_e3_q <= `MAIA_DFF_DELAY {1{1'bx}}; + end +`endif + end + // verilint flop_checks on + // end of Macro DFF + + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt) + begin: uinst_e4 + if (ival_e3_q==1'b1) begin + sha1c_e4_q <= `MAIA_DFF_DELAY sha1c_e3_q; + sha1p_e4_q <= `MAIA_DFF_DELAY sha1p_e3_q; + sha1m_e4_q <= `MAIA_DFF_DELAY sha1m_e3_q; + sha256h_e4_q <= `MAIA_DFF_DELAY sha256h_e3_q; + sha256h2_e4_q <= `MAIA_DFF_DELAY sha256h2_e3_q; + sha256su1_e4_q <= `MAIA_DFF_DELAY sha256su1_e3_q; + end +`ifdef MAIA_XPROP_FLOP + else if ((ival_e3_q==1'b0)); + else begin + sha1c_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha1p_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha1m_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha256h_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha256h2_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha256su1_e4_q <= `MAIA_DFF_DELAY {1{1'bx}}; + end +`endif + end + // verilint flop_checks on + // end of Macro DFF + + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt) + begin: uinst_e5 + if (ival_e4_q==1'b1) begin + sha1c_e5_q <= `MAIA_DFF_DELAY sha1c_e4_q; + sha1p_e5_q <= `MAIA_DFF_DELAY sha1p_e4_q; + sha1m_e5_q <= `MAIA_DFF_DELAY sha1m_e4_q; + sha256h_e5_q <= `MAIA_DFF_DELAY sha256h_e4_q; + sha256h2_e5_q <= `MAIA_DFF_DELAY sha256h2_e4_q; + sha256su1_e5_q <= `MAIA_DFF_DELAY sha256su1_e4_q; + end +`ifdef MAIA_XPROP_FLOP + else if ((ival_e4_q==1'b0)); + else begin + sha1c_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha1p_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha1m_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha256h_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha256h2_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; + sha256su1_e5_q <= `MAIA_DFF_DELAY {1{1'bx}}; + end +`endif + end + // verilint flop_checks on + // end of Macro DFF + +// E1 + + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt) + begin: uops_e2 + if (ival_e1_q==1'b1) begin + qm_e2_q[127:0] <= `MAIA_DFF_DELAY qm_e1_q[127:0]; + qn_e2_q[127:0] <= `MAIA_DFF_DELAY qn_e1_q[127:0]; + end +`ifdef MAIA_XPROP_FLOP + else if ((ival_e1_q==1'b0)); + else begin + qm_e2_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; + qn_e2_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; + end +`endif + end + // verilint flop_checks on + // end of Macro DFF + +// E2 +assign x_e2[127:0] = qd_e2_q[127:0]; +assign y_e2[127:0] = qn_e2_q[127:0]; +assign z_e2[127:0] = qm_e2_q[127:0]; + +assign sha1_xin_e2[127:0] = {128{sha1cpm_e2}} & x_e2[127:0]; +assign sha1_yin_e2[ 31:0] = { 32{sha1cpm_e2}} & y_e2[ 31:0]; +assign sha1_zin_e2[ 31:0] = { 32{sha1cpm_e2}} & z_e2[ 31:0]; + +// sha1 hash update + maia_cx_sha1cpm usha1cpm_e2( + .choose (sha1c_e2_q), + .parity (sha1p_e2_q), + .majority (sha1m_e2_q), + .x (sha1_xin_e2[127:0]), + .y (sha1_yin_e2[31:0]), + .z (sha1_zin_e2[31:0]), + .newx (sha1cpm_x_e2[127:0]), + .newy (sha1cpm_y_e2[31:0]) +); +assign sha1cpm_y_e2[127:32] = {96{sha1cpm_e2}} & y_e2[127:32]; + +assign sha256_xin_e2[127:0] = {128{sha256hh2_e2}} & x_e2[127:0]; +assign sha256_yin_e2[127:0] = {128{sha256hh2_e2}} & y_e2[127:0]; +assign sha256_zin_e2[ 31:0] = { 32{sha256hh2_e2}} & z_e2[ 31:0]; + +// sha256 hash update (1 and 2) + maia_cx_sha256h32 usha256h32_e2( + .x (sha256_xin_e2[127:0]), + .y (sha256_yin_e2[127:0]), + .z (sha256_zin_e2[31:0]), + .newx (sha256h_x_e2[127:0]), + .newy (sha256h_y_e2[127:0]) +); + +// mux results +assign sha1cpm_e2 = sha1c_e2 | sha1p_e2 | sha1m_e2; +assign sha256hh2_e2 = sha256h_e2 | sha256h2_e2; +assign newx_e2[127:0] = ({128{sha1cpm_e2 }} & sha1cpm_x_e2[127:0]) + | ({128{sha256hh2_e2}} & sha256h_x_e2[127:0]) + | ({128{sha256su1_e2}} & x_e2[127:0]); +assign newy_e2[127:0] = ({128{sha1cpm_e2 }} & sha1cpm_y_e2[127:0]) + | ({128{sha256hh2_e2}} & sha256h_y_e2[127:0]) + | ({128{sha256su1_e2}} & {z_e2[31:0], y_e2[127:32]}); + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt) + begin: uops_e3 + if (ival_e2_q==1'b1) begin + x_e3_q[127:0] <= `MAIA_DFF_DELAY newx_e2[127:0]; + y_e3_q[127:0] <= `MAIA_DFF_DELAY newy_e2[127:0]; + z_e3_q[95:0] <= `MAIA_DFF_DELAY z_e2[127:32]; + end +`ifdef MAIA_XPROP_FLOP + else if ((ival_e2_q==1'b0)); + else begin + x_e3_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; + y_e3_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; + z_e3_q[95:0] <= `MAIA_DFF_DELAY {96{1'bx}}; + end +`endif + end + // verilint flop_checks on + // end of Macro DFF + +// E3 +assign x_e3[127:0] = x_e3_q[127:0]; +assign y_e3[127:0] = y_e3_q[127:0]; +assign z_e3[95:0] = z_e3_q[95:0]; + +// sha1 hash update + maia_cx_sha1cpm usha1cpm_e3( + .choose (sha1c_e3_q), + .parity (sha1p_e3_q), + .majority (sha1m_e3_q), + .x (x_e3[127:0]), + .y (y_e3[31:0]), + .z (z_e3[31:0]), + .newx (sha1cpm_x_e3[127:0]), + .newy (sha1cpm_y_e3[31:0]) +); +assign sha1cpm_y_e3[127:32] = y_e3[127:32]; + +// sha256 hash update (1 and 2) + maia_cx_sha256h32 usha256h32_e3( + .x (x_e3[127:0]), + .y (y_e3[127:0]), + .z (z_e3[31:0]), + .newx (sha256h_x_e3[127:0]), + .newy (sha256h_y_e3[127:0]) +); + +// sha256 schedule update 1, cycle 1 + maia_cx_sha256su1 usha256su1_e3( + .sha256su1_op (sha256su1_e3_q), + .x (x_e3[63:0]), // qd[63:0] + .y (y_e3[63:0]), // qn[95:32] + .z (z_e3[95:32]), // qm[127:64] + .newx (sha256su1_x_e3[63:0]) +); + +// mux results +assign sha1cpm_e3 = sha1c_e3_q | sha1p_e3_q | sha1m_e3_q; +assign sha256hh2_e3 = sha256h_e3_q | sha256h2_e3_q; +assign newx_e3[127:0] = ({128{sha1cpm_e3 }} & sha1cpm_x_e3[127:0]) + | ({128{sha256hh2_e3 }} & sha256h_x_e3[127:0]) + | ({128{sha256su1_e3_q}} & {x_e3[127:64], sha256su1_x_e3[63:0]}); +assign newy_e3[127:0] = ({128{sha1cpm_e3 }} & sha1cpm_y_e3[127:0]) + | ({128{sha256hh2_e3 }} & sha256h_y_e3[127:0]) + | ({128{sha256su1_e3_q}} & {y_e3[127:0]}); + + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt) + begin: uops_e4 + if (ival_e3_q==1'b1) begin + x_e4_q[127:0] <= `MAIA_DFF_DELAY newx_e3[127:0]; + y_e4_q[127:0] <= `MAIA_DFF_DELAY newy_e3[127:0]; + z_e4_q[63:0] <= `MAIA_DFF_DELAY z_e3[95:32]; + end +`ifdef MAIA_XPROP_FLOP + else if ((ival_e3_q==1'b0)); + else begin + x_e4_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; + y_e4_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; + z_e4_q[63:0] <= `MAIA_DFF_DELAY {64{1'bx}}; + end +`endif + end + // verilint flop_checks on + // end of Macro DFF + +// E4 +assign x_e4[127:0] = x_e4_q[127:0]; +assign y_e4[127:0] = y_e4_q[127:0]; +assign z_e4[63:0] = z_e4_q[63:0]; + +// sha1 hash update + maia_cx_sha1cpm usha1cpm_e4( + .choose (sha1c_e4_q), + .parity (sha1p_e4_q), + .majority (sha1m_e4_q), + .x (x_e4[127:0]), + .y (y_e4[31:0]), + .z (z_e4[31:0]), + .newx (sha1cpm_x_e4[127:0]), + .newy (sha1cpm_y_e4[31:0]) +); +assign sha1cpm_y_e4[127:32] = y_e4[127:32]; + +// sha256 hash update (1 and 2) + maia_cx_sha256h32 usha256h32_e4( + .x (x_e4[127:0]), + .y (y_e4[127:0]), + .z (z_e4[31:0]), + .newx (sha256h_x_e4[127:0]), + .newy (sha256h_y_e4[127:0]) +); + +// sha256 schedule update 1, cycle 2 + maia_cx_sha256su1 usha256su1_e4( + .sha256su1_op (sha256su1_e4_q), + .x (x_e4[127:64]), // qd[127:64] + .y (y_e4[127:64]), // {qm[31:0], qn[127:96]} + .z (x_e4[63:0]), // sha256su1_x_e3[63:0] + .newx (sha256su1_x_e4[63:0]) +); + +// mux results +assign sha1cpm_e4 = sha1c_e4_q | sha1p_e4_q | sha1m_e4_q; +assign sha256hh2_e4 = sha256h_e4_q | sha256h2_e4_q; +assign newx_e4[127:0] = ({128{sha1cpm_e4 }} & sha1cpm_x_e4[127:0]) + | ({128{sha256hh2_e4 }} & sha256h_x_e4[127:0]) + | ({128{sha256su1_e4_q}} & {sha256su1_x_e4[63:0], x_e4[63:0]}); +assign newy_e4[127:0] = ({128{sha1cpm_e4 }} & sha1cpm_y_e4[127:0]) + | ({128{sha256hh2_e4 }} & sha256h_y_e4[127:0]); + + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt) + begin: uops_e5 + if (ival_e4_q==1'b1) begin + x_e5_q[127:0] <= `MAIA_DFF_DELAY newx_e4[127:0]; + y_e5_q[127:0] <= `MAIA_DFF_DELAY newy_e4[127:0]; + z_e5_q[31:0] <= `MAIA_DFF_DELAY z_e4[63:32]; + end +`ifdef MAIA_XPROP_FLOP + else if ((ival_e4_q==1'b0)); + else begin + x_e5_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; + y_e5_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; + z_e5_q[31:0] <= `MAIA_DFF_DELAY {32{1'bx}}; + end +`endif + end + // verilint flop_checks on + // end of Macro DFF + +// E5 +assign x_e5[127:0] = x_e5_q[127:0]; +assign y_e5[127:0] = y_e5_q[127:0]; +assign z_e5[31:0] = z_e5_q[31:0]; + +// sha1 hash update + maia_cx_sha1cpm usha1cpm_e5( + .choose (sha1c_e5_q), + .parity (sha1p_e5_q), + .majority (sha1m_e5_q), + .x (x_e5[127:0]), + .y (y_e5[31:0]), + .z (z_e5[31:0]), + .newx (sha1cpm_x_e5[127:0]), + .newy (sha1cpm_y_e5[31:0]) +); + +// sha256 hash update (1 and 2) + maia_cx_sha256h32 usha256h32_e5( + .x (x_e5[127:0]), + .y (y_e5[127:0]), + .z (z_e5[31:0]), + .newx (sha256h_x_e5[127:0]), + .newy (sha256h_y_e5[127:0]) +); + +// mux results +assign sha1cpm_e5 = sha1c_e5_q | sha1p_e5_q | sha1m_e5_q; +assign crypt3_out_e5[127:0] = ({128{sha1cpm_e5}} & sha1cpm_x_e5[127:0]) + | ({128{sha256h_e5_q}} & sha256h_x_e5[127:0]) + | ({128{sha256h2_e5_q}} & sha256h_y_e5[127:0]) + | ({128{sha256su1_e5_q}} & x_e5[127:0]); + + // Macro DFF called + // verilint flop_checks off + always @(posedge ck_gclkcx_crypt) + begin: ures_e6 + if (ival_e5_q==1'b1) begin + crypt3_out_e6_q[127:0] <= `MAIA_DFF_DELAY crypt3_out_e5[127:0]; + end +`ifdef MAIA_XPROP_FLOP + else if ((ival_e5_q==1'b0)); + else begin + crypt3_out_e6_q[127:0] <= `MAIA_DFF_DELAY {128{1'bx}}; + end +`endif + end + // verilint flop_checks on + // end of Macro DFF + + +//----------------------------------------------------------------------------- +// regional clock gating (RCG) terms +//----------------------------------------------------------------------------- + +assign crypt3_active = (ival_e1_q | + ival_e2_q | + ival_e3_q | + ival_e4_q | + ival_e5_q + ); + + +endmodule + +//ARMAUTO UNDEF START +`define MAIA_UNDEFINE +`include "maia_header.v" +`undef MAIA_UNDEFINE +//ARMAUTO UNDEF END diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/Makefile_A64.inc b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/Makefile_A64.inc new file mode 100644 index 0000000000..901f74f773 --- /dev/null +++ b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/Makefile_A64.inc @@ -0,0 +1,41 @@ +############################################################################### +# The confidential and proprietary information contained in this file may +# only be used by a person authorised under and to the extent permitted +# by a subsisting licensing agreement from ARM Limited. +# +# (C) COPYRIGHT 2011-2013 ARM Limited. +# ALL RIGHTS RESERVED +# +# This entire notice must be reproduced on all copies of this file +# and copies of this file may only be made by a person if such person is +# permitted to do so under the terms of a subsisting license agreement +# from ARM Limited. +# +############################################################################### +# Makefile.inc for crypto64 +# setup source paths (crypto64) + +crypto64_base = crypto64 +crypto64_src = $(crypto64_base)/src +crypto64_obj = $(crypto64_base)/obj +crypto64_elf = $(crypto64_base)/elf + +#rules for crypto64 + +crypto64_asm_obj = $(incl_obj)/benchmark_boot_a64.o $(incl_obj)/vectors.o $(incl_obj)/num_cpus_a64.o $(crypto64_obj)/cryptolib_asm64.o +crypto64_c_obj = $(incl_obj)/sys_a64.o $(incl_obj)/stackheap_a64.o $(crypto64_obj)/cryptodata.o $(crypto64_obj)/crypto_test.o + +crypto64: clean_crypto64 $(crypto64_elf)/crypto64.elf + +$(crypto64_obj)/%.o: $(crypto64_src)/%.c + $(CC_A64) $(CC_A64_OPTS) $< -o $@ + +$(crypto64_obj)/%.o: $(crypto64_src)/%.s + $(AS_A64) $(AS_A64_OPTS) $< -o $@ + +$(crypto64_elf)/crypto64.elf: $(crypto64_asm_obj) $(crypto64_c_obj) + $(LINK_A64) $(LINK_A64_OPTS) $(crypto64_asm_obj) $(crypto64_c_obj) -o $@ + +clean_crypto64: + \rm -f $(crypto64_asm_obj) $(crypto64_c_obj) $(crypto64_elf)/crypto64.elf + diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/elf/crypto64.elf b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/elf/crypto64.elf new file mode 100644 index 0000000000..8a1b9e22b5 Binary files /dev/null and b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/elf/crypto64.elf differ diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/crypto_test.c b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/crypto_test.c new file mode 100644 index 0000000000..0b3272b8d2 --- /dev/null +++ b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/crypto_test.c @@ -0,0 +1,80 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2012-2013 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2013-03-19 09:12:51 +0000 (Tue, 19 Mar 2013) $ +// +// Revision : $Revision: 241584 $ +// +// Release Information : +// +//----------------------------------------------------------------------------- + +#include +#include +#include + +#include "cryptolib.h" +#include "cryptodata.h" +#include "benchmark.h" + +#ifndef BLOCK_SIZE +#define BLOCK_SIZE 1024 +#endif + +#ifndef ITERATIONS +#define ITERATIONS 10 +#endif + +uint8_t get_aes_index( int block_size) +{ + uint8_t index = 0; + uint8_t i; + for (i=4; i<13; i++) + { + if ((block_size >> i) & 0x1) + { + index = i-4; + break; + } + } + return index; +} + +int main() +{ + uint32_t block_size; + uint8_t index; + uint32_t cmpres = 0; + uint8_t i; + + block_size = BLOCK_SIZE; + + uint8_t kv[176]; + printf("AES128-ECB encryption\n"); + index = get_aes_index(block_size); + BENCHSTART + for ( i = 0; i < ITERATIONS; i++) + { + aes128_key_expand(aes128_ecb_encrypt_key[index], kv); + LOOPSTART + aes128_ecb_encrypt(kv, aes128_ecb_encrypt_input[index], aes128_ecb_encrypt_output[index], block_size); + LOOPEND + } + cmpres |= memcmp(aes128_ecb_encrypt_output[index], aes128_ecb_encrypt_ref_output[index], block_size); + if (cmpres) + printf("AES128-ECB encryption failed\n"); + BENCHFINISHED +} + diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.c b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.c new file mode 100644 index 0000000000..e82d909e49 --- /dev/null +++ b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.c @@ -0,0 +1,1591 @@ +const unsigned char aes128_ecb_encrypt_key[][16] __attribute__((aligned(64))) = { + { 0x0a, 0x73, 0xd4, 0x55, 0x90, 0x00, 0x2f, 0xfc, 0xbf, 0x5d, 0x59, 0x92, 0x21, 0x10, 0xf2, 0x27 + }, + { 0xf5, 0x03, 0x1c, 0xe1, 0x1d, 0xbf, 0x4b, 0xa4, 0x6c, 0x7f, 0x50, 0x6f, 0xa8, 0xb3, 0xc5, 0xcf + }, + { 0x44, 0xf3, 0x3a, 0xcc, 0x56, 0x95, 0xf1, 0xa4, 0xe6, 0x5d, 0x3d, 0x7c, 0xe9, 0x53, 0xd2, 0x4f + }, + { 0x49, 0xa5, 0x1e, 0x2b, 0x9d, 0x86, 0x9a, 0x49, 0x63, 0xcb, 0x59, 0xcc, 0x74, 0xb7, 0x47, 0xc1 + }, + { 0x69, 0x3c, 0x5e, 0x36, 0x8c, 0x2e, 0x84, 0x01, 0xe2, 0x80, 0xae, 0x98, 0x48, 0x2c, 0x43, 0xa4 + }, + { 0x58, 0x3b, 0x3f, 0x1e, 0x59, 0x0a, 0x40, 0xc6, 0x92, 0x31, 0xc8, 0x29, 0xbf, 0xbd, 0x80, 0x70 + }, + { 0x79, 0xa7, 0x65, 0xe9, 0xad, 0x9f, 0x54, 0x3d, 0xf3, 0xd2, 0x78, 0xcb, 0x79, 0xa3, 0xb9, 0x40 + }, + { 0x7c, 0x6e, 0xba, 0x1d, 0xf1, 0xf7, 0xaf, 0x50, 0xde, 0xaa, 0x27, 0x4d, 0x9f, 0xcf, 0x44, 0xba + }, + { 0x3c, 0xaa, 0xb1, 0xb5, 0x49, 0x52, 0x3e, 0x4d, 0xd0, 0xb5, 0x73, 0x69, 0x48, 0x83, 0x0c, 0xa4 + }, + }; + +const unsigned char aes128_ecb_encrypt_input[][4096] __attribute__((aligned(64))) = { + { 0x95, 0x37, 0xcd, 0x23, 0x9e, 0x35, 0x01, 0x92, 0xed, 0x56, 0xe3, 0x97, 0x64, 0xe5, 0xb1, 0x3a + }, + { 0x51, 0xfa, 0xad, 0x26, 0xdf, 0xb1, 0x60, 0x90, 0x79, 0x45, 0xef, 0x42, 0x89, 0xa5, 0x91, 0x81, + 0x33, 0x16, 0x47, 0xb3, 0xc1, 0xab, 0x9a, 0x5f, 0x82, 0x8c, 0xa7, 0xef, 0x31, 0x97, 0x14, 0x91 + }, + { 0xee, 0x97, 0xfb, 0x63, 0x32, 0x8a, 0xf5, 0xa5, 0x90, 0xfa, 0x59, 0xfe, 0xa5, 0xcf, 0xa7, 0x14, + 0x2e, 0x35, 0x1c, 0xfe, 0xdb, 0xa0, 0x10, 0xd8, 0x49, 0xb3, 0x59, 0xfe, 0x24, 0x40, 0xe7, 0xb6, + 0xe2, 0x6d, 0x43, 0x6a, 0x93, 0x89, 0xfa, 0xb2, 0xc2, 0x01, 0x3d, 0x7e, 0x7a, 0x19, 0x7f, 0xdc, + 0x66, 0xb1, 0x38, 0x6a, 0x71, 0x4b, 0xb8, 0x48, 0xac, 0x9e, 0x51, 0x14, 0x39, 0x59, 0xef, 0x8a + }, + { 0x5d, 0xbe, 0x5b, 0x17, 0x95, 0xfc, 0x10, 0x45, 0xfb, 0xd9, 0x66, 0xc9, 0x58, 0x87, 0x84, 0x38, + 0x8e, 0x75, 0xe7, 0x3d, 0xc5, 0x5b, 0x41, 0x54, 0xc6, 0xae, 0x98, 0xbc, 0x24, 0x71, 0x08, 0x4f, + 0x1f, 0xbd, 0xf0, 0x8e, 0xee, 0x7a, 0xcc, 0x8e, 0x8d, 0xec, 0x6e, 0xcb, 0xa5, 0x5b, 0xf3, 0xe3, + 0x49, 0xaa, 0x04, 0x83, 0x0c, 0x8e, 0x16, 0xde, 0x18, 0xd9, 0x70, 0x70, 0x95, 0x0f, 0x9c, 0xad, + 0x61, 0x65, 0x47, 0x02, 0xce, 0x04, 0xf8, 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0x59, 0x5c, 0xf0, 0xd4, 0x71, 0x54, 0x0d, 0x30, 0x12, 0x87, 0x6f + }, + }; + +const unsigned char aes128_ecb_encrypt_ref_output[][4096] __attribute__((aligned(64))) = { + { 0x24, 0x89, 0xab, 0xe4, 0x77, 0xdc, 0xdd, 0xcf, 0xeb, 0xc3, 0xca, 0xde, 0x5a, 0x52, 0x89, 0xaf + }, + { 0x8e, 0x25, 0x82, 0x01, 0x34, 0x2f, 0x89, 0x93, 0x12, 0x90, 0x47, 0xac, 0xc6, 0xc4, 0x8a, 0x62, + 0x54, 0xd2, 0x2b, 0xb5, 0x47, 0xc0, 0xdd, 0x20, 0x54, 0xe3, 0xd0, 0xbd, 0xf4, 0x81, 0xc4, 0x16 + }, + { 0x2c, 0x79, 0x73, 0x56, 0xbd, 0xa9, 0x2e, 0x0d, 0x33, 0x97, 0x94, 0x1d, 0xbc, 0x55, 0xc9, 0x59, + 0x11, 0x32, 0x0c, 0xc7, 0xbc, 0x82, 0xce, 0xc2, 0xd1, 0x06, 0xc7, 0xd0, 0x93, 0x47, 0x9d, 0x3d, + 0x08, 0x9a, 0xca, 0x5b, 0xd0, 0x8c, 0x95, 0x74, 0xc3, 0x96, 0x78, 0xcc, 0x73, 0x0b, 0x97, 0x3e, + 0x4a, 0xd9, 0x2c, 0x3c, 0x42, 0xf8, 0x66, 0x01, 0x58, 0x56, 0xb5, 0xcb, 0x15, 0xef, 0x05, 0x75 + }, + { 0xee, 0xc9, 0x6b, 0xcd, 0x43, 0xb8, 0xe2, 0x52, 0x47, 0xda, 0xca, 0x7f, 0x29, 0xa0, 0x01, 0xe0, + 0x44, 0x55, 0x22, 0x97, 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0xa2, 0x5a, 0x29, 0x12, 0x1e, 0x5f, 0x96, 0xd1, 0x9f, 0xae, 0xe2, 0x5d, 0xe2, 0x0f, + 0x06, 0xd2, 0xcf, 0x17, 0xaf, 0xbd, 0xec, 0xc8, 0xe0, 0x99, 0x4d, 0x35, 0x30, 0xd9, 0x97, 0x56, + 0x10, 0x4d, 0xd7, 0xc9, 0xe9, 0xca, 0x75, 0x6c, 0xc6, 0x70, 0xcc, 0x23, 0x9b, 0xa3, 0xfe, 0x40, + 0xf5, 0x7c, 0xa6, 0x4d, 0x06, 0x91, 0x7e, 0xd5, 0xc8, 0x79, 0xb9, 0x55, 0x33, 0xa9, 0x63, 0x34 + }, + }; + +unsigned char aes128_ecb_encrypt_output[][4096] __attribute__((aligned(64))) = { + { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + }, + { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + }, + { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 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0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, + 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff + }, + }; + + diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.h b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.h new file mode 100644 index 0000000000..79d8f125dd --- /dev/null +++ b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptodata.h @@ -0,0 +1,5 @@ +extern const unsigned char aes128_ecb_encrypt_key[][16]; +extern const unsigned char aes128_ecb_encrypt_input[][4096]; +extern const unsigned char aes128_ecb_encrypt_ref_output[][4096]; +extern unsigned char aes128_ecb_encrypt_output[][4096]; + diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib.h b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib.h new file mode 100644 index 0000000000..706bb8d62e --- /dev/null +++ b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib.h @@ -0,0 +1,26 @@ +//----------------------------------------------------------------------------- +// The confidential and proprietary information contained in this file may +// only be used by a person authorised under and to the extent permitted +// by a subsisting licensing agreement from ARM Limited. +// +// (C) COPYRIGHT 2012-2013 ARM Limited. +// ALL RIGHTS RESERVED +// +// This entire notice must be reproduced on all copies of this file +// and copies of this file may only be made by a person if such person is +// permitted to do so under the terms of a subsisting license agreement +// from ARM Limited. +// +// SVN Information +// +// Checked In : $Date: 2013-03-19 09:12:51 +0000 (Tue, 19 Mar 2013) $ +// +// Revision : $Revision: 241584 $ +// +// Release Information : +// +//----------------------------------------------------------------------------- + +extern void aes128_key_expand(const unsigned char *key_in, unsigned char *key_out); +extern void aes128_ecb_encrypt(const unsigned char *key, const unsigned char *in_data, unsigned char *out_data, unsigned int size); + diff --git a/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib_asm64.s b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib_asm64.s new file mode 100644 index 0000000000..0cf39040cf --- /dev/null +++ b/Security Algo Accelerator/logical/testbench/execution_tb/tests/crypto64/src/cryptolib_asm64.s @@ -0,0 +1,138 @@ +;#----------------------------------------------------------------------------- +;# The confidential and proprietary information contained in this file may +;# only be used by a person authorised under and to the extent permitted +;# by a subsisting licensing agreement from ARM Limited. +;# +;# (C) COPYRIGHT 2012-2013 ARM Limited. +;# ALL RIGHTS RESERVED +;# +;# This entire notice must be reproduced on all copies of this file +;# and copies of this file may only be made by a person if such person is +;# permitted to do so under the terms of a subsisting license agreement +;# from ARM Limited. +;# +;# SVN Information +;# +;# Checked In : $Date: 2013-03-19 09:12:51 +0000 (Tue, 19 Mar 2013) $ +;# +;# Revision : $Revision: 241584 $ +;# +;# Release Information : +;# +;#----------------------------------------------------------------------------- + + .section aes_code, "ax" + + .global aes128_key_expand + .global aes128_ecb_encrypt + + .align 6 +rcon_array: + .word 0x00000001 + .word 0x00000002 + .word 0x00000004 + .word 0x00000008 + .word 0x00000010 + .word 0x00000020 + .word 0x00000040 + .word 0x00000080 + .word 0x0000001b + .word 0x00000036 + + .align 6 +;# void aes128_key_expand(const unsigned char *key_in, unsigned char *key_out) + .type aes128_key_expand STT_FUNC +aes128_key_expand: + LD1 {v16.16B}, [x0] + MOVZ w2, #0x0e0d + DUP v17.16B, wzr + MOVK w2, #0x0c0f, lsl #16 + DUP v19.4S, w2 + ADR x3, rcon_array + MOV w4, #10 +exp: + TBL v18.16B, {v16.16B}, v19.16B + LD1R {v21.4S}, [x3], #4 + AESE v18.16B, v17.16B + EXT v20.16B, v17.16B, v16.16B, #12 + SHA1SU0 v21.4S, v18.4S, v17.4S + EOR v22.16B, v16.16B, v20.16B + ST1 {v16.16B}, [x1], #16 + SHA1SU0 v21.4S, v22.4S, v22.4S + + TBL v18.16B, {v21.16B}, v19.16B + LD1R {v16.4S}, [x3], #4 + AESE v18.16B, v17.16B + EXT v20.16B, v17.16B, v21.16B, #12 + SHA1SU0 v16.4S, v18.4S, v17.4S + EOR v22.16B, v21.16B, v20.16B + ST1 {v21.16B}, [x1], #16 + SUBS w4, w4, #2 + SHA1SU0 v16.4S, v22.4S, v22.4S + + B.NE exp + ST1 {v16.16B}, [x1] + RET + + .macro aes_enc_round keyreg + AESE v0.16B, \keyreg + AESMC v0.16B, v0.16B + AESE v1.16B, \keyreg + AESMC v1.16B, v1.16B + AESE v2.16B, \keyreg + AESMC v2.16B, v2.16B + .endm + + .macro aes_dec_round keyreg + AESD v0.16B, \keyreg + AESIMC v0.16B, v0.16B + AESD v1.16B, \keyreg + AESIMC v1.16B, v1.16B + AESD v2.16B, \keyreg + AESIMC v2.16B, v2.16B + .endm + +;# void aes128_ecb_encrypt(const unsigned char *key, const unsigned char *in_data, unsigned char *out_data, unsigned int size) + .type aes128_ecb_encrypt STT_FUNC +aes128_ecb_encrypt: + ;# Load the key + LD1 {v16.16B-v19.16B}, [x0], #64 + LD1 {v20.16B-v23.16B}, [x0], #64 + LD1 {v24.16B-v26.16B}, [x0] + +load_ip: + ;# Load data + LD1 {v0.16B-v2.16B}, [x1], #48 + ;# Rounds 1-9 + aes_enc_round v16.16B + aes_enc_round v17.16B + aes_enc_round v18.16B + aes_enc_round v19.16B + aes_enc_round v20.16B + aes_enc_round v21.16B + aes_enc_round v22.16B + aes_enc_round v23.16B + aes_enc_round v24.16B + ;# Round 10 + AESE v0.16B, v25.16B + PRFM PLDL1KEEP, [x1, #64] + EOR v0.16B, v0.16B, v26.16B + SUBS x3, x3, #16 + ST1 {v0.16B}, [x2], #16 + B.EQ end_enc + + AESE v1.16B, v25.16B + EOR v1.16B, v1.16B, v26.16B + SUBS x3, x3, #16 + ST1 {v1.16B}, [x2], #16 + B.EQ end_enc + + AESE v2.16B, v25.16B + EOR v2.16B, v2.16B, v26.16B + SUBS x3, x3, #16 + ST1 {v2.16B}, [x2], #16 + B.GT load_ip +end_enc: + RET + + .end