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update system architecture

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This commit is contained in:
balloonatic 2022-12-14 10:45:59 +05:00
parent 6fa7eac548
commit b59e9362c3
1921 changed files with 56832 additions and 16214 deletions
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32
arch/Kconfig
View File

@ -355,6 +355,12 @@ config HAVE_RSEQ
This symbol should be selected by an architecture if it
supports an implementation of restartable sequences.
config HAVE_RUST
bool
help
This symbol should be selected by an architecture if it
supports Rust.
config HAVE_FUNCTION_ARG_ACCESS_API
bool
help
@ -738,11 +744,13 @@ config ARCH_SUPPORTS_CFI_CLANG
An architecture should select this option if it can support Clang's
Control-Flow Integrity (CFI) checking.
config ARCH_USES_CFI_TRAPS
bool
config CFI_CLANG
bool "Use Clang's Control Flow Integrity (CFI)"
depends on LTO_CLANG && ARCH_SUPPORTS_CFI_CLANG
depends on CLANG_VERSION >= 140000
select KALLSYMS
depends on ARCH_SUPPORTS_CFI_CLANG
depends on $(cc-option,-fsanitize=kcfi)
help
This option enables Clang’s forward-edge Control Flow Integrity
(CFI) checking, where the compiler injects a runtime check to each
@ -754,16 +762,6 @@ config CFI_CLANG
https://clang.llvm.org/docs/ControlFlowIntegrity.html
config CFI_CLANG_SHADOW
bool "Use CFI shadow to speed up cross-module checks"
default y
depends on CFI_CLANG && MODULES
help
If you select this option, the kernel builds a fast look-up table of
CFI check functions in loaded modules to reduce performance overhead.
If unsure, say Y.
config CFI_PERMISSIVE
bool "Use CFI in permissive mode"
depends on CFI_CLANG
@ -1418,6 +1416,14 @@ config DYNAMIC_SIGFRAME
config HAVE_ARCH_NODE_DEV_GROUP
bool
config ARCH_HAS_NONLEAF_PMD_YOUNG
bool
help
Architectures that select this option are capable of setting the
accessed bit in non-leaf PMD entries when using them as part of linear
address translations. Page table walkers that clear the accessed bit
may use this capability to reduce their search space.
source "kernel/gcov/Kconfig"
source "scripts/gcc-plugins/Kconfig"

2
arch/alpha/Makefile
View File

@ -36,8 +36,6 @@ cflags-y += $(cpuflags-y)
# BWX is most important, but we don't really want any emulation ever.
KBUILD_CFLAGS += $(cflags-y) -Wa,-mev6
head-y := arch/alpha/kernel/head.o
libs-y += arch/alpha/lib/
# export what is needed by arch/alpha/boot/Makefile

2
arch/alpha/configs/defconfig
View File

@ -65,7 +65,7 @@ CONFIG_NFSD=m
CONFIG_NLS_CODEPAGE_437=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_KERNEL=y
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_ALPHA_LEGACY_START_ADDRESS=y
CONFIG_MATHEMU=y
CONFIG_CRYPTO_HMAC=y

22
arch/alpha/include/asm/core_apecs.h
View File

@ -384,7 +384,7 @@ struct el_apecs_procdata
} \
} while (0)
__EXTERN_INLINE unsigned int apecs_ioread8(const void __iomem *xaddr)
__EXTERN_INLINE u8 apecs_ioread8(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
unsigned long result, base_and_type;
@ -420,7 +420,7 @@ __EXTERN_INLINE void apecs_iowrite8(u8 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + base_and_type) = w;
}
__EXTERN_INLINE unsigned int apecs_ioread16(const void __iomem *xaddr)
__EXTERN_INLINE u16 apecs_ioread16(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
unsigned long result, base_and_type;
@ -456,7 +456,7 @@ __EXTERN_INLINE void apecs_iowrite16(u16 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + base_and_type) = w;
}
__EXTERN_INLINE unsigned int apecs_ioread32(const void __iomem *xaddr)
__EXTERN_INLINE u32 apecs_ioread32(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
if (addr < APECS_DENSE_MEM)
@ -472,6 +472,22 @@ __EXTERN_INLINE void apecs_iowrite32(u32 b, void __iomem *xaddr)
*(vuip)addr = b;
}
__EXTERN_INLINE u64 apecs_ioread64(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
if (addr < APECS_DENSE_MEM)
addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
return *(vulp)addr;
}
__EXTERN_INLINE void apecs_iowrite64(u64 b, void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
if (addr < APECS_DENSE_MEM)
addr = ((addr - APECS_IO) << 5) + APECS_IO + 0x18;
*(vulp)addr = b;
}
__EXTERN_INLINE void __iomem *apecs_ioportmap(unsigned long addr)
{
return (void __iomem *)(addr + APECS_IO);

22
arch/alpha/include/asm/core_cia.h
View File

@ -342,7 +342,7 @@ struct el_CIA_sysdata_mcheck {
#define vuip volatile unsigned int __force *
#define vulp volatile unsigned long __force *
__EXTERN_INLINE unsigned int cia_ioread8(const void __iomem *xaddr)
__EXTERN_INLINE u8 cia_ioread8(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
unsigned long result, base_and_type;
@ -374,7 +374,7 @@ __EXTERN_INLINE void cia_iowrite8(u8 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + base_and_type) = w;
}
__EXTERN_INLINE unsigned int cia_ioread16(const void __iomem *xaddr)
__EXTERN_INLINE u16 cia_ioread16(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
unsigned long result, base_and_type;
@ -404,7 +404,7 @@ __EXTERN_INLINE void cia_iowrite16(u16 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + base_and_type) = w;
}
__EXTERN_INLINE unsigned int cia_ioread32(const void __iomem *xaddr)
__EXTERN_INLINE u32 cia_ioread32(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
if (addr < CIA_DENSE_MEM)
@ -420,6 +420,22 @@ __EXTERN_INLINE void cia_iowrite32(u32 b, void __iomem *xaddr)
*(vuip)addr = b;
}
__EXTERN_INLINE u64 cia_ioread64(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
if (addr < CIA_DENSE_MEM)
addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
return *(vulp)addr;
}
__EXTERN_INLINE void cia_iowrite64(u64 b, void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
if (addr < CIA_DENSE_MEM)
addr = ((addr - CIA_IO) << 5) + CIA_IO + 0x18;
*(vulp)addr = b;
}
__EXTERN_INLINE void __iomem *cia_ioportmap(unsigned long addr)
{
return (void __iomem *)(addr + CIA_IO);

22
arch/alpha/include/asm/core_lca.h
View File

@ -230,7 +230,7 @@ union el_lca {
} while (0)
__EXTERN_INLINE unsigned int lca_ioread8(const void __iomem *xaddr)
__EXTERN_INLINE u8 lca_ioread8(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
unsigned long result, base_and_type;
@ -266,7 +266,7 @@ __EXTERN_INLINE void lca_iowrite8(u8 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + base_and_type) = w;
}
__EXTERN_INLINE unsigned int lca_ioread16(const void __iomem *xaddr)
__EXTERN_INLINE u16 lca_ioread16(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
unsigned long result, base_and_type;
@ -302,7 +302,7 @@ __EXTERN_INLINE void lca_iowrite16(u16 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + base_and_type) = w;
}
__EXTERN_INLINE unsigned int lca_ioread32(const void __iomem *xaddr)
__EXTERN_INLINE u32 lca_ioread32(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
if (addr < LCA_DENSE_MEM)
@ -318,6 +318,22 @@ __EXTERN_INLINE void lca_iowrite32(u32 b, void __iomem *xaddr)
*(vuip)addr = b;
}
__EXTERN_INLINE u64 lca_ioread64(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
if (addr < LCA_DENSE_MEM)
addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18;
return *(vulp)addr;
}
__EXTERN_INLINE void lca_iowrite64(u64 b, void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;
if (addr < LCA_DENSE_MEM)
addr = ((addr - LCA_IO) << 5) + LCA_IO + 0x18;
*(vulp)addr = b;
}
__EXTERN_INLINE void __iomem *lca_ioportmap(unsigned long addr)
{
return (void __iomem *)(addr + LCA_IO);

4
arch/alpha/include/asm/core_marvel.h
View File

@ -332,10 +332,10 @@ struct io7 {
#define vucp volatile unsigned char __force *
#define vusp volatile unsigned short __force *
extern unsigned int marvel_ioread8(const void __iomem *);
extern u8 marvel_ioread8(const void __iomem *);
extern void marvel_iowrite8(u8 b, void __iomem *);
__EXTERN_INLINE unsigned int marvel_ioread16(const void __iomem *addr)
__EXTERN_INLINE u16 marvel_ioread16(const void __iomem *addr)
{
return __kernel_ldwu(*(vusp)addr);
}

28
arch/alpha/include/asm/core_mcpcia.h
View File

@ -248,6 +248,7 @@ struct el_MCPCIA_uncorrected_frame_mcheck {
#define vip volatile int __force *
#define vuip volatile unsigned int __force *
#define vulp volatile unsigned long __force *
#ifndef MCPCIA_ONE_HAE_WINDOW
#define MCPCIA_FROB_MMIO \
@ -267,7 +268,7 @@ extern inline int __mcpcia_is_mmio(unsigned long addr)
return (addr & 0x80000000UL) == 0;
}
__EXTERN_INLINE unsigned int mcpcia_ioread8(const void __iomem *xaddr)
__EXTERN_INLINE u8 mcpcia_ioread8(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
@ -291,7 +292,7 @@ __EXTERN_INLINE void mcpcia_iowrite8(u8 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + hose + 0x00) = w;
}
__EXTERN_INLINE unsigned int mcpcia_ioread16(const void __iomem *xaddr)
__EXTERN_INLINE u16 mcpcia_ioread16(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long)xaddr & MCPCIA_MEM_MASK;
unsigned long hose = (unsigned long)xaddr & ~MCPCIA_MEM_MASK;
@ -315,7 +316,7 @@ __EXTERN_INLINE void mcpcia_iowrite16(u16 b, void __iomem *xaddr)
*(vuip) ((addr << 5) + hose + 0x08) = w;
}
__EXTERN_INLINE unsigned int mcpcia_ioread32(const void __iomem *xaddr)
__EXTERN_INLINE u32 mcpcia_ioread32(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long)xaddr;
@ -335,6 +336,26 @@ __EXTERN_INLINE void mcpcia_iowrite32(u32 b, void __iomem *xaddr)
*(vuip)addr = b;
}
__EXTERN_INLINE u64 mcpcia_ioread64(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long)xaddr;
if (!__mcpcia_is_mmio(addr))
addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
return *(vulp)addr;
}
__EXTERN_INLINE void mcpcia_iowrite64(u64 b, void __iomem *xaddr)
{
unsigned long addr = (unsigned long)xaddr;
if (!__mcpcia_is_mmio(addr))
addr = ((addr & 0xffff) << 5) + (addr & ~0xfffful) + 0x18;
*(vulp)addr = b;
}
__EXTERN_INLINE void __iomem *mcpcia_ioportmap(unsigned long addr)
{
@ -362,6 +383,7 @@ __EXTERN_INLINE int mcpcia_is_mmio(const volatile void __iomem *xaddr)
#undef vip
#undef vuip
#undef vulp
#undef __IO_PREFIX
#define __IO_PREFIX mcpcia

16
arch/alpha/include/asm/core_t2.h
View File

@ -360,6 +360,7 @@ struct el_t2_frame_corrected {
#define vip volatile int *
#define vuip volatile unsigned int *
#define vulp volatile unsigned long *
extern inline u8 t2_inb(unsigned long addr)
{
@ -402,6 +403,17 @@ extern inline void t2_outl(u32 b, unsigned long addr)
mb();
}
extern inline u64 t2_inq(unsigned long addr)
{
return *(vulp) ((addr << 5) + T2_IO + 0x18);
}
extern inline void t2_outq(u64 b, unsigned long addr)
{
*(vulp) ((addr << 5) + T2_IO + 0x18) = b;
mb();
}
/*
* Memory functions.
@ -572,7 +584,7 @@ __EXTERN_INLINE int t2_is_mmio(const volatile void __iomem *addr)
it doesn't make sense to merge the pio and mmio routines. */
#define IOPORT(OS, NS) \
__EXTERN_INLINE unsigned int t2_ioread##NS(const void __iomem *xaddr) \
__EXTERN_INLINE u##NS t2_ioread##NS(const void __iomem *xaddr) \
{ \
if (t2_is_mmio(xaddr)) \
return t2_read##OS(xaddr); \
@ -590,11 +602,13 @@ __EXTERN_INLINE void t2_iowrite##NS(u##NS b, void __iomem *xaddr) \
IOPORT(b, 8)
IOPORT(w, 16)
IOPORT(l, 32)
IOPORT(q, 64)
#undef IOPORT
#undef vip
#undef vuip
#undef vulp
#undef __IO_PREFIX
#define __IO_PREFIX t2

97
arch/alpha/include/asm/io.h
View File

@ -90,6 +90,8 @@ static inline void * phys_to_virt(unsigned long address)
}
#endif
#define virt_to_phys virt_to_phys
#define phys_to_virt phys_to_virt
#define page_to_phys(page) page_to_pa(page)
/* Maximum PIO space address supported? */
@ -153,6 +155,7 @@ static inline void generic_##NAME(TYPE b, QUAL void __iomem *addr) \
REMAP1(unsigned int, ioread8, const)
REMAP1(unsigned int, ioread16, const)
REMAP1(unsigned int, ioread32, const)
REMAP1(u64, ioread64, const)
REMAP1(u8, readb, const volatile)
REMAP1(u16, readw, const volatile)
REMAP1(u32, readl, const volatile)
@ -161,6 +164,7 @@ REMAP1(u64, readq, const volatile)
REMAP2(u8, iowrite8, /**/)
REMAP2(u16, iowrite16, /**/)
REMAP2(u32, iowrite32, /**/)
REMAP2(u64, iowrite64, /**/)
REMAP2(u8, writeb, volatile)
REMAP2(u16, writew, volatile)
REMAP2(u32, writel, volatile)
@ -242,6 +246,12 @@ extern u32 inl(unsigned long port);
extern void outb(u8 b, unsigned long port);
extern void outw(u16 b, unsigned long port);
extern void outl(u32 b, unsigned long port);
#define inb inb
#define inw inw
#define inl inl
#define outb outb
#define outw outw
#define outl outl
extern u8 readb(const volatile void __iomem *addr);
extern u16 readw(const volatile void __iomem *addr);
@ -251,6 +261,14 @@ extern void writeb(u8 b, volatile void __iomem *addr);
extern void writew(u16 b, volatile void __iomem *addr);
extern void writel(u32 b, volatile void __iomem *addr);
extern void writeq(u64 b, volatile void __iomem *addr);
#define readb readb
#define readw readw
#define readl readl
#define readq readq
#define writeb writeb
#define writew writew
#define writel writel
#define writeq writeq
extern u8 __raw_readb(const volatile void __iomem *addr);
extern u16 __raw_readw(const volatile void __iomem *addr);
@ -260,6 +278,14 @@ extern void __raw_writeb(u8 b, volatile void __iomem *addr);
extern void __raw_writew(u16 b, volatile void __iomem *addr);
extern void __raw_writel(u32 b, volatile void __iomem *addr);
extern void __raw_writeq(u64 b, volatile void __iomem *addr);
#define __raw_readb __raw_readb
#define __raw_readw __raw_readw
#define __raw_readl __raw_readl
#define __raw_readq __raw_readq
#define __raw_writeb __raw_writeb
#define __raw_writew __raw_writew
#define __raw_writel __raw_writel
#define __raw_writeq __raw_writeq
/*
* Mapping from port numbers to __iomem space is pretty easy.
@ -277,6 +303,9 @@ extern inline void ioport_unmap(void __iomem *addr)
{
}
#define ioport_map ioport_map
#define ioport_unmap ioport_unmap
static inline void __iomem *ioremap(unsigned long port, unsigned long size)
{
return IO_CONCAT(__IO_PREFIX,ioremap) (port, size);
@ -358,6 +387,11 @@ extern inline void outw(u16 b, unsigned long port)
}
#endif
#define ioread8 ioread8
#define ioread16 ioread16
#define iowrite8 iowrite8
#define iowrite16 iowrite16
#if IO_CONCAT(__IO_PREFIX,trivial_io_lq)
extern inline unsigned int ioread32(const void __iomem *addr)
{
@ -368,12 +402,27 @@ extern inline unsigned int ioread32(const void __iomem *addr)
return ret;
}
extern inline u64 ioread64(const void __iomem *addr)
{
unsigned int ret;
mb();
ret = IO_CONCAT(__IO_PREFIX,ioread64)(addr);
mb();
return ret;
}
extern inline void iowrite32(u32 b, void __iomem *addr)
{
mb();
IO_CONCAT(__IO_PREFIX, iowrite32)(b, addr);
}
extern inline void iowrite64(u64 b, void __iomem *addr)
{
mb();
IO_CONCAT(__IO_PREFIX, iowrite64)(b, addr);
}
extern inline u32 inl(unsigned long port)
{
return ioread32(ioport_map(port, 4));
@ -385,6 +434,11 @@ extern inline void outl(u32 b, unsigned long port)
}
#endif
#define ioread32 ioread32
#define ioread64 ioread64
#define iowrite32 iowrite32
#define iowrite64 iowrite64
#if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1
extern inline u8 __raw_readb(const volatile void __iomem *addr)
{
@ -505,6 +559,10 @@ extern u8 readb_relaxed(const volatile void __iomem *addr);
extern u16 readw_relaxed(const volatile void __iomem *addr);
extern u32 readl_relaxed(const volatile void __iomem *addr);
extern u64 readq_relaxed(const volatile void __iomem *addr);
#define readb_relaxed readb_relaxed
#define readw_relaxed readw_relaxed
#define readl_relaxed readl_relaxed
#define readq_relaxed readq_relaxed
#if IO_CONCAT(__IO_PREFIX,trivial_io_bw)
extern inline u8 readb_relaxed(const volatile void __iomem *addr)
@ -557,6 +615,10 @@ static inline void memsetw_io(volatile void __iomem *addr, u16 c, long len)
_memset_c_io(addr, 0x0001000100010001UL * c, len);
}
#define memset_io memset_io
#define memcpy_fromio memcpy_fromio
#define memcpy_toio memcpy_toio
/*
* String versions of in/out ops:
*/
@ -567,6 +629,13 @@ extern void outsb (unsigned long port, const void *src, unsigned long count);
extern void outsw (unsigned long port, const void *src, unsigned long count);
extern void outsl (unsigned long port, const void *src, unsigned long count);
#define insb insb
#define insw insw
#define insl insl
#define outsb outsb
#define outsw outsw
#define outsl outsl
/*
* The Alpha Jensen hardware for some rather strange reason puts
* the RTC clock at 0x170 instead of 0x70. Probably due to some
@ -586,22 +655,30 @@ extern void outsl (unsigned long port, const void *src, unsigned long count);
#endif
#define RTC_ALWAYS_BCD 0
/*
* Some mucking forons use if[n]def writeq to check if platform has it.
* It's a bloody bad idea and we probably want ARCH_HAS_WRITEQ for them
* to play with; for now just use cpp anti-recursion logics and make sure
* that damn thing is defined and expands to itself.
*/
#define writeq writeq
#define readq readq
/*
* Convert a physical pointer to a virtual kernel pointer for /dev/mem
* access
*/
#define xlate_dev_mem_ptr(p) __va(p)
/*
* These get provided from <asm-generic/iomap.h> since alpha does not
* select GENERIC_IOMAP.
*/
#define ioread64 ioread64
#define iowrite64 iowrite64
#define ioread64be ioread64be
#define iowrite64be iowrite64be
#define ioread8_rep ioread8_rep
#define ioread16_rep ioread16_rep
#define ioread32_rep ioread32_rep
#define iowrite8_rep iowrite8_rep
#define iowrite16_rep iowrite16_rep
#define iowrite32_rep iowrite32_rep
#define pci_iounmap pci_iounmap
#include <asm-generic/io.h>
#endif /* __KERNEL__ */
#endif /* __ALPHA_IO_H */

18
arch/alpha/include/asm/io_trivial.h
View File

@ -6,13 +6,13 @@
/* This file may be included multiple times. */
#if IO_CONCAT(__IO_PREFIX,trivial_io_bw)
__EXTERN_INLINE unsigned int
__EXTERN_INLINE u8
IO_CONCAT(__IO_PREFIX,ioread8)(const void __iomem *a)
{
return __kernel_ldbu(*(const volatile u8 __force *)a);
}
__EXTERN_INLINE unsigned int
__EXTERN_INLINE u16
IO_CONCAT(__IO_PREFIX,ioread16)(const void __iomem *a)
{
return __kernel_ldwu(*(const volatile u16 __force *)a);
@ -32,7 +32,7 @@ IO_CONCAT(__IO_PREFIX,iowrite16)(u16 b, void __iomem *a)
#endif
#if IO_CONCAT(__IO_PREFIX,trivial_io_lq)
__EXTERN_INLINE unsigned int
__EXTERN_INLINE u32
IO_CONCAT(__IO_PREFIX,ioread32)(const void __iomem *a)
{
return *(const volatile u32 __force *)a;
@ -43,6 +43,18 @@ IO_CONCAT(__IO_PREFIX,iowrite32)(u32 b, void __iomem *a)
{
*(volatile u32 __force *)a = b;
}
__EXTERN_INLINE u64
IO_CONCAT(__IO_PREFIX,ioread64)(const void __iomem *a)
{
return *(const volatile u64 __force *)a;
}
__EXTERN_INLINE void
IO_CONCAT(__IO_PREFIX,iowrite64)(u64 b, void __iomem *a)
{
*(volatile u64 __force *)a = b;
}
#endif
#if IO_CONCAT(__IO_PREFIX,trivial_rw_bw) == 1

18
arch/alpha/include/asm/jensen.h
View File

@ -98,6 +98,7 @@ __EXTERN_INLINE void jensen_set_hae(unsigned long addr)
}
#define vuip volatile unsigned int *
#define vulp volatile unsigned long *
/*
* IO functions
@ -183,6 +184,12 @@ __EXTERN_INLINE u32 jensen_inl(unsigned long addr)
return *(vuip) ((addr << 7) + EISA_IO + 0x60);
}
__EXTERN_INLINE u64 jensen_inq(unsigned long addr)
{
jensen_set_hae(0);
return *(vulp) ((addr << 7) + EISA_IO + 0x60);
}
__EXTERN_INLINE void jensen_outw(u16 b, unsigned long addr)
{
jensen_set_hae(0);
@ -197,6 +204,13 @@ __EXTERN_INLINE void jensen_outl(u32 b, unsigned long addr)
mb();
}
__EXTERN_INLINE void jensen_outq(u64 b, unsigned long addr)
{
jensen_set_hae(0);
*(vulp) ((addr << 7) + EISA_IO + 0x60) = b;
mb();
}
/*
* Memory functions.
*/
@ -305,7 +319,7 @@ __EXTERN_INLINE int jensen_is_mmio(const volatile void __iomem *addr)
that it doesn't make sense to merge them. */
#define IOPORT(OS, NS) \
__EXTERN_INLINE unsigned int jensen_ioread##NS(const void __iomem *xaddr) \
__EXTERN_INLINE u##NS jensen_ioread##NS(const void __iomem *xaddr) \
{ \
if (jensen_is_mmio(xaddr)) \
return jensen_read##OS(xaddr - 0x100000000ul); \
@ -323,10 +337,12 @@ __EXTERN_INLINE void jensen_iowrite##NS(u##NS b, void __iomem *xaddr) \
IOPORT(b, 8)
IOPORT(w, 16)
IOPORT(l, 32)
IOPORT(q, 64)
#undef IOPORT
#undef vuip
#undef vulp
#undef __IO_PREFIX
#define __IO_PREFIX jensen

8
arch/alpha/include/asm/machvec.h
View File

@ -46,13 +46,15 @@ struct alpha_machine_vector
void (*mv_pci_tbi)(struct pci_controller *hose,
dma_addr_t start, dma_addr_t end);
unsigned int (*mv_ioread8)(const void __iomem *);
unsigned int (*mv_ioread16)(const void __iomem *);
unsigned int (*mv_ioread32)(const void __iomem *);
u8 (*mv_ioread8)(const void __iomem *);
u16 (*mv_ioread16)(const void __iomem *);
u32 (*mv_ioread32)(const void __iomem *);
u64 (*mv_ioread64)(const void __iomem *);
void (*mv_iowrite8)(u8, void __iomem *);
void (*mv_iowrite16)(u16, void __iomem *);
void (*mv_iowrite32)(u32, void __iomem *);
void (*mv_iowrite64)(u64, void __iomem *);
u8 (*mv_readb)(const volatile void __iomem *);
u16 (*mv_readw)(const volatile void __iomem *);

2
arch/alpha/include/asm/processor.h
View File

@ -36,8 +36,6 @@ extern void start_thread(struct pt_regs *, unsigned long, unsigned long);
/* Free all resources held by a thread. */
struct task_struct;
extern void release_thread(struct task_struct *);
unsigned long __get_wchan(struct task_struct *p);
#define KSTK_EIP(tsk) (task_pt_regs(tsk)->pc)

2
arch/alpha/include/uapi/asm/mman.h
View File

@ -76,6 +76,8 @@
#define MADV_DONTNEED_LOCKED 24 /* like DONTNEED, but drop locked pages too */
#define MADV_COLLAPSE 25 /* Synchronous hugepage collapse */
/* compatibility flags */
#define MAP_FILE 0

10
arch/alpha/kernel/Makefile
View File

@ -3,13 +3,13 @@
# Makefile for the linux kernel.
#
extra-y := head.o vmlinux.lds
extra-y := vmlinux.lds
asflags-y := $(KBUILD_CFLAGS)
ccflags-y := -Wno-sign-compare
obj-y := entry.o traps.o process.o osf_sys.o irq.o \
obj-y := head.o entry.o traps.o process.o osf_sys.o irq.o \
irq_alpha.o signal.o setup.o ptrace.o time.o \
systbls.o err_common.o io.o bugs.o
systbls.o err_common.o io.o bugs.o termios.o
obj-$(CONFIG_VGA_HOSE) += console.o
obj-$(CONFIG_SMP) += smp.o
@ -47,10 +47,6 @@ else
# Misc support
obj-$(CONFIG_ALPHA_SRM) += srmcons.o
ifdef CONFIG_BINFMT_AOUT
obj-y += binfmt_loader.o
endif
# Core logic support
obj-$(CONFIG_ALPHA_APECS) += core_apecs.o
obj-$(CONFIG_ALPHA_CIA) += core_cia.o

2
arch/alpha/kernel/core_marvel.c
View File

@ -803,7 +803,7 @@ void __iomem *marvel_ioportmap (unsigned long addr)
return (void __iomem *)addr;
}
unsigned int
u8
marvel_ioread8(const void __iomem *xaddr)
{
unsigned long addr = (unsigned long) xaddr;

17
arch/alpha/kernel/io.c
View File

@ -41,6 +41,15 @@ unsigned int ioread32(const void __iomem *addr)
return ret;
}
u64 ioread64(const void __iomem *addr)
{
unsigned int ret;
mb();
ret = IO_CONCAT(__IO_PREFIX,ioread64)(addr);
mb();
return ret;
}
void iowrite8(u8 b, void __iomem *addr)
{
mb();
@ -59,12 +68,20 @@ void iowrite32(u32 b, void __iomem *addr)
IO_CONCAT(__IO_PREFIX,iowrite32)(b, addr);
}
void iowrite64(u64 b, void __iomem *addr)
{
mb();
IO_CONCAT(__IO_PREFIX,iowrite64)(b, addr);
}
EXPORT_SYMBOL(ioread8);
EXPORT_SYMBOL(ioread16);
EXPORT_SYMBOL(ioread32);
EXPORT_SYMBOL(ioread64);
EXPORT_SYMBOL(iowrite8);
EXPORT_SYMBOL(iowrite16);
EXPORT_SYMBOL(iowrite32);
EXPORT_SYMBOL(iowrite64);
u8 inb(unsigned long port)
{

2
arch/alpha/kernel/machvec_impl.h
View File

@ -78,9 +78,11 @@
.mv_ioread8 = CAT(low,_ioread8), \
.mv_ioread16 = CAT(low,_ioread16), \
.mv_ioread32 = CAT(low,_ioread32), \
.mv_ioread64 = CAT(low,_ioread64), \
.mv_iowrite8 = CAT(low,_iowrite8), \
.mv_iowrite16 = CAT(low,_iowrite16), \
.mv_iowrite32 = CAT(low,_iowrite32), \
.mv_iowrite64 = CAT(low,_iowrite64), \
.mv_readb = CAT(low,_readb), \
.mv_readw = CAT(low,_readw), \
.mv_readl = CAT(low,_readl), \

52
arch/alpha/kernel/osf_sys.c
View File

@ -108,7 +108,7 @@ struct osf_dirent_callback {
int error;
};
static int
static bool
osf_filldir(struct dir_context *ctx, const char *name, int namlen,
loff_t offset, u64 ino, unsigned int d_type)
{
@ -120,11 +120,11 @@ osf_filldir(struct dir_context *ctx, const char *name, int namlen,
buf->error = -EINVAL; /* only used if we fail */
if (reclen > buf->count)
return -EINVAL;
return false;
d_ino = ino;
if (sizeof(d_ino) < sizeof(ino) && d_ino != ino) {
buf->error = -EOVERFLOW;
return -EOVERFLOW;
return false;
}
if (buf->basep) {
if (put_user(offset, buf->basep))
@ -141,10 +141,10 @@ osf_filldir(struct dir_context *ctx, const char *name, int namlen,
dirent = (void __user *)dirent + reclen;
buf->dirent = dirent;
buf->count -= reclen;
return 0;
return true;
Efault:
buf->error = -EFAULT;
return -EFAULT;
return false;
}
SYSCALL_DEFINE4(osf_getdirentries, unsigned int, fd,
@ -1278,48 +1278,6 @@ arch_get_unmapped_area(struct file *filp, unsigned long addr,
return addr;
}
#ifdef CONFIG_OSF4_COMPAT
/* Clear top 32 bits of iov_len in the user's buffer for
compatibility with old versions of OSF/1 where iov_len
was defined as int. */
static int
osf_fix_iov_len(const struct iovec __user *iov, unsigned long count)
{
unsigned long i;
for (i = 0 ; i < count ; i++) {
int __user *iov_len_high = (int __user *)&iov[i].iov_len + 1;
if (put_user(0, iov_len_high))
return -EFAULT;
}
return 0;
}
#endif
SYSCALL_DEFINE3(osf_readv, unsigned long, fd,
const struct iovec __user *, vector, unsigned long, count)
{
#ifdef CONFIG_OSF4_COMPAT
if (unlikely(personality(current->personality) == PER_OSF4))
if (osf_fix_iov_len(vector, count))
return -EFAULT;
#endif
return sys_readv(fd, vector, count);
}
SYSCALL_DEFINE3(osf_writev, unsigned long, fd,
const struct iovec __user *, vector, unsigned long, count)
{
#ifdef CONFIG_OSF4_COMPAT
if (unlikely(personality(current->personality) == PER_OSF4))
if (osf_fix_iov_len(vector, count))
return -EFAULT;
#endif
return sys_writev(fd, vector, count);
}
SYSCALL_DEFINE2(osf_getpriority, int, which, int, who)
{
int prio = sys_getpriority(which, who);

5
arch/alpha/kernel/process.c
View File

@ -225,11 +225,6 @@ flush_thread(void)
current_thread_info()->pcb.unique = 0;
}
void
release_thread(struct task_struct *dead_task)
{
}
/*
* Copy architecture-specific thread state
*/

4
arch/alpha/kernel/setup.c
View File

@ -491,9 +491,9 @@ setup_arch(char **cmdline_p)
boot flags depending on the boot mode, we need some shorthand.
This should do for installation. */
if (strcmp(COMMAND_LINE, "INSTALL") == 0) {
strlcpy(command_line, "root=/dev/fd0 load_ramdisk=1", sizeof command_line);
strscpy(command_line, "root=/dev/fd0 load_ramdisk=1", sizeof(command_line));
} else {
strlcpy(command_line, COMMAND_LINE, sizeof command_line);
strscpy(command_line, COMMAND_LINE, sizeof(command_line));
}
strcpy(boot_command_line, command_line);
*cmdline_p = command_line;

4
arch/alpha/kernel/syscalls/syscall.tbl
View File

@ -125,8 +125,8 @@
116 common osf_gettimeofday sys_osf_gettimeofday
117 common osf_getrusage sys_osf_getrusage
118 common getsockopt sys_getsockopt
120 common readv sys_osf_readv
121 common writev sys_osf_writev
120 common readv sys_readv
121 common writev sys_writev
122 common osf_settimeofday sys_osf_settimeofday
123 common fchown sys_fchown
124 common fchmod sys_fchmod

56
arch/alpha/kernel/termios.c Normal file
View File

@ -0,0 +1,56 @@
// SPDX-License-Identifier: GPL-2.0
#include <linux/termios_internal.h>
int user_termio_to_kernel_termios(struct ktermios *termios,
struct termio __user *termio)
{
struct termio v;
bool canon;
if (copy_from_user(&v, termio, sizeof(struct termio)))
return -EFAULT;
termios->c_iflag = (0xffff0000 & termios->c_iflag) | v.c_iflag;
termios->c_oflag = (0xffff0000 & termios->c_oflag) | v.c_oflag;
termios->c_cflag = (0xffff0000 & termios->c_cflag) | v.c_cflag;
termios->c_lflag = (0xffff0000 & termios->c_lflag) | v.c_lflag;
termios->c_line = (0xffff0000 & termios->c_lflag) | v.c_line;
canon = v.c_lflag & ICANON;
termios->c_cc[VINTR] = v.c_cc[_VINTR];
termios->c_cc[VQUIT] = v.c_cc[_VQUIT];
termios->c_cc[VERASE] = v.c_cc[_VERASE];
termios->c_cc[VKILL] = v.c_cc[_VKILL];
termios->c_cc[VEOL2] = v.c_cc[_VEOL2];
termios->c_cc[VSWTC] = v.c_cc[_VSWTC];
termios->c_cc[canon ? VEOF : VMIN] = v.c_cc[_VEOF];
termios->c_cc[canon ? VEOL : VTIME] = v.c_cc[_VEOL];
return 0;
}
int kernel_termios_to_user_termio(struct termio __user *termio,
struct ktermios *termios)
{
struct termio v;
bool canon;
memset(&v, 0, sizeof(struct termio));
v.c_iflag = termios->c_iflag;
v.c_oflag = termios->c_oflag;
v.c_cflag = termios->c_cflag;
v.c_lflag = termios->c_lflag;
v.c_line = termios->c_line;
canon = v.c_lflag & ICANON;
v.c_cc[_VINTR] = termios->c_cc[VINTR];
v.c_cc[_VQUIT] = termios->c_cc[VQUIT];
v.c_cc[_VERASE] = termios->c_cc[VERASE];
v.c_cc[_VKILL] = termios->c_cc[VKILL];
v.c_cc[_VEOF] = termios->c_cc[canon ? VEOF : VMIN];
v.c_cc[_VEOL] = termios->c_cc[canon ? VEOL : VTIME];
v.c_cc[_VEOL2] = termios->c_cc[VEOL2];
v.c_cc[_VSWTC] = termios->c_cc[VSWTC];
return copy_to_user(termio, &v, sizeof(struct termio));
}

2
arch/arc/Kconfig
View File

@ -554,7 +554,7 @@ config ARC_BUILTIN_DTB_NAME
endmenu # "ARC Architecture Configuration"
config FORCE_MAX_ZONEORDER
config ARCH_FORCE_MAX_ORDER
int "Maximum zone order"
default "12" if ARC_HUGEPAGE_16M
default "11"

2
arch/arc/Makefile
View File

@ -82,8 +82,6 @@ KBUILD_CFLAGS += $(cflags-y)
KBUILD_AFLAGS += $(KBUILD_CFLAGS)
KBUILD_LDFLAGS += $(ldflags-y)
head-y := arch/arc/kernel/head.o
# w/o this dtb won't embed into kernel binary
core-y += arch/arc/boot/dts/

4
arch/arc/boot/dts/axc003.dtsi
View File

@ -103,11 +103,11 @@ ethernet@18000 {
dma-coherent;
};
ehci@40000 {
usb@40000 {
dma-coherent;
};
ohci@60000 {
usb@60000 {
dma-coherent;
};

4
arch/arc/boot/dts/axc003_idu.dtsi
View File

@ -110,11 +110,11 @@ ethernet@18000 {
dma-coherent;
};
ehci@40000 {
usb@40000 {
dma-coherent;
};
ohci@60000 {
usb@60000 {
dma-coherent;
};

4
arch/arc/boot/dts/axs10x_mb.dtsi
View File

@ -87,13 +87,13 @@ gmac: ethernet@18000 {
mac-address = [00 00 00 00 00 00]; /* Filled in by U-Boot */
};
ehci@40000 {
usb@40000 {
compatible = "generic-ehci";
reg = < 0x40000 0x100 >;
interrupts = < 8 >;
};
ohci@60000 {
usb@60000 {
compatible = "generic-ohci";
reg = < 0x60000 0x100 >;
interrupts = < 8 >;

4
arch/arc/boot/dts/hsdk.dts
View File

@ -234,7 +234,7 @@ phy0: ethernet-phy@0 { /* Micrel KSZ9031 */
};
};
ohci@60000 {
usb@60000 {
compatible = "snps,hsdk-v1.0-ohci", "generic-ohci";
reg = <0x60000 0x100>;
interrupts = <15>;
@ -242,7 +242,7 @@ ohci@60000 {
dma-coherent;
};
ehci@40000 {
usb@40000 {
compatible = "snps,hsdk-v1.0-ehci", "generic-ehci";
reg = <0x40000 0x100>;
interrupts = <15>;

2
arch/arc/boot/dts/vdk_axs10x_mb.dtsi
View File

@ -46,7 +46,7 @@ ethernet@18000 {
clock-names = "stmmaceth";
};
ehci@40000 {
usb@40000 {
compatible = "generic-ehci";
reg = < 0x40000 0x100 >;
interrupts = < 8 >;

4
arch/arc/configs/axs101_defconfig
View File

@ -35,9 +35,6 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
@ -99,7 +96,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10

4
arch/arc/configs/axs103_defconfig
View File

@ -34,9 +34,6 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
@ -97,7 +94,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10

4
arch/arc/configs/axs103_smp_defconfig
View File

@ -35,9 +35,6 @@ CONFIG_IP_PNP=y
CONFIG_IP_PNP_DHCP=y
CONFIG_IP_PNP_BOOTP=y
CONFIG_IP_PNP_RARP=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
CONFIG_DEVTMPFS=y
# CONFIG_STANDALONE is not set
@ -100,7 +97,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10

1
arch/arc/configs/haps_hs_defconfig
View File

@ -59,6 +59,5 @@ CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_DEBUG_MEMORY_INIT=y
# CONFIG_DEBUG_PREEMPT is not set

1
arch/arc/configs/haps_hs_smp_defconfig
View File

@ -59,6 +59,5 @@ CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_SOFTLOCKUP_DETECTOR=y
# CONFIG_DEBUG_PREEMPT is not set

1
arch/arc/configs/hsdk_defconfig
View File

@ -85,7 +85,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_SOFTLOCKUP_DETECTOR=y
CONFIG_DEFAULT_HUNG_TASK_TIMEOUT=10

1
arch/arc/configs/nsim_700_defconfig
View File

@ -56,5 +56,4 @@ CONFIG_EXT2_FS_XATTR=y
CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
# CONFIG_ENABLE_MUST_CHECK is not set
# CONFIG_DEBUG_PREEMPT is not set

1
arch/arc/configs/nsimosci_defconfig
View File

@ -65,4 +65,3 @@ CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
# CONFIG_ENABLE_MUST_CHECK is not set

1
arch/arc/configs/nsimosci_hs_defconfig
View File

@ -63,4 +63,3 @@ CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
# CONFIG_ENABLE_MUST_CHECK is not set

6
arch/arc/configs/nsimosci_hs_smp_defconfig
View File

@ -26,9 +26,6 @@ CONFIG_UNIX=y
CONFIG_UNIX_DIAG=y
CONFIG_NET_KEY=y
CONFIG_INET=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
@ -37,7 +34,6 @@ CONFIG_DEVTMPFS=y
# CONFIG_BLK_DEV is not set
CONFIG_NETDEVICES=y
# CONFIG_NET_VENDOR_ARC is not set
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
CONFIG_EZCHIP_NPS_MANAGEMENT_ENET=y
# CONFIG_NET_VENDOR_INTEL is not set
@ -74,5 +70,5 @@ CONFIG_TMPFS=y
# CONFIG_MISC_FILESYSTEMS is not set
CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_FTRACE=y
# CONFIG_NET_VENDOR_CADENCE is not set

9
arch/arc/configs/tb10x_defconfig
View File

@ -35,15 +35,11 @@ CONFIG_PACKET=y
CONFIG_UNIX=y
CONFIG_INET=y
CONFIG_IP_MULTICAST=y
# CONFIG_INET_XFRM_MODE_TRANSPORT is not set
# CONFIG_INET_XFRM_MODE_TUNNEL is not set
# CONFIG_INET_XFRM_MODE_BEET is not set
# CONFIG_INET_DIAG is not set
# CONFIG_IPV6 is not set
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_NETDEVICES=y
# CONFIG_NET_CADENCE is not set
# CONFIG_NET_VENDOR_BROADCOM is not set
# CONFIG_NET_VENDOR_INTEL is not set
# CONFIG_NET_VENDOR_MARVELL is not set
@ -90,16 +86,15 @@ CONFIG_TMPFS=y
CONFIG_CONFIGFS_FS=y
# CONFIG_MISC_FILESYSTEMS is not set
# CONFIG_NETWORK_FILESYSTEMS is not set
CONFIG_DEBUG_INFO=y
CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_FS=y
CONFIG_HEADERS_INSTALL=y
CONFIG_HEADERS_CHECK=y
CONFIG_DEBUG_SECTION_MISMATCH=y
CONFIG_MAGIC_SYSRQ=y
CONFIG_DEBUG_MEMORY_INIT=y
CONFIG_DEBUG_STACKOVERFLOW=y
CONFIG_DETECT_HUNG_TASK=y
CONFIG_SCHEDSTATS=y
CONFIG_TIMER_STATS=y
# CONFIG_CRYPTO_HW is not set
# CONFIG_NET_VENDOR_CADENCE is not set

3
arch/arc/configs/vdk_hs38_defconfig
View File

@ -58,8 +58,6 @@ CONFIG_SERIAL_OF_PLATFORM=y
# CONFIG_HW_RANDOM is not set
# CONFIG_HWMON is not set
CONFIG_FB=y
CONFIG_ARCPGU_RGB888=y
CONFIG_ARCPGU_DISPTYPE=0
# CONFIG_VGA_CONSOLE is not set
CONFIG_FRAMEBUFFER_CONSOLE=y
CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
@ -87,7 +85,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_SOFTLOCKUP_DETECTOR=y

1
arch/arc/configs/vdk_hs38_smp_defconfig
View File

@ -91,7 +91,6 @@ CONFIG_NFS_FS=y
CONFIG_NFS_V3_ACL=y
CONFIG_NLS_CODEPAGE_437=y
CONFIG_NLS_ISO8859_1=y
# CONFIG_ENABLE_MUST_CHECK is not set
CONFIG_STRIP_ASM_SYMS=y
CONFIG_DEBUG_SHIRQ=y
CONFIG_SOFTLOCKUP_DETECTOR=y

4
arch/arc/include/asm/bitops.h
View File

@ -82,7 +82,7 @@ static inline __attribute__ ((const)) int fls(unsigned int x)
/*
* __fls: Similar to fls, but zero based (0-31)
*/
static inline __attribute__ ((const)) int __fls(unsigned long x)
static inline __attribute__ ((const)) unsigned long __fls(unsigned long x)
{
if (!x)
return 0;
@ -131,7 +131,7 @@ static inline __attribute__ ((const)) int fls(unsigned int x)
/*
* __fls: Similar to fls, but zero based (0-31). Also 0 if no bit set
*/
static inline __attribute__ ((const)) int __fls(unsigned long x)
static inline __attribute__ ((const)) unsigned long __fls(unsigned long x)
{
/* FLS insn has exactly same semantics as the API */
return __builtin_arc_fls(x);

2
arch/arc/include/asm/entry-compact.h
View File

@ -21,7 +21,7 @@
* r25 contains the kernel current task ptr
* - Defined Stack Switching Macro to be reused in all intr/excp hdlrs
* - Shaved off 11 instructions from RESTORE_ALL_INT1 by using the
* address Write back load ld.ab instead of seperate ld/add instn
* address Write back load ld.ab instead of separate ld/add instn
*
* Amit Bhor, Sameer Dhavale: Codito Technologies 2004
*/

2
arch/arc/include/asm/io.h
View File

@ -32,7 +32,7 @@ static inline void ioport_unmap(void __iomem *addr)
{
}
extern void iounmap(const void __iomem *addr);
extern void iounmap(const volatile void __iomem *addr);
/*
* io{read,write}{16,32}be() macros

2
arch/arc/include/asm/pgtable-levels.h
View File

@ -161,7 +161,7 @@
#define pmd_pfn(pmd) ((pmd_val(pmd) & PAGE_MASK) >> PAGE_SHIFT)
#define pmd_page(pmd) virt_to_page(pmd_page_vaddr(pmd))
#define set_pmd(pmdp, pmd) (*(pmdp) = pmd)
#define pmd_pgtable(pmd) ((pgtable_t) pmd_page_vaddr(pmd))
#define pmd_pgtable(pmd) ((pgtable_t) pmd_page(pmd))
/*
* 4th level paging: pte

3
arch/arc/include/asm/processor.h
View File

@ -43,9 +43,6 @@ struct task_struct;
#define task_pt_regs(p) \
((struct pt_regs *)(THREAD_SIZE + (void *)task_stack_page(p)) - 1)
/* Free all resources held by a thread */
#define release_thread(thread) do { } while (0)
/*
* A lot of busy-wait loops in SMP are based off of non-volatile data otherwise
* get optimised away by gcc

4
arch/arc/kernel/Makefile
View File

@ -3,7 +3,7 @@
# Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
#
obj-y := arcksyms.o setup.o irq.o reset.o ptrace.o process.o devtree.o
obj-y := head.o arcksyms.o setup.o irq.o reset.o ptrace.o process.o devtree.o
obj-y += signal.o traps.o sys.o troubleshoot.o stacktrace.o disasm.o
obj-$(CONFIG_ISA_ARCOMPACT) += entry-compact.o intc-compact.o
obj-$(CONFIG_ISA_ARCV2) += entry-arcv2.o intc-arcv2.o
@ -31,4 +31,4 @@ else
obj-y += ctx_sw_asm.o
endif
extra-y := vmlinux.lds head.o
extra-y := vmlinux.lds

2
arch/arc/kernel/smp.c
View File

@ -385,7 +385,7 @@ irqreturn_t do_IPI(int irq, void *dev_id)
* API called by platform code to hookup arch-common ISR to their IPI IRQ
*
* Note: If IPI is provided by platform (vs. say ARC MCIP), their intc setup/map
* function needs to call call irq_set_percpu_devid() for IPI IRQ, otherwise
* function needs to call irq_set_percpu_devid() for IPI IRQ, otherwise
* request_percpu_irq() below will fail
*/
static DEFINE_PER_CPU(int, ipi_dev);

4
arch/arc/mm/cache.c
View File

@ -750,7 +750,7 @@ static inline void arc_slc_enable(void)
* -In SMP, if hardware caches are coherent
*
* There's a corollary case, where kernel READs from a userspace mapped page.
* If the U-mapping is not congruent to to K-mapping, former needs flushing.
* If the U-mapping is not congruent to K-mapping, former needs flushing.
*/
void flush_dcache_page(struct page *page)
{
@ -910,7 +910,7 @@ EXPORT_SYMBOL(flush_icache_range);
* @vaddr is typically user vaddr (breakpoint) or kernel vaddr (vmalloc)
* However in one instance, when called by kprobe (for a breakpt in
* builtin kernel code) @vaddr will be paddr only, meaning CDU operation will
* use a paddr to index the cache (despite VIPT). This is fine since since a
* use a paddr to index the cache (despite VIPT). This is fine since a
* builtin kernel page will not have any virtual mappings.
* kprobe on loadable module will be kernel vaddr.
*/

2
arch/arc/mm/ioremap.c
View File

@ -94,7 +94,7 @@ void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size,
EXPORT_SYMBOL(ioremap_prot);
void iounmap(const void __iomem *addr)
void iounmap(const volatile void __iomem *addr)
{
/* weird double cast to handle phys_addr_t > 32 bits */
if (arc_uncached_addr_space((phys_addr_t)(u32)addr))

141
arch/arm/Kconfig
View File

@ -28,7 +28,6 @@ config ARM
select ARCH_HAS_GCOV_PROFILE_ALL
select ARCH_KEEP_MEMBLOCK
select ARCH_MIGHT_HAVE_PC_PARPORT
select ARCH_NO_SG_CHAIN if !ARM_HAS_SG_CHAIN
select ARCH_OPTIONAL_KERNEL_RWX if ARCH_HAS_STRICT_KERNEL_RWX
select ARCH_OPTIONAL_KERNEL_RWX_DEFAULT if CPU_V7
select ARCH_SUPPORTS_ATOMIC_RMW
@ -42,6 +41,7 @@ config ARM
select ARCH_WANT_LD_ORPHAN_WARN
select BINFMT_FLAT_ARGVP_ENVP_ON_STACK
select BUILDTIME_TABLE_SORT if MMU
select COMMON_CLK if !(ARCH_RPC || ARCH_FOOTBRIDGE)
select CLONE_BACKWARDS
select CPU_PM if SUSPEND || CPU_IDLE
select DCACHE_WORD_ACCESS if HAVE_EFFICIENT_UNALIGNED_ACCESS
@ -110,6 +110,7 @@ config ARM
select HAVE_MOD_ARCH_SPECIFIC
select HAVE_NMI
select HAVE_OPTPROBES if !THUMB2_KERNEL
select HAVE_PCI if MMU
select HAVE_PERF_EVENTS
select HAVE_PERF_REGS
select HAVE_PERF_USER_STACK_DUMP
@ -126,13 +127,17 @@ config ARM
select OF_EARLY_FLATTREE if OF
select OLD_SIGACTION
select OLD_SIGSUSPEND3
select PCI_DOMAINS_GENERIC if PCI
select PCI_SYSCALL if PCI
select PERF_USE_VMALLOC
select RTC_LIB
select SPARSE_IRQ if !(ARCH_FOOTBRIDGE || ARCH_RPC)
select SYS_SUPPORTS_APM_EMULATION
select THREAD_INFO_IN_TASK
select TIMER_OF if OF
select HAVE_ARCH_VMAP_STACK if MMU && ARM_HAS_GROUP_RELOCS
select TRACE_IRQFLAGS_SUPPORT if !CPU_V7M
select USE_OF if !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
# Above selects are sorted alphabetically; please add new ones
# according to that. Thanks.
help
@ -154,12 +159,8 @@ config ARM_HAS_GROUP_RELOCS
which is usually sufficient, but not for allyesconfig, so we disable
this feature when doing compile testing.
config ARM_HAS_SG_CHAIN
bool
config ARM_DMA_USE_IOMMU
bool
select ARM_HAS_SG_CHAIN
select NEED_SG_DMA_LENGTH
if ARM_DMA_USE_IOMMU
@ -245,7 +246,7 @@ config ARCH_MTD_XIP
config ARM_PATCH_PHYS_VIRT
bool "Patch physical to virtual translations at runtime" if EMBEDDED
default y
depends on !XIP_KERNEL && MMU
depends on MMU
help
Patch phys-to-virt and virt-to-phys translation functions at
boot and module load time according to the position of the
@ -274,7 +275,7 @@ config NEED_MACH_MEMORY_H
config PHYS_OFFSET
hex "Physical address of main memory" if MMU
depends on !ARM_PATCH_PHYS_VIRT
depends on !ARM_PATCH_PHYS_VIRT || !AUTO_ZRELADDR
default DRAM_BASE if !MMU
default 0x00000000 if ARCH_FOOTBRIDGE
default 0x10000000 if ARCH_OMAP1 || ARCH_RPC
@ -307,13 +308,8 @@ config MMU
config ARM_SINGLE_ARMV7M
def_bool !MMU
select ARM_NVIC
select AUTO_ZRELADDR
select TIMER_OF
select COMMON_CLK
select CPU_V7M
select NO_IOPORT_MAP
select SPARSE_IRQ
select USE_OF
config ARCH_MMAP_RND_BITS_MIN
default 8
@ -323,94 +319,31 @@ config ARCH_MMAP_RND_BITS_MAX
default 15 if PAGE_OFFSET=0x80000000
default 16
#
# The "ARM system type" choice list is ordered alphabetically by option
# text. Please add new entries in the option alphabetic order.
#
choice
prompt "ARM system type"
depends on MMU
default ARCH_MULTIPLATFORM
config ARCH_MULTIPLATFORM
bool "Allow multiple platforms to be selected"
select ARCH_FLATMEM_ENABLE
select ARCH_SPARSEMEM_ENABLE
select ARCH_SELECT_MEMORY_MODEL
select ARM_HAS_SG_CHAIN
select ARM_PATCH_PHYS_VIRT
select AUTO_ZRELADDR
select TIMER_OF
select COMMON_CLK
select HAVE_PCI
select PCI_DOMAINS_GENERIC if PCI
select SPARSE_IRQ
select USE_OF
config ARCH_FOOTBRIDGE
bool "FootBridge"
depends on CPU_LITTLE_ENDIAN
depends on ATAGS
select CPU_SA110
select FOOTBRIDGE
select NEED_MACH_MEMORY_H
bool "Require kernel to be portable to multiple machines" if EXPERT
depends on MMU && !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
default y
help
Support for systems based on the DC21285 companion chip
("FootBridge"), such as the Simtec CATS and the Rebel NetWinder.
In general, all Arm machines can be supported in a single
kernel image, covering either Armv4/v5 or Armv6/v7.
config ARCH_RPC
bool "RiscPC"
depends on !CC_IS_CLANG && GCC_VERSION < 90100 && GCC_VERSION >= 60000
depends on CPU_LITTLE_ENDIAN
depends on ATAGS
select ARCH_ACORN
select ARCH_MAY_HAVE_PC_FDC
select ARCH_SPARSEMEM_ENABLE
select ARM_HAS_SG_CHAIN
select CPU_SA110
select FIQ
select HAVE_PATA_PLATFORM
select ISA_DMA_API
select LEGACY_TIMER_TICK
select NEED_MACH_IO_H
select NEED_MACH_MEMORY_H
select NO_IOPORT_MAP
help
On the Acorn Risc-PC, Linux can support the internal IDE disk and
CD-ROM interface, serial and parallel port, and the floppy drive.
However, some configuration options require hardcoding machine
specific physical addresses or enable errata workarounds that may
break other machines.
config ARCH_SA1100
bool "SA1100-based"
depends on CPU_LITTLE_ENDIAN
depends on ATAGS
select ARCH_MTD_XIP
select ARCH_SPARSEMEM_ENABLE
select CLKSRC_MMIO
select CLKSRC_PXA
select TIMER_OF if OF
select COMMON_CLK
select CPU_FREQ
select CPU_SA1100
select GPIOLIB
select IRQ_DOMAIN
select ISA
select NEED_MACH_MEMORY_H
select SPARSE_IRQ
help
Support for StrongARM 11x0 based boards.
Selecting N here allows using those options, including
DEBUG_UNCOMPRESS, XIP_KERNEL and ZBOOT_ROM. If unsure, say Y.
endchoice
menu "Multiple platform selection"
depends on ARCH_MULTIPLATFORM
menu "Platform selection"
depends on MMU
comment "CPU Core family selection"
config ARCH_MULTI_V4
bool "ARMv4 based platforms (FA526)"
bool "ARMv4 based platforms (FA526, StrongARM)"
depends on !ARCH_MULTI_V6_V7
select ARCH_MULTI_V4_V5
select CPU_FA526
select CPU_FA526 if !(CPU_SA110 || CPU_SA1100)
config ARCH_MULTI_V4T
bool "ARMv4T based platforms (ARM720T, ARM920T, ...)"
@ -472,7 +405,6 @@ config ARCH_AIROHA
select ARM_GIC_V3
select ARM_PSCI
select HAVE_ARM_ARCH_TIMER
select COMMON_CLK
help
Support for Airoha EN7523 SoCs
@ -573,6 +505,8 @@ source "arch/arm/mach-rda/Kconfig"
source "arch/arm/mach-realtek/Kconfig"
source "arch/arm/mach-rpc/Kconfig"
source "arch/arm/mach-rockchip/Kconfig"
source "arch/arm/mach-s3c/Kconfig"
@ -638,7 +572,6 @@ config ARCH_ACORN
config PLAT_ORION
bool
select CLKSRC_MMIO
select COMMON_CLK
select GENERIC_IRQ_CHIP
select IRQ_DOMAIN
@ -989,11 +922,6 @@ config ISA
(MCA) or VESA. ISA is an older system, now being displaced by PCI;
newer boards don't support it. If you have ISA, say Y, otherwise N.
# Select ISA DMA controller support
config ISA_DMA
bool
select ISA_DMA_API
# Select ISA DMA interface
config ISA_DMA_API
bool
@ -1054,7 +982,7 @@ config SMP
config SMP_ON_UP
bool "Allow booting SMP kernel on uniprocessor systems"
depends on SMP && !XIP_KERNEL && MMU
depends on SMP && MMU
default y
help
SMP kernels contain instructions which fail on non-SMP processors.
@ -1303,7 +1231,7 @@ config THUMB2_KERNEL
config ARM_PATCH_IDIV
bool "Runtime patch udiv/sdiv instructions into __aeabi_{u}idiv()"
depends on CPU_32v7 && !XIP_KERNEL
depends on CPU_32v7
default y
help
The ARM compiler inserts calls to __aeabi_idiv() and
@ -1358,13 +1286,13 @@ config OABI_COMPAT
at all). If in doubt say N.
config ARCH_SELECT_MEMORY_MODEL
bool
def_bool y
config ARCH_FLATMEM_ENABLE
bool
def_bool !(ARCH_RPC || ARCH_SA1100)
config ARCH_SPARSEMEM_ENABLE
bool
def_bool !ARCH_FOOTBRIDGE
select SPARSEMEM_STATIC if SPARSEMEM
config HIGHMEM
@ -1434,7 +1362,7 @@ config ARM_MODULE_PLTS
Disabling this is usually safe for small single-platform
configurations. If unsure, say y.
config FORCE_MAX_ZONEORDER
config ARCH_FORCE_MAX_ORDER
int "Maximum zone order"
default "12" if SOC_AM33XX
default "9" if SA1111
@ -1671,7 +1599,6 @@ config CMDLINE
choice
prompt "Kernel command line type" if CMDLINE != ""
default CMDLINE_FROM_BOOTLOADER
depends on ATAGS
config CMDLINE_FROM_BOOTLOADER
bool "Use bootloader kernel arguments if available"
@ -1698,6 +1625,7 @@ endchoice
config XIP_KERNEL
bool "Kernel Execute-In-Place from ROM"
depends on !ARM_LPAE && !ARCH_MULTIPLATFORM
depends on !ARM_PATCH_IDIV && !ARM_PATCH_PHYS_VIRT && !SMP_ON_UP
help
Execute-In-Place allows the kernel to run from non-volatile storage
directly addressable by the CPU, such as NOR flash. This saves RAM
@ -1772,7 +1700,8 @@ config CRASH_DUMP
For more details see Documentation/admin-guide/kdump/kdump.rst
config AUTO_ZRELADDR
bool "Auto calculation of the decompressed kernel image address"
bool "Auto calculation of the decompressed kernel image address" if !ARCH_MULTIPLATFORM
default !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
help
ZRELADDR is the physical address where the decompressed kernel
image will be placed. If AUTO_ZRELADDR is selected, the address
@ -1921,8 +1850,4 @@ config ARCH_HIBERNATION_POSSIBLE
endmenu
if CRYPTO
source "arch/arm/crypto/Kconfig"
endif
source "arch/arm/Kconfig.assembler"

8
arch/arm/Kconfig.debug
View File

@ -1904,7 +1904,8 @@ config DEBUG_UART_8250_PALMCHIP
config DEBUG_UNCOMPRESS
bool "Enable decompressor debugging via DEBUG_LL output"
depends on ARCH_MULTIPLATFORM || PLAT_SAMSUNG || ARM_SINGLE_ARMV7M
depends on !ARCH_MULTIPLATFORM
depends on !(ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100)
depends on DEBUG_LL && !DEBUG_OMAP2PLUS_UART && \
(!DEBUG_TEGRA_UART || !ZBOOT_ROM) && \
!DEBUG_BRCMSTB_UART && !DEBUG_SEMIHOSTING
@ -1921,9 +1922,8 @@ config DEBUG_UNCOMPRESS
config UNCOMPRESS_INCLUDE
string
default "debug/uncompress.h" if ARCH_MULTIPLATFORM || ARCH_MSM || \
PLAT_SAMSUNG || ARM_SINGLE_ARMV7M
default "mach/uncompress.h"
default "mach/uncompress.h" if ARCH_FOOTBRIDGE || ARCH_RPC || ARCH_SA1100
default "debug/uncompress.h"
config EARLY_PRINTK
bool "Early printk"

46
arch/arm/Makefile
View File

@ -22,6 +22,9 @@ GZFLAGS :=-9
# Never generate .eh_frame
KBUILD_CFLAGS += $(call cc-option,-fno-dwarf2-cfi-asm)
# Disable FDPIC ABI
KBUILD_CFLAGS += $(call cc-option,-mno-fdpic)
# This should work on most of the modern platforms
KBUILD_DEFCONFIG := multi_v7_defconfig
@ -134,9 +137,6 @@ KBUILD_AFLAGS +=$(CFLAGS_ABI) $(AFLAGS_ISA) $(arch-y) $(tune-y) -include asm/uni
CHECKFLAGS += -D__arm__
#Default value
head-y := arch/arm/kernel/head$(MMUEXT).o
# Text offset. This list is sorted numerically by address in order to
# provide a means to avoid/resolve conflicts in multi-arch kernels.
# Note: the 32kB below this value is reserved for use by the kernel
@ -224,40 +224,24 @@ machine-$(CONFIG_ARCH_ZYNQ) += zynq
machine-$(CONFIG_PLAT_VERSATILE) += versatile
machine-$(CONFIG_PLAT_SPEAR) += spear
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
plat-$(CONFIG_PLAT_ORION) += orion
# legacy platforms provide their own mach/*.h headers globally,
# these three are mutually exclusive
machdirs-$(CONFIG_ARCH_FOOTBRIDGE) += arch/arm/mach-footbridge
machdirs-$(CONFIG_ARCH_RPC) += arch/arm/mach-rpc
machdirs-$(CONFIG_ARCH_SA1100) += arch/arm/mach-sa1100
KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%/include,$(machdirs-y))
# The byte offset of the kernel image in RAM from the start of RAM.
TEXT_OFFSET := $(textofs-y)
# The first directory contains additional information for the boot setup code
ifneq ($(machine-y),)
MACHINE := arch/arm/mach-$(word 1,$(machine-y))/
else
MACHINE :=
endif
ifeq ($(CONFIG_ARCH_MULTIPLATFORM),y)
MACHINE :=
endif
machdirs := $(patsubst %,arch/arm/mach-%/,$(machine-y))
platdirs := $(patsubst %,arch/arm/plat-%/,$(sort $(plat-y)))
ifneq ($(CONFIG_ARCH_MULTIPLATFORM),y)
ifneq ($(CONFIG_ARM_SINGLE_ARMV7M),y)
KBUILD_CPPFLAGS += $(patsubst %,-I$(srctree)/%include,$(machdirs) $(platdirs))
endif
endif
export TEXT_OFFSET GZFLAGS MMUEXT
# If we have a machine-specific directory, then include it in the build.
core-y += $(machdirs) $(platdirs)
core-y += $(patsubst %,arch/arm/mach-%/,$(machine-y))
# For cleaning
core- += $(patsubst %,arch/arm/mach-%/, $(machine-))
core- += $(patsubst %,arch/arm/plat-%/, $(plat-))
core- += $(patsubst %,arch/arm/mach-%/,$(machine-))
core-$(CONFIG_PLAT_ORION) += arch/arm/plat-orion/
libs-y := arch/arm/lib/ $(libs-y)
@ -310,7 +294,7 @@ bootpImage uImage: zImage
zImage: Image
$(BOOT_TARGETS): vmlinux
$(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/$@
$(Q)$(MAKE) $(build)=$(boot) $(boot)/$@
@$(kecho) ' Kernel: $(boot)/$@ is ready'
$(INSTALL_TARGETS): KBUILD_IMAGE = $(boot)/$(patsubst %install,%Image,$@)
@ -324,7 +308,7 @@ ifeq ($(CONFIG_VDSO),y)
endif
# My testing targets (bypasses dependencies)
bp:; $(Q)$(MAKE) $(build)=$(boot) MACHINE=$(MACHINE) $(boot)/bootpImage
bp:; $(Q)$(MAKE) $(build)=$(boot) $(boot)/bootpImage
define archhelp

27
arch/arm/boot/Makefile
View File

@ -10,22 +10,16 @@
#
# Copyright (C) 1995-2002 Russell King
#
OBJCOPYFLAGS :=-O binary -R .comment -S
ifneq ($(MACHINE),)
include $(MACHINE)/Makefile.boot
# ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
ifdef CONFIG_PHYS_OFFSET
add_hex = $(shell printf 0x%x $$(( $(1) + $(2) )) )
ZRELADDR := $(call add_hex, $(CONFIG_PHYS_OFFSET), $(TEXT_OFFSET))
endif
# Note: the following conditions must always be true:
# ZRELADDR == virt_to_phys(PAGE_OFFSET + TEXT_OFFSET)
# PARAMS_PHYS must be within 4MB of ZRELADDR
# INITRD_PHYS must be in RAM
ZRELADDR := $(zreladdr-y)
PARAMS_PHYS := $(params_phys-y)
INITRD_PHYS := $(initrd_phys-y)
export ZRELADDR INITRD_PHYS PARAMS_PHYS
PHYS_OFFSET := $(CONFIG_PHYS_OFFSET)
export ZRELADDR PARAMS_PHYS PHYS_OFFSET
targets := Image zImage xipImage bootpImage uImage
@ -90,17 +84,10 @@ $(obj)/uImage: $(obj)/zImage FORCE
@$(check_for_multiple_loadaddr)
$(call if_changed,uimage)
$(obj)/bootp/bootp: $(obj)/zImage initrd FORCE
$(obj)/bootp/bootp: $(obj)/zImage FORCE
$(Q)$(MAKE) $(build)=$(obj)/bootp $@
$(obj)/bootpImage: $(obj)/bootp/bootp FORCE
$(call if_changed,objcopy)
PHONY += initrd
initrd:
@test "$(INITRD_PHYS)" != "" || \
(echo This machine does not support INITRD; exit -1)
@test "$(INITRD)" != "" || \
(echo You must specify INITRD; exit -1)
subdir- := bootp compressed dts

35
arch/arm/boot/bootp/Makefile
View File

@ -5,9 +5,40 @@
# This file is included by the global makefile so that you can add your own
# architecture-specific flags and dependencies.
#
GCOV_PROFILE := n
ifdef PHYS_OFFSET
add_hex = $(shell printf 0x%x $$(( $(1) + $(2) )) )
# If PHYS_OFFSET is set, INITRD_PHYS and PARAMS_PHYS can be derived,
# otherwise they must be passed on the command line.
#
# Note: the following conditions must always be true:
# PARAMS_PHYS must be within 4MB of ZRELADDR
# INITRD_PHYS must be in RAM
PARAMS_PHYS := $(call add_hex, $(PHYS_OFFSET), 0x100)
# guess an initrd location if possible
initrd_offset-$(CONFIG_ARCH_FOOTBRIDGE) += 0x00800000
initrd_offset-$(CONFIG_ARCH_SA1100) += 0x00800000
initrd_offset-$(CONFIG_ARCH_RPC) += 0x08000000
INITRD_OFFSET := $(initrd_offset-y)
ifdef INITRD_OFFSET
INITRD_PHYS := $(call add_hex, $(PHYS_OFFSET), $(INITRD_OFFSET))
endif
endif
PHONY += initrd
initrd:
@test "$(PARAMS_PHYS)" != "" || \
(echo bootpImage: You must specify PHYS_OFFSET of PARAMS_PHYS ; exit -1)
@test "$(INITRD_PHYS)" != "" || \
(echo bootpImage: You must specify INITRD_OFFSET or INITRD_PHYS ; exit -1)
@test "$(INITRD)" != "" || \
(echo bootpImage: You must specify INITRD; exit -1)
LDFLAGS_bootp := --no-undefined -X \
--defsym initrd_phys=$(INITRD_PHYS) \
--defsym params_phys=$(PARAMS_PHYS) -T
@ -24,6 +55,6 @@ $(obj)/bootp: $(src)/bootp.lds $(addprefix $(obj)/,init.o kernel.o initrd.o) FOR
$(obj)/kernel.o: arch/arm/boot/zImage FORCE
$(obj)/initrd.o: $(INITRD) FORCE
$(obj)/initrd.o: initrd $(INITRD) FORCE
PHONY += $(INITRD)

4
arch/arm/boot/compressed/head.S
View File

@ -67,11 +67,7 @@
#if defined(CONFIG_ARCH_SA1100)
.macro loadsp, rb, tmp1, tmp2
mov \rb, #0x80000000 @ physical base address
#ifdef CONFIG_DEBUG_LL_SER3
add \rb, \rb, #0x00050000 @ Ser3
#else
add \rb, \rb, #0x00010000 @ Ser1
#endif
.endm
#else
.macro loadsp, rb, tmp1, tmp2

2
arch/arm/boot/compressed/misc.c
View File

@ -23,7 +23,9 @@ unsigned int __machine_arch_type;
#include <linux/types.h>
#include <linux/linkage.h>
#include "misc.h"
#ifdef CONFIG_ARCH_EP93XX
#include "misc-ep93xx.h"
#endif
static void putstr(const char *ptr);

2
arch/arm/boot/compressed/vmlinux.lds.S
View File

@ -23,6 +23,7 @@ SECTIONS
*(.ARM.extab*)
*(.note.*)
*(.rel.*)
*(.printk_index)
/*
* Discard any r/w data - this produces a link error if we have any,
* which is required for PIC decompression. Local data generates
@ -57,6 +58,7 @@ SECTIONS
*(.rodata)
*(.rodata.*)
*(.data.rel.ro)
*(.data.rel.ro.*)
}
.piggydata : {
*(.piggydata)

12
arch/arm/boot/dts/Makefile
View File

@ -82,6 +82,7 @@ dtb-$(CONFIG_SOC_SAM_V7) += \
at91-sama5d2_icp.dtb \
at91-sama5d2_ptc_ek.dtb \
at91-sama5d2_xplained.dtb \
at91-sama5d3_eds.dtb \
at91-sama5d3_ksz9477_evb.dtb \
at91-sama5d3_xplained.dtb \
at91-dvk_som60.dtb \
@ -727,8 +728,8 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ul-geam.dtb \
imx6ul-isiot-emmc.dtb \
imx6ul-isiot-nand.dtb \
imx6ul-kontron-n6310-s.dtb \
imx6ul-kontron-n6310-s-43.dtb \
imx6ul-kontron-bl.dtb \
imx6ul-kontron-bl-43.dtb \
imx6ul-liteboard.dtb \
imx6ul-tqma6ul1-mba6ulx.dtb \
imx6ul-tqma6ul2-mba6ulx.dtb \
@ -757,6 +758,7 @@ dtb-$(CONFIG_SOC_IMX6UL) += \
imx6ull-colibri-wifi-iris.dtb \
imx6ull-colibri-wifi-iris-v2.dtb \
imx6ull-jozacp.dtb \
imx6ull-kontron-bl.dtb \
imx6ull-myir-mys-6ulx-eval.dtb \
imx6ull-opos6uldev.dtb \
imx6ull-phytec-segin-ff-rdk-nand.dtb \
@ -809,6 +811,7 @@ dtb-$(CONFIG_SOC_IMXRT) += \
dtb-$(CONFIG_SOC_LAN966) += \
lan966x-kontron-kswitch-d10-mmt-6g-2gs.dtb \
lan966x-kontron-kswitch-d10-mmt-8g.dtb \
lan966x-pcb8290.dtb \
lan966x-pcb8291.dtb \
lan966x-pcb8309.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
@ -1068,6 +1071,9 @@ dtb-$(CONFIG_ARCH_QCOM) += \
qcom-ipq8064-rb3011.dtb \
qcom-msm8226-samsung-s3ve3g.dtb \
qcom-msm8660-surf.dtb \
qcom-msm8916-samsung-e5.dtb \
qcom-msm8916-samsung-e7.dtb \
qcom-msm8916-samsung-grandmax.dtb \
qcom-msm8916-samsung-serranove.dtb \
qcom-msm8960-cdp.dtb \
qcom-msm8974-lge-nexus5-hammerhead.dtb \
@ -1595,8 +1601,10 @@ dtb-$(CONFIG_ARCH_ASPEED) += \
aspeed-ast2500-evb.dtb \
aspeed-ast2600-evb-a1.dtb \
aspeed-ast2600-evb.dtb \
aspeed-bmc-amd-daytonax.dtb \
aspeed-bmc-amd-ethanolx.dtb \
aspeed-bmc-ampere-mtjade.dtb \
aspeed-bmc-ampere-mtmitchell.dtb \
aspeed-bmc-arm-stardragon4800-rep2.dtb \
aspeed-bmc-asrock-e3c246d4i.dtb \
aspeed-bmc-asrock-romed8hm3.dtb \

144
arch/arm/boot/dts/am335x-baltos-ir2110.dts
View File

@ -81,3 +81,147 @@ &mmc1 {
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
};
&gpio0 {
gpio-line-names =
"MDIO",
"MDC",
"NC",
"NC",
"I2C1_SDA",
"I2C1_SCL",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"UART1_CTSN",
"UART1_RTSN",
"UART1_RX",
"UART1_TX",
"onrisc:blue:wlan",
"onrisc:green:app",
"USB0_DRVVBUS",
"ETH2_INT",
"NC",
"RMII1_TXD1",
"MMC1_DAT0",
"MMC1_DAT1",
"NC",
"NC",
"MMC1_DAT2",
"MMC1_DAT3",
"RMII1_TXD0",
"NC",
"GPMC_WAIT0",
"GPMC_WP_N";
};
&gpio1 {
gpio-line-names =
"GPMC_AD0",
"GPMC_AD1",
"GPMC_AD2",
"GPMC_AD3",
"GPMC_AD4",
"GPMC_AD5",
"GPMC_AD6",
"GPMC_AD7",
"NC",
"NC",
"CONSOLE_RX",
"CONSOLE_TX",
"NC",
"NC",
"NC",
"SD_CD",
"RGMII2_TCTL",
"RGMII2_RCTL",
"RGMII2_TD3",
"RGMII2_TD2",
"RGMII2_TD1",
"RGMII2_TD0",
"RGMII2_TCLK",
"RGMII2_RCLK",
"RGMII2_RD3",
"RGMII2_RD2",
"RGMII2_RD1",
"RGMII2_RD0",
"PMIC_INT1",
"GPMC_CSN0_Flash",
"MMC1_CLK",
"MMC1_CMD";
};
&gpio2 {
gpio-line-names =
"GPMC_CSN3_BUS",
"GPMC_CLK",
"GPMC_ADVN_ALE",
"GPMC_OEN_RE_N",
"GPMC_WE_N",
"GPMC_BEN0_CLE",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"SW2_0",
"SW2_1",
"RMII1_RXD1",
"RMII1_RXD0",
"UART1_DTR",
"UART1_DSR",
"UART1_DCD",
"UART1_RI",
"MMC0_DAT3",
"MMC0_DAT2",
"MMC0_DAT1",
"MMC0_DAT0",
"MMC0_CLK",
"MMC0_CMD";
};
&gpio3 {
gpio-line-names =
"onrisc:red:power",
"RMII1_CRS_DV",
"RMII1_RXER",
"RMII1_TXEN",
"NC",
"NC",
"NC",
"WLAN_IRQ",
"WLAN_EN",
"SW2_2",
"SW2_3",
"NC",
"NC",
"NC",
"ModeA0",
"ModeA1",
"ModeA2",
"ModeA3",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC";
};

148
arch/arm/boot/dts/am335x-baltos-ir3220.dts
View File

@ -91,6 +91,10 @@ tca6416: gpio@20 {
interrupts = <20 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&tca6416_pins>;
gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3",
"GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3",
"ModeA0", "ModeA1", "ModeA2", "ModeA3",
"ModeB0", "ModeB1", "ModeB2", "ModeB3";
};
};
@ -123,3 +127,147 @@ &mmc1 {
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
};
&gpio0 {
gpio-line-names =
"MDIO",
"MDC",
"UART2_RX",
"UART2_TX",
"I2C1_SDA",
"I2C1_SCL",
"WLAN_BTN",
"W_DISABLE",
"NC",
"NC",
"NC",
"NC",
"UART1_CTSN",
"UART1_RTSN",
"UART1_RX",
"UART1_TX",
"onrisc:blue:wlan",
"onrisc:green:app",
"USB0_DRVVBUS",
"ETH2_INT",
"TCA6416_INT",
"RMII1_TXD1",
"MMC1_DAT0",
"MMC1_DAT1",
"NC",
"NC",
"MMC1_DAT2",
"MMC1_DAT3",
"RMII1_TXD0",
"NC",
"GPMC_WAIT0",
"GPMC_WP_N";
};
&gpio1 {
gpio-line-names =
"GPMC_AD0",
"GPMC_AD1",
"GPMC_AD2",
"GPMC_AD3",
"GPMC_AD4",
"GPMC_AD5",
"GPMC_AD6",
"GPMC_AD7",
"NC",
"NC",
"CONSOLE_RX",
"CONSOLE_TX",
"UART2_DTR",
"UART2_DSR",
"UART2_DCD",
"UART2_RI",
"RGMII2_TCTL",
"RGMII2_RCTL",
"RGMII2_TD3",
"RGMII2_TD2",
"RGMII2_TD1",
"RGMII2_TD0",
"RGMII2_TCLK",
"RGMII2_RCLK",
"RGMII2_RD3",
"RGMII2_RD2",
"RGMII2_RD1",
"RGMII2_RD0",
"PMIC_INT1",
"GPMC_CSN0_Flash",
"MMC1_CLK",
"MMC1_CMD";
};
&gpio2 {
gpio-line-names =
"GPMC_CSN3_BUS",
"GPMC_CLK",
"GPMC_ADVN_ALE",
"GPMC_OEN_RE_N",
"GPMC_WE_N",
"GPMC_BEN0_CLE",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"SD_CD",
"SD_WP",
"RMII1_RXD1",
"RMII1_RXD0",
"UART1_DTR",
"UART1_DSR",
"UART1_DCD",
"UART1_RI",
"MMC0_DAT3",
"MMC0_DAT2",
"MMC0_DAT1",
"MMC0_DAT0",
"MMC0_CLK",
"MMC0_CMD";
};
&gpio3 {
gpio-line-names =
"onrisc:red:power",
"RMII1_CRS_DV",
"RMII1_RXER",
"RMII1_TXEN",
"3G_PWR_EN",
"UART2_CTSN",
"UART2_RTSN",
"WLAN_IRQ",
"WLAN_EN",
"NC",
"NC",
"NC",
"NC",
"USB1_DRVVBUS",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC";
};

148
arch/arm/boot/dts/am335x-baltos-ir5221.dts
View File

@ -99,6 +99,10 @@ tca6416: gpio@20 {
interrupts = <20 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&tca6416_pins>;
gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3",
"GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3",
"ModeA0", "ModeA1", "ModeA2", "ModeA3",
"ModeB0", "ModeB1", "ModeB2", "ModeB3";
};
};
@ -147,3 +151,147 @@ &mmc1 {
pinctrl-0 = <&mmc1_pins>;
cd-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>;
};
&gpio0 {
gpio-line-names =
"MDIO",
"MDC",
"UART2_RX",
"UART2_TX",
"I2C1_SDA",
"I2C1_SCL",
"WLAN_BTN",
"W_DISABLE",
"NC",
"NC",
"NC",
"NC",
"UART1_CTSN",
"UART1_RTSN",
"UART1_RX",
"UART1_TX",
"onrisc:blue:wlan",
"onrisc:green:app",
"USB0_DRVVBUS",
"ETH2_INT",
"TCA6416_INT",
"RMII1_TXD1",
"MMC1_DAT0",
"MMC1_DAT1",
"NC",
"NC",
"MMC1_DAT2",
"MMC1_DAT3",
"RMII1_TXD0",
"NC",
"GPMC_WAIT0",
"GPMC_WP_N";
};
&gpio1 {
gpio-line-names =
"GPMC_AD0",
"GPMC_AD1",
"GPMC_AD2",
"GPMC_AD3",
"GPMC_AD4",
"GPMC_AD5",
"GPMC_AD6",
"GPMC_AD7",
"DCAN1_TX",
"DCAN1_RX",
"CONSOLE_RX",
"CONSOLE_TX",
"UART2_DTR",
"UART2_DSR",
"UART2_DCD",
"UART2_RI",
"RGMII2_TCTL",
"RGMII2_RCTL",
"RGMII2_TD3",
"RGMII2_TD2",
"RGMII2_TD1",
"RGMII2_TD0",
"RGMII2_TCLK",
"RGMII2_RCLK",
"RGMII2_RD3",
"RGMII2_RD2",
"RGMII2_RD1",
"RGMII2_RD0",
"PMIC_INT1",
"GPMC_CSN0_Flash",
"MMC1_CLK",
"MMC1_CMD";
};
&gpio2 {
gpio-line-names =
"GPMC_CSN3_BUS",
"GPMC_CLK",
"GPMC_ADVN_ALE",
"GPMC_OEN_RE_N",
"GPMC_WE_N",
"GPMC_BEN0_CLE",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"SD_CD",
"SD_WP",
"RMII1_RXD1",
"RMII1_RXD0",
"UART1_DTR",
"UART1_DSR",
"UART1_DCD",
"UART1_RI",
"MMC0_DAT3",
"MMC0_DAT2",
"MMC0_DAT1",
"MMC0_DAT0",
"MMC0_CLK",
"MMC0_CMD";
};
&gpio3 {
gpio-line-names =
"onrisc:red:power",
"RMII1_CRS_DV",
"RMII1_RXER",
"RMII1_TXEN",
"3G_PWR_EN",
"UART2_CTSN",
"UART2_RTSN",
"WLAN_IRQ",
"WLAN_EN",
"NC",
"NC",
"NC",
"NC",
"USB1_DRVVBUS",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC";
};

2
arch/arm/boot/dts/am335x-baltos.dtsi
View File

@ -197,7 +197,7 @@ nand@0,0 {
rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
nand-bus-width = <8>;
ti,nand-ecc-opt = "bch8";
ti,nand-xfer-type = "polled";
ti,nand-xfer-type = "prefetch-dma";
gpmc,device-nand = "true";
gpmc,device-width = <1>;

144
arch/arm/boot/dts/am335x-netcan-plus-1xx.dts
View File

@ -85,3 +85,147 @@ &dcan1 {
status = "okay";
};
&gpio0 {
gpio-line-names =
"MDIO",
"MDC",
"NC",
"NC",
"I2C1_SDA",
"I2C1_SCL",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"can_data",
"can_error",
"onrisc:blue:wlan",
"onrisc:green:app",
"USB0_DRVVBUS",
"ETH2_INT",
"NC",
"NC",
"MMC1_DAT0",
"MMC1_DAT1",
"NC",
"NC",
"MMC1_DAT2",
"MMC1_DAT3",
"NC",
"NC",
"GPMC_WAIT0",
"GPMC_WP_N";
};
&gpio1 {
gpio-line-names =
"GPMC_AD0",
"GPMC_AD1",
"GPMC_AD2",
"GPMC_AD3",
"GPMC_AD4",
"GPMC_AD5",
"GPMC_AD6",
"GPMC_AD7",
"DCAN1_TX",
"DCAN1_RX",
"CONSOLE_RX",
"CONSOLE_TX",
"NC",
"NC",
"NC",
"NC",
"RGMII2_TCTL",
"RGMII2_RCTL",
"RGMII2_TD3",
"RGMII2_TD2",
"RGMII2_TD1",
"RGMII2_TD0",
"RGMII2_TCLK",
"RGMII2_RCLK",
"RGMII2_RD3",
"RGMII2_RD2",
"RGMII2_RD1",
"RGMII2_RD0",
"PMIC_INT1",
"GPMC_CSN0_Flash",
"MMC1_CLK",
"MMC1_CMD";
};
&gpio2 {
gpio-line-names =
"GPMC_CSN3_BUS",
"GPMC_CLK",
"GPMC_ADVN_ALE",
"GPMC_OEN_RE_N",
"GPMC_WE_N",
"GPMC_BEN0_CLE",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"SW2_0",
"SW2_1",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"MMC0_DAT3",
"MMC0_DAT2",
"MMC0_DAT1",
"MMC0_DAT0",
"MMC0_CLK",
"MMC0_CMD";
};
&gpio3 {
gpio-line-names =
"onrisc:red:power",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"WLAN_IRQ",
"WLAN_EN",
"SW2_2",
"SW2_3",
"NC",
"NC",
"NC",
"ModeA0",
"ModeA1",
"ModeA2",
"ModeA3",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC";
};

144
arch/arm/boot/dts/am335x-netcom-plus-2xx.dts
View File

@ -93,3 +93,147 @@ &cpsw_port2 {
ti,dual-emac-pvid = <2>;
phy-handle = <&phy1>;
};
&gpio0 {
gpio-line-names =
"MDIO",
"MDC",
"UART2_RX",
"UART2_TX",
"I2C1_SDA",
"I2C1_SCL",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"UART1_CTSN",
"UART1_RTSN",
"UART1_RX",
"UART1_TX",
"onrisc:blue:wlan",
"onrisc:green:app",
"USB0_DRVVBUS",
"ETH2_INT",
"NC",
"NC",
"MMC1_DAT0",
"MMC1_DAT1",
"NC",
"NC",
"MMC1_DAT2",
"MMC1_DAT3",
"NC",
"NC",
"GPMC_WAIT0",
"GPMC_WP_N";
};
&gpio1 {
gpio-line-names =
"GPMC_AD0",
"GPMC_AD1",
"GPMC_AD2",
"GPMC_AD3",
"GPMC_AD4",
"GPMC_AD5",
"GPMC_AD6",
"GPMC_AD7",
"NC",
"NC",
"CONSOLE_RX",
"CONSOLE_TX",
"UART2_DTR",
"UART2_DSR",
"UART2_DCD",
"UART2_RI",
"RGMII2_TCTL",
"RGMII2_RCTL",
"RGMII2_TD3",
"RGMII2_TD2",
"RGMII2_TD1",
"RGMII2_TD0",
"RGMII2_TCLK",
"RGMII2_RCLK",
"RGMII2_RD3",
"RGMII2_RD2",
"RGMII2_RD1",
"RGMII2_RD0",
"PMIC_INT1",
"GPMC_CSN0_Flash",
"MMC1_CLK",
"MMC1_CMD";
};
&gpio2 {
gpio-line-names =
"GPMC_CSN3_BUS",
"GPMC_CLK",
"GPMC_ADVN_ALE",
"GPMC_OEN_RE_N",
"GPMC_WE_N",
"GPMC_BEN0_CLE",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"SW2_0",
"SW2_1",
"NC",
"NC",
"UART1_DTR",
"UART1_DSR",
"UART1_DCD",
"UART1_RI",
"MMC0_DAT3",
"MMC0_DAT2",
"MMC0_DAT1",
"MMC0_DAT0",
"MMC0_CLK",
"MMC0_CMD";
};
&gpio3 {
gpio-line-names =
"onrisc:red:power",
"NC",
"NC",
"NC",
"NC",
"UART2_CTSN",
"UART2_RTSN",
"WLAN_IRQ",
"WLAN_EN",
"SW2_2",
"SW2_3",
"NC",
"NC",
"NC",
"ModeA0",
"ModeA1",
"ModeA2",
"ModeA3",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC";
};

156
arch/arm/boot/dts/am335x-netcom-plus-8xx.dts
View File

@ -71,6 +71,10 @@ tca6416a: gpio@20 {
interrupts = <20 IRQ_TYPE_EDGE_RISING>;
pinctrl-names = "default";
pinctrl-0 = <&tca6416_pins>;
gpio-line-names = "GP_IN0", "GP_IN1", "GP_IN2", "GP_IN3",
"GP_IN4", "GP_IN5", "GP_IN6", "GP_IN7",
"GP_OUT0", "GP_OUT1", "GP_OUT2", "GP_OUT3",
"GP_OUT4", "GP_OUT5", "GP_OUT6", "GP_OUT7";
};
};
@ -86,6 +90,10 @@ tca6416b: gpio@20 {
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "CH1_M0", "CH1_M1", "CH1_M2", "CH1_M3",
"CH2_M0", "CH2_M1", "CH2_M2", "CH2_M3",
"CH3_M0", "CH3_M1", "CH3_M2", "CH3_M3",
"CH4_M0", "CH4_M1", "CH4_M2", "CH4_M3";
};
tca6416c: gpio@21 {
@ -93,6 +101,10 @@ tca6416c: gpio@21 {
reg = <0x21>;
gpio-controller;
#gpio-cells = <2>;
gpio-line-names = "CH5_M0", "CH5_M1", "CH5_M2", "CH5_M3",
"CH6_M0", "CH6_M1", "CH6_M2", "CH6_M3",
"CH7_M0", "CH7_M1", "CH7_M2", "CH7_M3",
"CH8_M0", "CH8_M1", "CH8_M2", "CH8_M3";
};
};
@ -113,3 +125,147 @@ &cpsw_port2 {
ti,dual-emac-pvid = <2>;
phy-handle = <&phy1>;
};
&gpio0 {
gpio-line-names =
"MDIO",
"MDC",
"NC",
"NC",
"I2C1_SDA",
"I2C1_SCL",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"I2C2_SDA",
"I2C2_SCL",
"NC",
"NC",
"onrisc:blue:wlan",
"onrisc:green:app",
"USB0_DRVVBUS",
"ETH2_INT",
"NC",
"NC",
"MMC1_DAT0",
"MMC1_DAT1",
"NC",
"NC",
"MMC1_DAT2",
"MMC1_DAT3",
"NC",
"NC",
"GPMC_WAIT0",
"GPMC_WP_N";
};
&gpio1 {
gpio-line-names =
"GPMC_AD0",
"GPMC_AD1",
"GPMC_AD2",
"GPMC_AD3",
"GPMC_AD4",
"GPMC_AD5",
"GPMC_AD6",
"GPMC_AD7",
"NC",
"NC",
"CONSOLE_RX",
"CONSOLE_TX",
"SW2_0_alt",
"SW2_1_alt",
"SW2_2_alt",
"SW2_3_alt",
"RGMII2_TCTL",
"RGMII2_RCTL",
"RGMII2_TD3",
"RGMII2_TD2",
"RGMII2_TD1",
"RGMII2_TD0",
"RGMII2_TCLK",
"RGMII2_RCLK",
"RGMII2_RD3",
"RGMII2_RD2",
"RGMII2_RD1",
"RGMII2_RD0",
"PMIC_INT1",
"GPMC_CSN0_Flash",
"MMC1_CLK",
"MMC1_CMD";
};
&gpio2 {
gpio-line-names =
"GPMC_CSN3_BUS",
"GPMC_CLK",
"GPMC_ADVN_ALE",
"GPMC_OEN_RE_N",
"GPMC_WE_N",
"GPMC_BEN0_CLE",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"SW2_0",
"SW2_1",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"MMC0_DAT3",
"MMC0_DAT2",
"MMC0_DAT1",
"MMC0_DAT0",
"MMC0_CLK",
"MMC0_CMD";
};
&gpio3 {
gpio-line-names =
"onrisc:red:power",
"NC",
"NC",
"NC",
"3G_PWR_EN",
"NC",
"NC",
"WLAN_IRQ",
"WLAN_EN",
"SW2_2",
"SW2_3",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC",
"NC";
};

28
arch/arm/boot/dts/am335x-pcm-953.dtsi
View File

@ -12,22 +12,20 @@ / {
compatible = "phytec,am335x-pcm-953", "phytec,am335x-phycore-som", "ti,am33xx";
/* Power */
regulators {
vcc3v3: fixedregulator@1 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
vcc3v3: fixedregulator1 {
compatible = "regulator-fixed";
regulator-name = "vcc3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
};
vcc1v8: fixedregulator@2 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
vcc1v8: fixedregulator2 {
compatible = "regulator-fixed";
regulator-name = "vcc1v8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-boot-on;
};
/* User IO */

3
arch/arm/boot/dts/am33xx-l4.dtsi
View File

@ -1502,8 +1502,7 @@ SYSC_OMAP2_SOFTRESET |
mmc1: mmc@0 {
compatible = "ti,am335-sdhci";
ti,needs-special-reset;
dmas = <&edma_xbar 24 0 0
&edma_xbar 25 0 0>;
dmas = <&edma 24 0>, <&edma 25 0>;
dma-names = "tx", "rx";
interrupts = <64>;
reg = <0x0 0x1000>;

4
arch/arm/boot/dts/am5748.dtsi
View File

@ -25,6 +25,10 @@ &usb3_tm {
status = "disabled";
};
&usb4_tm {
status = "disabled";
};
&atl_tm {
status = "disabled";
};

28
arch/arm/boot/dts/armada-370.dtsi
View File

@ -60,16 +60,26 @@ pcie0: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 58>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
<0 0 0 2 &pcie0_intc 1>,
<0 0 0 3 &pcie0_intc 2>,
<0 0 0 4 &pcie0_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
pcie0_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie2: pcie@2,0 {
@ -78,16 +88,26 @@ pcie2: pcie@2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 62>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2_intc 0>,
<0 0 0 2 &pcie2_intc 1>,
<0 0 0 3 &pcie2_intc 2>,
<0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
pcie2_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
};

28
arch/arm/boot/dts/armada-375.dtsi
View File

@ -568,16 +568,26 @@ pcie0: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie0_intc 0>,
<0 0 0 2 &pcie0_intc 1>,
<0 0 0 3 &pcie0_intc 2>,
<0 0 0 4 &pcie0_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
pcie0_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie1: pcie@2,0 {
@ -586,16 +596,26 @@ pcie1: pcie@2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
<0 0 0 2 &pcie1_intc 1>,
<0 0 0 3 &pcie1_intc 2>,
<0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
pcie1_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
};

42
arch/arm/boot/dts/armada-380.dtsi
View File

@ -64,16 +64,26 @@ pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
<0 0 0 2 &pcie1_intc 1>,
<0 0 0 3 &pcie1_intc 2>,
<0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
status = "disabled";
pcie1_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
/* x1 port */
@ -83,16 +93,26 @@ pcie@2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2_intc 0>,
<0 0 0 2 &pcie2_intc 1>,
<0 0 0 3 &pcie2_intc 2>,
<0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
pcie2_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
/* x1 port */
@ -102,16 +122,26 @@ pcie@3,0 {
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3_intc 0>,
<0 0 0 2 &pcie3_intc 1>,
<0 0 0 3 &pcie3_intc 2>,
<0 0 0 4 &pcie3_intc 3>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 6>;
status = "disabled";
pcie3_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
};
};

32
arch/arm/boot/dts/armada-385-turris-omnia.dts
View File

@ -105,6 +105,33 @@ sfp: sfp {
*/
status = "disabled";
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "SPDIF";
simple-audio-card,format = "i2s";
simple-audio-card,cpu {
sound-dai = <&audio_controller 1>;
};
simple-audio-card,codec {
sound-dai = <&spdif_out>;
};
};
spdif_out: spdif-out {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
};
};
&audio_controller {
/* Pin header U16, GPIO51 in SPDIFO mode */
pinctrl-0 = <&spdif_pins>;
pinctrl-names = "default";
spdif-mode;
status = "okay";
};
&bm {
@ -166,6 +193,7 @@ &eth2 {
buffer-manager = <&bm>;
bm,pool-long = <2>;
bm,pool-short = <3>;
label = "wan";
};
&i2c0 {
@ -476,7 +504,7 @@ spi0cs0_pins: spi0cs0-pins {
marvell,function = "spi0";
};
spi0cs1_pins: spi0cs1-pins {
spi0cs2_pins: spi0cs2-pins {
marvell,pins = "mpp26";
marvell,function = "spi0";
};
@ -511,7 +539,7 @@ partition@100000 {
};
};
/* MISO, MOSI, SCLK and CS1 are routed to pin header CN11 */
/* MISO, MOSI, SCLK and CS2 are routed to pin header CN11 */
};
&uart0 {

69
arch/arm/boot/dts/armada-388-db.dts
View File

@ -36,6 +36,11 @@ internal-regs {
i2c@11000 {
status = "okay";
clock-frequency = <100000>;
audio_codec: audio-codec@4a {
#sound-dai-cells = <0>;
compatible = "cirrus,cs42l51";
reg = <0x4a>;
};
};
i2c@11100 {
@ -99,6 +104,12 @@ sdhci@d8000 {
no-1-8-v;
};
audio-controller@e8000 {
pinctrl-0 = <&i2s_pins>;
pinctrl-names = "default";
status = "disabled";
};
usb3@f0000 {
status = "okay";
};
@ -128,6 +139,64 @@ pcie@2,0 {
};
};
};
sound {
compatible = "simple-audio-card";
simple-audio-card,name = "Armada 385 DB Audio";
simple-audio-card,mclk-fs = <256>;
simple-audio-card,widgets =
"Headphone", "Out Jack",
"Line", "In Jack";
simple-audio-card,routing =
"Out Jack", "HPL",
"Out Jack", "HPR",
"AIN1L", "In Jack",
"AIN1R", "In Jack";
status = "disabled";
simple-audio-card,dai-link@0 {
format = "i2s";
cpu {
sound-dai = <&audio_controller 0>;
};
codec {
sound-dai = <&audio_codec>;
};
};
simple-audio-card,dai-link@1 {
format = "i2s";
cpu {
sound-dai = <&audio_controller 1>;
};
codec {
sound-dai = <&spdif_out>;
};
};
simple-audio-card,dai-link@2 {
format = "i2s";
cpu {
sound-dai = <&audio_controller 1>;
};
codec {
sound-dai = <&spdif_in>;
};
};
};
spdif_out: spdif-out {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dit";
};
spdif_in: spdif-in {
#sound-dai-cells = <0>;
compatible = "linux,spdif-dir";
};
};
&spi0 {

26
arch/arm/boot/dts/armada-38x.dtsi
View File

@ -289,6 +289,18 @@ sata3_pins: sata-pins-3 {
marvell,pins = "mpp44";
marvell,function = "sata3";
};
i2s_pins: i2s-pins {
marvell,pins = "mpp48", "mpp49",
"mpp50", "mpp51",
"mpp52", "mpp53";
marvell,function = "audio";
};
spdif_pins: spdif-pins {
marvell,pins = "mpp51";
marvell,function = "audio";
};
};
gpio0: gpio@18100 {
@ -298,6 +310,7 @@ gpio0: gpio@18100 {
reg-names = "gpio", "pwm";
ngpios = <32>;
gpio-controller;
gpio-ranges = <&pinctrl 0 0 32>;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
@ -316,6 +329,7 @@ gpio1: gpio@18140 {
reg-names = "gpio", "pwm";
ngpios = <28>;
gpio-controller;
gpio-ranges = <&pinctrl 0 32 28>;
#gpio-cells = <2>;
#pwm-cells = <2>;
interrupt-controller;
@ -618,6 +632,18 @@ sdhci: sdhci@d8000 {
status = "disabled";
};
audio_controller: audio-controller@e8000 {
#sound-dai-cells = <1>;
compatible = "marvell,armada-380-audio";
reg = <0xe8000 0x4000>, <0x18410 0xc>,
<0x18204 0x4>;
reg-names = "i2s_regs", "pll_regs", "soc_ctrl";
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&gateclk 0>;
clock-names = "internal";
status = "disabled";
};
usb3_0: usb3@f0000 {
compatible = "marvell,armada-380-xhci";
reg = <0xf0000 0x4000>,<0xf4000 0x4000>;

56
arch/arm/boot/dts/armada-39x.dtsi
View File

@ -438,16 +438,26 @@ pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
<0 0 0 2 &pcie1_intc 1>,
<0 0 0 3 &pcie1_intc 2>,
<0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 8>;
status = "disabled";
pcie1_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
/* x1 port */
@ -457,16 +467,26 @@ pcie@2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2_intc 0>,
<0 0 0 2 &pcie2_intc 1>,
<0 0 0 3 &pcie2_intc 2>,
<0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
pcie2_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
/* x1 port */
@ -476,16 +496,26 @@ pcie@3,0 {
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3_intc 0>,
<0 0 0 2 &pcie3_intc 1>,
<0 0 0 3 &pcie3_intc 2>,
<0 0 0 4 &pcie3_intc 3>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 6>;
status = "disabled";
pcie3_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
/*
@ -498,16 +528,26 @@ pcie@4,0 {
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &gic GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie4_intc 0>,
<0 0 0 2 &pcie4_intc 1>,
<0 0 0 3 &pcie4_intc 2>,
<0 0 0 4 &pcie4_intc 3>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 7>;
status = "disabled";
pcie4_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
};

14
arch/arm/boot/dts/armada-xp-98dx3236.dtsi
View File

@ -76,16 +76,26 @@ pcie1: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 58>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
<0 0 0 2 &pcie1_intc 1>,
<0 0 0 3 &pcie1_intc 2>,
<0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
pcie1_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
};

2
arch/arm/boot/dts/armada-xp-lenovo-ix4-300d.dts
View File

@ -164,7 +164,7 @@ scroll-button {
};
};
spi3 {
spi-3 {
compatible = "spi-gpio";
status = "okay";
gpio-sck = <&gpio0 25 GPIO_ACTIVE_LOW>;

70
arch/arm/boot/dts/armada-xp-mv78230.dtsi
View File

@ -83,16 +83,26 @@ pcie1: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 58>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
<0 0 0 2 &pcie1_intc 1>,
<0 0 0 3 &pcie1_intc 2>,
<0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
pcie1_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie2: pcie@2,0 {
@ -101,16 +111,26 @@ pcie2: pcie@2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 59>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2_intc 0>,
<0 0 0 2 &pcie2_intc 1>,
<0 0 0 3 &pcie2_intc 2>,
<0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
pcie2_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie3: pcie@3,0 {
@ -119,16 +139,26 @@ pcie3: pcie@3,0 {
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 60>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3_intc 0>,
<0 0 0 2 &pcie3_intc 1>,
<0 0 0 3 &pcie3_intc 2>,
<0 0 0 4 &pcie3_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
pcie3_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie4: pcie@4,0 {
@ -137,16 +167,26 @@ pcie4: pcie@4,0 {
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 61>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie4_intc 0>,
<0 0 0 2 &pcie4_intc 1>,
<0 0 0 3 &pcie4_intc 2>,
<0 0 0 4 &pcie4_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
pcie4_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie5: pcie@5,0 {
@ -155,16 +195,26 @@ pcie5: pcie@5,0 {
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 62>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie5_intc 0>,
<0 0 0 2 &pcie5_intc 1>,
<0 0 0 3 &pcie5_intc 2>,
<0 0 0 4 &pcie5_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
pcie5_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
};

126
arch/arm/boot/dts/armada-xp-mv78260.dtsi
View File

@ -98,16 +98,26 @@ pcie1: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 58>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
<0 0 0 2 &pcie1_intc 1>,
<0 0 0 3 &pcie1_intc 2>,
<0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
pcie1_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie2: pcie@2,0 {
@ -116,16 +126,26 @@ pcie2: pcie@2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 59>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2_intc 0>,
<0 0 0 2 &pcie2_intc 1>,
<0 0 0 3 &pcie2_intc 2>,
<0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
pcie2_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie3: pcie@3,0 {
@ -134,16 +154,26 @@ pcie3: pcie@3,0 {
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 60>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3_intc 0>,
<0 0 0 2 &pcie3_intc 1>,
<0 0 0 3 &pcie3_intc 2>,
<0 0 0 4 &pcie3_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
pcie3_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie4: pcie@4,0 {
@ -152,16 +182,26 @@ pcie4: pcie@4,0 {
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 61>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie4_intc 0>,
<0 0 0 2 &pcie4_intc 1>,
<0 0 0 3 &pcie4_intc 2>,
<0 0 0 4 &pcie4_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
pcie4_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie5: pcie@5,0 {
@ -170,16 +210,26 @@ pcie5: pcie@5,0 {
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 62>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie5_intc 0>,
<0 0 0 2 &pcie5_intc 1>,
<0 0 0 3 &pcie5_intc 2>,
<0 0 0 4 &pcie5_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
pcie5_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie6: pcie@6,0 {
@ -188,16 +238,26 @@ pcie6: pcie@6,0 {
reg = <0x3000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 63>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie6_intc 0>,
<0 0 0 2 &pcie6_intc 1>,
<0 0 0 3 &pcie6_intc 2>,
<0 0 0 4 &pcie6_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
status = "disabled";
pcie6_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie7: pcie@7,0 {
@ -206,16 +266,26 @@ pcie7: pcie@7,0 {
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 64>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie7_intc 0>,
<0 0 0 2 &pcie7_intc 1>,
<0 0 0 3 &pcie7_intc 2>,
<0 0 0 4 &pcie7_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
status = "disabled";
pcie7_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie8: pcie@8,0 {
@ -224,16 +294,26 @@ pcie8: pcie@8,0 {
reg = <0x4000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 65>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie8_intc 0>,
<0 0 0 2 &pcie8_intc 1>,
<0 0 0 3 &pcie8_intc 2>,
<0 0 0 4 &pcie8_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
status = "disabled";
pcie8_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie9: pcie@9,0 {
@ -242,16 +322,26 @@ pcie9: pcie@9,0 {
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 99>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie9_intc 0>,
<0 0 0 2 &pcie9_intc 1>,
<0 0 0 3 &pcie9_intc 2>,
<0 0 0 4 &pcie9_intc 3>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
pcie9_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
};

140
arch/arm/boot/dts/armada-xp-mv78460.dtsi
View File

@ -119,16 +119,26 @@ pcie1: pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 58>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
0x81000000 0 0 0x81000000 0x1 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 58>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie1_intc 0>,
<0 0 0 2 &pcie1_intc 1>,
<0 0 0 3 &pcie1_intc 2>,
<0 0 0 4 &pcie1_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 5>;
status = "disabled";
pcie1_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie2: pcie@2,0 {
@ -137,16 +147,26 @@ pcie2: pcie@2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 59>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
0x81000000 0 0 0x81000000 0x2 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 59>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie2_intc 0>,
<0 0 0 2 &pcie2_intc 1>,
<0 0 0 3 &pcie2_intc 2>,
<0 0 0 4 &pcie2_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 6>;
status = "disabled";
pcie2_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie3: pcie@3,0 {
@ -155,16 +175,26 @@ pcie3: pcie@3,0 {
reg = <0x1800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 60>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x3 0 1 0
0x81000000 0 0 0x81000000 0x3 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 60>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie3_intc 0>,
<0 0 0 2 &pcie3_intc 1>,
<0 0 0 3 &pcie3_intc 2>,
<0 0 0 4 &pcie3_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 7>;
status = "disabled";
pcie3_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie4: pcie@4,0 {
@ -173,16 +203,26 @@ pcie4: pcie@4,0 {
reg = <0x2000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 61>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x4 0 1 0
0x81000000 0 0 0x81000000 0x4 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 61>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie4_intc 0>,
<0 0 0 2 &pcie4_intc 1>,
<0 0 0 3 &pcie4_intc 2>,
<0 0 0 4 &pcie4_intc 3>;
marvell,pcie-port = <0>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 8>;
status = "disabled";
pcie4_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie5: pcie@5,0 {
@ -191,16 +231,26 @@ pcie5: pcie@5,0 {
reg = <0x2800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 62>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x5 0 1 0
0x81000000 0 0 0x81000000 0x5 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 62>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie5_intc 0>,
<0 0 0 2 &pcie5_intc 1>,
<0 0 0 3 &pcie5_intc 2>,
<0 0 0 4 &pcie5_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 9>;
status = "disabled";
pcie5_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie6: pcie@6,0 {
@ -209,16 +259,26 @@ pcie6: pcie@6,0 {
reg = <0x3000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 63>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x6 0 1 0
0x81000000 0 0 0x81000000 0x6 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 63>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie6_intc 0>,
<0 0 0 2 &pcie6_intc 1>,
<0 0 0 3 &pcie6_intc 2>,
<0 0 0 4 &pcie6_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <1>;
clocks = <&gateclk 10>;
status = "disabled";
pcie6_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie7: pcie@7,0 {
@ -227,16 +287,26 @@ pcie7: pcie@7,0 {
reg = <0x3800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 64>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x7 0 1 0
0x81000000 0 0 0x81000000 0x7 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 64>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie7_intc 0>,
<0 0 0 2 &pcie7_intc 1>,
<0 0 0 3 &pcie7_intc 2>,
<0 0 0 4 &pcie7_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <2>;
clocks = <&gateclk 11>;
status = "disabled";
pcie7_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie8: pcie@8,0 {
@ -245,16 +315,26 @@ pcie8: pcie@8,0 {
reg = <0x4000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 65>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x8 0 1 0
0x81000000 0 0 0x81000000 0x8 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 65>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie8_intc 0>,
<0 0 0 2 &pcie8_intc 1>,
<0 0 0 3 &pcie8_intc 2>,
<0 0 0 4 &pcie8_intc 3>;
marvell,pcie-port = <1>;
marvell,pcie-lane = <3>;
clocks = <&gateclk 12>;
status = "disabled";
pcie8_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie9: pcie@9,0 {
@ -263,16 +343,26 @@ pcie9: pcie@9,0 {
reg = <0x4800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 99>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0x9 0 1 0
0x81000000 0 0 0x81000000 0x9 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 99>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie9_intc 0>,
<0 0 0 2 &pcie9_intc 1>,
<0 0 0 3 &pcie9_intc 2>,
<0 0 0 4 &pcie9_intc 3>;
marvell,pcie-port = <2>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 26>;
status = "disabled";
pcie9_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
pcie10: pcie@a,0 {
@ -281,16 +371,26 @@ pcie10: pcie@a,0 {
reg = <0x5000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
interrupt-names = "intx";
interrupts-extended = <&mpic 103>;
#interrupt-cells = <1>;
ranges = <0x82000000 0 0 0x82000000 0xa 0 1 0
0x81000000 0 0 0x81000000 0xa 0 1 0>;
bus-range = <0x00 0xff>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &mpic 103>;
interrupt-map-mask = <0 0 0 7>;
interrupt-map = <0 0 0 1 &pcie10_intc 0>,
<0 0 0 2 &pcie10_intc 1>,
<0 0 0 3 &pcie10_intc 2>,
<0 0 0 4 &pcie10_intc 3>;
marvell,pcie-port = <3>;
marvell,pcie-lane = <0>;
clocks = <&gateclk 27>;
status = "disabled";
pcie10_intc: interrupt-controller {
interrupt-controller;
#interrupt-cells = <1>;
};
};
};

2
arch/arm/boot/dts/aspeed-ast2600-evb-a1.dts
View File

@ -5,7 +5,7 @@
/ {
model = "AST2600 A1 EVB";
compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600";
compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600-evb", "aspeed,ast2600";
/delete-node/regulator-vcc-sdhci0;
/delete-node/regulator-vcc-sdhci1;

25
arch/arm/boot/dts/aspeed-ast2600-evb.dts
View File

@ -8,7 +8,7 @@
/ {
model = "AST2600 EVB";
compatible = "aspeed,ast2600-evb-a1", "aspeed,ast2600";
compatible = "aspeed,ast2600-evb", "aspeed,ast2600";
aliases {
serial4 = &uart5;
@ -182,6 +182,7 @@ flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-rx-bus-width = <4>;
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-64.dtsi"
};
@ -196,6 +197,7 @@ flash@0 {
status = "okay";
m25p,fast-read;
label = "pnor";
spi-rx-bus-width = <4>;
spi-max-frequency = <100000000>;
};
};
@ -207,11 +209,6 @@ &uart5 {
&i2c0 {
status = "okay";
temp@2e {
compatible = "adi,adt7490";
reg = <0x2e>;
};
};
&i2c1 {
@ -240,10 +237,26 @@ &i2c6 {
&i2c7 {
status = "okay";
temp@2e {
compatible = "adi,adt7490";
reg = <0x2e>;
};
eeprom@50 {
compatible = "atmel,24c08";
reg = <0x50>;
pagesize = <16>;
};
};
&i2c8 {
status = "okay";
lm75@4d {
compatible = "national,lm75";
reg = <0x4d>;
};
};
&i2c9 {

319
arch/arm/boot/dts/aspeed-bmc-amd-daytonax.dts Normal file
View File

@ -0,0 +1,319 @@
// SPDX-License-Identifier: GPL-2.0
/dts-v1/;
#include "aspeed-g5.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>
/ {
model = "AMD DaytonaX BMC";
compatible = "amd,daytonax-bmc", "aspeed,ast2500";
memory@80000000 {
reg = <0x80000000 0x20000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
video_engine_memory: jpegbuffer {
size = <0x02000000>; /* 32M */
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
};
aliases {
serial0 = &uart1;
serial4 = &uart5;
};
chosen {
stdout-path = &uart5;
bootargs = "console=ttyS4,115200";
};
leds {
compatible = "gpio-leds";
led-fault {
gpios = <&gpio ASPEED_GPIO(A, 2) GPIO_ACTIVE_LOW>;
};
led-identify {
gpios = <&gpio ASPEED_GPIO(A, 3) GPIO_ACTIVE_LOW>;
};
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc 0>, <&adc 1>, <&adc 2>, <&adc 3>, <&adc 4>,
<&adc 5>, <&adc 6>, <&adc 7>, <&adc 8>, <&adc 9>,
<&adc 10>, <&adc 11>, <&adc 12>, <&adc 13>, <&adc 14>,
<&adc 15>;
};
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
#include "openbmc-flash-layout.dtsi"
};
};
&mac0 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii1_default &pinctrl_mdio1_default>;
};
&uart1 {
//Host Console
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_txd1_default
&pinctrl_rxd1_default
&pinctrl_nrts1_default
&pinctrl_ndtr1_default
&pinctrl_ndsr1_default
&pinctrl_ncts1_default
&pinctrl_ndcd1_default
&pinctrl_nri1_default>;
};
&uart5 {
//BMC Console
status = "okay";
};
&vuart {
status = "okay";
aspeed,lpc-io-reg = <0x3f8>;
aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
};
&adc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_default
&pinctrl_adc1_default
&pinctrl_adc2_default
&pinctrl_adc3_default
&pinctrl_adc4_default
&pinctrl_adc5_default
&pinctrl_adc6_default
&pinctrl_adc7_default
&pinctrl_adc8_default
&pinctrl_adc9_default
&pinctrl_adc10_default
&pinctrl_adc11_default
&pinctrl_adc12_default
&pinctrl_adc13_default
&pinctrl_adc14_default
&pinctrl_adc15_default>;
};
&gpio {
status = "okay";
gpio-line-names =
/*A0-A7*/ "","","led-fault","led-identify","","","","",
/*B0-B7*/ "","","","","","","","",
/*C0-C7*/ "id-button","","","","","","","",
/*D0-D7*/ "","","ASSERT_BMC_READY","","","","","",
/*E0-E7*/ "reset-button","reset-control","power-button","power-control","",
"power-good","power-ok","",
/*F0-F7*/ "","","","","","","BATTERY_DETECT","",
/*G0-G7*/ "","","","","","","","",
/*H0-H7*/ "","","","","","","","",
/*I0-I7*/ "","","","","","","","",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","","","","","","","",
/*N0-N7*/ "","","","","","","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "","","","","","","","",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","","","","","","",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "","","","","","","","",
/*W0-W7*/ "","","","","","","","",
/*X0-X7*/ "","","","","","","","",
/*Y0-Y7*/ "","","","","","","","",
/*Z0-Z7*/ "","","","","","","","",
/*AA0-AA7*/ "","","","","","","","",
/*AB0-AB7*/ "FM_BMC_READ_SPD_TEMP","","","","","","","",
/*AC0-AC7*/ "","","","","","","","";
};
&i2c0 {
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
};
&i2c5 {
status = "okay";
};
&i2c6 {
status = "okay";
};
&i2c7 {
status = "okay";
};
&i2c8 {
status = "okay";
};
&i2c10 {
status = "okay";
};
&i2c11 {
status = "okay";
};
&i2c12 {
status = "okay";
};
&kcs3 {
status = "okay";
aspeed,lpc-io-reg = <0xca2>;
};
&lpc_snoop {
status = "okay";
snoop-ports = <0x80>, <0x81>;
};
&lpc_ctrl {
status = "okay";
};
&pwm_tacho {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm0_default
&pinctrl_pwm1_default
&pinctrl_pwm2_default
&pinctrl_pwm3_default
&pinctrl_pwm4_default
&pinctrl_pwm5_default
&pinctrl_pwm6_default
&pinctrl_pwm7_default>;
fan@0 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x00>;
};
fan@1 {
reg = <0x00>;
aspeed,fan-tach-ch = /bits/ 8 <0x01>;
};
fan@2 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x02>;
};
fan@3 {
reg = <0x01>;
aspeed,fan-tach-ch = /bits/ 8 <0x03>;
};
fan@4 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x04>;
};
fan@5 {
reg = <0x02>;
aspeed,fan-tach-ch = /bits/ 8 <0x05>;
};
fan@6 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x06>;
};
fan@7 {
reg = <0x03>;
aspeed,fan-tach-ch = /bits/ 8 <0x07>;
};
fan@8 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x08>;
};
fan@9 {
reg = <0x04>;
aspeed,fan-tach-ch = /bits/ 8 <0x09>;
};
fan@10 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x0a>;
};
fan@11 {
reg = <0x05>;
aspeed,fan-tach-ch = /bits/ 8 <0x0b>;
};
fan@12 {
reg = <0x06>;
aspeed,fan-tach-ch = /bits/ 8 <0x0c>;
};
fan@13 {
reg = <0x06>;
aspeed,fan-tach-ch = /bits/ 8 <0x0d>;
};
fan@14 {
reg = <0x07>;
aspeed,fan-tach-ch = /bits/ 8 <0x0e>;
};
fan@15 {
reg = <0x07>;
aspeed,fan-tach-ch = /bits/ 8 <0x0f>;
};
};
&video {
status = "okay";
memory-region = <&video_engine_memory>;
};
&vhub {
status = "okay";
};

95
arch/arm/boot/dts/aspeed-bmc-ampere-mtjade.dts
View File

@ -97,101 +97,6 @@ identify {
};
};
gpio-keys {
compatible = "gpio-keys";
event-shutdown-ack {
label = "SHUTDOWN_ACK";
gpios = <&gpio ASPEED_GPIO(G, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(G, 2)>;
};
event-reboot-ack {
label = "REBOOT_ACK";
gpios = <&gpio ASPEED_GPIO(J, 3) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 3)>;
};
event-s0-overtemp {
label = "S0_OVERTEMP";
gpios = <&gpio ASPEED_GPIO(G, 3) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(G, 3)>;
};
event-s0-hightemp {
label = "S0_HIGHTEMP";
gpios = <&gpio ASPEED_GPIO(J, 0) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 0)>;
};
event-s0-cpu-fault {
label = "S0_CPU_FAULT";
gpios = <&gpio ASPEED_GPIO(J, 1) GPIO_ACTIVE_HIGH>;
linux,code = <ASPEED_GPIO(J, 1)>;
};
event-s0-scp-auth-fail {
label = "S0_SCP_AUTH_FAIL";
gpios = <&gpio ASPEED_GPIO(J, 2) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(J, 2)>;
};
event-s1-scp-auth-fail {
label = "S1_SCP_AUTH_FAIL";
gpios = <&gpio ASPEED_GPIO(Z, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(Z, 5)>;
};
event-s1-overtemp {
label = "S1_OVERTEMP";
gpios = <&gpio ASPEED_GPIO(Z, 6) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(Z, 6)>;
};
event-s1-hightemp {
label = "S1_HIGHTEMP";
gpios = <&gpio ASPEED_GPIO(AB, 0) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(AB, 0)>;
};
event-s1-cpu-fault {
label = "S1_CPU_FAULT";
gpios = <&gpio ASPEED_GPIO(Z, 1) GPIO_ACTIVE_HIGH>;
linux,code = <ASPEED_GPIO(Z, 1)>;
};
event-id {
label = "ID_BUTTON";
gpios = <&gpio ASPEED_GPIO(Q, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(Q, 5)>;
};
event-psu1-vin-good {
label = "PSU1_VIN_GOOD";
gpios = <&gpio ASPEED_GPIO(H, 4) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(H, 4)>;
};
event-psu2-vin-good {
label = "PSU2_VIN_GOOD";
gpios = <&gpio ASPEED_GPIO(H, 5) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(H, 5)>;
};
event-psu1-present {
label = "PSU1_PRESENT";
gpios = <&gpio ASPEED_GPIO(I, 0) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(I, 0)>;
};
event-psu2-present {
label = "PSU2_PRESENT";
gpios = <&gpio ASPEED_GPIO(I, 1) GPIO_ACTIVE_LOW>;
linux,code = <ASPEED_GPIO(I, 1)>;
};
};
gpioA0mux: mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;

546
arch/arm/boot/dts/aspeed-bmc-ampere-mtmitchell.dts Normal file
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@ -0,0 +1,546 @@
// SPDX-License-Identifier: GPL-2.0-only
// Copyright (c) 2022, Ampere Computing LLC
/dts-v1/;
#include "aspeed-g6.dtsi"
#include <dt-bindings/gpio/aspeed-gpio.h>
/ {
model = "Ampere Mt.Mitchell BMC";
compatible = "ampere,mtmitchell-bmc", "aspeed,ast2600";
chosen {
stdout-path = &uart5;
};
memory@80000000 {
device_type = "memory";
reg = <0x80000000 0x80000000>;
};
reserved-memory {
#address-cells = <1>;
#size-cells = <1>;
ranges;
gfx_memory: framebuffer {
size = <0x01000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
video_engine_memory: video {
size = <0x04000000>;
alignment = <0x01000000>;
compatible = "shared-dma-pool";
reusable;
};
vga_memory: region@bf000000 {
no-map;
compatible = "shared-dma-pool";
reg = <0xbf000000 0x01000000>; /* 16M */
};
};
voltage_mon_reg: voltage-mon-regulator {
compatible = "regulator-fixed";
regulator-name = "ltc2497_reg";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
gpioI5mux: mux-controller {
compatible = "gpio-mux";
#mux-control-cells = <0>;
mux-gpios = <&gpio0 ASPEED_GPIO(I, 5) GPIO_ACTIVE_HIGH>;
};
adc0mux: adc0mux {
compatible = "io-channel-mux";
io-channels = <&adc0 0>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc1mux: adc1mux {
compatible = "io-channel-mux";
io-channels = <&adc0 1>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc2mux: adc2mux {
compatible = "io-channel-mux";
io-channels = <&adc0 2>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc3mux: adc3mux {
compatible = "io-channel-mux";
io-channels = <&adc0 3>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc4mux: adc4mux {
compatible = "io-channel-mux";
io-channels = <&adc0 4>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc5mux: adc5mux {
compatible = "io-channel-mux";
io-channels = <&adc0 5>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc6mux: adc6mux {
compatible = "io-channel-mux";
io-channels = <&adc0 6>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc7mux: adc7mux {
compatible = "io-channel-mux";
io-channels = <&adc0 7>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc8mux: adc8mux {
compatible = "io-channel-mux";
io-channels = <&adc1 0>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc9mux: adc9mux {
compatible = "io-channel-mux";
io-channels = <&adc1 1>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc10mux: adc10mux {
compatible = "io-channel-mux";
io-channels = <&adc1 2>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc11mux: adc11mux {
compatible = "io-channel-mux";
io-channels = <&adc1 3>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc12mux: adc12mux {
compatible = "io-channel-mux";
io-channels = <&adc1 4>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc13mux: adc13mux {
compatible = "io-channel-mux";
io-channels = <&adc1 5>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc14mux: adc14mux {
compatible = "io-channel-mux";
io-channels = <&adc1 6>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
adc15mux: adc15mux {
compatible = "io-channel-mux";
io-channels = <&adc1 7>;
#io-channel-cells = <1>;
io-channel-names = "parent";
mux-controls = <&gpioI5mux>;
channels = "s0", "s1";
};
iio-hwmon {
compatible = "iio-hwmon";
io-channels = <&adc0mux 0>, <&adc0mux 1>,
<&adc1mux 0>, <&adc1mux 1>,
<&adc2mux 0>, <&adc2mux 1>,
<&adc3mux 0>, <&adc3mux 1>,
<&adc4mux 0>, <&adc4mux 1>,
<&adc5mux 0>, <&adc5mux 1>,
<&adc6mux 0>, <&adc6mux 1>,
<&adc7mux 0>, <&adc7mux 1>,
<&adc8mux 0>, <&adc8mux 1>,
<&adc9mux 0>, <&adc9mux 1>,
<&adc10mux 0>, <&adc10mux 1>,
<&adc11mux 0>, <&adc11mux 1>,
<&adc12mux 0>, <&adc12mux 1>,
<&adc13mux 0>, <&adc13mux 1>,
<&adc14mux 0>, <&adc14mux 1>,
<&adc15mux 0>, <&adc15mux 1>,
<&adc_i2c 0>, <&adc_i2c 1>,
<&adc_i2c 2>, <&adc_i2c 3>,
<&adc_i2c 4>, <&adc_i2c 5>,
<&adc_i2c 6>, <&adc_i2c 7>,
<&adc_i2c 8>, <&adc_i2c 9>,
<&adc_i2c 10>, <&adc_i2c 11>,
<&adc_i2c 12>, <&adc_i2c 13>,
<&adc_i2c 14>, <&adc_i2c 15>;
};
};
&mdio0 {
status = "okay";
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
};
};
&mac0 {
status = "okay";
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii1_default>;
};
&fmc {
status = "okay";
flash@0 {
status = "okay";
m25p,fast-read;
label = "bmc";
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-64.dtsi"
};
flash@1 {
status = "okay";
m25p,fast-read;
label = "alt-bmc";
spi-max-frequency = <50000000>;
#include "openbmc-flash-layout-64-alt.dtsi"
};
};
&spi1 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_spi1_default>;
flash@0 {
status = "okay";
m25p,fast-read;
label = "pnor";
spi-max-frequency = <20000000>;
};
};
&uart1 {
status = "okay";
};
&uart2 {
status = "okay";
};
&uart3 {
status = "okay";
};
&uart4 {
status = "okay";
};
&i2c0 {
status = "okay";
temperature-sensor@2e {
compatible = "adi,adt7490";
reg = <0x2e>;
};
};
&i2c1 {
status = "okay";
};
&i2c2 {
status = "okay";
psu@58 {
compatible = "pmbus";
reg = <0x58>;
};
psu@59 {
compatible = "pmbus";
reg = <0x59>;
};
};
&i2c3 {
status = "okay";
};
&i2c4 {
status = "okay";
adc_i2c: adc@16 {
compatible = "lltc,ltc2497";
reg = <0x16>;
vref-supply = <&voltage_mon_reg>;
#io-channel-cells = <1>;
};
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
i2c-mux@70 {
compatible = "nxp,pca9545";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c-mux-idle-disconnect;
i2c4_bus70_chn0: i2c@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0>;
outlet_temp1: temperature-sensor@48 {
compatible = "ti,tmp75";
reg = <0x48>;
};
psu1_inlet_temp2: temperature-sensor@49 {
compatible = "ti,tmp75";
reg = <0x49>;
};
};
i2c4_bus70_chn1: i2c@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x1>;
pcie_zone_temp1: temperature-sensor@48 {
compatible = "ti,tmp75";
reg = <0x48>;
};
psu0_inlet_temp2: temperature-sensor@49 {
compatible = "ti,tmp75";
reg = <0x49>;
};
};
i2c4_bus70_chn2: i2c@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x2>;
pcie_zone_temp2: temperature-sensor@48 {
compatible = "ti,tmp75";
reg = <0x48>;
};
outlet_temp2: temperature-sensor@49 {
compatible = "ti,tmp75";
reg = <0x49>;
};
};
i2c4_bus70_chn3: i2c@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0x3>;
mb_inlet_temp1: temperature-sensor@7c {
compatible = "microchip,emc1413";
reg = <0x7c>;
};
mb_inlet_temp2: temperature-sensor@4c {
compatible = "microchip,emc1413";
reg = <0x4c>;
};
};
};
};
&i2c5 {
status = "okay";
i2c-mux@70 {
compatible = "nxp,pca9548";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x70>;
i2c-mux-idle-disconnect;
};
};
&i2c6 {
status = "okay";
rtc@51 {
compatible = "nxp,pcf85063a";
reg = <0x51>;
};
};
&i2c7 {
status = "okay";
};
&i2c9 {
status = "okay";
};
&i2c11 {
status = "okay";
};
&i2c14 {
status = "okay";
eeprom@50 {
compatible = "atmel,24c64";
reg = <0x50>;
pagesize = <32>;
};
bmc_ast2600_cpu: temperature-sensor@35 {
compatible = "ti,tmp175";
reg = <0x35>;
};
};
&adc0 {
ref_voltage = <2500>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc0_default &pinctrl_adc1_default
&pinctrl_adc2_default &pinctrl_adc3_default
&pinctrl_adc4_default &pinctrl_adc5_default
&pinctrl_adc6_default &pinctrl_adc7_default>;
};
&adc1 {
ref_voltage = <2500>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_adc8_default &pinctrl_adc9_default
&pinctrl_adc10_default &pinctrl_adc11_default
&pinctrl_adc12_default &pinctrl_adc13_default
&pinctrl_adc14_default &pinctrl_adc15_default>;
};
&vhub {
status = "okay";
};
&video {
status = "okay";
memory-region = <&video_engine_memory>;
};
&gpio0 {
gpio-line-names =
/*A0-A7*/ "","","","","","i2c2-reset-n","i2c6-reset-n","i2c4-reset-n",
/*B0-B7*/ "","","","","host0-sysreset-n","host0-pmin-n","","",
/*C0-C7*/ "s0-vrd-fault-n","s1-vrd-fault-n","","",
"irq-n","","vrd-sel","spd-sel",
/*D0-D7*/ "presence-ps0","presence-ps1","hsc-12vmain-alt2-n","ext-high-temp-n",
"","bmc-ncsi-txen","","",
/*E0-E7*/ "","","clk50m-bmc-ncsi","","","","","",
/*F0-F7*/ "s0-pcp-oc-warn-n","s1-pcp-oc-warn-n","power-chassis-control",
"cpu-bios-recover","s0-heartbeat","hs-csout-prochot",
"s0-vr-hot-n","s1-vr-hot-n",
/*G0-G7*/ "","","hsc-12vmain-alt1-n","","","","","",
/*H0-H7*/ "","","wd-disable-n","power-chassis-good","","","","",
/*I0-I7*/ "","","","","","adc-sw","power-button","rtc-battery-voltage-read-enable",
/*J0-J7*/ "","","","","","","","",
/*K0-K7*/ "","","","","","","","",
/*L0-L7*/ "","","","","","","","",
/*M0-M7*/ "","s0-ddr-save","soc-spi-nor-access","presence-cpu0",
"s0-rtc-lock","","","",
/*N0-N7*/ "hpm-fw-recovery","hpm-stby-rst-n","jtag-sel-s0","led-sw-hb",
"jtag-dbgr-prsnt-n","s1-heartbeat","","",
/*O0-O7*/ "","","","","","","","",
/*P0-P7*/ "ps0-ac-loss-n","ps1-ac-loss-n","","",
"led-fault","cpld-user-mode","jtag-srst-n","led-bmc-hb",
/*Q0-Q7*/ "","","","","","","","",
/*R0-R7*/ "","","","","","","","",
/*S0-S7*/ "","","identify-button","led-identify",
"s1-ddr-save","spi-nor-access","sys-pgood","presence-cpu1",
/*T0-T7*/ "","","","","","","","",
/*U0-U7*/ "","","","","","","","",
/*V0-V7*/ "s0-hightemp-n","s0-fault-alert","s0-sys-auth-failure-n",
"host0-reboot-ack-n","host0-ready","host0-shd-req-n",
"host0-shd-ack-n","s0-overtemp-n",
/*W0-W7*/ "ocp-aux-pwren","ocp-main-pwren","ocp-pgood","",
"bmc-ok","bmc-ready","spi0-program-sel","spi0-backup-sel",
/*X0-X7*/ "i2c-backup-sel","s1-fault-alert","s1-fw-boot-ok",
"s1-hightemp-n","s0-spi-auth-fail-n","s1-sys-auth-failure-n",
"s1-overtemp-n","s1-spi-auth-fail-n",
/*Y0-Y7*/ "","","","","","","","host0-special-boot",
/*Z0-Z7*/ "reset-button","ps0-pgood","ps1-pgood","","","","","";
};
&gpio1 {
gpio-line-names =
/*18A0-18A7*/ "","","","","","","","",
/*18B0-18B7*/ "","","","","","","s0-soc-pgood","",
/*18C0-18C7*/ "uart1-mode0","uart1-mode1","uart2-mode0","uart2-mode1",
"uart3-mode0","uart3-mode1","uart4-mode0","uart4-mode1",
/*18D0-18D7*/ "","","","","","","","",
/*18E0-18E3*/ "","","","";
};

13
arch/arm/boot/dts/aspeed-bmc-facebook-bletchley.dts
View File

@ -7,6 +7,7 @@
#include <dt-bindings/usb/pd.h>
#include <dt-bindings/leds/leds-pca955x.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/i2c/i2c.h>
/ {
model = "Facebook Bletchley BMC";
@ -792,11 +793,6 @@ tmp421@4f {
reg = <0x4f>;
};
hdc1080@40 {
compatible = "ti,hdc1080";
reg = <0x40>;
};
front_leds: pca9552@67 {
compatible = "nxp,pca9552";
reg = <0x67>;
@ -857,6 +853,13 @@ &i2c13 {
multi-master;
aspeed,hw-timeout-ms = <1000>;
status = "okay";
//USB Debug Connector
ipmb13@10 {
compatible = "ipmb-dev";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
i2c-protocol;
};
};
&gpio0 {

18
arch/arm/boot/dts/aspeed-bmc-facebook-elbert.dts
View File

@ -183,3 +183,21 @@ imux31: i2c@7 {
&i2c11 {
status = "okay";
};
/*
* BMC's "mac3" controller is connected to BCM53134P's IMP_RGMII port
* directly (fixed link, no PHY in between).
* Note: BMC's "mdio0" controller is connected to BCM53134P's MDIO
* interface, and the MDIO channel will be enabled in dts later, when
* BCM53134 is added to "bcm53xx" DSA driver.
*/
&mac3 {
status = "okay";
phy-mode = "rgmii";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_rgmii4_default>;
fixed-link {
speed = <1000>;
full-duplex;
};
};

15
arch/arm/boot/dts/aspeed-bmc-facebook-yosemitev2.dts
View File

@ -207,11 +207,16 @@ tmp421@1f {
&i2c12 {
status = "okay";
//MEZZ_FRU
eeprom@51 {
compatible = "atmel,24c64";
reg = <0x51>;
pagesize = <32>;
};
&i2c13 {
status = "okay";
// Debug Card
multi-master;
ipmb13@10 {
compatible = "ipmb-dev";
reg = <(0x10 | I2C_OWN_SLAVE_ADDRESS)>;
i2c-protocol;
};
};

8
arch/arm/boot/dts/aspeed-g5.dtsi
View File

@ -262,6 +262,14 @@ rng: hwrng@1e6e2078 {
quality = <100>;
};
hace: crypto@1e6e3000 {
compatible = "aspeed,ast2500-hace";
reg = <0x1e6e3000 0x100>;
interrupts = <4>;
clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
resets = <&syscon ASPEED_RESET_HACE>;
};
gfx: display@1e6e6000 {
compatible = "aspeed,ast2500-gfx", "syscon";
reg = <0x1e6e6000 0x1000>;

64
arch/arm/boot/dts/aspeed-g6.dtsi
View File

@ -323,6 +323,14 @@ apb {
#size-cells = <1>;
ranges;
hace: crypto@1e6d0000 {
compatible = "aspeed,ast2600-hace";
reg = <0x1e6d0000 0x200>;
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_YCLK>;
resets = <&syscon ASPEED_RESET_HACE>;
};
syscon: syscon@1e6e2000 {
compatible = "aspeed,ast2600-scu", "syscon", "simple-mfd";
reg = <0x1e6e2000 0x1000>;
@ -756,6 +764,62 @@ uart4: serial@1e78f000 {
status = "disabled";
};
uart6: serial@1e790000 {
compatible = "ns16550a";
reg = <0x1e790000 0x20>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_UART6CLK>;
no-loopback-test;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart6_default>;
status = "disabled";
};
uart7: serial@1e790100 {
compatible = "ns16550a";
reg = <0x1e790100 0x20>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_UART7CLK>;
no-loopback-test;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart7_default>;
status = "disabled";
};
uart8: serial@1e790200 {
compatible = "ns16550a";
reg = <0x1e790200 0x20>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_UART8CLK>;
no-loopback-test;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart8_default>;
status = "disabled";
};
uart9: serial@1e790300 {
compatible = "ns16550a";
reg = <0x1e790300 0x20>;
reg-shift = <2>;
reg-io-width = <4>;
interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&syscon ASPEED_CLK_GATE_UART9CLK>;
no-loopback-test;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart9_default>;
status = "disabled";
};
i2c: bus@1e78a000 {
compatible = "simple-bus";
#address-cells = <1>;

81
arch/arm/boot/dts/at91-sam9x60ek.dts
View File

@ -34,48 +34,6 @@ main_xtal {
};
};
regulators: regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vdd_1v8: fixed-regulator-vdd_1v8@0 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
status = "okay";
};
vdd_1v15: fixed-regulator-vdd_1v15@1 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V15";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
status = "okay";
};
vdd1_3v3: fixed-regulator-vdd1_3v3@2 {
compatible = "regulator-fixed";
regulator-name = "VDD1_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
status = "okay";
};
vdd2_3v3: regulator-fixed-vdd2_3v3@3 {
compatible = "regulator-fixed";
regulator-name = "VDD2_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
status = "okay";
};
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@ -111,6 +69,42 @@ blue {
linux,default-trigger = "heartbeat";
};
};
vdd_1v8: fixed-regulator-vdd_1v8 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
status = "okay";
};
vdd_1v15: fixed-regulator-vdd_1v15 {
compatible = "regulator-fixed";
regulator-name = "VDD_1V15";
regulator-min-microvolt = <1150000>;
regulator-max-microvolt = <1150000>;
regulator-always-on;
status = "okay";
};
vdd1_3v3: fixed-regulator-vdd1_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDD1_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
status = "okay";
};
vdd2_3v3: regulator-fixed-vdd2_3v3 {
compatible = "regulator-fixed";
regulator-name = "VDD2_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
status = "okay";
};
};
&adc {
@ -264,8 +258,9 @@ &flx5 {
status = "okay";
uart1: serial@200 {
compatible = "microchip,sam9x60-usart", "atmel,at91sam9260-usart";
compatible = "microchip,sam9x60-dbgu", "microchip,sam9x60-usart", "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0x200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>;
dmas = <&dma0
(AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |

32
arch/arm/boot/dts/at91-sama5d2_icp.dts
View File

@ -3,7 +3,6 @@
* at91-sama5d2_icp.dts - Device Tree file for SAMA5D2-ICP board
*
* Copyright (C) 2019 Microchip Technology Inc. and its subsidiaries
* Copyright (C) 2022 Qortal Project
*
* Author: Radu Pirea & Razvan Stefanescu,
* Codrin Ciubotariu <codrin.ciubotariu@microchip.com>,
@ -25,8 +24,8 @@ aliases {
serial1 = &uart1; /* mikro BUS 3 */
serial3 = &uart3; /* mikro BUS 2 */
serial5 = &uart7; /* flx2 */
i2c0 = &i2c0;
i2c1 = &i2c1;
i2c0 = &i2c0;
i2c1 = &i2c1;
};
chosen {
@ -43,14 +42,13 @@ main_xtal {
};
};
gpio_keys {
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio_default>;
status = "okay";
sw4 {
button-1 {
label = "USER_PB1";
gpios = <&pioA PIN_PD0 GPIO_ACTIVE_LOW>;
linux,code = <KEY_PROG1>;
@ -307,8 +305,11 @@ regulator-state-mem {
};
&i2c0 { /* mikrobus i2c */
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_mikrobus_i2c>;
pinctrl-1 = <&pinctrl_i2c0_gpio>;
sda-gpios = <&pioA PIN_PD21 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
@ -316,8 +317,11 @@ &i2c0 { /* mikrobus i2c */
&i2c1 {
dmas = <0>, <0>;
pinctrl-names = "default";
pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1_default>;
pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&pioA PIN_PD19 GPIO_ACTIVE_HIGH>;
scl-gpios = <&pioA PIN_PD20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
i2c-digital-filter;
i2c-digital-filter-width-ns = <35>;
status = "okay";
@ -402,6 +406,12 @@ pinctrl_i2c1_default: i2c1_default {
bias-disable;
};
pinctrl_i2c1_gpio: i2c1_gpio {
pinmux = <PIN_PD19__GPIO>,
<PIN_PD20__GPIO>;
bias-disable;
};
pinctrl_key_gpio_default: key_gpio_default {
pinmux = <PIN_PD0__GPIO>;
bias-pull-up;
@ -463,6 +473,12 @@ pinctrl_mikrobus_i2c: mikrobus_i2c {
bias-disable;
};
pinctrl_i2c0_gpio: i2c0_gpio {
pinmux = <PIN_PD21__GPIO>,
<PIN_PD22__GPIO>;
bias-disable;
};
pinctrl_mikrobus1_an: mikrobus1_an {
pinmux = <PIN_PD26__GPIO>;
bias-disable;

307
arch/arm/boot/dts/at91-sama5d3_eds.dts Normal file
View File

@ -0,0 +1,307 @@
// SPDX-License-Identifier: GPL-2.0+ OR MIT
/*
* at91-sama5d3_eds.dts - Device Tree file for the SAMA5D3 Ethernet
* Development System board.
*
* Copyright (C) 2022 Microchip Technology Inc. and its subsidiaries
*
* Author: Jerry Ray <jerry.ray@microchip.com>
*/
/dts-v1/;
#include "sama5d36.dtsi"
/ {
model = "SAMA5D3 Ethernet Development System";
compatible = "microchip,sama5d3-eds", "atmel,sama5d36",
"atmel,sama5d3", "atmel,sama5";
chosen {
stdout-path = "serial0:115200n8";
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_key_gpio>;
button-3 {
label = "PB_USER";
gpios = <&pioE 29 GPIO_ACTIVE_LOW>;
linux,code = <0x104>;
wakeup-source;
};
};
memory@20000000 {
reg = <0x20000000 0x10000000>;
};
vcc_3v3_reg: regulator-1 {
compatible = "regulator-fixed";
regulator-name = "VCC_3V3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vcc_2v5_reg: regulator-2 {
compatible = "regulator-fixed";
regulator-name = "VCC_2V5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <2500000>;
regulator-always-on;
vin-supply = <&vcc_3v3_reg>;
};
vcc_1v8_reg: regulator-3 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V8";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
regulator-always-on;
vin-supply = <&vcc_3v3_reg>;
};
vcc_1v2_reg: regulator-4 {
compatible = "regulator-fixed";
regulator-name = "VCC_1V2";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <1200000>;
regulator-always-on;
};
vcc_mmc0_reg: regulator-5 {
compatible = "regulator-fixed";
regulator-name = "mmc0-card-supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vcc_mmc0_reg_gpio>;
gpio = <&pioE 2 GPIO_ACTIVE_LOW>;
};
};
&can0 {
status = "okay";
};
&dbgu {
status = "okay";
};
&ebi {
pinctrl-0 = <&pinctrl_ebi_nand_addr>;
pinctrl-names = "default";
status = "okay";
nand_controller: nand-controller {
status = "okay";
nand@3 {
reg = <0x3 0x0 0x2>;
atmel,rb = <0>;
nand-bus-width = <8>;
nand-ecc-mode = "hw";
nand-ecc-strength = <4>;
nand-ecc-step-size = <512>;
nand-on-flash-bbt;
label = "atmel_nand";
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;
at91bootstrap@0 {
label = "at91bootstrap";
reg = <0x0 0x40000>;
};
bootloader@40000 {
label = "bootloader";
reg = <0x40000 0xc0000>;
};
bootloaderenvred@100000 {
label = "bootloader env redundant";
reg = <0x100000 0x40000>;
};
bootloaderenv@140000 {
label = "bootloader env";
reg = <0x140000 0x40000>;
};
dtb@180000 {
label = "device tree";
reg = <0x180000 0x80000>;
};
kernel@200000 {
label = "kernel";
reg = <0x200000 0x600000>;
};
rootfs@800000 {
label = "rootfs";
reg = <0x800000 0x0f800000>;
};
};
};
};
};
&i2c0 {
pinctrl-0 = <&pinctrl_i2c0_pu>;
status = "okay";
};
&i2c1 {
status = "okay";
};
&i2c2 {
pinctrl-0 = <&pinctrl_i2c2_pu>;
status = "okay";
};
&main_xtal {
clock-frequency = <12000000>;
};
&mmc0 {
pinctrl-0 = <&pinctrl_mmc0_clk_cmd_dat0 &pinctrl_mmc0_dat1_3
&pinctrl_mmc0_dat4_7 &pinctrl_mmc0_cd>;
vmmc-supply = <&vcc_mmc0_reg>;
vqmmc-supply = <&vcc_3v3_reg>;
status = "okay";
slot@0 {
reg = <0>;
bus-width = <8>;
cd-gpios = <&pioE 0 GPIO_ACTIVE_LOW>;
};
};
&pinctrl {
board {
pinctrl_i2c0_pu: i2c0-pu {
atmel,pins =
<AT91_PIOA 30 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>;
};
pinctrl_i2c2_pu: i2c2-pu {
atmel,pins =
<AT91_PIOA 18 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>,
<AT91_PIOA 19 AT91_PERIPH_B AT91_PINCTRL_PULL_UP>;
};
pinctrl_key_gpio: key-gpio-0 {
atmel,pins =
<AT91_PIOE 29 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
pinctrl_mmc0_cd: mmc0-cd {
atmel,pins =
<AT91_PIOE 0 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
/* Reserved for reset signal to the RGMII connector. */
pinctrl_rgmii_rstn: rgmii-rstn {
atmel,pins =
<AT91_PIOD 18 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP_DEGLITCH>;
};
/* Reserved for an interrupt line from the RMII and RGMII connectors. */
pinctrl_spi_irqn: spi-irqn {
atmel,pins =
<AT91_PIOB 28 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
pinctrl_spi0_cs: spi0-cs-default {
atmel,pins =
<AT91_PIOD 13 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOD 16 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_spi1_cs: spi1-cs-default {
atmel,pins = <AT91_PIOC 25 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOC 28 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
pinctrl_usba_vbus: usba-vbus {
atmel,pins =
<AT91_PIOE 9 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
pinctrl_usb_default: usb-default {
atmel,pins =
<AT91_PIOE 3 AT91_PERIPH_GPIO AT91_PINCTRL_NONE
AT91_PIOE 4 AT91_PERIPH_GPIO AT91_PINCTRL_NONE>;
};
/* Reserved for VBUS fault interrupt. */
pinctrl_vbusfault_irqn: vbusfault-irqn {
atmel,pins =
<AT91_PIOE 5 AT91_PERIPH_GPIO AT91_PINCTRL_DEGLITCH>;
};
pinctrl_vcc_mmc0_reg_gpio: vcc-mmc0-reg-gpio-default {
atmel,pins = <AT91_PIOE 2 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>;
};
};
};
&slow_xtal {
clock-frequency = <32768>;
};
&spi0 {
pinctrl-names = "default", "cs";
pinctrl-1 = <&pinctrl_spi0_cs>;
cs-gpios = <&pioD 13 0>, <0>, <0>, <&pioD 16 0>;
status = "okay";
};
&spi1 {
pinctrl-names = "default", "cs";
pinctrl-1 = <&pinctrl_spi1_cs>;
cs-gpios = <&pioC 25 0>, <0>, <0>, <&pioC 28 0>;
status = "okay";
};
&tcb0 {
timer0: timer@0 {
compatible = "atmel,tcb-timer";
reg = <0>;
};
timer1: timer@1 {
compatible = "atmel,tcb-timer";
reg = <1>;
};
};
&usb0 { /* USB Device port with VBUS detection. */
atmel,vbus-gpio = <&pioE 9 GPIO_ACTIVE_HIGH>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usba_vbus>;
status = "okay";
};
&usb1 { /* 3-port Host. First port is unused. */
atmel,vbus-gpio = <0
&pioE 3 GPIO_ACTIVE_HIGH
&pioE 4 GPIO_ACTIVE_HIGH
>;
num-ports = <3>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_default>;
status = "okay";
};
&usb2 {
status = "okay";
};

8
arch/arm/boot/dts/at91rm9200.dtsi
View File

@ -13,6 +13,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/mfd/at91-usart.h>
/ {
#address-cells = <1>;
@ -596,6 +597,7 @@ pioD: gpio@fffffa00 {
dbgu: serial@fffff200 {
compatible = "atmel,at91rm9200-dbgu", "atmel,at91rm9200-usart";
reg = <0xfffff200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
@ -607,6 +609,7 @@ dbgu: serial@fffff200 {
usart0: serial@fffc0000 {
compatible = "atmel,at91rm9200-usart";
reg = <0xfffc0000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -620,6 +623,7 @@ usart0: serial@fffc0000 {
usart1: serial@fffc4000 {
compatible = "atmel,at91rm9200-usart";
reg = <0xfffc4000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -633,6 +637,7 @@ usart1: serial@fffc4000 {
usart2: serial@fffc8000 {
compatible = "atmel,at91rm9200-usart";
reg = <0xfffc8000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -646,6 +651,7 @@ usart2: serial@fffc8000 {
usart3: serial@fffcc000 {
compatible = "atmel,at91rm9200-usart";
reg = <0xfffcc000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -660,7 +666,7 @@ usb1: gadget@fffb0000 {
compatible = "atmel,at91rm9200-udc";
reg = <0xfffb0000 0x4000>;
interrupts = <11 IRQ_TYPE_LEVEL_HIGH 2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 2>;
clocks = <&pmc PMC_TYPE_PERIPHERAL 11>, <&pmc PMC_TYPE_SYSTEM 1>;
clock-names = "pclk", "hclk";
status = "disabled";
};

8
arch/arm/boot/dts/at91sam9260.dtsi
View File

@ -11,6 +11,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/mfd/at91-usart.h>
/ {
#address-cells = <1>;
@ -532,6 +533,7 @@ pioC: gpio@fffff800 {
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;
@ -543,6 +545,7 @@ dbgu: serial@fffff200 {
usart0: serial@fffb0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb0000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -556,6 +559,7 @@ usart0: serial@fffb0000 {
usart1: serial@fffb4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb4000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -569,6 +573,7 @@ usart1: serial@fffb4000 {
usart2: serial@fffb8000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb8000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -582,6 +587,7 @@ usart2: serial@fffb8000 {
usart3: serial@fffd0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd0000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <23 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -595,6 +601,7 @@ usart3: serial@fffd0000 {
uart0: serial@fffd4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd4000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <24 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -608,6 +615,7 @@ uart0: serial@fffd4000 {
uart1: serial@fffd8000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffd8000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;

5
arch/arm/boot/dts/at91sam9261.dtsi
View File

@ -9,6 +9,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/clock/at91.h>
#include <dt-bindings/mfd/at91-usart.h>
/ {
#address-cells = <1>;
@ -179,6 +180,7 @@ i2c0: i2c@fffac000 {
usart0: serial@fffb0000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb0000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <6 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -192,6 +194,7 @@ usart0: serial@fffb0000 {
usart1: serial@fffb4000 {
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb4000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -205,6 +208,7 @@ usart1: serial@fffb4000 {
usart2: serial@fffb8000{
compatible = "atmel,at91sam9260-usart";
reg = <0xfffb8000 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
atmel,use-dma-rx;
atmel,use-dma-tx;
@ -301,6 +305,7 @@ aic: interrupt-controller@fffff000 {
dbgu: serial@fffff200 {
compatible = "atmel,at91sam9260-dbgu", "atmel,at91sam9260-usart";
reg = <0xfffff200 0x200>;
atmel,usart-mode = <AT91_USART_MODE_SERIAL>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dbgu>;

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