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04c1822c0a
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45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Intel Cherry Trail Crystal Cove PMIC operation region driver
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*
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* Copyright (C) 2019 Hans de Goede <hdegoede@redhat.com>
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*/
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#include <linux/acpi.h>
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#include <linux/init.h>
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#include <linux/mfd/intel_soc_pmic.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include "intel_pmic.h"
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/*
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* We have no docs for the CHT Crystal Cove PMIC. The Asus Zenfone-2 kernel
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* code has 2 Crystal Cove regulator drivers, one calls the PMIC a "Crystal
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* Cove Plus" PMIC and talks about Cherry Trail, so presumably that one
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* could be used to get register info for the regulators if we need to
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* implement regulator support in the future.
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*
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* For now the sole purpose of this driver is to make
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* intel_soc_pmic_exec_mipi_pmic_seq_element work on devices with a
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* CHT Crystal Cove PMIC.
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*/
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static struct intel_pmic_opregion_data intel_chtcrc_pmic_opregion_data = {
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.pmic_i2c_address = 0x6e,
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};
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static int intel_chtcrc_pmic_opregion_probe(struct platform_device *pdev)
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{
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struct intel_soc_pmic *pmic = dev_get_drvdata(pdev->dev.parent);
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return intel_pmic_install_opregion_handler(&pdev->dev,
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ACPI_HANDLE(pdev->dev.parent), pmic->regmap,
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&intel_chtcrc_pmic_opregion_data);
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}
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static struct platform_driver intel_chtcrc_pmic_opregion_driver = {
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.probe = intel_chtcrc_pmic_opregion_probe,
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.driver = {
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.name = "cht_crystal_cove_pmic",
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},
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};
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builtin_platform_driver(intel_chtcrc_pmic_opregion_driver);
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