forked from Qortal/Brooklyn
a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
41 lines
1.2 KiB
YAML
41 lines
1.2 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/soc/microchip/microchip,mpfs-sys-controller.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Microchip PolarFire SoC (MPFS) MSS (microprocessor subsystem) system controller
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maintainers:
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- Conor Dooley <conor.dooley@microchip.com>
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description: |
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PolarFire SoC devices include a microcontroller acting as the system controller,
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which provides "services" to the main processor and to the FPGA fabric. These
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services include hardware rng, reprogramming of the FPGA and verfification of the
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eNVM contents etc. More information on these services can be found online, at
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https://onlinedocs.microchip.com/pr/GUID-1409CF11-8EF9-4C24-A94E-70979A688632-en-US-1/index.html
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Communication with the system controller is done via a mailbox, of which the client
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portion is documented here.
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properties:
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mboxes:
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maxItems: 1
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compatible:
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const: microchip,mpfs-sys-controller
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required:
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- compatible
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- mboxes
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additionalProperties: false
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examples:
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- |
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syscontroller {
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compatible = "microchip,mpfs-sys-controller";
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mboxes = <&mbox 0>;
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};
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