forked from Qortal/Brooklyn
a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
91 lines
2.0 KiB
YAML
91 lines
2.0 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/ufs/ti,j721e-ufs.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: TI J721e UFS Host Controller Glue Driver
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maintainers:
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- Vignesh Raghavendra <vigneshr@ti.com>
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properties:
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compatible:
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items:
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- const: ti,j721e-ufs
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reg:
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maxItems: 1
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description: address of TI UFS glue registers
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clocks:
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maxItems: 1
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description: phandle to the M-PHY clock
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power-domains:
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maxItems: 1
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assigned-clocks:
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maxItems: 1
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assigned-clock-parents:
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maxItems: 1
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"#address-cells":
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const: 2
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"#size-cells":
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const: 2
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ranges: true
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required:
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- compatible
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- reg
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- clocks
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- power-domains
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patternProperties:
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"^ufs@[0-9a-f]+$":
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$ref: cdns,ufshc.yaml
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description: |
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Cadence UFS controller node must be the child node.
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unevaluatedProperties: false
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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ufs-wrapper@4e80000 {
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compatible = "ti,j721e-ufs";
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reg = <0x0 0x4e80000 0x0 0x100>;
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power-domains = <&k3_pds 277>;
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clocks = <&k3_clks 277 1>;
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assigned-clocks = <&k3_clks 277 1>;
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assigned-clock-parents = <&k3_clks 277 4>;
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ranges = <0x0 0x0 0x0 0x4e80000 0x0 0x14000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ufs@4000 {
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compatible = "cdns,ufshc-m31-16nm", "jedec,ufs-2.0";
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reg = <0x0 0x4000 0x0 0x10000>;
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interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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freq-table-hz = <19200000 19200000>;
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power-domains = <&k3_pds 277>;
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clocks = <&k3_clks 277 1>;
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assigned-clocks = <&k3_clks 277 1>;
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assigned-clock-parents = <&k3_clks 277 4>;
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clock-names = "core_clk";
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};
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};
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};
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