forked from Qortal/Brooklyn
131 lines
4.3 KiB
C
131 lines
4.3 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DCN20_DCCG_H__
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#define __DCN20_DCCG_H__
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#include "dccg.h"
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#define DCCG_COMMON_REG_LIST_DCN_BASE() \
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SR(DPPCLK_DTO_CTRL),\
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DCCG_SRII(DTO_PARAM, DPPCLK, 0),\
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DCCG_SRII(DTO_PARAM, DPPCLK, 1),\
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DCCG_SRII(DTO_PARAM, DPPCLK, 2),\
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DCCG_SRII(DTO_PARAM, DPPCLK, 3),\
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SR(REFCLK_CNTL)
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#define DCCG_REG_LIST_DCN2() \
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DCCG_COMMON_REG_LIST_DCN_BASE(),\
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DCCG_SRII(DTO_PARAM, DPPCLK, 4),\
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DCCG_SRII(DTO_PARAM, DPPCLK, 5)
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#define DCCG_SF(reg_name, field_name, post_fix)\
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.field_name = reg_name ## __ ## field_name ## post_fix
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#define DCCG_SFI(reg_name, field_name, field_prefix, inst, post_fix)\
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.field_prefix ## _ ## field_name[inst] = reg_name ## __ ## field_prefix ## inst ## _ ## field_name ## post_fix
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#define DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh) \
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DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 0, mask_sh),\
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DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
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DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 1, mask_sh),\
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DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 1, mask_sh),\
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DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 2, mask_sh),\
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DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 2, mask_sh),\
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DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 3, mask_sh),\
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DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 3, mask_sh),\
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DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_PHASE, mask_sh),\
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DCCG_SF(DPPCLK0_DTO_PARAM, DPPCLK0_DTO_MODULO, mask_sh),\
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DCCG_SF(REFCLK_CNTL, REFCLK_CLOCK_EN, mask_sh),\
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DCCG_SF(REFCLK_CNTL, REFCLK_SRC_SEL, mask_sh)
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#define DCCG_MASK_SH_LIST_DCN2(mask_sh) \
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DCCG_COMMON_MASK_SH_LIST_DCN_COMMON_BASE(mask_sh),\
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DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 4, mask_sh),\
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DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 4, mask_sh),\
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DCCG_SFI(DPPCLK_DTO_CTRL, DTO_ENABLE, DPPCLK, 5, mask_sh),\
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DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 5, mask_sh)
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#define DCCG_REG_FIELD_LIST(type) \
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type DPPCLK0_DTO_PHASE;\
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type DPPCLK0_DTO_MODULO;\
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type DPPCLK_DTO_ENABLE[6];\
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type DPPCLK_DTO_DB_EN[6];\
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type REFCLK_CLOCK_EN;\
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type REFCLK_SRC_SEL;
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#define DCCG3_REG_FIELD_LIST(type) \
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type PHYASYMCLK_FORCE_EN;\
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type PHYASYMCLK_FORCE_SRC_SEL;\
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type PHYBSYMCLK_FORCE_EN;\
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type PHYBSYMCLK_FORCE_SRC_SEL;\
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type PHYCSYMCLK_FORCE_EN;\
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type PHYCSYMCLK_FORCE_SRC_SEL;
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struct dccg_shift {
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DCCG_REG_FIELD_LIST(uint8_t)
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DCCG3_REG_FIELD_LIST(uint8_t)
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};
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struct dccg_mask {
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DCCG_REG_FIELD_LIST(uint32_t)
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DCCG3_REG_FIELD_LIST(uint32_t)
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};
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struct dccg_registers {
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uint32_t DPPCLK_DTO_CTRL;
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uint32_t DPPCLK_DTO_PARAM[6];
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uint32_t REFCLK_CNTL;
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uint32_t HDMICHARCLK_CLOCK_CNTL[6];
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uint32_t PHYASYMCLK_CLOCK_CNTL;
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uint32_t PHYBSYMCLK_CLOCK_CNTL;
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uint32_t PHYCSYMCLK_CLOCK_CNTL;
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};
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struct dcn_dccg {
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struct dccg base;
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const struct dccg_registers *regs;
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const struct dccg_shift *dccg_shift;
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const struct dccg_mask *dccg_mask;
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};
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void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
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void dccg2_get_dccg_ref_freq(struct dccg *dccg,
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unsigned int xtalin_freq_inKhz,
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unsigned int *dccg_ref_freq_inKhz);
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void dccg2_init(struct dccg *dccg);
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struct dccg *dccg2_create(
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struct dc_context *ctx,
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const struct dccg_registers *regs,
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const struct dccg_shift *dccg_shift,
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const struct dccg_mask *dccg_mask);
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void dcn_dccg_destroy(struct dccg **dccg);
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#endif //__DCN20_DCCG_H__
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