forked from Qortal/Brooklyn
303 lines
9.4 KiB
Verilog
303 lines
9.4 KiB
Verilog
`include "settings.h"
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module ARM
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(
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input clk,
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input rst,
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input enableForwarding
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);
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wire [`WORD_WIDTH-1:0] IF_stage_pc_out;
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wire [`WORD_WIDTH-1:0] IF_stage_instruction_out;
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wire [`WORD_WIDTH-1:0] branch_address;
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wire EXE_stage_B_out;
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wire hazard_detected;
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IF_Stage IF_Stage_Inst (
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.clk(clk),
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.rst(rst),
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.freeze(hazard_detected),
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.branch_taken(EXE_stage_B_out),
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.branch_addr(branch_address),
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.pc(IF_stage_pc_out),
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.instruction(IF_stage_instruction_out)
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);
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wire [`WORD_WIDTH-1:0] IF_reg_pc_out;
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wire [`WORD_WIDTH-1:0] IF_reg_instruction_out;
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IF_Reg IF_Reg_Inst (
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.clk(clk),
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.rst(rst),
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.freeze(hazard_detected),
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.flush(EXE_stage_B_out),
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.pc_in(IF_stage_pc_out),
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.instruction_in(IF_stage_instruction_out),
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.pc(IF_reg_pc_out),
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.instruction(IF_reg_instruction_out)
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);
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wire [`WORD_WIDTH-1:0] ID_stage_pc_out;
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wire [`WORD_WIDTH-1:0] ID_stage_instruction_out;
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wire [`REG_FILE_DEPTH-1:0] ID_stage_reg_file_dst;
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wire [`REG_FILE_DEPTH-1:0] ID_stage_reg_file_src1, ID_stage_reg_file_src2;
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wire [`WORD_WIDTH-1:0] ID_stage_val_Rn, ID_stage_val_Rm;
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wire [`SIGNED_IMM_WIDTH-1:0] ID_stage_signed_immediate;
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wire [`SHIFTER_OPERAND_WIDTH-1:0] ID_stage_shifter_operand;
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wire [3:0] ID_stage_EX_command_out;
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wire [3:0] status;
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wire ID_stage_mem_read_out, ID_stage_mem_write_out,
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ID_stage_WB_en_out,
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ID_stage_Imm_out,
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ID_stage_B_out,
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ID_stage_SR_update_out;
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wire [`REG_FILE_DEPTH-1:0] WB_Stage_dst_out;
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wire [`WORD_WIDTH-1:0] WB_Value;
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wire WB_Stage_WB_en_out;
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wire has_src2;
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ID_Stage ID_Stage_Inst(
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.clk(clk),
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.rst(rst),
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.freeze(hazard_detected),
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.pc_in(IF_reg_pc_out),
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.instruction_in(IF_reg_instruction_out),
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.reg_file_wb_address(WB_Stage_dst_out),
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.reg_file_wb_data(WB_Value),
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.reg_file_enable(WB_Stage_WB_en_out),
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.reg_file_src1(ID_stage_reg_file_src1),
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.reg_file_src2(ID_stage_reg_file_src2),
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.status_register(status),
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.pc(ID_stage_pc_out),
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.instruction(ID_stage_instruction_out),
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.reg_file_dst(ID_stage_reg_file_dst),
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.val_Rn(ID_stage_val_Rn), .val_Rm(ID_stage_val_Rm),
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.signed_immediate(ID_stage_signed_immediate),
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.shifter_operand(ID_stage_shifter_operand),
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.EX_command_out(ID_stage_EX_command_out),
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.mem_read_out(ID_stage_mem_read_out), .mem_write_out(ID_stage_mem_write_out),
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.WB_en_out(ID_stage_WB_en_out),
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.Imm_out(ID_stage_Imm_out),
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.B_out(ID_stage_B_out),
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.SR_update_out(ID_stage_SR_update_out),
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.has_src2(has_src2),
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.has_src1(has_src1)
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);
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wire [`WORD_WIDTH-1:0] ID_reg_pc_out;
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wire [`WORD_WIDTH-1:0] ID_reg_instruction_out;
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wire [`REG_FILE_DEPTH-1:0] ID_reg_reg_file_dst_out;
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wire [`WORD_WIDTH-1:0] ID_reg_val_Rn_out, ID_reg_val_Rm_out;
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wire [`SIGNED_IMM_WIDTH-1:0] ID_reg_signed_immediate_out;
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wire [`SHIFTER_OPERAND_WIDTH-1:0] ID_reg_shifter_operand_out;
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wire [3:0] ID_reg_SR_out, ID_reg_EX_command_out;
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wire ID_reg_mem_read_out, ID_reg_mem_write_out,
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ID_reg_WB_en_out,
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ID_reg_Imm_out,
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ID_reg_B_out,
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ID_reg_SR_update_out;
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wire [`REG_FILE_DEPTH-1:0] ID_reg_reg_file_src1, ID_reg_reg_file_src2;
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ID_Reg ID_Reg_Inst(
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.clk(clk),
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.rst(rst),
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.flush(EXE_stage_B_out),
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.pc_in(ID_stage_pc_out),
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.instruction_in(ID_stage_instruction_out),
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.reg_file_dst_in(ID_stage_reg_file_dst),
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.val_Rn_in(ID_stage_val_Rn), .val_Rm_in(ID_stage_val_Rm),
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.signed_immediate_in(ID_stage_signed_immediate),
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.shifter_operand_in(ID_stage_shifter_operand),
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.EX_command_in(ID_stage_EX_command_out),
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.mem_read_in(ID_stage_mem_read_out), .mem_write_in(ID_stage_mem_write_out),
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.WB_en_in(ID_stage_WB_en_out),
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.Imm_in(ID_stage_Imm_out),
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.B_in(ID_stage_B_out),
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.SR_update_in(ID_stage_SR_update_out),
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.reg_file_src1_in(ID_stage_reg_file_src1),
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.reg_file_src2_in(ID_stage_reg_file_src2),
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.pc(ID_reg_pc_out),
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.instruction(ID_reg_instruction_out),
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.reg_file_dst_out(ID_reg_reg_file_dst_out),
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.val_Rn_out(ID_reg_val_Rn_out), .val_Rm_out(ID_reg_val_Rm_out),
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.signed_immediate_out(ID_reg_signed_immediate_out),
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.shifter_operand_out(ID_reg_shifter_operand_out),
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.EX_command_out(ID_reg_EX_command_out),
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.mem_read_out(ID_reg_mem_read_out), .mem_write_out(ID_reg_mem_write_out),
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.WB_en_out(ID_reg_WB_en_out),
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.Imm_out(ID_reg_Imm_out),
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.B_out(ID_reg_B_out),
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.SR_update_out(ID_reg_SR_update_out),
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.status_register_in(status),
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.status_register_out(ID_reg_SR_out),
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.reg_file_src1_out(ID_reg_reg_file_src1),
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.reg_file_src2_out(ID_reg_reg_file_src2)
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);
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wire [`WORD_WIDTH-1:0] EXE_stage_pc_out;
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wire [`WORD_WIDTH-1:0] EXE_stage_instruction_out;
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wire [`REG_FILE_DEPTH-1:0] EXE_stage_reg_file_dst_out;
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wire [`WORD_WIDTH-1:0] EXE_stage_val_Rm_out;
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wire [3:0] EXE_stage_SR_out;
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wire [`WORD_WIDTH-1:0] ALU_res;
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wire EXE_stage_mem_read_out, EXE_stage_mem_write_out,
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EXE_stage_WB_en_out;
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wire [1:0] EXE_sel_src1, EXE_sel_src2;
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wire [`WORD_WIDTH-1:0] Mem_Stage_ALU_res_out;
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EXE_Stage EXE_Stage_Inst(
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.clk(clk),
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.rst(rst),
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.pc_in(ID_reg_pc_out),
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.instruction_in(ID_reg_instruction_out),
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.MEM_stage_val(Mem_Stage_ALU_res_out),
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.WB_stage_val(WB_Value),
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.signed_immediate(ID_reg_signed_immediate_out),
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.EX_command(ID_reg_EX_command_out),
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.SR_in(ID_reg_SR_out),
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.shifter_operand(ID_reg_shifter_operand_out),
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.dst_in(ID_reg_reg_file_dst_out),
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.mem_read_in(ID_reg_mem_read_out), .mem_write_in(ID_reg_mem_write_out),
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.imm(ID_reg_Imm_out),
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.WB_en_in(ID_reg_WB_en_out),
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.B_in(ID_reg_B_out),
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.val_Rn_in(ID_reg_val_Rn_out), .val_Rm_in(ID_reg_val_Rm_out),
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.sel_src1(EXE_sel_src1),
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.sel_src2(EXE_sel_src2),
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.dst_out(EXE_stage_reg_file_dst_out),
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.SR_out(EXE_stage_SR_out),
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.ALU_res(ALU_res),
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.val_Rm_out(EXE_stage_val_Rm_out),
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.branch_address(branch_address),
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.mem_read_out(EXE_stage_mem_read_out), .mem_write_out(EXE_stage_mem_write_out),
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.WB_en_out(EXE_stage_WB_en_out),
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.B_out(EXE_stage_B_out),
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.pc(EXE_stage_pc_out),
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.instruction(EXE_stage_instruction_out)
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);
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wire [`WORD_WIDTH-1:0] EXE_reg_pc_out;
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wire [`WORD_WIDTH-1:0] EXE_reg_instruction_out;
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wire [`REG_FILE_DEPTH-1:0] EXE_reg_dst_out;
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wire [`WORD_WIDTH-1:0] EXE_reg_ALU_res_out;
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wire [`WORD_WIDTH-1:0] EXE_reg_val_Rm_out;
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wire EXE_reg_mem_read_out, EXE_reg_mem_write_out, EXE_reg_WB_en_out;
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EXE_Reg EXE_Reg_Inst(
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.clk(clk),
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.rst(rst),
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.pc_in(EXE_stage_pc_out),
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.instruction_in(EXE_stage_instruction_out),
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.dst_in(EXE_stage_reg_file_dst_out),
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.mem_read_in(EXE_stage_mem_read_out), .mem_write_in(EXE_stage_mem_write_out),
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.WB_en_in(EXE_stage_WB_en_out),
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.val_Rm_in(EXE_stage_val_Rm_out),
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.ALU_res_in(ALU_res),
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.dst_out(EXE_reg_dst_out),
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.ALU_res_out(EXE_reg_ALU_res_out),
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.val_Rm_out(EXE_reg_val_Rm_out),
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.mem_read_out(EXE_reg_mem_read_out), .mem_write_out(EXE_reg_mem_write_out),
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.WB_en_out(EXE_reg_WB_en_out),
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.pc(EXE_reg_pc_out),
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.instruction(EXE_reg_instruction_out)
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);
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wire [`REG_FILE_DEPTH-1:0] Mem_Stage_dst_out;
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wire [`WORD_WIDTH-1:0] Mem_Stage_mem_out;
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wire Mem_Stage_read_out, Mem_Stage_WB_en_out;
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Mem_Stage Mem_Stage_Inst(
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.clk(clk),
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.rst(rst),
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.dst(EXE_reg_dst_out),
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.ALU_res(EXE_reg_ALU_res_out),
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.val_Rm(EXE_reg_val_Rm_out),
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.mem_read(EXE_reg_mem_read_out),
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.mem_write(EXE_reg_mem_write_out),
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.WB_en(EXE_reg_WB_en_out),
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.dst_out(Mem_Stage_dst_out),
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.ALU_res_out(Mem_Stage_ALU_res_out),
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.mem_out(Mem_Stage_mem_out),
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.mem_read_out(Mem_Stage_read_out),
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.WB_en_out(Mem_Stage_WB_en_out)
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);
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wire [`REG_FILE_DEPTH-1:0] Mem_Reg_dst_out;
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wire [`WORD_WIDTH-1:0] Mem_Reg_ALU_res_out;
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wire [`WORD_WIDTH-1:0] Mem_Reg_mem_out;
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wire Mem_Reg_read_out, Mem_Reg_WB_en_out;
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MEM_Reg Mem_Reg_Inst(
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.clk(clk),
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.rst(rst),
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.dst(Mem_Stage_dst_out),
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.ALU_res(Mem_Stage_ALU_res_out),
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.mem(Mem_Stage_mem_out),
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.mem_read(Mem_Stage_read_out),
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.WB_en(Mem_Stage_WB_en_out),
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.dst_out(Mem_Reg_dst_out),
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.ALU_res_out(Mem_Reg_ALU_res_out),
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.mem_out(Mem_Reg_mem_out),
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.mem_read_out(Mem_Reg_read_out),
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.WB_en_out(Mem_Reg_WB_en_out)
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);
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WB_Stage WB_Stage_Inst(
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.clk(clk),
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.rst(rst),
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.dst(Mem_Reg_dst_out),
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.ALU_res(Mem_Reg_ALU_res_out),
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.mem(Mem_Reg_mem_out),
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.mem_read(Mem_Reg_read_out),
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.WB_en(Mem_Reg_WB_en_out),
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.WB_Dest(WB_Stage_dst_out),
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.WB_en_out(WB_Stage_WB_en_out),
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.WB_Value(WB_Value)
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);
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Status_Reg Status_Reg_Inst(
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.clk(clk),
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.rst(rst),
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.load(ID_reg_SR_update_out),
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.status_in(EXE_stage_SR_out),
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.status(status)
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);
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wire EXE_WB_en = ID_reg_WB_en_out;
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wire MEM_WB_en = EXE_reg_WB_en_out;
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wire[`REG_FILE_DEPTH-1:0] EXE_dest = ID_reg_reg_file_dst_out;
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wire[`REG_FILE_DEPTH-1:0] MEM_dest = EXE_reg_dst_out;
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Hazard_Detection_Unit Hazard_Detection_Unit_Inst(
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.enableForwarding(enableForwarding),
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.src1(ID_stage_reg_file_src1),
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.src2(ID_stage_reg_file_src2),
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.EXE_dest(EXE_dest),
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.MEM_dest(MEM_dest),
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.EXE_WB_en(EXE_WB_en),
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.MEM_WB_en(MEM_WB_en),
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.EXE_memread_en(EXE_stage_mem_read_out),
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.has_src1(has_src1),
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.has_src2(has_src2),
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.hazard_detected(hazard_detected)
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);
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Forwarding_Unit Forwarding_Unit_Inst(
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.enable(enableForwarding),
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.src1(ID_reg_reg_file_src1),
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.src2(ID_reg_reg_file_src2),
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.MEM_dest(MEM_dest),
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.WB_dest(WB_Stage_dst_out),
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.MEM_WB_en(MEM_WB_en),
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.WB_WB_en(WB_Stage_WB_en_out),
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.sel_src1(EXE_sel_src1),
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.sel_src2(EXE_sel_src2)
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);
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endmodule
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