forked from Qortal/Brooklyn
247 lines
9.6 KiB
Systemverilog
247 lines
9.6 KiB
Systemverilog
//-----------------------------------------------------------------------------
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// The confidential and proprietary information contained in this file may
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// only be used by a person authorised under and to the extent permitted
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// by a subsisting licensing agreement from ARM Limited or its affiliates.
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//
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// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
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// ALL RIGHTS RESERVED
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//
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// This entire notice must be reproduced on all copies of this file
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// and copies of this file may only be made by a person if such person is
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// permitted to do so under the terms of a subsisting license agreement
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// from ARM Limited or its affiliates.
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//
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// Release Information : HERCULESAE-MP106-r0p1-00eac0
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//
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//-----------------------------------------------------------------------------
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// SystemVerilog (IEEE Std 1800-2012)
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//-----------------------------------------------------------------------------
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`include "herculesae_header.sv"
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module herculesae_vx_aes
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(
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input wire clk,
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input wire reset,
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input wire ival_v1_q,
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input wire aesd_v1_q,
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input wire aese_v1_q,
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input wire aesd_or_e_v1_q,
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input wire aesmc_v1_q,
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input wire aesimc_v1_q,
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input wire aesdimc_v1_q,
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input wire aesemc_v1_q,
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input wire [127:0] opa_v1,
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input wire [127:0] opb_v1,
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output wire [127:0] aesout_v2
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);
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wire [15:0] aes_shf_v1;
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wire [127:0] aesd_out_v2;
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wire [15:0] aesd_shf_v1;
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wire [127:0] aesd_v1;
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reg aesdimc_h_v2_q;
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reg aesdimc_l_v2_q;
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wire [127:0] aesdimc_out_v2;
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wire [127:0] aese_out_v2;
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wire [15:0] aese_shf_v1;
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wire [127:0] aese_v1;
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wire [127:0] aesed_lut_in_v1;
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wire [127:0] aesed_lut_out_v1;
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reg aesemc_h_v2_q;
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reg aesemc_l_v2_q;
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wire [127:0] aesemc_out_v2;
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reg aesimc_h_v2_q;
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reg aesimc_l_v2_q;
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wire [127:0] aesimc_out_v2;
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reg aesmc_h_v2_q;
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reg aesmc_l_v2_q;
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wire [127:0] aesmc_out_v2;
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wire block_opa_passthrough;
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wire [127:0] opa_aes_nxt_v1;
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reg [127:0] opa_aes_v2_q;
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wire [127:0] qx_v1;
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reg sel_aesd_h_v2_q;
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reg sel_aesd_l_v2_q;
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wire sel_aesd_v1;
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reg sel_aese_h_v2_q;
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reg sel_aese_l_v2_q;
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wire sel_aese_v1;
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assign sel_aesd_v1 = aesd_v1_q & ~aesdimc_v1_q;
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assign sel_aese_v1 = aese_v1_q & ~aesemc_v1_q;
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assign block_opa_passthrough = aesd_or_e_v1_q;
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always_ff @(posedge clk or posedge reset)
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begin: u_aesmc_h_v2_q_grp
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if (reset == 1'b1) begin
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aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
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aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
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aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
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aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
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aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
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aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
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aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
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aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
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sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
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sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
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sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
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sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
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end
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`ifdef HERCULESAE_XPROP_FLOP
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else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
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aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
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aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
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aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
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aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
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aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
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aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
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aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
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aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
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sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
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sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
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sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
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sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
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end
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else if (reset == 1'b0 && ival_v1_q == 1'b0)
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begin
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end
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else begin
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aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
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aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
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aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
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aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
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aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
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aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
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aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
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aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
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sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
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sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
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sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
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sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
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end
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`else
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else if (ival_v1_q == 1'b1) begin
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aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
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aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
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aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
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aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
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aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
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aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
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aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
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aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
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sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
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sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
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sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
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sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
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end
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`endif
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end
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assign qx_v1[127:0] = {128{aesd_or_e_v1_q}} & (opb_v1[127:0] ^ opa_v1[127:0]);
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herculesae_vx_aese1 u_aese1(
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.q (qx_v1[127:0]),
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.aese_out (aese_v1[127:0]),
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.aese_shf (aese_shf_v1[15:0]));
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herculesae_vx_aesd1 u_aesd1(
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.q (qx_v1[127:0]),
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.aesd_out (aesd_v1[127:0]),
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.aesd_shf (aesd_shf_v1[15:0]));
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assign aes_shf_v1[15:0] = {16{aese_v1_q}} & aese_shf_v1[15:0] |
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{16{aesd_v1_q}} & aesd_shf_v1[15:0];
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assign aesed_lut_in_v1[127:0] = ({128{aese_v1_q}} & aese_v1[127:0]) | ({128{aesd_v1_q}} & aesd_v1[127:0]);
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herculesae_vx_aesed2_lut u_aesed2_lut_v1(
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.lut_in (aesed_lut_in_v1[127:0]),
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.lut_out (aesed_lut_out_v1[127:0]));
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assign opa_aes_nxt_v1[127:0] = ({128{aesd_or_e_v1_q}} & aesed_lut_out_v1[127:0])
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| ({128{~block_opa_passthrough}} & opa_v1[127:0]);
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always_ff @(posedge clk or posedge reset)
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begin: u_opa_aes_v2_q_127_0
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if (reset == 1'b1)
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opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
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`ifdef HERCULESAE_XPROP_FLOP
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else if (reset == 1'b0 && ival_v1_q == 1'b1)
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opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY opa_aes_nxt_v1[127:0];
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else if (reset == 1'b0 && ival_v1_q == 1'b0)
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begin
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end
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else
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opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
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`else
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else if (ival_v1_q == 1'b1)
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opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY opa_aes_nxt_v1[127:0];
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`endif
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end
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herculesae_vx_aesmc u_aesmc(
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.d_in (opa_aes_v2_q[127:0]),
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.mc (aesmc_out_v2[127:0]));
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herculesae_vx_aesimc u_aesimc(
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.d_in (opa_aes_v2_q[127:0]),
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.imc (aesimc_out_v2[127:0]));
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herculesae_vx_aesed2 u_aesed2(
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.clk (clk),
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.reset (reset),
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.ival_v1_q (ival_v1_q),
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.aes_din_v1 (aesed_lut_out_v1[127:0]),
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.aes_shf_v1 (aes_shf_v1[15:0]),
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.aesd_out (aesd_out_v2[127:0]),
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.aese_out (aese_out_v2[127:0]),
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.aesemc_out (aesemc_out_v2[127:0]),
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.aesdimc_out (aesdimc_out_v2[127:0]));
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assign aesout_v2[127:64] = ({64{sel_aesd_h_v2_q}} & aesd_out_v2[127:64])
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| ({64{sel_aese_h_v2_q}} & aese_out_v2[127:64])
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| ({64{aesmc_h_v2_q}} & aesmc_out_v2[127:64])
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| ({64{aesemc_h_v2_q}} & aesemc_out_v2[127:64])
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| ({64{aesimc_h_v2_q}} & aesimc_out_v2[127:64])
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| ({64{aesdimc_h_v2_q}} & aesdimc_out_v2[127:64]);
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assign aesout_v2[63:0] = ({64{sel_aesd_l_v2_q}} & aesd_out_v2[63:0])
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| ({64{sel_aese_l_v2_q}} & aese_out_v2[63:0])
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| ({64{aesmc_l_v2_q}} & aesmc_out_v2[63:0])
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| ({64{aesemc_l_v2_q}} & aesemc_out_v2[63:0])
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| ({64{aesimc_l_v2_q}} & aesimc_out_v2[63:0])
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| ({64{aesdimc_l_v2_q}} & aesdimc_out_v2[63:0]);
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endmodule
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`define HERCULESAE_UNDEFINE
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`include "herculesae_header.sv"
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`undef HERCULESAE_UNDEFINE
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