forked from Qortal/Brooklyn
107 lines
3.2 KiB
C
107 lines
3.2 KiB
C
/*
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* Copyright 2012 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Ben Skeggs
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*/
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#include "ior.h"
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#include <subdev/timer.h>
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void
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nv50_sor_clock(struct nvkm_ior *sor)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const int div = sor->asy.link == 3;
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const u32 soff = nv50_ior_base(sor);
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nvkm_mask(device, 0x614300 + soff, 0x00000707, (div << 8) | div);
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}
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static void
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nv50_sor_power_wait(struct nvkm_device *device, u32 soff)
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{
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nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x61c004 + soff) & 0x80000000))
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break;
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);
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}
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void
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nv50_sor_power(struct nvkm_ior *sor, bool normal, bool pu,
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bool data, bool vsync, bool hsync)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 soff = nv50_ior_base(sor);
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const u32 shift = normal ? 0 : 16;
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const u32 state = 0x80000000 | (0x00000001 * !!pu) << shift;
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const u32 field = 0x80000000 | (0x00000001 << shift);
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nv50_sor_power_wait(device, soff);
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nvkm_mask(device, 0x61c004 + soff, field, state);
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nv50_sor_power_wait(device, soff);
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nvkm_msec(device, 2000,
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if (!(nvkm_rd32(device, 0x61c030 + soff) & 0x10000000))
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break;
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);
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}
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void
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nv50_sor_state(struct nvkm_ior *sor, struct nvkm_ior_state *state)
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{
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struct nvkm_device *device = sor->disp->engine.subdev.device;
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const u32 coff = sor->id * 8 + (state == &sor->arm) * 4;
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u32 ctrl = nvkm_rd32(device, 0x610b70 + coff);
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state->proto_evo = (ctrl & 0x00000f00) >> 8;
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switch (state->proto_evo) {
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case 0: state->proto = LVDS; state->link = 1; break;
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case 1: state->proto = TMDS; state->link = 1; break;
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case 2: state->proto = TMDS; state->link = 2; break;
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case 5: state->proto = TMDS; state->link = 3; break;
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default:
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state->proto = UNKNOWN;
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break;
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}
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state->head = ctrl & 0x00000003;
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}
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static const struct nvkm_ior_func
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nv50_sor = {
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.state = nv50_sor_state,
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.power = nv50_sor_power,
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.clock = nv50_sor_clock,
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};
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int
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nv50_sor_new(struct nvkm_disp *disp, int id)
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{
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return nvkm_ior_new_(&nv50_sor, disp, SOR, id);
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}
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int
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nv50_sor_cnt(struct nvkm_disp *disp, unsigned long *pmask)
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{
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struct nvkm_device *device = disp->engine.subdev.device;
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*pmask = (nvkm_rd32(device, 0x610184) & 0x03000000) >> 24;
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return 2;
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}
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