forked from Qortal/Brooklyn
2a709f28fa
* 0day explit mitigation * Memory corruption prevention * Privilege escalation prevention * Buffer over flow prevention * File System corruption defense * Thread escape prevention This may very well be the most intensive inclusion to BrooklynR. This will not be part of an x86 suite nor it will be released as tool kit. The security core toolkit will remain part of kernel base.
254 lines
5.9 KiB
C
254 lines
5.9 KiB
C
/* irq.h
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*
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* Copyright (c) 2012 Samsung Electronics Co., Ltd
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* http://www.samsung.com
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*
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*/
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#ifndef __LINUX_MFD_SEC_IRQ_H
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#define __LINUX_MFD_SEC_IRQ_H
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enum s2mpa01_irq {
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S2MPA01_IRQ_PWRONF,
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S2MPA01_IRQ_PWRONR,
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S2MPA01_IRQ_JIGONBF,
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S2MPA01_IRQ_JIGONBR,
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S2MPA01_IRQ_ACOKBF,
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S2MPA01_IRQ_ACOKBR,
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S2MPA01_IRQ_PWRON1S,
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S2MPA01_IRQ_MRB,
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S2MPA01_IRQ_RTC60S,
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S2MPA01_IRQ_RTCA1,
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S2MPA01_IRQ_RTCA0,
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S2MPA01_IRQ_SMPL,
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S2MPA01_IRQ_RTC1S,
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S2MPA01_IRQ_WTSR,
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S2MPA01_IRQ_INT120C,
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S2MPA01_IRQ_INT140C,
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S2MPA01_IRQ_LDO3_TSD,
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S2MPA01_IRQ_B16_TSD,
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S2MPA01_IRQ_B24_TSD,
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S2MPA01_IRQ_B35_TSD,
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S2MPA01_IRQ_NR,
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};
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#define S2MPA01_IRQ_PWRONF_MASK (1 << 0)
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#define S2MPA01_IRQ_PWRONR_MASK (1 << 1)
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#define S2MPA01_IRQ_JIGONBF_MASK (1 << 2)
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#define S2MPA01_IRQ_JIGONBR_MASK (1 << 3)
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#define S2MPA01_IRQ_ACOKBF_MASK (1 << 4)
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#define S2MPA01_IRQ_ACOKBR_MASK (1 << 5)
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#define S2MPA01_IRQ_PWRON1S_MASK (1 << 6)
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#define S2MPA01_IRQ_MRB_MASK (1 << 7)
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#define S2MPA01_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPA01_IRQ_RTCA1_MASK (1 << 1)
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#define S2MPA01_IRQ_RTCA0_MASK (1 << 2)
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#define S2MPA01_IRQ_SMPL_MASK (1 << 3)
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#define S2MPA01_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPA01_IRQ_WTSR_MASK (1 << 5)
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#define S2MPA01_IRQ_INT120C_MASK (1 << 0)
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#define S2MPA01_IRQ_INT140C_MASK (1 << 1)
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#define S2MPA01_IRQ_LDO3_TSD_MASK (1 << 2)
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#define S2MPA01_IRQ_B16_TSD_MASK (1 << 3)
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#define S2MPA01_IRQ_B24_TSD_MASK (1 << 4)
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#define S2MPA01_IRQ_B35_TSD_MASK (1 << 5)
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enum s2mps11_irq {
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S2MPS11_IRQ_PWRONF,
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S2MPS11_IRQ_PWRONR,
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S2MPS11_IRQ_JIGONBF,
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S2MPS11_IRQ_JIGONBR,
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S2MPS11_IRQ_ACOKBF,
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S2MPS11_IRQ_ACOKBR,
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S2MPS11_IRQ_PWRON1S,
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S2MPS11_IRQ_MRB,
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S2MPS11_IRQ_RTC60S,
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S2MPS11_IRQ_RTCA1,
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S2MPS11_IRQ_RTCA0,
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S2MPS11_IRQ_SMPL,
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S2MPS11_IRQ_RTC1S,
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S2MPS11_IRQ_WTSR,
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S2MPS11_IRQ_INT120C,
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S2MPS11_IRQ_INT140C,
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S2MPS11_IRQ_NR,
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};
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#define S2MPS11_IRQ_PWRONF_MASK (1 << 0)
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#define S2MPS11_IRQ_PWRONR_MASK (1 << 1)
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#define S2MPS11_IRQ_JIGONBF_MASK (1 << 2)
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#define S2MPS11_IRQ_JIGONBR_MASK (1 << 3)
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#define S2MPS11_IRQ_ACOKBF_MASK (1 << 4)
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#define S2MPS11_IRQ_ACOKBR_MASK (1 << 5)
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#define S2MPS11_IRQ_PWRON1S_MASK (1 << 6)
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#define S2MPS11_IRQ_MRB_MASK (1 << 7)
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#define S2MPS11_IRQ_RTC60S_MASK (1 << 0)
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#define S2MPS11_IRQ_RTCA1_MASK (1 << 1)
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#define S2MPS11_IRQ_RTCA0_MASK (1 << 2)
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#define S2MPS11_IRQ_SMPL_MASK (1 << 3)
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#define S2MPS11_IRQ_RTC1S_MASK (1 << 4)
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#define S2MPS11_IRQ_WTSR_MASK (1 << 5)
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#define S2MPS11_IRQ_INT120C_MASK (1 << 0)
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#define S2MPS11_IRQ_INT140C_MASK (1 << 1)
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enum s2mps14_irq {
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S2MPS14_IRQ_PWRONF,
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S2MPS14_IRQ_PWRONR,
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S2MPS14_IRQ_JIGONBF,
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S2MPS14_IRQ_JIGONBR,
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S2MPS14_IRQ_ACOKBF,
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S2MPS14_IRQ_ACOKBR,
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S2MPS14_IRQ_PWRON1S,
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S2MPS14_IRQ_MRB,
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S2MPS14_IRQ_RTC60S,
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S2MPS14_IRQ_RTCA1,
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S2MPS14_IRQ_RTCA0,
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S2MPS14_IRQ_SMPL,
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S2MPS14_IRQ_RTC1S,
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S2MPS14_IRQ_WTSR,
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S2MPS14_IRQ_INT120C,
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S2MPS14_IRQ_INT140C,
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S2MPS14_IRQ_TSD,
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S2MPS14_IRQ_NR,
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};
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enum s2mpu02_irq {
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S2MPU02_IRQ_PWRONF,
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S2MPU02_IRQ_PWRONR,
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S2MPU02_IRQ_JIGONBF,
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S2MPU02_IRQ_JIGONBR,
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S2MPU02_IRQ_ACOKBF,
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S2MPU02_IRQ_ACOKBR,
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S2MPU02_IRQ_PWRON1S,
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S2MPU02_IRQ_MRB,
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S2MPU02_IRQ_RTC60S,
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S2MPU02_IRQ_RTCA1,
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S2MPU02_IRQ_RTCA0,
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S2MPU02_IRQ_SMPL,
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S2MPU02_IRQ_RTC1S,
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S2MPU02_IRQ_WTSR,
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S2MPU02_IRQ_INT120C,
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S2MPU02_IRQ_INT140C,
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S2MPU02_IRQ_TSD,
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S2MPU02_IRQ_NR,
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};
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/* Masks for interrupts are the same as in s2mps11 */
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#define S2MPS14_IRQ_TSD_MASK (1 << 2)
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enum s5m8767_irq {
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S5M8767_IRQ_PWRR,
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S5M8767_IRQ_PWRF,
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S5M8767_IRQ_PWR1S,
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S5M8767_IRQ_JIGR,
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S5M8767_IRQ_JIGF,
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S5M8767_IRQ_LOWBAT2,
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S5M8767_IRQ_LOWBAT1,
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S5M8767_IRQ_MRB,
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S5M8767_IRQ_DVSOK2,
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S5M8767_IRQ_DVSOK3,
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S5M8767_IRQ_DVSOK4,
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S5M8767_IRQ_RTC60S,
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S5M8767_IRQ_RTCA1,
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S5M8767_IRQ_RTCA2,
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S5M8767_IRQ_SMPL,
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S5M8767_IRQ_RTC1S,
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S5M8767_IRQ_WTSR,
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S5M8767_IRQ_NR,
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};
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#define S5M8767_IRQ_PWRR_MASK (1 << 0)
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#define S5M8767_IRQ_PWRF_MASK (1 << 1)
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#define S5M8767_IRQ_PWR1S_MASK (1 << 3)
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#define S5M8767_IRQ_JIGR_MASK (1 << 4)
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#define S5M8767_IRQ_JIGF_MASK (1 << 5)
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#define S5M8767_IRQ_LOWBAT2_MASK (1 << 6)
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#define S5M8767_IRQ_LOWBAT1_MASK (1 << 7)
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#define S5M8767_IRQ_MRB_MASK (1 << 2)
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#define S5M8767_IRQ_DVSOK2_MASK (1 << 3)
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#define S5M8767_IRQ_DVSOK3_MASK (1 << 4)
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#define S5M8767_IRQ_DVSOK4_MASK (1 << 5)
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#define S5M8767_IRQ_RTC60S_MASK (1 << 0)
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#define S5M8767_IRQ_RTCA1_MASK (1 << 1)
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#define S5M8767_IRQ_RTCA2_MASK (1 << 2)
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#define S5M8767_IRQ_SMPL_MASK (1 << 3)
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#define S5M8767_IRQ_RTC1S_MASK (1 << 4)
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#define S5M8767_IRQ_WTSR_MASK (1 << 5)
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enum s5m8763_irq {
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S5M8763_IRQ_DCINF,
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S5M8763_IRQ_DCINR,
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S5M8763_IRQ_JIGF,
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S5M8763_IRQ_JIGR,
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S5M8763_IRQ_PWRONF,
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S5M8763_IRQ_PWRONR,
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S5M8763_IRQ_WTSREVNT,
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S5M8763_IRQ_SMPLEVNT,
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S5M8763_IRQ_ALARM1,
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S5M8763_IRQ_ALARM0,
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S5M8763_IRQ_ONKEY1S,
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S5M8763_IRQ_TOPOFFR,
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S5M8763_IRQ_DCINOVPR,
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S5M8763_IRQ_CHGRSTF,
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S5M8763_IRQ_DONER,
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S5M8763_IRQ_CHGFAULT,
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S5M8763_IRQ_LOBAT1,
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S5M8763_IRQ_LOBAT2,
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S5M8763_IRQ_NR,
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};
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#define S5M8763_IRQ_DCINF_MASK (1 << 2)
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#define S5M8763_IRQ_DCINR_MASK (1 << 3)
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#define S5M8763_IRQ_JIGF_MASK (1 << 4)
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#define S5M8763_IRQ_JIGR_MASK (1 << 5)
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#define S5M8763_IRQ_PWRONF_MASK (1 << 6)
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#define S5M8763_IRQ_PWRONR_MASK (1 << 7)
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#define S5M8763_IRQ_WTSREVNT_MASK (1 << 0)
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#define S5M8763_IRQ_SMPLEVNT_MASK (1 << 1)
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#define S5M8763_IRQ_ALARM1_MASK (1 << 2)
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#define S5M8763_IRQ_ALARM0_MASK (1 << 3)
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#define S5M8763_IRQ_ONKEY1S_MASK (1 << 0)
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#define S5M8763_IRQ_TOPOFFR_MASK (1 << 2)
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#define S5M8763_IRQ_DCINOVPR_MASK (1 << 3)
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#define S5M8763_IRQ_CHGRSTF_MASK (1 << 4)
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#define S5M8763_IRQ_DONER_MASK (1 << 5)
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#define S5M8763_IRQ_CHGFAULT_MASK (1 << 7)
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#define S5M8763_IRQ_LOBAT1_MASK (1 << 0)
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#define S5M8763_IRQ_LOBAT2_MASK (1 << 1)
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#define S5M8763_ENRAMP (1 << 4)
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#endif /* __LINUX_MFD_SEC_IRQ_H */
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