forked from Qortal/Brooklyn
2a709f28fa
* 0day explit mitigation * Memory corruption prevention * Privilege escalation prevention * Buffer over flow prevention * File System corruption defense * Thread escape prevention This may very well be the most intensive inclusion to BrooklynR. This will not be part of an x86 suite nor it will be released as tool kit. The security core toolkit will remain part of kernel base.
89 lines
2.7 KiB
C
89 lines
2.7 KiB
C
/*
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* TI EDMA definitions
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*
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* Copyright (C) 2006-2013 Texas Instruments.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* This EDMA3 programming framework exposes two basic kinds of resource:
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*
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* Channel Triggers transfers, usually from a hardware event but
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* also manually or by "chaining" from DMA completions.
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* Each channel is coupled to a Parameter RAM (PaRAM) slot.
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*
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* Slot Each PaRAM slot holds a DMA transfer descriptor (PaRAM
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* "set"), source and destination addresses, a link to a
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* next PaRAM slot (if any), options for the transfer, and
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* instructions for updating those addresses. There are
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* more than twice as many slots as event channels.
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*
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* Each PaRAM set describes a sequence of transfers, either for one large
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* buffer or for several discontiguous smaller buffers. An EDMA transfer
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* is driven only from a channel, which performs the transfers specified
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* in its PaRAM slot until there are no more transfers. When that last
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* transfer completes, the "link" field may be used to reload the channel's
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* PaRAM slot with a new transfer descriptor.
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*
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* The EDMA Channel Controller (CC) maps requests from channels into physical
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* Transfer Controller (TC) requests when the channel triggers (by hardware
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* or software events, or by chaining). The two physical DMA channels provided
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* by the TCs are thus shared by many logical channels.
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*
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* DaVinci hardware also has a "QDMA" mechanism which is not currently
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* supported through this interface. (DSP firmware uses it though.)
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*/
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#ifndef EDMA_H_
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#define EDMA_H_
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enum dma_event_q {
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EVENTQ_0 = 0,
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EVENTQ_1 = 1,
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EVENTQ_2 = 2,
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EVENTQ_3 = 3,
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EVENTQ_DEFAULT = -1
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};
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#define EDMA_CTLR_CHAN(ctlr, chan) (((ctlr) << 16) | (chan))
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#define EDMA_CTLR(i) ((i) >> 16)
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#define EDMA_CHAN_SLOT(i) ((i) & 0xffff)
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#define EDMA_FILTER_PARAM(ctlr, chan) ((int[]) { EDMA_CTLR_CHAN(ctlr, chan) })
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struct edma_rsv_info {
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const s16 (*rsv_chans)[2];
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const s16 (*rsv_slots)[2];
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};
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struct dma_slave_map;
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/* platform_data for EDMA driver */
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struct edma_soc_info {
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/*
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* Default queue is expected to be a low-priority queue.
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* This way, long transfers on the default queue started
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* by the codec engine will not cause audio defects.
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*/
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enum dma_event_q default_queue;
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/* Resource reservation for other cores */
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struct edma_rsv_info *rsv;
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/* List of channels allocated for memcpy, terminated with -1 */
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s32 *memcpy_channels;
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s8 (*queue_priority_mapping)[2];
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const s16 (*xbar_chans)[2];
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const struct dma_slave_map *slave_map;
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int slavecnt;
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};
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#endif
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