forked from Qortal/Brooklyn
7d3018da4c
* NVME, SATA NAND Security added * Qortal Core exception fetcher is now redone. * Update DT overlays for firmware * Fix for bvb clockj settings * Fix for no audio for sissy desktop porn watchers -_- ( thanks crowetic for watching gay porn and reporting me that bug asshat ) * Normalize the fetch() stream while doing a peer to peer handshake for nodes * Fix for RNG token editing error while performing a SHA256 encryption * Now under voltage errors will blink red led constantly for 5 minutes then go solid. * Improve kernel thread scaling for Qortal 2.0 core * HDMI circuit is now enabled at power up instead. * Added KMS * Added line replication instead of interpolation for VC4 GPU resulting in slightly better frame rates * Fix for long and doubles * Backplane clock is now set at standard rate * Capped HVEC clocks * Add support for Creative Cinema webcam for donkers who like sharing dick pics. *looks at crowetic* * More scanline XGA modes for people who have weird ass monitors of all sorts. * TX/RX flow control support is now 100% stable. No lags over 1Gbps ethernet. ( Hello Qortal 3.0 ) * Using flush cache instead of fetch for QC 2.0 resulting in performance gains * VC4 clock is now enforced for desktop oriented images. * Ondemand governor now waits for 2 seconds instead of 0.5ms to scale down to the lowest safest clock freq preventing lags to the core. * Timeout of OC set at 35ms from 90ms resulting in way better clocks and sync for Qortal 2.0 core
105 lines
2.7 KiB
C
105 lines
2.7 KiB
C
/*
|
|
* Kernel virtual memory layout definitions.
|
|
*
|
|
* This file is subject to the terms and conditions of the GNU General
|
|
* Public License. See the file "COPYING" in the main directory of
|
|
* this archive for more details.
|
|
*
|
|
* Copyright (C) 2016 Cadence Design Systems Inc.
|
|
*/
|
|
|
|
#ifndef _XTENSA_KMEM_LAYOUT_H
|
|
#define _XTENSA_KMEM_LAYOUT_H
|
|
|
|
#include <asm/core.h>
|
|
#include <asm/types.h>
|
|
|
|
#ifdef CONFIG_MMU
|
|
|
|
/*
|
|
* Fixed TLB translations in the processor.
|
|
*/
|
|
|
|
#define XCHAL_PAGE_TABLE_VADDR __XTENSA_UL_CONST(0x80000000)
|
|
#define XCHAL_PAGE_TABLE_SIZE __XTENSA_UL_CONST(0x00400000)
|
|
|
|
#if defined(CONFIG_XTENSA_KSEG_MMU_V2)
|
|
|
|
#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xd0000000)
|
|
#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xd8000000)
|
|
#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x08000000)
|
|
#define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x08000000)
|
|
#define XCHAL_KSEG_TLB_WAY 5
|
|
#define XCHAL_KIO_TLB_WAY 6
|
|
|
|
#elif defined(CONFIG_XTENSA_KSEG_256M)
|
|
|
|
#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xb0000000)
|
|
#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000)
|
|
#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x10000000)
|
|
#define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000)
|
|
#define XCHAL_KSEG_TLB_WAY 6
|
|
#define XCHAL_KIO_TLB_WAY 6
|
|
|
|
#elif defined(CONFIG_XTENSA_KSEG_512M)
|
|
|
|
#define XCHAL_KSEG_CACHED_VADDR __XTENSA_UL_CONST(0xa0000000)
|
|
#define XCHAL_KSEG_BYPASS_VADDR __XTENSA_UL_CONST(0xc0000000)
|
|
#define XCHAL_KSEG_SIZE __XTENSA_UL_CONST(0x20000000)
|
|
#define XCHAL_KSEG_ALIGNMENT __XTENSA_UL_CONST(0x10000000)
|
|
#define XCHAL_KSEG_TLB_WAY 6
|
|
#define XCHAL_KIO_TLB_WAY 6
|
|
|
|
#else
|
|
#error Unsupported KSEG configuration
|
|
#endif
|
|
|
|
#ifdef CONFIG_KSEG_PADDR
|
|
#define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(CONFIG_KSEG_PADDR)
|
|
#else
|
|
#define XCHAL_KSEG_PADDR __XTENSA_UL_CONST(0x00000000)
|
|
#endif
|
|
|
|
#if XCHAL_KSEG_PADDR & (XCHAL_KSEG_ALIGNMENT - 1)
|
|
#error XCHAL_KSEG_PADDR is not properly aligned to XCHAL_KSEG_ALIGNMENT
|
|
#endif
|
|
|
|
#endif
|
|
|
|
/* KIO definition */
|
|
|
|
#if XCHAL_HAVE_PTP_MMU
|
|
#define XCHAL_KIO_CACHED_VADDR 0xe0000000
|
|
#define XCHAL_KIO_BYPASS_VADDR 0xf0000000
|
|
#define XCHAL_KIO_DEFAULT_PADDR 0xf0000000
|
|
#else
|
|
#define XCHAL_KIO_BYPASS_VADDR XCHAL_KIO_PADDR
|
|
#define XCHAL_KIO_DEFAULT_PADDR 0x90000000
|
|
#endif
|
|
#define XCHAL_KIO_SIZE 0x10000000
|
|
|
|
#if (!XCHAL_HAVE_PTP_MMU || XCHAL_HAVE_SPANNING_WAY) && defined(CONFIG_USE_OF)
|
|
#define XCHAL_KIO_PADDR xtensa_get_kio_paddr()
|
|
#ifndef __ASSEMBLY__
|
|
extern unsigned long xtensa_kio_paddr;
|
|
|
|
static inline unsigned long xtensa_get_kio_paddr(void)
|
|
{
|
|
return xtensa_kio_paddr;
|
|
}
|
|
#endif
|
|
#else
|
|
#define XCHAL_KIO_PADDR XCHAL_KIO_DEFAULT_PADDR
|
|
#endif
|
|
|
|
/* KERNEL_STACK definition */
|
|
|
|
#ifndef CONFIG_KASAN
|
|
#define KERNEL_STACK_SHIFT 13
|
|
#else
|
|
#define KERNEL_STACK_SHIFT 15
|
|
#endif
|
|
#define KERNEL_STACK_SIZE (1 << KERNEL_STACK_SHIFT)
|
|
|
|
#endif
|