forked from Qortal/Brooklyn
84ba5b15ac
* Enhance GPIO addon for Noctua Fans for the Qortector upcoming case. This will put PWM signal to real-time. * Fixed RDP not letting a user login if not logged out on Cinnamon release (reported by Crowetic) * Update i2c sensor db * Fixed DRM broadcast over HDMI 2+ * Ease up DHCP security only to prevent Brooklyn blocking routers. * Add possibility to add extra memory for Cinnamon Desktop Release * Fix error message of Software Render mode on Cinnamon Desktop * Add proper offset for HD screens for pixel array *Fixed HDMI jitter for videocore4 GPU * Enable all radios (including Bluetooth)
506 lines
12 KiB
Plaintext
506 lines
12 KiB
Plaintext
// SPDX-License-Identifier: BSD-3-Clause
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/*
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* SDX55 SoC device tree source
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*
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* Copyright (c) 2018, The Linux Foundation. All rights reserved.
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* Copyright (c) 2020, Linaro Ltd.
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*/
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#include <dt-bindings/clock/qcom,gcc-sdx55.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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qcom,msm-id = <357 0x10000>, <368 0x10000>, <418 0x10000>;
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interrupt-parent = <&intc>;
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memory {
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device_type = "memory";
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reg = <0 0>;
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};
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clocks {
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xo_board: xo-board {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <38400000>;
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clock-output-names = "xo_board";
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};
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sleep_clk: sleep-clk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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};
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nand_clk_dummy: nand-clk-dummy {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32000>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a7";
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reg = <0x0>;
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enable-method = "psci";
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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hyp_mem: memory@8fc00000 {
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no-map;
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reg = <0x8fc00000 0x80000>;
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};
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ac_db_mem: memory@8fc80000 {
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no-map;
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reg = <0x8fc80000 0x40000>;
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};
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secdata_mem: memory@8fcfd000 {
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no-map;
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reg = <0x8fcfd000 0x1000>;
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};
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sbl_mem: memory@8fd00000 {
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no-map;
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reg = <0x8fd00000 0x100000>;
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};
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aop_image: memory@8fe00000 {
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no-map;
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reg = <0x8fe00000 0x20000>;
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};
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aop_cmd_db: memory@8fe20000 {
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compatible = "qcom,cmd-db";
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reg = <0x8fe20000 0x20000>;
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no-map;
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};
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smem_mem: memory@8fe40000 {
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no-map;
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reg = <0x8fe40000 0xc0000>;
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};
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tz_mem: memory@8ff00000 {
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no-map;
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reg = <0x8ff00000 0x100000>;
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};
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tz_apps_mem: memory@0x90000000 {
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no-map;
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reg = <0x90000000 0x500000>;
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};
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};
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smem {
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compatible = "qcom,smem";
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memory-region = <&smem_mem>;
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hwlocks = <&tcsr_mutex 3>;
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};
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soc: soc {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "simple-bus";
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gcc: clock-controller@100000 {
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compatible = "qcom,gcc-sdx55";
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reg = <0x100000 0x1f0000>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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#power-domain-cells = <1>;
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clock-names = "bi_tcxo", "sleep_clk";
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clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
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};
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blsp1_uart3: serial@831000 {
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compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
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reg = <0x00831000 0x200>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_LOW>;
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clocks = <&gcc 30>,
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<&gcc 9>;
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clock-names = "core", "iface";
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status = "disabled";
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};
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usb_hsphy: phy@ff4000 {
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compatible = "qcom,usb-snps-hs-7nm-phy";
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reg = <0x00ff4000 0x114>;
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status = "disabled";
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#phy-cells = <0>;
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clocks = <&rpmhcc RPMH_CXO_CLK>;
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clock-names = "ref";
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resets = <&gcc GCC_QUSB2PHY_BCR>;
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};
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usb_qmpphy: phy@ff6000 {
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compatible = "qcom,sdx55-qmp-usb3-uni-phy";
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reg = <0x00ff6000 0x1c0>;
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status = "disabled";
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB3_PHY_AUX_CLK>,
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<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
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<&gcc GCC_USB3_PRIM_CLKREF_CLK>;
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clock-names = "aux", "cfg_ahb", "ref";
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resets = <&gcc GCC_USB3PHY_PHY_BCR>,
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<&gcc GCC_USB3_PHY_BCR>;
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reset-names = "phy", "common";
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usb_ssphy: phy@ff6200 {
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reg = <0x00ff6200 0x170>,
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<0x00ff6400 0x200>,
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<0x00ff6800 0x800>;
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#phy-cells = <0>;
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#clock-cells = <0>;
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clocks = <&gcc GCC_USB3_PHY_PIPE_CLK>;
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clock-names = "pipe0";
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clock-output-names = "usb3_uni_phy_pipe_clk_src";
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};
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};
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qpic_bam: dma-controller@1b04000 {
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compatible = "qcom,bam-v1.7.0";
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reg = <0x01b04000 0x1c000>;
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interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&rpmhcc RPMH_QPIC_CLK>;
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clock-names = "bam_clk";
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#dma-cells = <1>;
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qcom,ee = <0>;
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qcom,controlled-remotely;
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status = "disabled";
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};
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qpic_nand: nand@1b30000 {
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compatible = "qcom,sdx55-nand";
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reg = <0x01b30000 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&rpmhcc RPMH_QPIC_CLK>,
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<&nand_clk_dummy>;
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clock-names = "core", "aon";
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dmas = <&qpic_bam 0>,
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<&qpic_bam 1>,
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<&qpic_bam 2>;
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dma-names = "tx", "rx", "cmd";
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status = "disabled";
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};
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tcsr_mutex: hwlock@1f40000 {
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compatible = "qcom,tcsr-mutex";
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reg = <0x01f40000 0x40000>;
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#hwlock-cells = <1>;
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};
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sdhc_1: sdhci@8804000 {
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compatible = "qcom,sdx55-sdhci", "qcom,sdhci-msm-v5";
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reg = <0x08804000 0x1000>;
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interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hc_irq", "pwr_irq";
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clocks = <&gcc GCC_SDCC1_AHB_CLK>,
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<&gcc GCC_SDCC1_APPS_CLK>;
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clock-names = "iface", "core";
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status = "disabled";
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};
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usb: usb@a6f8800 {
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compatible = "qcom,sdx55-dwc3", "qcom,dwc3";
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reg = <0x0a6f8800 0x400>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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clocks = <&gcc GCC_USB30_SLV_AHB_CLK>,
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<&gcc GCC_USB30_MASTER_CLK>,
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<&gcc GCC_USB30_MSTR_AXI_CLK>,
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<&gcc GCC_USB30_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_SLEEP_CLK>;
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clock-names = "cfg_noc", "core", "iface", "mock_utmi",
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"sleep";
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assigned-clocks = <&gcc GCC_USB30_MOCK_UTMI_CLK>,
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<&gcc GCC_USB30_MASTER_CLK>;
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assigned-clock-rates = <19200000>, <200000000>;
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interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "hs_phy_irq", "ss_phy_irq",
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"dm_hs_phy_irq", "dp_hs_phy_irq";
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power-domains = <&gcc USB30_GDSC>;
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resets = <&gcc GCC_USB30_BCR>;
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usb_dwc3: dwc3@a600000 {
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compatible = "snps,dwc3";
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reg = <0x0a600000 0xcd00>;
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interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
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iommus = <&apps_smmu 0x1a0 0x0>;
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snps,dis_u2_susphy_quirk;
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snps,dis_enblslpm_quirk;
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phys = <&usb_hsphy>, <&usb_ssphy>;
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phy-names = "usb2-phy", "usb3-phy";
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};
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};
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pdc: interrupt-controller@b210000 {
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compatible = "qcom,sdx55-pdc", "qcom,pdc";
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reg = <0x0b210000 0x30000>;
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qcom,pdc-ranges = <0 179 52>;
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#interrupt-cells = <3>;
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interrupt-parent = <&intc>;
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interrupt-controller;
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};
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restart@c264000 {
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compatible = "qcom,pshold";
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reg = <0x0c264000 0x1000>;
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};
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spmi_bus: qcom,spmi@c440000 {
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compatible = "qcom,spmi-pmic-arb";
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reg = <0x0c440000 0x0000d00>,
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<0x0c600000 0x2000000>,
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<0x0e600000 0x0100000>,
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<0x0e700000 0x00a0000>,
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<0x0c40a000 0x0000700>;
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reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
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interrupt-names = "periph_irq";
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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qcom,ee = <0>;
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qcom,channel = <0>;
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#address-cells = <2>;
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#size-cells = <0>;
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interrupt-controller;
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#interrupt-cells = <4>;
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cell-index = <0>;
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};
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tlmm: pinctrl@f100000 {
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compatible = "qcom,sdx55-pinctrl";
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reg = <0xf100000 0x300000>;
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interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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apps_smmu: iommu@15000000 {
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compatible = "qcom,sdx55-smmu-500", "arm,mmu-500";
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reg = <0x15000000 0x20000>;
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#iommu-cells = <2>;
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#global-interrupts = <1>;
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interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
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};
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intc: interrupt-controller@17800000 {
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compatible = "qcom,msm-qgic2";
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interrupt-controller;
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interrupt-parent = <&intc>;
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#interrupt-cells = <3>;
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reg = <0x17800000 0x1000>,
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<0x17802000 0x1000>;
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};
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watchdog@17817000 {
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compatible = "qcom,apss-wdt-sdx55", "qcom,kpss-wdt";
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reg = <0x17817000 0x1000>;
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clocks = <&sleep_clk>;
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};
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timer@17820000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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compatible = "arm,armv7-timer-mem";
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reg = <0x17820000 0x1000>;
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clock-frequency = <19200000>;
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frame@17821000 {
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frame-number = <0>;
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interrupts = <GIC_SPI 7 0x4>,
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<GIC_SPI 6 0x4>;
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reg = <0x17821000 0x1000>,
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<0x17822000 0x1000>;
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};
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frame@17823000 {
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frame-number = <1>;
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interrupts = <GIC_SPI 8 0x4>;
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reg = <0x17823000 0x1000>;
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status = "disabled";
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};
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frame@17824000 {
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frame-number = <2>;
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interrupts = <GIC_SPI 9 0x4>;
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reg = <0x17824000 0x1000>;
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status = "disabled";
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};
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frame@17825000 {
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frame-number = <3>;
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interrupts = <GIC_SPI 10 0x4>;
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reg = <0x17825000 0x1000>;
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status = "disabled";
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};
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frame@17826000 {
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frame-number = <4>;
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interrupts = <GIC_SPI 11 0x4>;
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reg = <0x17826000 0x1000>;
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status = "disabled";
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};
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frame@17827000 {
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frame-number = <5>;
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interrupts = <GIC_SPI 12 0x4>;
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reg = <0x17827000 0x1000>;
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status = "disabled";
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};
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frame@17828000 {
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frame-number = <6>;
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interrupts = <GIC_SPI 13 0x4>;
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reg = <0x17828000 0x1000>;
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status = "disabled";
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};
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frame@17829000 {
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frame-number = <7>;
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interrupts = <GIC_SPI 14 0x4>;
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reg = <0x17829000 0x1000>;
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status = "disabled";
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};
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};
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apps_rsc: rsc@17840000 {
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compatible = "qcom,rpmh-rsc";
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reg = <0x17830000 0x10000>, <0x17840000 0x10000>;
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reg-names = "drv-0", "drv-1";
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interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
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qcom,tcs-offset = <0xd00>;
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qcom,drv-id = <1>;
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qcom,tcs-config = <ACTIVE_TCS 2>, <SLEEP_TCS 2>,
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<WAKE_TCS 2>, <CONTROL_TCS 1>;
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rpmhcc: clock-controller {
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compatible = "qcom,sdx55-rpmh-clk";
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#clock-cells = <1>;
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clock-names = "xo";
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clocks = <&xo_board>;
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};
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rpmhpd: power-controller {
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compatible = "qcom,sdx55-rpmhpd";
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#power-domain-cells = <1>;
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operating-points-v2 = <&rpmhpd_opp_table>;
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rpmhpd_opp_table: opp-table {
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compatible = "operating-points-v2";
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rpmhpd_opp_ret: opp1 {
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opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
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};
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rpmhpd_opp_min_svs: opp2 {
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opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
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};
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rpmhpd_opp_low_svs: opp3 {
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opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
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};
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rpmhpd_opp_svs: opp4 {
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opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
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};
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rpmhpd_opp_svs_l1: opp5 {
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opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
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};
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rpmhpd_opp_nom: opp6 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
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};
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rpmhpd_opp_nom_l1: opp7 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
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};
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rpmhpd_opp_nom_l2: opp8 {
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opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
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};
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rpmhpd_opp_turbo: opp9 {
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
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};
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rpmhpd_opp_turbo_l1: opp10 {
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opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv7-timer";
|
|
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
};
|