forked from Qortal/Brooklyn
461 lines
14 KiB
C
461 lines
14 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2018-2020 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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#ifndef HL_BOOT_IF_H
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#define HL_BOOT_IF_H
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#define LKD_HARD_RESET_MAGIC 0xED7BD694
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#define HL_POWER9_HOST_MAGIC 0x1DA30009
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#define BOOT_FIT_SRAM_OFFSET 0x200000
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#define VERSION_MAX_LEN 128
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/*
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* CPU error bits in BOOT_ERROR registers
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*
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* CPU_BOOT_ERR0_DRAM_INIT_FAIL DRAM initialization failed.
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* DRAM is not reliable to use.
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*
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* CPU_BOOT_ERR0_FIT_CORRUPTED FIT data integrity verification of the
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* image provided by the host has failed.
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*
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* CPU_BOOT_ERR0_TS_INIT_FAIL Thermal Sensor initialization failed.
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* Boot continues as usual, but keep in
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* mind this is a warning.
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*
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* CPU_BOOT_ERR0_DRAM_SKIPPED DRAM initialization has been skipped.
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* Skipping DRAM initialization has been
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* requested (e.g. strap, command, etc.)
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* and FW skipped the DRAM initialization.
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* Host can initialize the DRAM.
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*
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* CPU_BOOT_ERR0_BMC_WAIT_SKIPPED Waiting for BMC data will be skipped.
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* Meaning the BMC data might not be
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* available until reset.
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*
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* CPU_BOOT_ERR0_NIC_DATA_NOT_RDY NIC data from BMC is not ready.
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* BMC has not provided the NIC data yet.
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* Once provided this bit will be cleared.
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*
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* CPU_BOOT_ERR0_NIC_FW_FAIL NIC FW loading failed.
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* The NIC FW loading and initialization
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* failed. This means NICs are not usable.
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*
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* CPU_BOOT_ERR0_SECURITY_NOT_RDY Chip security initialization has been
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* started, but is not ready yet - chip
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* cannot be accessed.
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*
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* CPU_BOOT_ERR0_SECURITY_FAIL Security related tasks have failed.
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* The tasks are security init (root of
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* trust), boot authentication (chain of
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* trust), data packets authentication.
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*
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* CPU_BOOT_ERR0_EFUSE_FAIL Reading from eFuse failed.
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* The PCI device ID might be wrong.
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*
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* CPU_BOOT_ERR0_PRI_IMG_VER_FAIL Verification of primary image failed.
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* It mean that ppboot checksum
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* verification for the preboot primary
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* image has failed to match expected
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* checksum. Trying to program image again
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* might solve this.
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*
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* CPU_BOOT_ERR0_SEC_IMG_VER_FAIL Verification of secondary image failed.
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* It mean that ppboot checksum
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* verification for the preboot secondary
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* image has failed to match expected
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* checksum. Trying to program image again
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* might solve this.
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*
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* CPU_BOOT_ERR0_PLL_FAIL PLL settings failed, meaning that one
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* of the PLLs remains in REF_CLK
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*
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* CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL Device is unusable and customer support
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* should be contacted.
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*
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* CPU_BOOT_ERR0_ENABLED Error registers enabled.
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* This is a main indication that the
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* running FW populates the error
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* registers. Meaning the error bits are
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* not garbage, but actual error statuses.
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*/
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#define CPU_BOOT_ERR0_DRAM_INIT_FAIL (1 << 0)
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#define CPU_BOOT_ERR0_FIT_CORRUPTED (1 << 1)
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#define CPU_BOOT_ERR0_TS_INIT_FAIL (1 << 2)
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#define CPU_BOOT_ERR0_DRAM_SKIPPED (1 << 3)
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#define CPU_BOOT_ERR0_BMC_WAIT_SKIPPED (1 << 4)
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#define CPU_BOOT_ERR0_NIC_DATA_NOT_RDY (1 << 5)
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#define CPU_BOOT_ERR0_NIC_FW_FAIL (1 << 6)
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#define CPU_BOOT_ERR0_SECURITY_NOT_RDY (1 << 7)
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#define CPU_BOOT_ERR0_SECURITY_FAIL (1 << 8)
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#define CPU_BOOT_ERR0_EFUSE_FAIL (1 << 9)
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#define CPU_BOOT_ERR0_PRI_IMG_VER_FAIL (1 << 10)
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#define CPU_BOOT_ERR0_SEC_IMG_VER_FAIL (1 << 11)
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#define CPU_BOOT_ERR0_PLL_FAIL (1 << 12)
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#define CPU_BOOT_ERR0_DEVICE_UNUSABLE_FAIL (1 << 13)
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#define CPU_BOOT_ERR0_ENABLED (1 << 31)
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/*
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* BOOT DEVICE STATUS bits in BOOT_DEVICE_STS registers
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*
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* CPU_BOOT_DEV_STS0_SECURITY_EN Security is Enabled.
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* This is an indication for security
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* enabled in FW, which means that
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* all conditions for security are met:
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* device is indicated as security enabled,
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* registers are protected, and device
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* uses keys for image verification.
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* Initialized in: preboot
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*
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* CPU_BOOT_DEV_STS0_DEBUG_EN Debug is enabled.
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* Enabled when JTAG or DEBUG is enabled
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* in FW.
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* Initialized in: preboot
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*
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* CPU_BOOT_DEV_STS0_WATCHDOG_EN Watchdog is enabled.
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* Watchdog is enabled in FW.
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* Initialized in: preboot
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*
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* CPU_BOOT_DEV_STS0_DRAM_INIT_EN DRAM initialization is enabled.
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* DRAM initialization has been done in FW.
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* Initialized in: u-boot
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*
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* CPU_BOOT_DEV_STS0_BMC_WAIT_EN Waiting for BMC data enabled.
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* If set, it means that during boot,
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* FW waited for BMC data.
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* Initialized in: u-boot
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*
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* CPU_BOOT_DEV_STS0_E2E_CRED_EN E2E credits initialized.
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* FW initialized E2E credits.
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* Initialized in: u-boot
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*
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* CPU_BOOT_DEV_STS0_HBM_CRED_EN HBM credits initialized.
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* FW initialized HBM credits.
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* Initialized in: u-boot
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*
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* CPU_BOOT_DEV_STS0_RL_EN Rate limiter initialized.
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* FW initialized rate limiter.
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* Initialized in: u-boot
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*
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* CPU_BOOT_DEV_STS0_SRAM_SCR_EN SRAM scrambler enabled.
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* FW initialized SRAM scrambler.
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* Initialized in: linux
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*
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* CPU_BOOT_DEV_STS0_DRAM_SCR_EN DRAM scrambler enabled.
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* FW initialized DRAM scrambler.
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* Initialized in: u-boot
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*
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* CPU_BOOT_DEV_STS0_FW_HARD_RST_EN FW hard reset procedure is enabled.
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* FW has the hard reset procedure
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* implemented. This means that FW will
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* perform hard reset procedure on
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* receiving the halt-machine event.
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* Initialized in: preboot, u-boot, linux
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*
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* CPU_BOOT_DEV_STS0_PLL_INFO_EN FW retrieval of PLL info is enabled.
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* Initialized in: linux
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*
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* CPU_BOOT_DEV_STS0_SP_SRAM_EN SP SRAM is initialized and available
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* for use.
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* Initialized in: preboot
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*
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* CPU_BOOT_DEV_STS0_CLK_GATE_EN Clock Gating enabled.
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* FW initialized Clock Gating.
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* Initialized in: preboot
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*
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* CPU_BOOT_DEV_STS0_HBM_ECC_EN HBM ECC handling Enabled.
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* FW handles HBM ECC indications.
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* Initialized in: linux
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*
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* CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN Packets ack value used in the armcpd
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* is set to the PI counter.
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* Initialized in: linux
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*
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* CPU_BOOT_DEV_STS0_FW_LD_COM_EN Flexible FW loading communication
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* protocol is enabled.
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* Initialized in: preboot
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*
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* CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN FW iATU configuration is enabled.
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* This bit if set, means the iATU has been
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* configured and is ready for use.
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* Initialized in: ppboot
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*
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* CPU_BOOT_DEV_STS0_DYN_PLL_EN Dynamic PLL configuration is enabled.
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* FW sends to host a bitmap of supported
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* PLLs.
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* Initialized in: linux
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*
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* CPU_BOOT_DEV_STS0_ENABLED Device status register enabled.
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* This is a main indication that the
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* running FW populates the device status
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* register. Meaning the device status
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* bits are not garbage, but actual
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* statuses.
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* Initialized in: preboot
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*
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*/
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#define CPU_BOOT_DEV_STS0_SECURITY_EN (1 << 0)
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#define CPU_BOOT_DEV_STS0_DEBUG_EN (1 << 1)
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#define CPU_BOOT_DEV_STS0_WATCHDOG_EN (1 << 2)
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#define CPU_BOOT_DEV_STS0_DRAM_INIT_EN (1 << 3)
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#define CPU_BOOT_DEV_STS0_BMC_WAIT_EN (1 << 4)
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#define CPU_BOOT_DEV_STS0_E2E_CRED_EN (1 << 5)
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#define CPU_BOOT_DEV_STS0_HBM_CRED_EN (1 << 6)
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#define CPU_BOOT_DEV_STS0_RL_EN (1 << 7)
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#define CPU_BOOT_DEV_STS0_SRAM_SCR_EN (1 << 8)
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#define CPU_BOOT_DEV_STS0_DRAM_SCR_EN (1 << 9)
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#define CPU_BOOT_DEV_STS0_FW_HARD_RST_EN (1 << 10)
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#define CPU_BOOT_DEV_STS0_PLL_INFO_EN (1 << 11)
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#define CPU_BOOT_DEV_STS0_SP_SRAM_EN (1 << 12)
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#define CPU_BOOT_DEV_STS0_CLK_GATE_EN (1 << 13)
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#define CPU_BOOT_DEV_STS0_HBM_ECC_EN (1 << 14)
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#define CPU_BOOT_DEV_STS0_PKT_PI_ACK_EN (1 << 15)
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#define CPU_BOOT_DEV_STS0_FW_LD_COM_EN (1 << 16)
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#define CPU_BOOT_DEV_STS0_FW_IATU_CONF_EN (1 << 17)
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#define CPU_BOOT_DEV_STS0_DYN_PLL_EN (1 << 19)
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#define CPU_BOOT_DEV_STS0_ENABLED (1 << 31)
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enum cpu_boot_status {
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CPU_BOOT_STATUS_NA = 0, /* Default value after reset of chip */
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CPU_BOOT_STATUS_IN_WFE = 1,
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CPU_BOOT_STATUS_DRAM_RDY = 2,
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CPU_BOOT_STATUS_SRAM_AVAIL = 3,
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CPU_BOOT_STATUS_IN_BTL = 4, /* BTL is H/W FSM */
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CPU_BOOT_STATUS_IN_PREBOOT = 5,
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CPU_BOOT_STATUS_IN_SPL, /* deprecated - not reported */
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CPU_BOOT_STATUS_IN_UBOOT = 7,
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CPU_BOOT_STATUS_DRAM_INIT_FAIL, /* deprecated - will be removed */
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CPU_BOOT_STATUS_FIT_CORRUPTED, /* deprecated - will be removed */
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/* U-Boot console prompt activated, commands are not processed */
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CPU_BOOT_STATUS_UBOOT_NOT_READY = 10,
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/* Finished NICs init, reported after DRAM and NICs */
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CPU_BOOT_STATUS_NIC_FW_RDY = 11,
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CPU_BOOT_STATUS_TS_INIT_FAIL, /* deprecated - will be removed */
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CPU_BOOT_STATUS_DRAM_SKIPPED, /* deprecated - will be removed */
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CPU_BOOT_STATUS_BMC_WAITING_SKIPPED, /* deprecated - will be removed */
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/* Last boot loader progress status, ready to receive commands */
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CPU_BOOT_STATUS_READY_TO_BOOT = 15,
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/* Internal Boot finished, ready for boot-fit */
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CPU_BOOT_STATUS_WAITING_FOR_BOOT_FIT = 16,
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/* Internal Security has been initialized, device can be accessed */
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CPU_BOOT_STATUS_SECURITY_READY = 17,
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};
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enum kmd_msg {
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KMD_MSG_NA = 0,
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KMD_MSG_GOTO_WFE,
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KMD_MSG_FIT_RDY,
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KMD_MSG_SKIP_BMC,
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RESERVED,
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KMD_MSG_RST_DEV,
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KMD_MSG_LAST
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};
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enum cpu_msg_status {
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CPU_MSG_CLR = 0,
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CPU_MSG_OK,
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CPU_MSG_ERR,
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};
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/* communication registers mapping - consider ABI when changing */
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struct cpu_dyn_regs {
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uint32_t cpu_pq_base_addr_low;
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uint32_t cpu_pq_base_addr_high;
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uint32_t cpu_pq_length;
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uint32_t cpu_pq_init_status;
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uint32_t cpu_eq_base_addr_low;
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uint32_t cpu_eq_base_addr_high;
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uint32_t cpu_eq_length;
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uint32_t cpu_eq_ci;
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uint32_t cpu_cq_base_addr_low;
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uint32_t cpu_cq_base_addr_high;
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uint32_t cpu_cq_length;
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uint32_t cpu_pf_pq_pi;
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uint32_t cpu_boot_dev_sts0;
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uint32_t cpu_boot_dev_sts1;
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uint32_t cpu_boot_err0;
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uint32_t cpu_boot_err1;
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uint32_t cpu_boot_status;
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uint32_t fw_upd_sts;
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uint32_t fw_upd_cmd;
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uint32_t fw_upd_pending_sts;
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uint32_t fuse_ver_offset;
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uint32_t preboot_ver_offset;
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uint32_t uboot_ver_offset;
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uint32_t hw_state;
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uint32_t kmd_msg_to_cpu;
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uint32_t cpu_cmd_status_to_host;
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uint32_t reserved1[32]; /* reserve for future use */
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};
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/* HCDM - Habana Communications Descriptor Magic */
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#define HL_COMMS_DESC_MAGIC 0x4843444D
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#define HL_COMMS_DESC_VER 1
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/* this is the comms descriptor header - meta data */
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struct comms_desc_header {
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uint32_t magic; /* magic for validation */
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uint32_t crc32; /* CRC32 of the descriptor w/o header */
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uint16_t size; /* size of the descriptor w/o header */
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uint8_t version; /* descriptor version */
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uint8_t reserved[5]; /* pad to 64 bit */
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};
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/* this is the main FW descriptor - consider ABI when changing */
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struct lkd_fw_comms_desc {
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struct comms_desc_header header;
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struct cpu_dyn_regs cpu_dyn_regs;
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char fuse_ver[VERSION_MAX_LEN];
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char cur_fw_ver[VERSION_MAX_LEN];
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/* can be used for 1 more version w/o ABI change */
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char reserved0[VERSION_MAX_LEN];
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uint64_t img_addr; /* address for next FW component load */
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};
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/*
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* LKD commands:
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*
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* COMMS_NOOP Used to clear the command register and no actual
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* command is send.
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*
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* COMMS_CLR_STS Clear status command - FW should clear the
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* status register. Used for synchronization
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* between the commands as part of the race free
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* protocol.
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*
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* COMMS_RST_STATE Reset the current communication state which is
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* kept by FW for proper responses.
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* Should be used in the beginning of the
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* communication cycle to clean any leftovers from
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* previous communication attempts.
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*
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* COMMS_PREP_DESC Prepare descriptor for setting up the
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* communication and other dynamic data:
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* struct lkd_fw_comms_desc.
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* This command has a parameter stating the next FW
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* component size, so the FW can actually prepare a
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* space for it and in the status response provide
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* the descriptor offset. The Offset of the next FW
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* data component is a part of the descriptor
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* structure.
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*
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* COMMS_DATA_RDY The FW data has been uploaded and is ready for
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* validation.
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*
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* COMMS_EXEC Execute the next FW component.
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*
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* COMMS_RST_DEV Reset the device.
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*
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* COMMS_GOTO_WFE Execute WFE command. Allowed only on non-secure
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* devices.
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*
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* COMMS_SKIP_BMC Perform actions required for BMC-less servers.
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* Do not wait for BMC response.
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*
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* COMMS_LOW_PLL_OPP Initialize PLLs for low OPP.
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*/
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enum comms_cmd {
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COMMS_NOOP = 0,
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COMMS_CLR_STS = 1,
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COMMS_RST_STATE = 2,
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COMMS_PREP_DESC = 3,
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COMMS_DATA_RDY = 4,
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COMMS_EXEC = 5,
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COMMS_RST_DEV = 6,
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COMMS_GOTO_WFE = 7,
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COMMS_SKIP_BMC = 8,
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COMMS_LOW_PLL_OPP = 9,
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COMMS_INVLD_LAST
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};
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#define COMMS_COMMAND_SIZE_SHIFT 0
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#define COMMS_COMMAND_SIZE_MASK 0x1FFFFFF
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#define COMMS_COMMAND_CMD_SHIFT 27
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#define COMMS_COMMAND_CMD_MASK 0xF8000000
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/*
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* LKD command to FW register structure
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* @size - FW component size
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* @cmd - command from enum comms_cmd
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*/
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struct comms_command {
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union { /* bit fields are only for FW use */
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struct {
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unsigned int size :25; /* 32MB max. */
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unsigned int reserved :2;
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enum comms_cmd cmd :5; /* 32 commands */
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};
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unsigned int val;
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};
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};
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/*
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* FW status
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*
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* COMMS_STS_NOOP Used to clear the status register and no actual
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* status is provided.
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*
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* COMMS_STS_ACK Command has been received and recognized.
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*
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* COMMS_STS_OK Command execution has finished successfully.
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*
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* COMMS_STS_ERR Command execution was unsuccessful and resulted
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* in error.
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*
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* COMMS_STS_VALID_ERR FW validation has failed.
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*
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* COMMS_STS_TIMEOUT_ERR Command execution has timed out.
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*/
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enum comms_sts {
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COMMS_STS_NOOP = 0,
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COMMS_STS_ACK = 1,
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COMMS_STS_OK = 2,
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COMMS_STS_ERR = 3,
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COMMS_STS_VALID_ERR = 4,
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COMMS_STS_TIMEOUT_ERR = 5,
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COMMS_STS_INVLD_LAST
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};
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/* RAM types for FW components loading - defines the base address */
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enum comms_ram_types {
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COMMS_SRAM = 0,
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COMMS_DRAM = 1,
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};
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#define COMMS_STATUS_OFFSET_SHIFT 0
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#define COMMS_STATUS_OFFSET_MASK 0x03FFFFFF
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#define COMMS_STATUS_OFFSET_ALIGN_SHIFT 2
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#define COMMS_STATUS_RAM_TYPE_SHIFT 26
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#define COMMS_STATUS_RAM_TYPE_MASK 0x0C000000
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#define COMMS_STATUS_STATUS_SHIFT 28
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#define COMMS_STATUS_STATUS_MASK 0xF0000000
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/*
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* FW status to LKD register structure
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* @offset - an offset from the base of the ram_type shifted right by
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* 2 bits (always aligned to 32 bits).
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* Allows a maximum addressable offset of 256MB from RAM base.
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* Example: for real offset in RAM of 0x800000 (8MB), the value
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* in offset field is (0x800000 >> 2) = 0x200000.
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* @ram_type - the RAM type that should be used for offset from
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* enum comms_ram_types
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* @status - status from enum comms_sts
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*/
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struct comms_status {
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union { /* bit fields are only for FW use */
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struct {
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|
unsigned int offset :26;
|
|
unsigned int ram_type :2;
|
|
enum comms_sts status :4; /* 16 statuses */
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|
};
|
|
unsigned int val;
|
|
};
|
|
};
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|
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#endif /* HL_BOOT_IF_H */
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