forked from Qortal/Brooklyn
105 lines
2.6 KiB
Verilog
105 lines
2.6 KiB
Verilog
`include "settings.h"
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module Control_Unit
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(
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input S,
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input [1:0] mode,
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input [3:0] op_code,
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output reg [3:0] EX_command,
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output reg mem_read,
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output reg mem_write,
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output reg WB_en,
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output reg B,
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output SR_update,
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output has_src1
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);
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always @(*) begin
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mem_read = 0;
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mem_write = 0;
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WB_en = 0;
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B = 0;
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case (mode)
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`MODE_MEM: begin
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case (S)
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0: begin
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EX_command = `EX_STR;
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mem_write = 1;
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end
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1: begin
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EX_command = `EX_LDR;
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mem_read = 1;
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WB_en = 1;
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end
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endcase
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end
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`MODE_ARITHMETIC: begin
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case (op_code)
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`OP_MOV: begin
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EX_command = `EX_MOV;
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WB_en = 1;
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end
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`OP_MVN: begin
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EX_command = `EX_MVN;
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WB_en = 1;
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end
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`OP_ADD: begin
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EX_command = `EX_ADD;
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WB_en = 1;
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end
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`OP_ADC: begin
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EX_command = `EX_ADC;
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WB_en = 1;
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end
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`OP_SUB: begin
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EX_command = `EX_SUB;
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WB_en = 1;
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end
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`OP_SBC: begin
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EX_command = `EX_SBC;
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WB_en = 1;
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end
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`OP_AND: begin
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EX_command = `EX_AND;
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WB_en = 1;
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end
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`OP_ORR: begin
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EX_command = `EX_ORR;
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WB_en = 1;
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end
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`OP_EOR: begin
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EX_command = `EX_EOR;
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WB_en = 1;
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end
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`OP_CMP: begin
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EX_command = `EX_CMP;
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end
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`OP_TST: begin
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EX_command = `EX_TST;
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end
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endcase
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end
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`MODE_BRANCH: begin
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B = 1;
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end
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endcase
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end
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assign SR_update = S;
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assign has_src1 = ((EX_command == `EX_MOV) ||
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(EX_command == `EX_MVN) || B) ? 1'b0 : 1'b1;
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endmodule
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