forked from Qortal/Brooklyn
25 lines
391 B
Verilog
25 lines
391 B
Verilog
`include "settings.h"
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module Status_Reg
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(
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input clk,
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input rst,
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input load,
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input [3:0] status_in,
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output reg [3:0] status
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);
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always @(negedge clk or posedge rst) begin
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if(rst) begin
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status <= 0;
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end
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else if(load) begin
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status <= status_in;
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end
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else begin
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status <= status;
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end
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end
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endmodule
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