forked from Qortal/Brooklyn
a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
43 lines
1.4 KiB
C
43 lines
1.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_DP_LINK_TRAINING_H__
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#define __INTEL_DP_LINK_TRAINING_H__
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#include <drm/dp/drm_dp_helper.h>
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struct intel_crtc_state;
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struct intel_dp;
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int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp);
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void intel_dp_get_adjust_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy,
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const u8 link_status[DP_LINK_STATUS_SIZE]);
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void intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy,
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u8 dp_train_pat);
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void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state,
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enum drm_dp_phy dp_phy);
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void intel_dp_start_link_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void intel_dp_stop_link_train(struct intel_dp *intel_dp,
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const struct intel_crtc_state *crtc_state);
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void
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intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy,
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const u8 link_status[DP_LINK_STATUS_SIZE]);
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/* Get the TPSx symbol type of the value programmed to DP_TRAINING_PATTERN_SET */
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static inline u8 intel_dp_training_pattern_symbol(u8 pattern)
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{
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return pattern & ~DP_LINK_SCRAMBLING_DISABLE;
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}
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#endif /* __INTEL_DP_LINK_TRAINING_H__ */
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