forked from Qortal/Brooklyn
a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
42 lines
1.3 KiB
C
42 lines
1.3 KiB
C
/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
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/* Microsemi Ocelot Switch driver
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*
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* Copyright (c) 2019 Microsemi Corporation
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*/
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#ifndef _MSCC_OCELOT_POLICE_H_
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#define _MSCC_OCELOT_POLICE_H_
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#include "ocelot.h"
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#include <net/flow_offload.h>
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enum mscc_qos_rate_mode {
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MSCC_QOS_RATE_MODE_DISABLED, /* Policer/shaper disabled */
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MSCC_QOS_RATE_MODE_LINE, /* Measure line rate in kbps incl. IPG */
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MSCC_QOS_RATE_MODE_DATA, /* Measures data rate in kbps excl. IPG */
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MSCC_QOS_RATE_MODE_FRAME, /* Measures frame rate in fps */
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__MSCC_QOS_RATE_MODE_END,
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NUM_MSCC_QOS_RATE_MODE = __MSCC_QOS_RATE_MODE_END,
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MSCC_QOS_RATE_MODE_MAX = __MSCC_QOS_RATE_MODE_END - 1,
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};
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struct qos_policer_conf {
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enum mscc_qos_rate_mode mode;
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bool dlb; /* Enable DLB (dual leaky bucket mode */
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bool cf; /* Coupling flag (ignored in SLB mode) */
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u32 cir; /* CIR in kbps/fps (ignored in SLB mode) */
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u32 cbs; /* CBS in bytes/frames (ignored in SLB mode) */
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u32 pir; /* PIR in kbps/fps */
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u32 pbs; /* PBS in bytes/frames */
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u8 ipg; /* Size of IPG when MSCC_QOS_RATE_MODE_LINE is chosen */
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};
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int qos_policer_conf_set(struct ocelot *ocelot, int port, u32 pol_ix,
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struct qos_policer_conf *conf);
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int ocelot_policer_validate(const struct flow_action *action,
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const struct flow_action_entry *a,
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struct netlink_ext_ack *extack);
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#endif /* _MSCC_OCELOT_POLICE_H_ */
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