forked from Qortal/Brooklyn
a94b3d14aa
Changes included (and more): 1. Dynamic RAM merge 2. Real-time page scan and allocation 3. Cache compression 4. Real-time IRQ checks 5. Dynamic I/O allocation for Java heap 6. Java page migration 7. Contiguous memory allocation 8. Idle pages tracking 9. Per CPU RAM usage tracking 10. ARM NEON scalar multiplication library 11. NEON/ARMv8 crypto extensions 12. NEON SHA, Blake, RIPEMD crypto extensions 13. Parallel NEON crypto engine for multi-algo based CPU stress reduction
49 lines
1.5 KiB
C
49 lines
1.5 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2019 Intel Corporation
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*/
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#ifndef __INTEL_GMBUS_H__
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#define __INTEL_GMBUS_H__
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#include <linux/types.h>
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struct drm_i915_private;
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struct i2c_adapter;
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#define GMBUS_PIN_DISABLED 0
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#define GMBUS_PIN_SSC 1
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#define GMBUS_PIN_VGADDC 2
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#define GMBUS_PIN_PANEL 3
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#define GMBUS_PIN_DPD_CHV 3 /* HDMID_CHV */
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#define GMBUS_PIN_DPC 4 /* HDMIC */
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#define GMBUS_PIN_DPB 5 /* SDVO, HDMIB */
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#define GMBUS_PIN_DPD 6 /* HDMID */
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#define GMBUS_PIN_RESERVED 7 /* 7 reserved */
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#define GMBUS_PIN_1_BXT 1 /* BXT+ (atom) and CNP+ (big core) */
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#define GMBUS_PIN_2_BXT 2
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#define GMBUS_PIN_3_BXT 3
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#define GMBUS_PIN_4_CNP 4
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#define GMBUS_PIN_9_TC1_ICP 9
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#define GMBUS_PIN_10_TC2_ICP 10
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#define GMBUS_PIN_11_TC3_ICP 11
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#define GMBUS_PIN_12_TC4_ICP 12
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#define GMBUS_PIN_13_TC5_TGP 13
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#define GMBUS_PIN_14_TC6_TGP 14
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#define GMBUS_NUM_PINS 15 /* including 0 */
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int intel_gmbus_setup(struct drm_i915_private *dev_priv);
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void intel_gmbus_teardown(struct drm_i915_private *dev_priv);
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bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
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unsigned int pin);
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int intel_gmbus_output_aksv(struct i2c_adapter *adapter);
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struct i2c_adapter *
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intel_gmbus_get_adapter(struct drm_i915_private *dev_priv, unsigned int pin);
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void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
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bool intel_gmbus_is_forced_bit(struct i2c_adapter *adapter);
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void intel_gmbus_reset(struct drm_i915_private *dev_priv);
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#endif /* __INTEL_GMBUS_H__ */
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