forked from Qortal/Brooklyn
31 lines
887 B
Verilog
31 lines
887 B
Verilog
`include "settings.h"
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module Forwarding_Unit (
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input enable,
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input [`REG_FILE_DEPTH-1:0] src1,
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input [`REG_FILE_DEPTH-1:0] src2,
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input [`REG_FILE_DEPTH-1:0] MEM_dest,
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input [`REG_FILE_DEPTH-1:0] WB_dest,
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input MEM_WB_en,
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input WB_WB_en,
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output reg [1:0] sel_src1,
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output reg [1:0] sel_src2
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);
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always @(*) begin
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sel_src1 = `FORWARDING_SEL_NOP;
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sel_src2 = `FORWARDING_SEL_NOP;
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if(enable) begin
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if ((src1 == MEM_dest) && (MEM_WB_en == 1'b1))
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sel_src1 = `FORWARDING_SEL_MEM;
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else if ((src1 == WB_dest) && (WB_WB_en == 1'b1))
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sel_src1 = `FORWARDING_SEL_WB;
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if ((src2 == MEM_dest) && (MEM_WB_en == 1'b1))
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sel_src2 = `FORWARDING_SEL_MEM;
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else if ((src2 == WB_dest) && (WB_WB_en == 1'b1))
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sel_src2 = `FORWARDING_SEL_WB;
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end
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end
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endmodule
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