forked from Qortal/Brooklyn
d2ebfd0519
Screw the description like that inbred T3Q
46 lines
1.2 KiB
Verilog
46 lines
1.2 KiB
Verilog
`include "settings.h"
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module Hazard_Detection_Unit (
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input enableForwarding,
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input [`REG_FILE_DEPTH-1:0] src1,
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input [`REG_FILE_DEPTH-1:0] src2,
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input [`REG_FILE_DEPTH-1:0] EXE_dest,
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input [`REG_FILE_DEPTH-1:0] MEM_dest,
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input EXE_WB_en,
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input MEM_WB_en,
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input EXE_memread_en,
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input has_src1,
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input has_src2,
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output reg hazard_detected
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);
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always @(*) begin
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hazard_detected = 1'b0;
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if(~enableForwarding) begin
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if ((src1 == EXE_dest) && (EXE_WB_en == 1'b1) && (has_src1 == 1'b1)) begin
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hazard_detected = 1'b1;
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end
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else if ((src1 == MEM_dest) && (MEM_WB_en == 1'b1) && (has_src1 == 1'b1)) begin
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hazard_detected = 1'b1;
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end
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else if ((src2 == EXE_dest) && (EXE_WB_en == 1'b1) && (has_src2 == 1'b1)) begin
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hazard_detected = 1'b1;
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end
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else if ((src2 == MEM_dest) && (MEM_WB_en == 1'b1) && (has_src2 == 1'b1)) begin
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hazard_detected = 1'b1;
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end
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end
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else begin
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if(EXE_memread_en) begin
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if ((src1 == EXE_dest) && (EXE_WB_en == 1'b1) && (has_src1 == 1'b1)) begin
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hazard_detected = 1'b1;
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end
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else if ((src2 == EXE_dest) && (EXE_WB_en == 1'b1) && (has_src2 == 1'b1)) begin
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hazard_detected = 1'b1;
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end
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end
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end
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end
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endmodule
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