forked from Qortal/Brooklyn
53 lines
1.5 KiB
Verilog
53 lines
1.5 KiB
Verilog
`include "settings.h"
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module Val2_Generator
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(
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input [`SHIFTER_OPERAND_WIDTH-1:0] shifter_operand,
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input imm, is_for_memory,
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input [`WORD_WIDTH-1:0] val_Rm,
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output reg [`WORD_WIDTH-1:0] val2_out
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);
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reg [`WORD_WIDTH-1:0] _32bit_immd_temp;
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integer i;
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always @(*) begin
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if(is_for_memory == 1'b1)
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val2_out = {20'b0, shifter_operand};
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else if(imm == 1'b1) begin
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_32bit_immd_temp = {24'b0, shifter_operand[7:0]};
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for (i=0; i<{shifter_operand[11:8], 1'b0}; i=i+1) begin
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_32bit_immd_temp = {_32bit_immd_temp[0], _32bit_immd_temp[`WORD_WIDTH-1:1]};
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end
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val2_out = _32bit_immd_temp;
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end
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else begin
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case (shifter_operand[6:5])
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00: begin
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val2_out = val_Rm << shifter_operand[11:7];
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end
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01: begin
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val2_out = val_Rm >> shifter_operand[11:7];
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end
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10: begin
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val2_out = val_Rm >>> shifter_operand[11:7];
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end
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11: begin
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val2_out = val_Rm;
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for (i=0; i<{shifter_operand[11:7]}; i=i+1) begin
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val2_out = {val2_out[0], val2_out[`WORD_WIDTH-1:1]};
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end
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end
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default:begin
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val2_out = val_Rm << shifter_operand[11:7];
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end
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endcase
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end
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end
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endmodule
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