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96 lines
2.1 KiB
Plaintext
96 lines
2.1 KiB
Plaintext
Qualcomm Camera Control Interface (CCI) I2C controller
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PROPERTIES:
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- compatible:
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Usage: required
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Value type: <string>
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Definition: must be one of:
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"qcom,msm8916-cci"
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"qcom,msm8996-cci"
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"qcom,sdm845-cci"
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"qcom,sm8250-cci"
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"qcom,sm8450-cci"
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- reg
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Usage: required
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Value type: <prop-encoded-array>
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Definition: base address CCI I2C controller and length of memory
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mapped region.
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- interrupts:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: specifies the CCI I2C interrupt. The format of the
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specifier is defined by the binding document describing
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the node's interrupt parent.
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- clocks:
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Usage: required
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Value type: <prop-encoded-array>
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Definition: a list of phandle, should contain an entry for each
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entries in clock-names.
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- clock-names
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Usage: required
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Value type: <string>
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Definition: a list of clock names, must include "cci" clock.
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- power-domains
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Usage: required for "qcom,msm8996-cci"
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Value type: <prop-encoded-array>
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Definition:
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SUBNODES:
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The CCI provides I2C masters for one (msm8916) or two i2c busses (msm8996,
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sdm845, sm8250 and sm8450), described as subdevices named "i2c-bus@0" and
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"i2c-bus@1".
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PROPERTIES:
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- reg:
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Usage: required
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Value type: <u32>
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Definition: Index of the CCI bus/master
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- clock-frequency:
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Usage: optional
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Value type: <u32>
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Definition: Desired I2C bus clock frequency in Hz, defaults to 100
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kHz if omitted.
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Example:
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cci@a0c000 {
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compatible = "qcom,msm8996-cci";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xa0c000 0x1000>;
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interrupts = <GIC_SPI 295 IRQ_TYPE_EDGE_RISING>;
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clocks = <&mmcc MMSS_MMAGIC_AHB_CLK>,
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<&mmcc CAMSS_TOP_AHB_CLK>,
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<&mmcc CAMSS_CCI_AHB_CLK>,
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<&mmcc CAMSS_CCI_CLK>,
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<&mmcc CAMSS_AHB_CLK>;
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clock-names = "mmss_mmagic_ahb",
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"camss_top_ahb",
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"cci_ahb",
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"cci",
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"camss_ahb";
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i2c-bus@0 {
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reg = <0>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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i2c-bus@1 {
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reg = <1>;
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clock-frequency = <400000>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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