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* Implement latest sec algo routines for ARM SoC ( experimental for Sinclair beta releases )
This commit is contained in:
Scare Crowe 2021-10-27 13:11:29 +05:00
parent a68fed6dd5
commit 5fda0edaad
24 changed files with 6189 additions and 0 deletions
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Security Algo Accelerator/logical/herculesae_vexecute/verilog/herculesae_vx_aes.sv Normal file
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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aes
(
input wire clk,
input wire reset,
input wire ival_v1_q,
input wire aesd_v1_q,
input wire aese_v1_q,
input wire aesd_or_e_v1_q,
input wire aesmc_v1_q,
input wire aesimc_v1_q,
input wire aesdimc_v1_q,
input wire aesemc_v1_q,
input wire [127:0] opa_v1,
input wire [127:0] opb_v1,
output wire [127:0] aesout_v2
);
wire [15:0] aes_shf_v1;
wire [127:0] aesd_out_v2;
wire [15:0] aesd_shf_v1;
wire [127:0] aesd_v1;
reg aesdimc_h_v2_q;
reg aesdimc_l_v2_q;
wire [127:0] aesdimc_out_v2;
wire [127:0] aese_out_v2;
wire [15:0] aese_shf_v1;
wire [127:0] aese_v1;
wire [127:0] aesed_lut_in_v1;
wire [127:0] aesed_lut_out_v1;
reg aesemc_h_v2_q;
reg aesemc_l_v2_q;
wire [127:0] aesemc_out_v2;
reg aesimc_h_v2_q;
reg aesimc_l_v2_q;
wire [127:0] aesimc_out_v2;
reg aesmc_h_v2_q;
reg aesmc_l_v2_q;
wire [127:0] aesmc_out_v2;
wire block_opa_passthrough;
wire [127:0] opa_aes_nxt_v1;
reg [127:0] opa_aes_v2_q;
wire [127:0] qx_v1;
reg sel_aesd_h_v2_q;
reg sel_aesd_l_v2_q;
wire sel_aesd_v1;
reg sel_aese_h_v2_q;
reg sel_aese_l_v2_q;
wire sel_aese_v1;
assign sel_aesd_v1 = aesd_v1_q & ~aesdimc_v1_q;
assign sel_aese_v1 = aese_v1_q & ~aesemc_v1_q;
assign block_opa_passthrough = aesd_or_e_v1_q;
always_ff @(posedge clk or posedge reset)
begin: u_aesmc_h_v2_q_grp
if (reset == 1'b1) begin
aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
end
else if (reset == 1'b0 && ival_v1_q == 1'b0)
begin
end
else begin
aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
end
`else
else if (ival_v1_q == 1'b1) begin
aesmc_h_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
aesmc_l_v2_q <= `HERCULESAE_DFF_DELAY aesmc_v1_q;
aesimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
aesimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesimc_v1_q;
aesdimc_h_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
aesdimc_l_v2_q <= `HERCULESAE_DFF_DELAY aesdimc_v1_q;
aesemc_h_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
aesemc_l_v2_q <= `HERCULESAE_DFF_DELAY aesemc_v1_q;
sel_aesd_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
sel_aesd_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aesd_v1;
sel_aese_h_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
sel_aese_l_v2_q <= `HERCULESAE_DFF_DELAY sel_aese_v1;
end
`endif
end
assign qx_v1[127:0] = {128{aesd_or_e_v1_q}} & (opb_v1[127:0] ^ opa_v1[127:0]);
herculesae_vx_aese1 u_aese1(
.q (qx_v1[127:0]),
.aese_out (aese_v1[127:0]),
.aese_shf (aese_shf_v1[15:0]));
herculesae_vx_aesd1 u_aesd1(
.q (qx_v1[127:0]),
.aesd_out (aesd_v1[127:0]),
.aesd_shf (aesd_shf_v1[15:0]));
assign aes_shf_v1[15:0] = {16{aese_v1_q}} & aese_shf_v1[15:0] |
{16{aesd_v1_q}} & aesd_shf_v1[15:0];
assign aesed_lut_in_v1[127:0] = ({128{aese_v1_q}} & aese_v1[127:0]) | ({128{aesd_v1_q}} & aesd_v1[127:0]);
herculesae_vx_aesed2_lut u_aesed2_lut_v1(
.lut_in (aesed_lut_in_v1[127:0]),
.lut_out (aesed_lut_out_v1[127:0]));
assign opa_aes_nxt_v1[127:0] = ({128{aesd_or_e_v1_q}} & aesed_lut_out_v1[127:0])
| ({128{~block_opa_passthrough}} & opa_v1[127:0]);
always_ff @(posedge clk or posedge reset)
begin: u_opa_aes_v2_q_127_0
if (reset == 1'b1)
opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v1_q == 1'b1)
opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY opa_aes_nxt_v1[127:0];
else if (reset == 1'b0 && ival_v1_q == 1'b0)
begin
end
else
opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
`else
else if (ival_v1_q == 1'b1)
opa_aes_v2_q[127:0] <= `HERCULESAE_DFF_DELAY opa_aes_nxt_v1[127:0];
`endif
end
herculesae_vx_aesmc u_aesmc(
.d_in (opa_aes_v2_q[127:0]),
.mc (aesmc_out_v2[127:0]));
herculesae_vx_aesimc u_aesimc(
.d_in (opa_aes_v2_q[127:0]),
.imc (aesimc_out_v2[127:0]));
herculesae_vx_aesed2 u_aesed2(
.clk (clk),
.reset (reset),
.ival_v1_q (ival_v1_q),
.aes_din_v1 (aesed_lut_out_v1[127:0]),
.aes_shf_v1 (aes_shf_v1[15:0]),
.aesd_out (aesd_out_v2[127:0]),
.aese_out (aese_out_v2[127:0]),
.aesemc_out (aesemc_out_v2[127:0]),
.aesdimc_out (aesdimc_out_v2[127:0]));
assign aesout_v2[127:64] = ({64{sel_aesd_h_v2_q}} & aesd_out_v2[127:64])
| ({64{sel_aese_h_v2_q}} & aese_out_v2[127:64])
| ({64{aesmc_h_v2_q}} & aesmc_out_v2[127:64])
| ({64{aesemc_h_v2_q}} & aesemc_out_v2[127:64])
| ({64{aesimc_h_v2_q}} & aesimc_out_v2[127:64])
| ({64{aesdimc_h_v2_q}} & aesdimc_out_v2[127:64]);
assign aesout_v2[63:0] = ({64{sel_aesd_l_v2_q}} & aesd_out_v2[63:0])
| ({64{sel_aese_l_v2_q}} & aese_out_v2[63:0])
| ({64{aesmc_l_v2_q}} & aesmc_out_v2[63:0])
| ({64{aesemc_l_v2_q}} & aesemc_out_v2[63:0])
| ({64{aesimc_l_v2_q}} & aesimc_out_v2[63:0])
| ({64{aesdimc_l_v2_q}} & aesdimc_out_v2[63:0]);
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aesd1
(
input wire [127:0] q,
output wire [127:0] aesd_out,
output wire [15:0] aesd_shf
);
wire [127:0] aesd_noshf;
wire [7:0] s00;
wire [7:0] s01;
wire [7:0] s02;
wire [7:0] s03;
wire [7:0] s10;
wire [7:0] s11;
wire [7:0] s12;
wire [7:0] s13;
wire [7:0] s20;
wire [7:0] s21;
wire [7:0] s22;
wire [7:0] s23;
wire [7:0] s30;
wire [7:0] s31;
wire [7:0] s32;
wire [7:0] s33;
wire [7:0] sp00;
wire [7:0] sp01;
wire [7:0] sp02;
wire [7:0] sp03;
wire [7:0] sp10;
wire [7:0] sp11;
wire [7:0] sp12;
wire [7:0] sp13;
wire [7:0] sp20;
wire [7:0] sp21;
wire [7:0] sp22;
wire [7:0] sp23;
wire [7:0] sp30;
wire [7:0] sp31;
wire [7:0] sp32;
wire [7:0] sp33;
assign s33[7:0] = q[127:120];
assign s23[7:0] = q[119:112];
assign s13[7:0] = q[111:104];
assign s03[7:0] = q[103:96];
assign s32[7:0] = q[95:88];
assign s22[7:0] = q[87:80];
assign s12[7:0] = q[79:72];
assign s02[7:0] = q[71:64];
assign s31[7:0] = q[63:56];
assign s21[7:0] = q[55:48];
assign s11[7:0] = q[47:40];
assign s01[7:0] = q[39:32];
assign s30[7:0] = q[31:24];
assign s20[7:0] = q[23:16];
assign s10[7:0] = q[15:8];
assign s00[7:0] = q[7:0];
assign sp00[7:0] = s00[7:0];
assign sp01[7:0] = s01[7:0];
assign sp02[7:0] = s02[7:0];
assign sp03[7:0] = s03[7:0];
assign sp10[7:0] = s13[7:0];
assign sp11[7:0] = s10[7:0];
assign sp12[7:0] = s11[7:0];
assign sp13[7:0] = s12[7:0];
assign sp20[7:0] = s22[7:0];
assign sp21[7:0] = s23[7:0];
assign sp22[7:0] = s20[7:0];
assign sp23[7:0] = s21[7:0];
assign sp30[7:0] = s31[7:0];
assign sp31[7:0] = s32[7:0];
assign sp32[7:0] = s33[7:0];
assign sp33[7:0] = s30[7:0];
assign aesd_noshf[0] = sp00[2] ^ sp00[5] ^ sp00[7] ^ 1'b1;
assign aesd_noshf[1] = sp00[0] ^ sp00[3] ^ sp00[6] ^ 1'b0;
assign aesd_noshf[2] = sp00[1] ^ sp00[4] ^ sp00[7] ^ 1'b1;
assign aesd_noshf[3] = sp00[0] ^ sp00[2] ^ sp00[5] ^ 1'b0;
assign aesd_noshf[4] = sp00[1] ^ sp00[3] ^ sp00[6] ^ 1'b0;
assign aesd_noshf[5] = sp00[2] ^ sp00[4] ^ sp00[7] ^ 1'b0;
assign aesd_noshf[6] = sp00[0] ^ sp00[3] ^ sp00[5] ^ 1'b0;
assign aesd_noshf[7] = sp00[1] ^ sp00[4] ^ sp00[6] ^ 1'b0;
assign aesd_noshf[32] = sp01[2] ^ sp01[5] ^ sp01[7] ^ 1'b1;
assign aesd_noshf[33] = sp01[0] ^ sp01[3] ^ sp01[6] ^ 1'b0;
assign aesd_noshf[34] = sp01[1] ^ sp01[4] ^ sp01[7] ^ 1'b1;
assign aesd_noshf[35] = sp01[0] ^ sp01[2] ^ sp01[5] ^ 1'b0;
assign aesd_noshf[36] = sp01[1] ^ sp01[3] ^ sp01[6] ^ 1'b0;
assign aesd_noshf[37] = sp01[2] ^ sp01[4] ^ sp01[7] ^ 1'b0;
assign aesd_noshf[38] = sp01[0] ^ sp01[3] ^ sp01[5] ^ 1'b0;
assign aesd_noshf[39] = sp01[1] ^ sp01[4] ^ sp01[6] ^ 1'b0;
assign aesd_noshf[64] = sp02[2] ^ sp02[5] ^ sp02[7] ^ 1'b1;
assign aesd_noshf[65] = sp02[0] ^ sp02[3] ^ sp02[6] ^ 1'b0;
assign aesd_noshf[66] = sp02[1] ^ sp02[4] ^ sp02[7] ^ 1'b1;
assign aesd_noshf[67] = sp02[0] ^ sp02[2] ^ sp02[5] ^ 1'b0;
assign aesd_noshf[68] = sp02[1] ^ sp02[3] ^ sp02[6] ^ 1'b0;
assign aesd_noshf[69] = sp02[2] ^ sp02[4] ^ sp02[7] ^ 1'b0;
assign aesd_noshf[70] = sp02[0] ^ sp02[3] ^ sp02[5] ^ 1'b0;
assign aesd_noshf[71] = sp02[1] ^ sp02[4] ^ sp02[6] ^ 1'b0;
assign aesd_noshf[96] = sp03[2] ^ sp03[5] ^ sp03[7] ^ 1'b1;
assign aesd_noshf[97] = sp03[0] ^ sp03[3] ^ sp03[6] ^ 1'b0;
assign aesd_noshf[98] = sp03[1] ^ sp03[4] ^ sp03[7] ^ 1'b1;
assign aesd_noshf[99] = sp03[0] ^ sp03[2] ^ sp03[5] ^ 1'b0;
assign aesd_noshf[100] = sp03[1] ^ sp03[3] ^ sp03[6] ^ 1'b0;
assign aesd_noshf[101] = sp03[2] ^ sp03[4] ^ sp03[7] ^ 1'b0;
assign aesd_noshf[102] = sp03[0] ^ sp03[3] ^ sp03[5] ^ 1'b0;
assign aesd_noshf[103] = sp03[1] ^ sp03[4] ^ sp03[6] ^ 1'b0;
assign aesd_noshf[8] = sp10[2] ^ sp10[5] ^ sp10[7] ^ 1'b1;
assign aesd_noshf[9] = sp10[0] ^ sp10[3] ^ sp10[6] ^ 1'b0;
assign aesd_noshf[10] = sp10[1] ^ sp10[4] ^ sp10[7] ^ 1'b1;
assign aesd_noshf[11] = sp10[0] ^ sp10[2] ^ sp10[5] ^ 1'b0;
assign aesd_noshf[12] = sp10[1] ^ sp10[3] ^ sp10[6] ^ 1'b0;
assign aesd_noshf[13] = sp10[2] ^ sp10[4] ^ sp10[7] ^ 1'b0;
assign aesd_noshf[14] = sp10[0] ^ sp10[3] ^ sp10[5] ^ 1'b0;
assign aesd_noshf[15] = sp10[1] ^ sp10[4] ^ sp10[6] ^ 1'b0;
assign aesd_noshf[40] = sp11[2] ^ sp11[5] ^ sp11[7] ^ 1'b1;
assign aesd_noshf[41] = sp11[0] ^ sp11[3] ^ sp11[6] ^ 1'b0;
assign aesd_noshf[42] = sp11[1] ^ sp11[4] ^ sp11[7] ^ 1'b1;
assign aesd_noshf[43] = sp11[0] ^ sp11[2] ^ sp11[5] ^ 1'b0;
assign aesd_noshf[44] = sp11[1] ^ sp11[3] ^ sp11[6] ^ 1'b0;
assign aesd_noshf[45] = sp11[2] ^ sp11[4] ^ sp11[7] ^ 1'b0;
assign aesd_noshf[46] = sp11[0] ^ sp11[3] ^ sp11[5] ^ 1'b0;
assign aesd_noshf[47] = sp11[1] ^ sp11[4] ^ sp11[6] ^ 1'b0;
assign aesd_noshf[72] = sp12[2] ^ sp12[5] ^ sp12[7] ^ 1'b1;
assign aesd_noshf[73] = sp12[0] ^ sp12[3] ^ sp12[6] ^ 1'b0;
assign aesd_noshf[74] = sp12[1] ^ sp12[4] ^ sp12[7] ^ 1'b1;
assign aesd_noshf[75] = sp12[0] ^ sp12[2] ^ sp12[5] ^ 1'b0;
assign aesd_noshf[76] = sp12[1] ^ sp12[3] ^ sp12[6] ^ 1'b0;
assign aesd_noshf[77] = sp12[2] ^ sp12[4] ^ sp12[7] ^ 1'b0;
assign aesd_noshf[78] = sp12[0] ^ sp12[3] ^ sp12[5] ^ 1'b0;
assign aesd_noshf[79] = sp12[1] ^ sp12[4] ^ sp12[6] ^ 1'b0;
assign aesd_noshf[104] = sp13[2] ^ sp13[5] ^ sp13[7] ^ 1'b1;
assign aesd_noshf[105] = sp13[0] ^ sp13[3] ^ sp13[6] ^ 1'b0;
assign aesd_noshf[106] = sp13[1] ^ sp13[4] ^ sp13[7] ^ 1'b1;
assign aesd_noshf[107] = sp13[0] ^ sp13[2] ^ sp13[5] ^ 1'b0;
assign aesd_noshf[108] = sp13[1] ^ sp13[3] ^ sp13[6] ^ 1'b0;
assign aesd_noshf[109] = sp13[2] ^ sp13[4] ^ sp13[7] ^ 1'b0;
assign aesd_noshf[110] = sp13[0] ^ sp13[3] ^ sp13[5] ^ 1'b0;
assign aesd_noshf[111] = sp13[1] ^ sp13[4] ^ sp13[6] ^ 1'b0;
assign aesd_noshf[16] = sp20[2] ^ sp20[5] ^ sp20[7] ^ 1'b1;
assign aesd_noshf[17] = sp20[0] ^ sp20[3] ^ sp20[6] ^ 1'b0;
assign aesd_noshf[18] = sp20[1] ^ sp20[4] ^ sp20[7] ^ 1'b1;
assign aesd_noshf[19] = sp20[0] ^ sp20[2] ^ sp20[5] ^ 1'b0;
assign aesd_noshf[20] = sp20[1] ^ sp20[3] ^ sp20[6] ^ 1'b0;
assign aesd_noshf[21] = sp20[2] ^ sp20[4] ^ sp20[7] ^ 1'b0;
assign aesd_noshf[22] = sp20[0] ^ sp20[3] ^ sp20[5] ^ 1'b0;
assign aesd_noshf[23] = sp20[1] ^ sp20[4] ^ sp20[6] ^ 1'b0;
assign aesd_noshf[48] = sp21[2] ^ sp21[5] ^ sp21[7] ^ 1'b1;
assign aesd_noshf[49] = sp21[0] ^ sp21[3] ^ sp21[6] ^ 1'b0;
assign aesd_noshf[50] = sp21[1] ^ sp21[4] ^ sp21[7] ^ 1'b1;
assign aesd_noshf[51] = sp21[0] ^ sp21[2] ^ sp21[5] ^ 1'b0;
assign aesd_noshf[52] = sp21[1] ^ sp21[3] ^ sp21[6] ^ 1'b0;
assign aesd_noshf[53] = sp21[2] ^ sp21[4] ^ sp21[7] ^ 1'b0;
assign aesd_noshf[54] = sp21[0] ^ sp21[3] ^ sp21[5] ^ 1'b0;
assign aesd_noshf[55] = sp21[1] ^ sp21[4] ^ sp21[6] ^ 1'b0;
assign aesd_noshf[80] = sp22[2] ^ sp22[5] ^ sp22[7] ^ 1'b1;
assign aesd_noshf[81] = sp22[0] ^ sp22[3] ^ sp22[6] ^ 1'b0;
assign aesd_noshf[82] = sp22[1] ^ sp22[4] ^ sp22[7] ^ 1'b1;
assign aesd_noshf[83] = sp22[0] ^ sp22[2] ^ sp22[5] ^ 1'b0;
assign aesd_noshf[84] = sp22[1] ^ sp22[3] ^ sp22[6] ^ 1'b0;
assign aesd_noshf[85] = sp22[2] ^ sp22[4] ^ sp22[7] ^ 1'b0;
assign aesd_noshf[86] = sp22[0] ^ sp22[3] ^ sp22[5] ^ 1'b0;
assign aesd_noshf[87] = sp22[1] ^ sp22[4] ^ sp22[6] ^ 1'b0;
assign aesd_noshf[112] = sp23[2] ^ sp23[5] ^ sp23[7] ^ 1'b1;
assign aesd_noshf[113] = sp23[0] ^ sp23[3] ^ sp23[6] ^ 1'b0;
assign aesd_noshf[114] = sp23[1] ^ sp23[4] ^ sp23[7] ^ 1'b1;
assign aesd_noshf[115] = sp23[0] ^ sp23[2] ^ sp23[5] ^ 1'b0;
assign aesd_noshf[116] = sp23[1] ^ sp23[3] ^ sp23[6] ^ 1'b0;
assign aesd_noshf[117] = sp23[2] ^ sp23[4] ^ sp23[7] ^ 1'b0;
assign aesd_noshf[118] = sp23[0] ^ sp23[3] ^ sp23[5] ^ 1'b0;
assign aesd_noshf[119] = sp23[1] ^ sp23[4] ^ sp23[6] ^ 1'b0;
assign aesd_noshf[24] = sp30[2] ^ sp30[5] ^ sp30[7] ^ 1'b1;
assign aesd_noshf[25] = sp30[0] ^ sp30[3] ^ sp30[6] ^ 1'b0;
assign aesd_noshf[26] = sp30[1] ^ sp30[4] ^ sp30[7] ^ 1'b1;
assign aesd_noshf[27] = sp30[0] ^ sp30[2] ^ sp30[5] ^ 1'b0;
assign aesd_noshf[28] = sp30[1] ^ sp30[3] ^ sp30[6] ^ 1'b0;
assign aesd_noshf[29] = sp30[2] ^ sp30[4] ^ sp30[7] ^ 1'b0;
assign aesd_noshf[30] = sp30[0] ^ sp30[3] ^ sp30[5] ^ 1'b0;
assign aesd_noshf[31] = sp30[1] ^ sp30[4] ^ sp30[6] ^ 1'b0;
assign aesd_noshf[56] = sp31[2] ^ sp31[5] ^ sp31[7] ^ 1'b1;
assign aesd_noshf[57] = sp31[0] ^ sp31[3] ^ sp31[6] ^ 1'b0;
assign aesd_noshf[58] = sp31[1] ^ sp31[4] ^ sp31[7] ^ 1'b1;
assign aesd_noshf[59] = sp31[0] ^ sp31[2] ^ sp31[5] ^ 1'b0;
assign aesd_noshf[60] = sp31[1] ^ sp31[3] ^ sp31[6] ^ 1'b0;
assign aesd_noshf[61] = sp31[2] ^ sp31[4] ^ sp31[7] ^ 1'b0;
assign aesd_noshf[62] = sp31[0] ^ sp31[3] ^ sp31[5] ^ 1'b0;
assign aesd_noshf[63] = sp31[1] ^ sp31[4] ^ sp31[6] ^ 1'b0;
assign aesd_noshf[88] = sp32[2] ^ sp32[5] ^ sp32[7] ^ 1'b1;
assign aesd_noshf[89] = sp32[0] ^ sp32[3] ^ sp32[6] ^ 1'b0;
assign aesd_noshf[90] = sp32[1] ^ sp32[4] ^ sp32[7] ^ 1'b1;
assign aesd_noshf[91] = sp32[0] ^ sp32[2] ^ sp32[5] ^ 1'b0;
assign aesd_noshf[92] = sp32[1] ^ sp32[3] ^ sp32[6] ^ 1'b0;
assign aesd_noshf[93] = sp32[2] ^ sp32[4] ^ sp32[7] ^ 1'b0;
assign aesd_noshf[94] = sp32[0] ^ sp32[3] ^ sp32[5] ^ 1'b0;
assign aesd_noshf[95] = sp32[1] ^ sp32[4] ^ sp32[6] ^ 1'b0;
assign aesd_noshf[120] = sp33[2] ^ sp33[5] ^ sp33[7] ^ 1'b1;
assign aesd_noshf[121] = sp33[0] ^ sp33[3] ^ sp33[6] ^ 1'b0;
assign aesd_noshf[122] = sp33[1] ^ sp33[4] ^ sp33[7] ^ 1'b1;
assign aesd_noshf[123] = sp33[0] ^ sp33[2] ^ sp33[5] ^ 1'b0;
assign aesd_noshf[124] = sp33[1] ^ sp33[3] ^ sp33[6] ^ 1'b0;
assign aesd_noshf[125] = sp33[2] ^ sp33[4] ^ sp33[7] ^ 1'b0;
assign aesd_noshf[126] = sp33[0] ^ sp33[3] ^ sp33[5] ^ 1'b0;
assign aesd_noshf[127] = sp33[1] ^ sp33[4] ^ sp33[6] ^ 1'b0;
assign aesd_shf[15] = ~aesd_noshf[127];
assign aesd_shf[14] = ~aesd_noshf[119];
assign aesd_shf[13] = ~aesd_noshf[111];
assign aesd_shf[12] = ~aesd_noshf[103];
assign aesd_shf[11] = ~aesd_noshf[ 95];
assign aesd_shf[10] = ~aesd_noshf[ 87];
assign aesd_shf[ 9] = ~aesd_noshf[ 79];
assign aesd_shf[ 8] = ~aesd_noshf[ 71];
assign aesd_shf[ 7] = ~aesd_noshf[ 63];
assign aesd_shf[ 6] = ~aesd_noshf[ 55];
assign aesd_shf[ 5] = ~aesd_noshf[ 47];
assign aesd_shf[ 4] = ~aesd_noshf[ 39];
assign aesd_shf[ 3] = ~aesd_noshf[ 31];
assign aesd_shf[ 2] = ~aesd_noshf[ 23];
assign aesd_shf[ 1] = ~aesd_noshf[ 15];
assign aesd_shf[ 0] = ~aesd_noshf[ 7];
assign aesd_out[127:120] = {8{ aesd_shf[15]}} & {aesd_noshf[126:120], 1'b0} |
{8{~aesd_shf[15]}} & aesd_noshf[127:120];
assign aesd_out[119:112] = {8{ aesd_shf[14]}} & {aesd_noshf[118:112], 1'b0} |
{8{~aesd_shf[14]}} & aesd_noshf[119:112];
assign aesd_out[111:104] = {8{ aesd_shf[13]}} & {aesd_noshf[110:104], 1'b0} |
{8{~aesd_shf[13]}} & aesd_noshf[111:104];
assign aesd_out[103: 96] = {8{ aesd_shf[12]}} & {aesd_noshf[102: 96], 1'b0} |
{8{~aesd_shf[12]}} & aesd_noshf[103: 96];
assign aesd_out[ 95: 88] = {8{ aesd_shf[11]}} & {aesd_noshf[ 94: 88], 1'b0} |
{8{~aesd_shf[11]}} & aesd_noshf[ 95: 88];
assign aesd_out[ 87: 80] = {8{ aesd_shf[10]}} & {aesd_noshf[ 86: 80], 1'b0} |
{8{~aesd_shf[10]}} & aesd_noshf[ 87: 80];
assign aesd_out[ 79: 72] = {8{ aesd_shf[ 9]}} & {aesd_noshf[ 78: 72], 1'b0} |
{8{~aesd_shf[ 9]}} & aesd_noshf[ 79: 72];
assign aesd_out[ 71: 64] = {8{ aesd_shf[ 8]}} & {aesd_noshf[ 70: 64], 1'b0} |
{8{~aesd_shf[ 8]}} & aesd_noshf[ 71: 64];
assign aesd_out[ 63: 56] = {8{ aesd_shf[ 7]}} & {aesd_noshf[ 62: 56], 1'b0} |
{8{~aesd_shf[ 7]}} & aesd_noshf[ 63: 56];
assign aesd_out[ 55: 48] = {8{ aesd_shf[ 6]}} & {aesd_noshf[ 54: 48], 1'b0} |
{8{~aesd_shf[ 6]}} & aesd_noshf[ 55: 48];
assign aesd_out[ 47: 40] = {8{ aesd_shf[ 5]}} & {aesd_noshf[ 46: 40], 1'b0} |
{8{~aesd_shf[ 5]}} & aesd_noshf[ 47: 40];
assign aesd_out[ 39: 32] = {8{ aesd_shf[ 4]}} & {aesd_noshf[ 38: 32], 1'b0} |
{8{~aesd_shf[ 4]}} & aesd_noshf[ 39: 32];
assign aesd_out[ 31: 24] = {8{ aesd_shf[ 3]}} & {aesd_noshf[ 30: 24], 1'b0} |
{8{~aesd_shf[ 3]}} & aesd_noshf[ 31: 24];
assign aesd_out[ 23: 16] = {8{ aesd_shf[ 2]}} & {aesd_noshf[ 22: 16], 1'b0} |
{8{~aesd_shf[ 2]}} & aesd_noshf[ 23: 16];
assign aesd_out[ 15: 8] = {8{ aesd_shf[ 1]}} & {aesd_noshf[ 14: 8], 1'b0} |
{8{~aesd_shf[ 1]}} & aesd_noshf[ 15: 8];
assign aesd_out[ 7: 0] = {8{ aesd_shf[ 0]}} & {aesd_noshf[ 6: 0], 1'b0} |
{8{~aesd_shf[ 0]}} & aesd_noshf[ 7: 0];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aese1
(
input wire [127:0] q,
output wire [127:0] aese_out,
output wire [15:0] aese_shf
);
wire [127:0] aese_noshf;
wire [7:0] s00;
wire [7:0] s01;
wire [7:0] s02;
wire [7:0] s03;
wire [7:0] s10;
wire [7:0] s11;
wire [7:0] s12;
wire [7:0] s13;
wire [7:0] s20;
wire [7:0] s21;
wire [7:0] s22;
wire [7:0] s23;
wire [7:0] s30;
wire [7:0] s31;
wire [7:0] s32;
wire [7:0] s33;
assign s33[7:0] = q[127:120];
assign s23[7:0] = q[119:112];
assign s13[7:0] = q[111:104];
assign s03[7:0] = q[103:96];
assign s32[7:0] = q[95:88];
assign s22[7:0] = q[87:80];
assign s12[7:0] = q[79:72];
assign s02[7:0] = q[71:64];
assign s31[7:0] = q[63:56];
assign s21[7:0] = q[55:48];
assign s11[7:0] = q[47:40];
assign s01[7:0] = q[39:32];
assign s30[7:0] = q[31:24];
assign s20[7:0] = q[23:16];
assign s10[7:0] = q[15:8];
assign s00[7:0] = q[7:0];
assign aese_noshf[7:0] = s00[7:0];
assign aese_noshf[39:32] = s01[7:0];
assign aese_noshf[71:64] = s02[7:0];
assign aese_noshf[103:96] = s03[7:0];
assign aese_noshf[15:8] = s11[7:0];
assign aese_noshf[47:40] = s12[7:0];
assign aese_noshf[79:72] = s13[7:0];
assign aese_noshf[111:104] = s10[7:0];
assign aese_noshf[23:16] = s22[7:0];
assign aese_noshf[55:48] = s23[7:0];
assign aese_noshf[87:80] = s20[7:0];
assign aese_noshf[119:112] = s21[7:0];
assign aese_noshf[31:24] = s33[7:0];
assign aese_noshf[63:56] = s30[7:0];
assign aese_noshf[95:88] = s31[7:0];
assign aese_noshf[127:120] = s32[7:0];
assign aese_shf[15] = ~aese_noshf[127];
assign aese_shf[14] = ~aese_noshf[119];
assign aese_shf[13] = ~aese_noshf[111];
assign aese_shf[12] = ~aese_noshf[103];
assign aese_shf[11] = ~aese_noshf[ 95];
assign aese_shf[10] = ~aese_noshf[ 87];
assign aese_shf[ 9] = ~aese_noshf[ 79];
assign aese_shf[ 8] = ~aese_noshf[ 71];
assign aese_shf[ 7] = ~aese_noshf[ 63];
assign aese_shf[ 6] = ~aese_noshf[ 55];
assign aese_shf[ 5] = ~aese_noshf[ 47];
assign aese_shf[ 4] = ~aese_noshf[ 39];
assign aese_shf[ 3] = ~aese_noshf[ 31];
assign aese_shf[ 2] = ~aese_noshf[ 23];
assign aese_shf[ 1] = ~aese_noshf[ 15];
assign aese_shf[ 0] = ~aese_noshf[ 7];
assign aese_out[127:120] = {8{ aese_shf[15]}} & {aese_noshf[126:120], 1'b0} |
{8{~aese_shf[15]}} & aese_noshf[127:120];
assign aese_out[119:112] = {8{ aese_shf[14]}} & {aese_noshf[118:112], 1'b0} |
{8{~aese_shf[14]}} & aese_noshf[119:112];
assign aese_out[111:104] = {8{ aese_shf[13]}} & {aese_noshf[110:104], 1'b0} |
{8{~aese_shf[13]}} & aese_noshf[111:104];
assign aese_out[103: 96] = {8{ aese_shf[12]}} & {aese_noshf[102: 96], 1'b0} |
{8{~aese_shf[12]}} & aese_noshf[103: 96];
assign aese_out[ 95: 88] = {8{ aese_shf[11]}} & {aese_noshf[ 94: 88], 1'b0} |
{8{~aese_shf[11]}} & aese_noshf[ 95: 88];
assign aese_out[ 87: 80] = {8{ aese_shf[10]}} & {aese_noshf[ 86: 80], 1'b0} |
{8{~aese_shf[10]}} & aese_noshf[ 87: 80];
assign aese_out[ 79: 72] = {8{ aese_shf[ 9]}} & {aese_noshf[ 78: 72], 1'b0} |
{8{~aese_shf[ 9]}} & aese_noshf[ 79: 72];
assign aese_out[ 71: 64] = {8{ aese_shf[ 8]}} & {aese_noshf[ 70: 64], 1'b0} |
{8{~aese_shf[ 8]}} & aese_noshf[ 71: 64];
assign aese_out[ 63: 56] = {8{ aese_shf[ 7]}} & {aese_noshf[ 62: 56], 1'b0} |
{8{~aese_shf[ 7]}} & aese_noshf[ 63: 56];
assign aese_out[ 55: 48] = {8{ aese_shf[ 6]}} & {aese_noshf[ 54: 48], 1'b0} |
{8{~aese_shf[ 6]}} & aese_noshf[ 55: 48];
assign aese_out[ 47: 40] = {8{ aese_shf[ 5]}} & {aese_noshf[ 46: 40], 1'b0} |
{8{~aese_shf[ 5]}} & aese_noshf[ 47: 40];
assign aese_out[ 39: 32] = {8{ aese_shf[ 4]}} & {aese_noshf[ 38: 32], 1'b0} |
{8{~aese_shf[ 4]}} & aese_noshf[ 39: 32];
assign aese_out[ 31: 24] = {8{ aese_shf[ 3]}} & {aese_noshf[ 30: 24], 1'b0} |
{8{~aese_shf[ 3]}} & aese_noshf[ 31: 24];
assign aese_out[ 23: 16] = {8{ aese_shf[ 2]}} & {aese_noshf[ 22: 16], 1'b0} |
{8{~aese_shf[ 2]}} & aese_noshf[ 23: 16];
assign aese_out[ 15: 8] = {8{ aese_shf[ 1]}} & {aese_noshf[ 14: 8], 1'b0} |
{8{~aese_shf[ 1]}} & aese_noshf[ 15: 8];
assign aese_out[ 7: 0] = {8{ aese_shf[ 0]}} & {aese_noshf[ 6: 0], 1'b0} |
{8{~aese_shf[ 0]}} & aese_noshf[ 7: 0];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aesed2
(
input wire clk,
input wire reset,
input wire ival_v1_q,
input wire [127:0] aes_din_v1,
input wire [15:0] aes_shf_v1,
output wire [127:0] aesd_out,
output wire [127:0] aese_out,
output wire [127:0] aesemc_out,
output wire [127:0] aesdimc_out
);
wire [127:0] aesimc_in;
wire [127:0] aesmc_in;
wire [7:0] b00_corr_v1;
wire [7:0] b00_redn_v1;
reg [7:0] b00_redn_v2_q;
wire [7:0] b00_shf_v1;
wire [7:0] b00_v1;
wire [7:0] b01_corr_v1;
wire [7:0] b01_redn_v1;
reg [7:0] b01_redn_v2_q;
wire [7:0] b01_shf_v1;
wire [7:0] b01_v1;
wire [7:0] b02_corr_v1;
wire [7:0] b02_redn_v1;
reg [7:0] b02_redn_v2_q;
wire [7:0] b02_shf_v1;
wire [7:0] b02_v1;
wire [7:0] b03_corr_v1;
wire [7:0] b03_redn_v1;
reg [7:0] b03_redn_v2_q;
wire [7:0] b03_shf_v1;
wire [7:0] b03_v1;
wire [7:0] b10_corr_v1;
wire [7:0] b10_redn_v1;
reg [7:0] b10_redn_v2_q;
wire [7:0] b10_shf_v1;
wire [7:0] b10_v1;
wire [7:0] b11_corr_v1;
wire [7:0] b11_redn_v1;
reg [7:0] b11_redn_v2_q;
wire [7:0] b11_shf_v1;
wire [7:0] b11_v1;
wire [7:0] b12_corr_v1;
wire [7:0] b12_redn_v1;
reg [7:0] b12_redn_v2_q;
wire [7:0] b12_shf_v1;
wire [7:0] b12_v1;
wire [7:0] b13_corr_v1;
wire [7:0] b13_redn_v1;
reg [7:0] b13_redn_v2_q;
wire [7:0] b13_shf_v1;
wire [7:0] b13_v1;
wire [7:0] b20_corr_v1;
wire [7:0] b20_redn_v1;
reg [7:0] b20_redn_v2_q;
wire [7:0] b20_shf_v1;
wire [7:0] b20_v1;
wire [7:0] b21_corr_v1;
wire [7:0] b21_redn_v1;
reg [7:0] b21_redn_v2_q;
wire [7:0] b21_shf_v1;
wire [7:0] b21_v1;
wire [7:0] b22_corr_v1;
wire [7:0] b22_redn_v1;
reg [7:0] b22_redn_v2_q;
wire [7:0] b22_shf_v1;
wire [7:0] b22_v1;
wire [7:0] b23_corr_v1;
wire [7:0] b23_redn_v1;
reg [7:0] b23_redn_v2_q;
wire [7:0] b23_shf_v1;
wire [7:0] b23_v1;
wire [7:0] b30_corr_v1;
wire [7:0] b30_redn_v1;
reg [7:0] b30_redn_v2_q;
wire [7:0] b30_shf_v1;
wire [7:0] b30_v1;
wire [7:0] b31_corr_v1;
wire [7:0] b31_redn_v1;
reg [7:0] b31_redn_v2_q;
wire [7:0] b31_shf_v1;
wire [7:0] b31_v1;
wire [7:0] b32_corr_v1;
wire [7:0] b32_redn_v1;
reg [7:0] b32_redn_v2_q;
wire [7:0] b32_shf_v1;
wire [7:0] b32_v1;
wire [7:0] b33_corr_v1;
wire [7:0] b33_redn_v1;
reg [7:0] b33_redn_v2_q;
wire [7:0] b33_shf_v1;
wire [7:0] b33_v1;
assign b33_v1[7:0] = aes_din_v1[127:120];
assign b23_v1[7:0] = aes_din_v1[119:112];
assign b13_v1[7:0] = aes_din_v1[111:104];
assign b03_v1[7:0] = aes_din_v1[103:96];
assign b32_v1[7:0] = aes_din_v1[95:88];
assign b22_v1[7:0] = aes_din_v1[87:80];
assign b12_v1[7:0] = aes_din_v1[79:72];
assign b02_v1[7:0] = aes_din_v1[71:64];
assign b31_v1[7:0] = aes_din_v1[63:56];
assign b21_v1[7:0] = aes_din_v1[55:48];
assign b11_v1[7:0] = aes_din_v1[47:40];
assign b01_v1[7:0] = aes_din_v1[39:32];
assign b30_v1[7:0] = aes_din_v1[31:24];
assign b20_v1[7:0] = aes_din_v1[23:16];
assign b10_v1[7:0] = aes_din_v1[15:8];
assign b00_v1[7:0] = aes_din_v1[7:0];
assign b33_shf_v1[7:0] = {8{ aes_shf_v1[15]}} & {b33_v1[6:0], 1'b0} |
{8{~aes_shf_v1[15]}} & {b33_v1[7:0]};
assign b23_shf_v1[7:0] = {8{ aes_shf_v1[14]}} & {b23_v1[6:0], 1'b0} |
{8{~aes_shf_v1[14]}} & {b23_v1[7:0]};
assign b13_shf_v1[7:0] = {8{ aes_shf_v1[13]}} & {b13_v1[6:0], 1'b0} |
{8{~aes_shf_v1[13]}} & {b13_v1[7:0]};
assign b03_shf_v1[7:0] = {8{ aes_shf_v1[12]}} & {b03_v1[6:0], 1'b0} |
{8{~aes_shf_v1[12]}} & {b03_v1[7:0]};
assign b32_shf_v1[7:0] = {8{ aes_shf_v1[11]}} & {b32_v1[6:0], 1'b0} |
{8{~aes_shf_v1[11]}} & {b32_v1[7:0]};
assign b22_shf_v1[7:0] = {8{ aes_shf_v1[10]}} & {b22_v1[6:0], 1'b0} |
{8{~aes_shf_v1[10]}} & {b22_v1[7:0]};
assign b12_shf_v1[7:0] = {8{ aes_shf_v1[ 9]}} & {b12_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 9]}} & {b12_v1[7:0]};
assign b02_shf_v1[7:0] = {8{ aes_shf_v1[ 8]}} & {b02_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 8]}} & {b02_v1[7:0]};
assign b31_shf_v1[7:0] = {8{ aes_shf_v1[ 7]}} & {b31_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 7]}} & {b31_v1[7:0]};
assign b21_shf_v1[7:0] = {8{ aes_shf_v1[ 6]}} & {b21_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 6]}} & {b21_v1[7:0]};
assign b11_shf_v1[7:0] = {8{ aes_shf_v1[ 5]}} & {b11_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 5]}} & {b11_v1[7:0]};
assign b01_shf_v1[7:0] = {8{ aes_shf_v1[ 4]}} & {b01_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 4]}} & {b01_v1[7:0]};
assign b30_shf_v1[7:0] = {8{ aes_shf_v1[ 3]}} & {b30_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 3]}} & {b30_v1[7:0]};
assign b20_shf_v1[7:0] = {8{ aes_shf_v1[ 2]}} & {b20_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 2]}} & {b20_v1[7:0]};
assign b10_shf_v1[7:0] = {8{ aes_shf_v1[ 1]}} & {b10_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 1]}} & {b10_v1[7:0]};
assign b00_shf_v1[7:0] = {8{ aes_shf_v1[ 0]}} & {b00_v1[6:0], 1'b0} |
{8{~aes_shf_v1[ 0]}} & {b00_v1[7:0]};
assign b33_corr_v1[7:0] = {8{aes_shf_v1[15]}} & {8{b33_v1[7]}} & 8'h1b;
assign b23_corr_v1[7:0] = {8{aes_shf_v1[14]}} & {8{b23_v1[7]}} & 8'h1b;
assign b13_corr_v1[7:0] = {8{aes_shf_v1[13]}} & {8{b13_v1[7]}} & 8'h1b;
assign b03_corr_v1[7:0] = {8{aes_shf_v1[12]}} & {8{b03_v1[7]}} & 8'h1b;
assign b32_corr_v1[7:0] = {8{aes_shf_v1[11]}} & {8{b32_v1[7]}} & 8'h1b;
assign b22_corr_v1[7:0] = {8{aes_shf_v1[10]}} & {8{b22_v1[7]}} & 8'h1b;
assign b12_corr_v1[7:0] = {8{aes_shf_v1[ 9]}} & {8{b12_v1[7]}} & 8'h1b;
assign b02_corr_v1[7:0] = {8{aes_shf_v1[ 8]}} & {8{b02_v1[7]}} & 8'h1b;
assign b31_corr_v1[7:0] = {8{aes_shf_v1[ 7]}} & {8{b31_v1[7]}} & 8'h1b;
assign b21_corr_v1[7:0] = {8{aes_shf_v1[ 6]}} & {8{b21_v1[7]}} & 8'h1b;
assign b11_corr_v1[7:0] = {8{aes_shf_v1[ 5]}} & {8{b11_v1[7]}} & 8'h1b;
assign b01_corr_v1[7:0] = {8{aes_shf_v1[ 4]}} & {8{b01_v1[7]}} & 8'h1b;
assign b30_corr_v1[7:0] = {8{aes_shf_v1[ 3]}} & {8{b30_v1[7]}} & 8'h1b;
assign b20_corr_v1[7:0] = {8{aes_shf_v1[ 2]}} & {8{b20_v1[7]}} & 8'h1b;
assign b10_corr_v1[7:0] = {8{aes_shf_v1[ 1]}} & {8{b10_v1[7]}} & 8'h1b;
assign b00_corr_v1[7:0] = {8{aes_shf_v1[ 0]}} & {8{b00_v1[7]}} & 8'h1b;
assign b33_redn_v1[7:0] = b33_corr_v1[7:0] ^ b33_shf_v1[7:0];
assign b23_redn_v1[7:0] = b23_corr_v1[7:0] ^ b23_shf_v1[7:0];
assign b13_redn_v1[7:0] = b13_corr_v1[7:0] ^ b13_shf_v1[7:0];
assign b03_redn_v1[7:0] = b03_corr_v1[7:0] ^ b03_shf_v1[7:0];
assign b32_redn_v1[7:0] = b32_corr_v1[7:0] ^ b32_shf_v1[7:0];
assign b22_redn_v1[7:0] = b22_corr_v1[7:0] ^ b22_shf_v1[7:0];
assign b12_redn_v1[7:0] = b12_corr_v1[7:0] ^ b12_shf_v1[7:0];
assign b02_redn_v1[7:0] = b02_corr_v1[7:0] ^ b02_shf_v1[7:0];
assign b31_redn_v1[7:0] = b31_corr_v1[7:0] ^ b31_shf_v1[7:0];
assign b21_redn_v1[7:0] = b21_corr_v1[7:0] ^ b21_shf_v1[7:0];
assign b11_redn_v1[7:0] = b11_corr_v1[7:0] ^ b11_shf_v1[7:0];
assign b01_redn_v1[7:0] = b01_corr_v1[7:0] ^ b01_shf_v1[7:0];
assign b30_redn_v1[7:0] = b30_corr_v1[7:0] ^ b30_shf_v1[7:0];
assign b20_redn_v1[7:0] = b20_corr_v1[7:0] ^ b20_shf_v1[7:0];
assign b10_redn_v1[7:0] = b10_corr_v1[7:0] ^ b10_shf_v1[7:0];
assign b00_redn_v1[7:0] = b00_corr_v1[7:0] ^ b00_shf_v1[7:0];
always_ff @(posedge clk or posedge reset)
begin: u_b33_redn_v2_q_7_0_grp
if (reset == 1'b1) begin
b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b33_redn_v1[7:0];
b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b23_redn_v1[7:0];
b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b13_redn_v1[7:0];
b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b03_redn_v1[7:0];
b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b32_redn_v1[7:0];
b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b22_redn_v1[7:0];
b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b12_redn_v1[7:0];
b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b02_redn_v1[7:0];
b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b31_redn_v1[7:0];
b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b21_redn_v1[7:0];
b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b11_redn_v1[7:0];
b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b01_redn_v1[7:0];
b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b30_redn_v1[7:0];
b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b20_redn_v1[7:0];
b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b10_redn_v1[7:0];
b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b00_redn_v1[7:0];
end
else if (reset == 1'b0 && ival_v1_q == 1'b0)
begin
end
else begin
b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY {8{1'bx}};
end
`else
else if (ival_v1_q == 1'b1) begin
b33_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b33_redn_v1[7:0];
b23_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b23_redn_v1[7:0];
b13_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b13_redn_v1[7:0];
b03_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b03_redn_v1[7:0];
b32_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b32_redn_v1[7:0];
b22_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b22_redn_v1[7:0];
b12_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b12_redn_v1[7:0];
b02_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b02_redn_v1[7:0];
b31_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b31_redn_v1[7:0];
b21_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b21_redn_v1[7:0];
b11_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b11_redn_v1[7:0];
b01_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b01_redn_v1[7:0];
b30_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b30_redn_v1[7:0];
b20_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b20_redn_v1[7:0];
b10_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b10_redn_v1[7:0];
b00_redn_v2_q[7:0] <= `HERCULESAE_DFF_DELAY b00_redn_v1[7:0];
end
`endif
end
assign aesd_out[127:120] = b33_redn_v2_q[7:0];
assign aesd_out[119:112] = b23_redn_v2_q[7:0];
assign aesd_out[111:104] = b13_redn_v2_q[7:0];
assign aesd_out[103:96] = b03_redn_v2_q[7:0];
assign aesd_out[95:88] = b32_redn_v2_q[7:0];
assign aesd_out[87:80] = b22_redn_v2_q[7:0];
assign aesd_out[79:72] = b12_redn_v2_q[7:0];
assign aesd_out[71:64] = b02_redn_v2_q[7:0];
assign aesd_out[63:56] = b31_redn_v2_q[7:0];
assign aesd_out[55:48] = b21_redn_v2_q[7:0];
assign aesd_out[47:40] = b11_redn_v2_q[7:0];
assign aesd_out[39:32] = b01_redn_v2_q[7:0];
assign aesd_out[31:24] = b30_redn_v2_q[7:0];
assign aesd_out[23:16] = b20_redn_v2_q[7:0];
assign aesd_out[15:8] = b10_redn_v2_q[7:0];
assign aesd_out[7:0] = b00_redn_v2_q[7:0];
assign aesimc_in[127:0] = aesd_out[127:0];
herculesae_vx_aesimc u_aesimc(
.d_in (aesimc_in[127:0]),
.imc (aesdimc_out[127:0])
);
assign aese_out[0] = b00_redn_v2_q[0] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1;
assign aese_out[1] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1;
assign aese_out[2] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0;
assign aese_out[3] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[7] ^ 1'b0;
assign aese_out[4] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ 1'b0;
assign aese_out[5] = b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ 1'b1;
assign aese_out[6] = b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ 1'b1;
assign aese_out[7] = b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0;
assign aese_out[8] = b10_redn_v2_q[0] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1;
assign aese_out[9] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1;
assign aese_out[10] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0;
assign aese_out[11] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[7] ^ 1'b0;
assign aese_out[12] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ 1'b0;
assign aese_out[13] = b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ 1'b1;
assign aese_out[14] = b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ 1'b1;
assign aese_out[15] = b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0;
assign aese_out[16] = b20_redn_v2_q[0] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1;
assign aese_out[17] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1;
assign aese_out[18] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0;
assign aese_out[19] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[7] ^ 1'b0;
assign aese_out[20] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ 1'b0;
assign aese_out[21] = b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ 1'b1;
assign aese_out[22] = b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ 1'b1;
assign aese_out[23] = b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0;
assign aese_out[24] = b30_redn_v2_q[0] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1;
assign aese_out[25] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1;
assign aese_out[26] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0;
assign aese_out[27] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[7] ^ 1'b0;
assign aese_out[28] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ 1'b0;
assign aese_out[29] = b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ 1'b1;
assign aese_out[30] = b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ 1'b1;
assign aese_out[31] = b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0;
assign aese_out[32] = b01_redn_v2_q[0] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1;
assign aese_out[33] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1;
assign aese_out[34] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0;
assign aese_out[35] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[7] ^ 1'b0;
assign aese_out[36] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ 1'b0;
assign aese_out[37] = b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ 1'b1;
assign aese_out[38] = b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ 1'b1;
assign aese_out[39] = b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0;
assign aese_out[40] = b11_redn_v2_q[0] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1;
assign aese_out[41] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1;
assign aese_out[42] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0;
assign aese_out[43] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[7] ^ 1'b0;
assign aese_out[44] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ 1'b0;
assign aese_out[45] = b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ 1'b1;
assign aese_out[46] = b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ 1'b1;
assign aese_out[47] = b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0;
assign aese_out[48] = b21_redn_v2_q[0] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1;
assign aese_out[49] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1;
assign aese_out[50] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0;
assign aese_out[51] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[7] ^ 1'b0;
assign aese_out[52] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ 1'b0;
assign aese_out[53] = b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ 1'b1;
assign aese_out[54] = b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ 1'b1;
assign aese_out[55] = b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0;
assign aese_out[56] = b31_redn_v2_q[0] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1;
assign aese_out[57] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1;
assign aese_out[58] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0;
assign aese_out[59] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[7] ^ 1'b0;
assign aese_out[60] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ 1'b0;
assign aese_out[61] = b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ 1'b1;
assign aese_out[62] = b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ 1'b1;
assign aese_out[63] = b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0;
assign aese_out[64] = b02_redn_v2_q[0] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1;
assign aese_out[65] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1;
assign aese_out[66] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0;
assign aese_out[67] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[7] ^ 1'b0;
assign aese_out[68] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ 1'b0;
assign aese_out[69] = b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ 1'b1;
assign aese_out[70] = b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ 1'b1;
assign aese_out[71] = b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0;
assign aese_out[72] = b12_redn_v2_q[0] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1;
assign aese_out[73] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1;
assign aese_out[74] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0;
assign aese_out[75] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[7] ^ 1'b0;
assign aese_out[76] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ 1'b0;
assign aese_out[77] = b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ 1'b1;
assign aese_out[78] = b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ 1'b1;
assign aese_out[79] = b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0;
assign aese_out[80] = b22_redn_v2_q[0] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1;
assign aese_out[81] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1;
assign aese_out[82] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0;
assign aese_out[83] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[7] ^ 1'b0;
assign aese_out[84] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ 1'b0;
assign aese_out[85] = b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ 1'b1;
assign aese_out[86] = b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ 1'b1;
assign aese_out[87] = b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0;
assign aese_out[88] = b32_redn_v2_q[0] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1;
assign aese_out[89] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1;
assign aese_out[90] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0;
assign aese_out[91] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[7] ^ 1'b0;
assign aese_out[92] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ 1'b0;
assign aese_out[93] = b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ 1'b1;
assign aese_out[94] = b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ 1'b1;
assign aese_out[95] = b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0;
assign aese_out[96] = b03_redn_v2_q[0] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1;
assign aese_out[97] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1;
assign aese_out[98] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0;
assign aese_out[99] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[7] ^ 1'b0;
assign aese_out[100] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ 1'b0;
assign aese_out[101] = b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ 1'b1;
assign aese_out[102] = b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ 1'b1;
assign aese_out[103] = b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0;
assign aese_out[104] = b13_redn_v2_q[0] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1;
assign aese_out[105] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1;
assign aese_out[106] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0;
assign aese_out[107] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[7] ^ 1'b0;
assign aese_out[108] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ 1'b0;
assign aese_out[109] = b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ 1'b1;
assign aese_out[110] = b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ 1'b1;
assign aese_out[111] = b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0;
assign aese_out[112] = b23_redn_v2_q[0] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1;
assign aese_out[113] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1;
assign aese_out[114] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0;
assign aese_out[115] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[7] ^ 1'b0;
assign aese_out[116] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ 1'b0;
assign aese_out[117] = b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ 1'b1;
assign aese_out[118] = b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ 1'b1;
assign aese_out[119] = b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0;
assign aese_out[120] = b33_redn_v2_q[0] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1;
assign aese_out[121] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1;
assign aese_out[122] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0;
assign aese_out[123] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[7] ^ 1'b0;
assign aese_out[124] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ 1'b0;
assign aese_out[125] = b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ 1'b1;
assign aese_out[126] = b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ 1'b1;
assign aese_out[127] = b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[0] = b00_redn_v2_q[0] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[1] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[2] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[3] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[4] = b00_redn_v2_q[0] ^ b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[5] = b00_redn_v2_q[1] ^ b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[6] = b00_redn_v2_q[2] ^ b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[7] = b00_redn_v2_q[3] ^ b00_redn_v2_q[4] ^ b00_redn_v2_q[5] ^ b00_redn_v2_q[6] ^ b00_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[8] = b10_redn_v2_q[0] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[9] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[10] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[11] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[12] = b10_redn_v2_q[0] ^ b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[13] = b10_redn_v2_q[1] ^ b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[14] = b10_redn_v2_q[2] ^ b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[15] = b10_redn_v2_q[3] ^ b10_redn_v2_q[4] ^ b10_redn_v2_q[5] ^ b10_redn_v2_q[6] ^ b10_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[16] = b20_redn_v2_q[0] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[17] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[18] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[19] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[20] = b20_redn_v2_q[0] ^ b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[21] = b20_redn_v2_q[1] ^ b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[22] = b20_redn_v2_q[2] ^ b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[23] = b20_redn_v2_q[3] ^ b20_redn_v2_q[4] ^ b20_redn_v2_q[5] ^ b20_redn_v2_q[6] ^ b20_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[24] = b30_redn_v2_q[0] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[25] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[26] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[27] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[28] = b30_redn_v2_q[0] ^ b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[29] = b30_redn_v2_q[1] ^ b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[30] = b30_redn_v2_q[2] ^ b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[31] = b30_redn_v2_q[3] ^ b30_redn_v2_q[4] ^ b30_redn_v2_q[5] ^ b30_redn_v2_q[6] ^ b30_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[32] = b01_redn_v2_q[0] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[33] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[34] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[35] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[36] = b01_redn_v2_q[0] ^ b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[37] = b01_redn_v2_q[1] ^ b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[38] = b01_redn_v2_q[2] ^ b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[39] = b01_redn_v2_q[3] ^ b01_redn_v2_q[4] ^ b01_redn_v2_q[5] ^ b01_redn_v2_q[6] ^ b01_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[40] = b11_redn_v2_q[0] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[41] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[42] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[43] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[44] = b11_redn_v2_q[0] ^ b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[45] = b11_redn_v2_q[1] ^ b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[46] = b11_redn_v2_q[2] ^ b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[47] = b11_redn_v2_q[3] ^ b11_redn_v2_q[4] ^ b11_redn_v2_q[5] ^ b11_redn_v2_q[6] ^ b11_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[48] = b21_redn_v2_q[0] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[49] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[50] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[51] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[52] = b21_redn_v2_q[0] ^ b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[53] = b21_redn_v2_q[1] ^ b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[54] = b21_redn_v2_q[2] ^ b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[55] = b21_redn_v2_q[3] ^ b21_redn_v2_q[4] ^ b21_redn_v2_q[5] ^ b21_redn_v2_q[6] ^ b21_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[56] = b31_redn_v2_q[0] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[57] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[58] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[59] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[60] = b31_redn_v2_q[0] ^ b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[61] = b31_redn_v2_q[1] ^ b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[62] = b31_redn_v2_q[2] ^ b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[63] = b31_redn_v2_q[3] ^ b31_redn_v2_q[4] ^ b31_redn_v2_q[5] ^ b31_redn_v2_q[6] ^ b31_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[64] = b02_redn_v2_q[0] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[65] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[66] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[67] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[68] = b02_redn_v2_q[0] ^ b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[69] = b02_redn_v2_q[1] ^ b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[70] = b02_redn_v2_q[2] ^ b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[71] = b02_redn_v2_q[3] ^ b02_redn_v2_q[4] ^ b02_redn_v2_q[5] ^ b02_redn_v2_q[6] ^ b02_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[72] = b12_redn_v2_q[0] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[73] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[74] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[75] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[76] = b12_redn_v2_q[0] ^ b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[77] = b12_redn_v2_q[1] ^ b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[78] = b12_redn_v2_q[2] ^ b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[79] = b12_redn_v2_q[3] ^ b12_redn_v2_q[4] ^ b12_redn_v2_q[5] ^ b12_redn_v2_q[6] ^ b12_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[80] = b22_redn_v2_q[0] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[81] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[82] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[83] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[84] = b22_redn_v2_q[0] ^ b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[85] = b22_redn_v2_q[1] ^ b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[86] = b22_redn_v2_q[2] ^ b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[87] = b22_redn_v2_q[3] ^ b22_redn_v2_q[4] ^ b22_redn_v2_q[5] ^ b22_redn_v2_q[6] ^ b22_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[88] = b32_redn_v2_q[0] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[89] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[90] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[91] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[92] = b32_redn_v2_q[0] ^ b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[93] = b32_redn_v2_q[1] ^ b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[94] = b32_redn_v2_q[2] ^ b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[95] = b32_redn_v2_q[3] ^ b32_redn_v2_q[4] ^ b32_redn_v2_q[5] ^ b32_redn_v2_q[6] ^ b32_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[96] = b03_redn_v2_q[0] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[97] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[98] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[99] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[100] = b03_redn_v2_q[0] ^ b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[101] = b03_redn_v2_q[1] ^ b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[102] = b03_redn_v2_q[2] ^ b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[103] = b03_redn_v2_q[3] ^ b03_redn_v2_q[4] ^ b03_redn_v2_q[5] ^ b03_redn_v2_q[6] ^ b03_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[104] = b13_redn_v2_q[0] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[105] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[106] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[107] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[108] = b13_redn_v2_q[0] ^ b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[109] = b13_redn_v2_q[1] ^ b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[110] = b13_redn_v2_q[2] ^ b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[111] = b13_redn_v2_q[3] ^ b13_redn_v2_q[4] ^ b13_redn_v2_q[5] ^ b13_redn_v2_q[6] ^ b13_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[112] = b23_redn_v2_q[0] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[113] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[114] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[115] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[116] = b23_redn_v2_q[0] ^ b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[117] = b23_redn_v2_q[1] ^ b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[118] = b23_redn_v2_q[2] ^ b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[119] = b23_redn_v2_q[3] ^ b23_redn_v2_q[4] ^ b23_redn_v2_q[5] ^ b23_redn_v2_q[6] ^ b23_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[120] = b33_redn_v2_q[0] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[121] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b1;
assign aesmc_in[122] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[123] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[7] ^ 1'b0;
assign aesmc_in[124] = b33_redn_v2_q[0] ^ b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ 1'b0;
assign aesmc_in[125] = b33_redn_v2_q[1] ^ b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ 1'b1;
assign aesmc_in[126] = b33_redn_v2_q[2] ^ b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ 1'b1;
assign aesmc_in[127] = b33_redn_v2_q[3] ^ b33_redn_v2_q[4] ^ b33_redn_v2_q[5] ^ b33_redn_v2_q[6] ^ b33_redn_v2_q[7] ^ 1'b0;
herculesae_vx_aesmc u_aesmc(
.d_in (aesmc_in[127:0]),
.mc (aesemc_out[127:0])
);
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aesed2_lut
(
input wire [127:0] lut_in,
output wire [127:0] lut_out
);
wire [7:0] b00;
wire [7:0] b01;
wire [7:0] b02;
wire [7:0] b03;
wire [7:0] b10;
wire [7:0] b11;
wire [7:0] b12;
wire [7:0] b13;
wire [7:0] b20;
wire [7:0] b21;
wire [7:0] b22;
wire [7:0] b23;
wire [7:0] b30;
wire [7:0] b31;
wire [7:0] b32;
wire [7:0] b33;
herculesae_vx_aesinv u_inv_lut0(.lut_in(lut_in[127:120]), .lut_out(b33[7:0]));
herculesae_vx_aesinv u_inv_lut1(.lut_in(lut_in[119:112]), .lut_out(b23[7:0]));
herculesae_vx_aesinv u_inv_lut2(.lut_in(lut_in[111:104]), .lut_out(b13[7:0]));
herculesae_vx_aesinv u_inv_lut3(.lut_in(lut_in[103:96]), .lut_out(b03[7:0]));
herculesae_vx_aesinv u_inv_lut4(.lut_in(lut_in[95:88]), .lut_out(b32[7:0]));
herculesae_vx_aesinv u_inv_lut5(.lut_in(lut_in[87:80]), .lut_out(b22[7:0]));
herculesae_vx_aesinv u_inv_lut6(.lut_in(lut_in[79:72]), .lut_out(b12[7:0]));
herculesae_vx_aesinv u_inv_lut7(.lut_in(lut_in[71:64]), .lut_out(b02[7:0]));
herculesae_vx_aesinv u_inv_lut8 (.lut_in(lut_in[63:56]), .lut_out(b31[7:0]));
herculesae_vx_aesinv u_inv_lut9 (.lut_in(lut_in[55:48]), .lut_out(b21[7:0]));
herculesae_vx_aesinv u_inv_lut10(.lut_in(lut_in[47:40]), .lut_out(b11[7:0]));
herculesae_vx_aesinv u_inv_lut11(.lut_in(lut_in[39:32]), .lut_out(b01[7:0]));
herculesae_vx_aesinv u_inv_lut12(.lut_in(lut_in[31:24]), .lut_out(b30[7:0]));
herculesae_vx_aesinv u_inv_lut13(.lut_in(lut_in[23:16]), .lut_out(b20[7:0]));
herculesae_vx_aesinv u_inv_lut14(.lut_in(lut_in[15:8]), .lut_out(b10[7:0]));
herculesae_vx_aesinv u_inv_lut15(.lut_in(lut_in[7:0]), .lut_out(b00[7:0]));
assign lut_out[127:0] = {b33[7:0],b23[7:0],b13[7:0],b03[7:0],
b32[7:0],b22[7:0],b12[7:0],b02[7:0],
b31[7:0],b21[7:0],b11[7:0],b01[7:0],
b30[7:0],b20[7:0],b10[7:0],b00[7:0]
};
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aesimc
(
input wire [127:0] d_in,
output wire [127:0] imc
);
wire [7:0] i00;
wire [7:0] i01;
wire [7:0] i02;
wire [7:0] i03;
wire [7:0] i10;
wire [7:0] i11;
wire [7:0] i12;
wire [7:0] i13;
wire [7:0] i20;
wire [7:0] i21;
wire [7:0] i22;
wire [7:0] i23;
wire [7:0] i30;
wire [7:0] i31;
wire [7:0] i32;
wire [7:0] i33;
wire [7:0] s00;
wire [10:0] s00_nr;
wire [7:0] s01;
wire [10:0] s01_nr;
wire [7:0] s02;
wire [10:0] s02_nr;
wire [7:0] s03;
wire [10:0] s03_nr;
wire [7:0] s10;
wire [10:0] s10_nr;
wire [7:0] s11;
wire [10:0] s11_nr;
wire [7:0] s12;
wire [10:0] s12_nr;
wire [7:0] s13;
wire [10:0] s13_nr;
wire [7:0] s20;
wire [10:0] s20_nr;
wire [7:0] s21;
wire [10:0] s21_nr;
wire [7:0] s22;
wire [10:0] s22_nr;
wire [7:0] s23;
wire [10:0] s23_nr;
wire [7:0] s30;
wire [10:0] s30_nr;
wire [7:0] s31;
wire [10:0] s31_nr;
wire [7:0] s32;
wire [10:0] s32_nr;
wire [7:0] s33;
wire [10:0] s33_nr;
assign i33[7:0] = d_in[127:120];
assign i23[7:0] = d_in[119:112];
assign i13[7:0] = d_in[111:104];
assign i03[7:0] = d_in[103:96];
assign i32[7:0] = d_in[95:88];
assign i22[7:0] = d_in[87:80];
assign i12[7:0] = d_in[79:72];
assign i02[7:0] = d_in[71:64];
assign i31[7:0] = d_in[63:56];
assign i21[7:0] = d_in[55:48];
assign i11[7:0] = d_in[47:40];
assign i01[7:0] = d_in[39:32];
assign i30[7:0] = d_in[31:24];
assign i20[7:0] = d_in[23:16];
assign i10[7:0] = d_in[15:8];
assign i00[7:0] = d_in[7:0];
assign s00_nr[10:0] = {i00[7:0],3'b000} ^ {1'b0,i00[7:0],2'b00} ^ {2'b00,i00[7:0],1'b0}
^ {i10[7:0],3'b000} ^ {2'b00,i10[7:0],1'b0} ^ {3'b000,i10[7:0]}
^ {i20[7:0],3'b000} ^ {1'b0,i20[7:0],2'b00} ^ {3'b000,i20[7:0]}
^ {i30[7:0],3'b000} ^ {3'b000,i30[7:0]};
assign s00[7:0] = s00_nr[7:0] ^ ({8{s00_nr[8]}} & 8'h1b) ^ ({8{s00_nr[9]}} & 8'h36) ^ ({8{s00_nr[10]}} & 8'h6c);
assign s01_nr[10:0] = {i01[7:0],3'b000} ^ {1'b0,i01[7:0],2'b00} ^ {2'b00,i01[7:0],1'b0}
^ {i11[7:0],3'b000} ^ {2'b00,i11[7:0],1'b0} ^ {3'b000,i11[7:0]}
^ {i21[7:0],3'b000} ^ {1'b0,i21[7:0],2'b00} ^ {3'b000,i21[7:0]}
^ {i31[7:0],3'b000} ^ {3'b000,i31[7:0]};
assign s01[7:0] = s01_nr[7:0] ^ ({8{s01_nr[8]}} & 8'h1b) ^ ({8{s01_nr[9]}} & 8'h36) ^ ({8{s01_nr[10]}} & 8'h6c);
assign s02_nr[10:0] = {i02[7:0],3'b000} ^ {1'b0,i02[7:0],2'b00} ^ {2'b00,i02[7:0],1'b0}
^ {i12[7:0],3'b000} ^ {2'b00,i12[7:0],1'b0} ^ {3'b000,i12[7:0]}
^ {i22[7:0],3'b000} ^ {1'b0,i22[7:0],2'b00} ^ {3'b000,i22[7:0]}
^ {i32[7:0],3'b000} ^ {3'b000,i32[7:0]};
assign s02[7:0] = s02_nr[7:0] ^ ({8{s02_nr[8]}} & 8'h1b) ^ ({8{s02_nr[9]}} & 8'h36) ^ ({8{s02_nr[10]}} & 8'h6c);
assign s03_nr[10:0] = {i03[7:0],3'b000} ^ {1'b0,i03[7:0],2'b00} ^ {2'b00,i03[7:0],1'b0}
^ {i13[7:0],3'b000} ^ {2'b00,i13[7:0],1'b0} ^ {3'b000,i13[7:0]}
^ {i23[7:0],3'b000} ^ {1'b0,i23[7:0],2'b00} ^ {3'b000,i23[7:0]}
^ {i33[7:0],3'b000} ^ {3'b000,i33[7:0]};
assign s03[7:0] = s03_nr[7:0] ^ ({8{s03_nr[8]}} & 8'h1b) ^ ({8{s03_nr[9]}} & 8'h36) ^ ({8{s03_nr[10]}} & 8'h6c);
assign s10_nr[10:0] = {i10[7:0],3'b000} ^ {1'b0,i10[7:0],2'b00} ^ {2'b00,i10[7:0],1'b0}
^ {i20[7:0],3'b000} ^ {2'b00,i20[7:0],1'b0} ^ {3'b000,i20[7:0]}
^ {i30[7:0],3'b000} ^ {1'b0,i30[7:0],2'b00} ^ {3'b000,i30[7:0]}
^ {i00[7:0],3'b000} ^ {3'b000,i00[7:0]};
assign s10[7:0] = s10_nr[7:0] ^ ({8{s10_nr[8]}} & 8'h1b) ^ ({8{s10_nr[9]}} & 8'h36) ^ ({8{s10_nr[10]}} & 8'h6c);
assign s11_nr[10:0] = {i11[7:0],3'b000} ^ {1'b0,i11[7:0],2'b00} ^ {2'b00,i11[7:0],1'b0}
^ {i21[7:0],3'b000} ^ {2'b00,i21[7:0],1'b0} ^ {3'b000,i21[7:0]}
^ {i31[7:0],3'b000} ^ {1'b0,i31[7:0],2'b00} ^ {3'b000,i31[7:0]}
^ {i01[7:0],3'b000} ^ {3'b000,i01[7:0]};
assign s11[7:0] = s11_nr[7:0] ^ ({8{s11_nr[8]}} & 8'h1b) ^ ({8{s11_nr[9]}} & 8'h36) ^ ({8{s11_nr[10]}} & 8'h6c);
assign s12_nr[10:0] = {i12[7:0],3'b000} ^ {1'b0,i12[7:0],2'b00} ^ {2'b00,i12[7:0],1'b0}
^ {i22[7:0],3'b000} ^ {2'b00,i22[7:0],1'b0} ^ {3'b000,i22[7:0]}
^ {i32[7:0],3'b000} ^ {1'b0,i32[7:0],2'b00} ^ {3'b000,i32[7:0]}
^ {i02[7:0],3'b000} ^ {3'b000,i02[7:0]};
assign s12[7:0] = s12_nr[7:0] ^ ({8{s12_nr[8]}} & 8'h1b) ^ ({8{s12_nr[9]}} & 8'h36) ^ ({8{s12_nr[10]}} & 8'h6c);
assign s13_nr[10:0] = {i13[7:0],3'b000} ^ {1'b0,i13[7:0],2'b00} ^ {2'b00,i13[7:0],1'b0}
^ {i23[7:0],3'b000} ^ {2'b00,i23[7:0],1'b0} ^ {3'b000,i23[7:0]}
^ {i33[7:0],3'b000} ^ {1'b0,i33[7:0],2'b00} ^ {3'b000,i33[7:0]}
^ {i03[7:0],3'b000} ^ {3'b000,i03[7:0]};
assign s13[7:0] = s13_nr[7:0] ^ ({8{s13_nr[8]}} & 8'h1b) ^ ({8{s13_nr[9]}} & 8'h36) ^ ({8{s13_nr[10]}} & 8'h6c);
assign s20_nr[10:0] = {i20[7:0],3'b000} ^ {1'b0,i20[7:0],2'b00} ^ {2'b00,i20[7:0],1'b0}
^ {i30[7:0],3'b000} ^ {2'b00,i30[7:0],1'b0} ^ {3'b000,i30[7:0]}
^ {i00[7:0],3'b000} ^ {1'b0,i00[7:0],2'b00} ^ {3'b000,i00[7:0]}
^ {i10[7:0],3'b000} ^ {3'b000,i10[7:0]};
assign s20[7:0] = s20_nr[7:0] ^ ({8{s20_nr[8]}} & 8'h1b) ^ ({8{s20_nr[9]}} & 8'h36) ^ ({8{s20_nr[10]}} & 8'h6c);
assign s21_nr[10:0] = {i21[7:0],3'b000} ^ {1'b0,i21[7:0],2'b00} ^ {2'b00,i21[7:0],1'b0}
^ {i31[7:0],3'b000} ^ {2'b00,i31[7:0],1'b0} ^ {3'b000,i31[7:0]}
^ {i01[7:0],3'b000} ^ {1'b0,i01[7:0],2'b00} ^ {3'b000,i01[7:0]}
^ {i11[7:0],3'b000} ^ {3'b000,i11[7:0]};
assign s21[7:0] = s21_nr[7:0] ^ ({8{s21_nr[8]}} & 8'h1b) ^ ({8{s21_nr[9]}} & 8'h36) ^ ({8{s21_nr[10]}} & 8'h6c);
assign s22_nr[10:0] = {i22[7:0],3'b000} ^ {1'b0,i22[7:0],2'b00} ^ {2'b00,i22[7:0],1'b0}
^ {i32[7:0],3'b000} ^ {2'b00,i32[7:0],1'b0} ^ {3'b000,i32[7:0]}
^ {i02[7:0],3'b000} ^ {1'b0,i02[7:0],2'b00} ^ {3'b000,i02[7:0]}
^ {i12[7:0],3'b000} ^ {3'b000,i12[7:0]};
assign s22[7:0] = s22_nr[7:0] ^ ({8{s22_nr[8]}} & 8'h1b) ^ ({8{s22_nr[9]}} & 8'h36) ^ ({8{s22_nr[10]}} & 8'h6c);
assign s23_nr[10:0] = {i23[7:0],3'b000} ^ {1'b0,i23[7:0],2'b00} ^ {2'b00,i23[7:0],1'b0}
^ {i33[7:0],3'b000} ^ {2'b00,i33[7:0],1'b0} ^ {3'b000,i33[7:0]}
^ {i03[7:0],3'b000} ^ {1'b0,i03[7:0],2'b00} ^ {3'b000,i03[7:0]}
^ {i13[7:0],3'b000} ^ {3'b000,i13[7:0]};
assign s23[7:0] = s23_nr[7:0] ^ ({8{s23_nr[8]}} & 8'h1b) ^ ({8{s23_nr[9]}} & 8'h36) ^ ({8{s23_nr[10]}} & 8'h6c);
assign s30_nr[10:0] = {i30[7:0],3'b000} ^ {1'b0,i30[7:0],2'b00} ^ {2'b00,i30[7:0],1'b0}
^ {i00[7:0],3'b000} ^ {2'b00,i00[7:0],1'b0} ^ {3'b000,i00[7:0]}
^ {i10[7:0],3'b000} ^ {1'b0,i10[7:0],2'b00} ^ {3'b000,i10[7:0]}
^ {i20[7:0],3'b000} ^ {3'b000,i20[7:0]};
assign s30[7:0] = s30_nr[7:0] ^ ({8{s30_nr[8]}} & 8'h1b) ^ ({8{s30_nr[9]}} & 8'h36) ^ ({8{s30_nr[10]}} & 8'h6c);
assign s31_nr[10:0] = {i31[7:0],3'b000} ^ {1'b0,i31[7:0],2'b00} ^ {2'b00,i31[7:0],1'b0}
^ {i01[7:0],3'b000} ^ {2'b00,i01[7:0],1'b0} ^ {3'b000,i01[7:0]}
^ {i11[7:0],3'b000} ^ {1'b0,i11[7:0],2'b00} ^ {3'b000,i11[7:0]}
^ {i21[7:0],3'b000} ^ {3'b000,i21[7:0]};
assign s31[7:0] = s31_nr[7:0] ^ ({8{s31_nr[8]}} & 8'h1b) ^ ({8{s31_nr[9]}} & 8'h36) ^ ({8{s31_nr[10]}} & 8'h6c);
assign s32_nr[10:0] = {i32[7:0],3'b000} ^ {1'b0,i32[7:0],2'b00} ^ {2'b00,i32[7:0],1'b0}
^ {i02[7:0],3'b000} ^ {2'b00,i02[7:0],1'b0} ^ {3'b000,i02[7:0]}
^ {i12[7:0],3'b000} ^ {1'b0,i12[7:0],2'b00} ^ {3'b000,i12[7:0]}
^ {i22[7:0],3'b000} ^ {3'b000,i22[7:0]};
assign s32[7:0] = s32_nr[7:0] ^ ({8{s32_nr[8]}} & 8'h1b) ^ ({8{s32_nr[9]}} & 8'h36) ^ ({8{s32_nr[10]}} & 8'h6c);
assign s33_nr[10:0] = {i33[7:0],3'b000} ^ {1'b0,i33[7:0],2'b00} ^ {2'b00,i33[7:0],1'b0}
^ {i03[7:0],3'b000} ^ {2'b00,i03[7:0],1'b0} ^ {3'b000,i03[7:0]}
^ {i13[7:0],3'b000} ^ {1'b0,i13[7:0],2'b00} ^ {3'b000,i13[7:0]}
^ {i23[7:0],3'b000} ^ {3'b000,i23[7:0]};
assign s33[7:0] = s33_nr[7:0] ^ ({8{s33_nr[8]}} & 8'h1b) ^ ({8{s33_nr[9]}} & 8'h36) ^ ({8{s33_nr[10]}} & 8'h6c);
assign imc[127:120] = s33[7:0];
assign imc[119:112] = s23[7:0];
assign imc[111:104] = s13[7:0];
assign imc[103:96] = s03[7:0];
assign imc[95:88] = s32[7:0];
assign imc[87:80] = s22[7:0];
assign imc[79:72] = s12[7:0];
assign imc[71:64] = s02[7:0];
assign imc[63:56] = s31[7:0];
assign imc[55:48] = s21[7:0];
assign imc[47:40] = s11[7:0];
assign imc[39:32] = s01[7:0];
assign imc[31:24] = s30[7:0];
assign imc[23:16] = s20[7:0];
assign imc[15:8] = s10[7:0];
assign imc[7:0] = s00[7:0];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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@ -0,0 +1,517 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aesinv
(
input wire [7:0] lut_in,
output wire [7:0] lut_out
);
assign lut_out[7] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[0]) | (
lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]
&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]
&lut_in[4]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (
!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]
&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[4]&!lut_in[3]
&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]
&lut_in[5]&!lut_in[4]&lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]
&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[1]
&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]
&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (
!lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]
&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]
&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[6]&!lut_in[5]
&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[6]
&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[7]
&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]
&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[2]&lut_in[1]) | (!lut_in[7]
&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[5]
&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]
&lut_in[6]&lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[4]
&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]
&lut_in[5]&lut_in[3]&!lut_in[2]) | (lut_in[6]&!lut_in[5]&!lut_in[4]
&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[3]&lut_in[1]) | (!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]
&lut_in[1]) | (lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[1]&lut_in[0]);
assign lut_out[6] = (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (
!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]
&lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]
&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]
&lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]
&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]
&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]
&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]&!lut_in[6]
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[7]&lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]
&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (!lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (
!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[0]) | (
!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]
&!lut_in[1]) | (lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (lut_in[6]&lut_in[4]&!lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]
&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
&!lut_in[4]&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]) | (!lut_in[6]&lut_in[5]&!lut_in[4]
&lut_in[1]&lut_in[0]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[1]
&lut_in[0]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&!lut_in[1]
&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[1]&lut_in[0]) | (
lut_in[6]&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[5]
&lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[4]
&lut_in[3]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[2]
&!lut_in[1]&lut_in[0]);
assign lut_out[5] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
&lut_in[5]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]
&!lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]
&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]
&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[0]) | (
!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]) | (
!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
&lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[4]
&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]
&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
!lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (
!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]
&!lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[5]&!lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[6]
&!lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]
&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[6]
&!lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[7]
&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[5]
&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[0]) | (!lut_in[7]&lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[5]&lut_in[3]
&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]
&!lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[1]
&lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[0]) | (
!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[2]&lut_in[1]) | (!lut_in[7]
&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[4]
&!lut_in[3]&!lut_in[1]&lut_in[0]) | (!lut_in[5]&!lut_in[4]&lut_in[3]
&lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[1]
&lut_in[0]) | (!lut_in[7]&!lut_in[4]&lut_in[2]&lut_in[1]);
assign lut_out[4] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]
&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (
lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]
&lut_in[2]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
&!lut_in[4]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
&!lut_in[5]&!lut_in[4]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (
lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]
&lut_in[3]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[4]
&lut_in[3]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]
&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]
&!lut_in[2]&lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]
&lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[7]&lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&lut_in[4]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[5]&!lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (
!lut_in[7]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (!lut_in[6]&lut_in[4]&lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
&!lut_in[1]&!lut_in[0]) | (!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]
&!lut_in[1]&lut_in[0]) | (lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[3]
&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]) | (!lut_in[7]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (
!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (
lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[7]&!lut_in[6]&lut_in[4]&lut_in[3]&!lut_in[1]) | (!lut_in[7]
&lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]) | (!lut_in[7]&!lut_in[6]
&lut_in[4]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[4]&!lut_in[3]
&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[2]
&!lut_in[1]&lut_in[0]);
assign lut_out[3] = (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]
&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]
&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[2]&!lut_in[0]) | (lut_in[7]
&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]
&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]
&!lut_in[3]&!lut_in[2]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]&lut_in[5]
&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[7]
&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (
!lut_in[7]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]
&!lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]
&!lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&lut_in[1]) | (!lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[4]
&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[4]
&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]
&!lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[6]&lut_in[4]
&lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[3]&!lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[4]&!lut_in[3]&!lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[0]) | (!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&!lut_in[1]
&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[1]) | (
!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[1]);
assign lut_out[2] = (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]
&lut_in[5]&!lut_in[4]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[3]
&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]
&lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]
&lut_in[2]&!lut_in[1]) | (lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]
&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[4]&lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[3]&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]
&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]
&lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]) | (
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]
&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[4]
&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[5]
&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&lut_in[5]
&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[5]
&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[6]
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]) | (!lut_in[6]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]
&lut_in[0]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]
&lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (!lut_in[6]
&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (
lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&lut_in[4]&lut_in[3]
&lut_in[2]&!lut_in[1]) | (lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[4]&lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[3]&lut_in[2]) | (!lut_in[6]&lut_in[4]&!lut_in[3]&!lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]
&lut_in[0]) | (!lut_in[5]&!lut_in[4]&lut_in[2]&lut_in[1]&lut_in[0]) | (
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (
lut_in[6]&lut_in[5]&!lut_in[3]&lut_in[2]&lut_in[0]) | (lut_in[6]
&lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]
&lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[1]) | (lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]
&!lut_in[5]&!lut_in[3]&!lut_in[1]);
assign lut_out[1] = (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]
&lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (
lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[3]&lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&!lut_in[4]
&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]&!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]
&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]) | (
lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (lut_in[7]&!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[6]
&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]) | (lut_in[7]&!lut_in[6]&lut_in[4]&!lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[3]
&!lut_in[2]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (
!lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]) | (
lut_in[6]&!lut_in[5]&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]
&lut_in[0]) | (lut_in[7]&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&lut_in[1]) | (!lut_in[7]&!lut_in[6]&lut_in[5]&lut_in[4]
&!lut_in[3]&lut_in[2]&!lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (!lut_in[6]&lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]
&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[6]
&lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[5]
&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[6]
&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]) | (lut_in[6]
&!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[7]
&!lut_in[6]&!lut_in[4]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]
&!lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]
&lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (lut_in[6]&!lut_in[5]
&lut_in[2]&lut_in[1]&lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
&!lut_in[4]&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]) | (!lut_in[7]&lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (!lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[5]&lut_in[4]&!lut_in[3]&lut_in[2]
&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]) | (lut_in[7]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[1]) | (
!lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]);
assign lut_out[0] = (lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]
&!lut_in[4]&!lut_in[3]&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[7]
&!lut_in[6]&!lut_in[5]&lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (
lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&!lut_in[6]&lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]
&!lut_in[3]&lut_in[2]&lut_in[1]&!lut_in[0]) | (lut_in[7]&!lut_in[6]
&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (
!lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]
&!lut_in[1]) | (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[6]&!lut_in[5]&!lut_in[4]
&!lut_in[3]&lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]
&!lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (lut_in[6]
&lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (
lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[3]&!lut_in[2]&lut_in[1]
&!lut_in[0]) | (lut_in[7]&!lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[3]&lut_in[1]&lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]
&!lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (lut_in[7]&!lut_in[6]
&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (!lut_in[7]
&!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&!lut_in[2]&!lut_in[1]) | (
!lut_in[6]&lut_in[5]&!lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
&lut_in[0]) | (lut_in[6]&lut_in[5]&lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[0]) | (lut_in[7]&lut_in[6]&!lut_in[4]&lut_in[3]&!lut_in[2]
&lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[5]&lut_in[4]&lut_in[3]
&!lut_in[1]&!lut_in[0]) | (lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&!lut_in[1]&!lut_in[0]) | (lut_in[6]&!lut_in[5]&lut_in[4]
&lut_in[3]&!lut_in[2]&!lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[6]
&!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]) | (!lut_in[6]&!lut_in[5]
&!lut_in[4]&lut_in[3]&!lut_in[2]&lut_in[1]&lut_in[0]) | (!lut_in[7]
&!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&lut_in[1]) | (
lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]&!lut_in[2]&!lut_in[1]
&!lut_in[0]) | (lut_in[5]&!lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]
&lut_in[0]) | (!lut_in[7]&lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]
&lut_in[2]) | (!lut_in[5]&lut_in[4]&lut_in[3]&lut_in[2]&!lut_in[1]
&!lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[4]&!lut_in[3]&lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[7]&lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&lut_in[3]
&!lut_in[2]&!lut_in[1]) | (!lut_in[6]&lut_in[5]&lut_in[4]&!lut_in[3]
&lut_in[2]&!lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[3]&!lut_in[2]
&lut_in[1]&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&lut_in[3]
&!lut_in[2]&lut_in[1]) | (lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[2]
&!lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[2]&lut_in[1]
&lut_in[0]) | (!lut_in[7]&!lut_in[6]&!lut_in[5]&!lut_in[4]&!lut_in[3]
&lut_in[2]) | (!lut_in[6]&lut_in[4]&!lut_in[3]&!lut_in[2]&lut_in[1]
&lut_in[0]) | (!lut_in[6]&lut_in[5]&lut_in[4]&lut_in[3]&lut_in[1]
&lut_in[0]) | (!lut_in[7]&lut_in[6]&!lut_in[4]&lut_in[3]&lut_in[1]) | (
!lut_in[7]&lut_in[6]&lut_in[5]&!lut_in[3]&!lut_in[2]&lut_in[1]) | (
!lut_in[7]&lut_in[6]&!lut_in[5]&!lut_in[3]&lut_in[1]) | (!lut_in[7]
&!lut_in[6]&lut_in[4]&lut_in[2]&!lut_in[1]) | (lut_in[6]&lut_in[5]
&!lut_in[4]&lut_in[1]&lut_in[0]);
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_aesmc
(
input wire [127:0] d_in,
output wire [127:0] mc
);
wire [7:0] i00;
wire [7:0] i01;
wire [7:0] i02;
wire [7:0] i03;
wire [7:0] i10;
wire [7:0] i11;
wire [7:0] i12;
wire [7:0] i13;
wire [7:0] i20;
wire [7:0] i21;
wire [7:0] i22;
wire [7:0] i23;
wire [7:0] i30;
wire [7:0] i31;
wire [7:0] i32;
wire [7:0] i33;
wire [7:0] s00;
wire [7:0] s01;
wire [7:0] s02;
wire [7:0] s03;
wire [7:0] s10;
wire [7:0] s11;
wire [7:0] s12;
wire [7:0] s13;
wire [7:0] s20;
wire [7:0] s21;
wire [7:0] s22;
wire [7:0] s23;
wire [7:0] s30;
wire [7:0] s31;
wire [7:0] s32;
wire [7:0] s33;
assign i33[7:0] = d_in[127:120];
assign i23[7:0] = d_in[119:112];
assign i13[7:0] = d_in[111:104];
assign i03[7:0] = d_in[103:96];
assign i32[7:0] = d_in[95:88];
assign i22[7:0] = d_in[87:80];
assign i12[7:0] = d_in[79:72];
assign i02[7:0] = d_in[71:64];
assign i31[7:0] = d_in[63:56];
assign i21[7:0] = d_in[55:48];
assign i11[7:0] = d_in[47:40];
assign i01[7:0] = d_in[39:32];
assign i30[7:0] = d_in[31:24];
assign i20[7:0] = d_in[23:16];
assign i10[7:0] = d_in[15:8];
assign i00[7:0] = d_in[7:0];
assign s00[7:0] = {i00[6:0],1'b0} ^ ({8{i00[7]}} & 8'h1b)
^ {i10[6:0],1'b0} ^ ({8{i10[7]}} & 8'h1b) ^ i10[7:0]
^ i20[7:0]
^ i30[7:0];
assign s01[7:0] = {i01[6:0],1'b0} ^ ({8{i01[7]}} & 8'h1b)
^ {i11[6:0],1'b0} ^ ({8{i11[7]}} & 8'h1b) ^ i11[7:0]
^ i21[7:0]
^ i31[7:0];
assign s02[7:0] = {i02[6:0],1'b0} ^ ({8{i02[7]}} & 8'h1b)
^ {i12[6:0],1'b0} ^ ({8{i12[7]}} & 8'h1b) ^ i12[7:0]
^ i22[7:0]
^ i32[7:0];
assign s03[7:0] = {i03[6:0],1'b0} ^ ({8{i03[7]}} & 8'h1b)
^ {i13[6:0],1'b0} ^ ({8{i13[7]}} & 8'h1b) ^ i13[7:0]
^ i23[7:0]
^ i33[7:0];
assign s10[7:0] = i00[7:0]
^ {i10[6:0],1'b0} ^ ({8{i10[7]}} & 8'h1b)
^ {i20[6:0],1'b0} ^ ({8{i20[7]}} & 8'h1b) ^ i20[7:0]
^ i30[7:0];
assign s11[7:0] = i01[7:0]
^ {i11[6:0],1'b0} ^ ({8{i11[7]}} & 8'h1b)
^ {i21[6:0],1'b0} ^ ({8{i21[7]}} & 8'h1b) ^ i21[7:0]
^ i31[7:0];
assign s12[7:0] = i02[7:0]
^ {i12[6:0],1'b0} ^ ({8{i12[7]}} & 8'h1b)
^ {i22[6:0],1'b0} ^ ({8{i22[7]}} & 8'h1b) ^ i22[7:0]
^ i32[7:0];
assign s13[7:0] = i03[7:0]
^ {i13[6:0],1'b0} ^ ({8{i13[7]}} & 8'h1b)
^ {i23[6:0],1'b0} ^ ({8{i23[7]}} & 8'h1b) ^ i23[7:0]
^ i33[7:0];
assign s20[7:0] = i00[7:0]
^ i10[7:0]
^ {i20[6:0],1'b0} ^ ({8{i20[7]}} & 8'h1b)
^ {i30[6:0],1'b0} ^ ({8{i30[7]}} & 8'h1b) ^ i30[7:0];
assign s21[7:0] = i01[7:0]
^ i11[7:0]
^ {i21[6:0],1'b0} ^ ({8{i21[7]}} & 8'h1b)
^ {i31[6:0],1'b0} ^ ({8{i31[7]}} & 8'h1b) ^ i31[7:0];
assign s22[7:0] = i02[7:0]
^ i12[7:0]
^ {i22[6:0],1'b0} ^ ({8{i22[7]}} & 8'h1b)
^ {i32[6:0],1'b0} ^ ({8{i32[7]}} & 8'h1b) ^ i32[7:0];
assign s23[7:0] = i03[7:0]
^ i13[7:0]
^ {i23[6:0],1'b0} ^ ({8{i23[7]}} & 8'h1b)
^ {i33[6:0],1'b0} ^ ({8{i33[7]}} & 8'h1b) ^ i33[7:0];
assign s30[7:0] = {i00[6:0],1'b0} ^ ({8{i00[7]}} & 8'h1b) ^ i00[7:0]
^ i10[7:0]
^ i20[7:0]
^ {i30[6:0],1'b0} ^ ({8{i30[7]}} & 8'h1b);
assign s31[7:0] = {i01[6:0],1'b0} ^ ({8{i01[7]}} & 8'h1b) ^ i01[7:0]
^ i11[7:0]
^ i21[7:0]
^ {i31[6:0],1'b0} ^ ({8{i31[7]}} & 8'h1b);
assign s32[7:0] = {i02[6:0],1'b0} ^ ({8{i02[7]}} & 8'h1b) ^ i02[7:0]
^ i12[7:0]
^ i22[7:0]
^ {i32[6:0],1'b0} ^ ({8{i32[7]}} & 8'h1b);
assign s33[7:0] = {i03[6:0],1'b0} ^ ({8{i03[7]}} & 8'h1b) ^ i03[7:0]
^ i13[7:0]
^ i23[7:0]
^ {i33[6:0],1'b0} ^ ({8{i33[7]}} & 8'h1b);
assign mc[127:120] = s33[7:0];
assign mc[119:112] = s23[7:0];
assign mc[111:104] = s13[7:0];
assign mc[103:96] = s03[7:0];
assign mc[95:88] = s32[7:0];
assign mc[87:80] = s22[7:0];
assign mc[79:72] = s12[7:0];
assign mc[71:64] = s02[7:0];
assign mc[63:56] = s31[7:0];
assign mc[55:48] = s21[7:0];
assign mc[47:40] = s11[7:0];
assign mc[39:32] = s01[7:0];
assign mc[31:24] = s30[7:0];
assign mc[23:16] = s20[7:0];
assign mc[15:8] = s10[7:0];
assign mc[7:0] = s00[7:0];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_crypt
(
input wire clk,
input wire reset,
input wire ival_v1_q,
input wire sha1c_v1_q,
input wire sha1p_v1_q,
input wire sha1m_v1_q,
input wire sha1cpm_v1_q,
input wire sha256h_v1_q,
input wire sha256h2_v1_q,
input wire sha256hh2_v1_q,
input wire sha1h_v1_q,
input wire sha1su0_v1_q,
input wire sha1su1_v1_q,
input wire sha256su0_v1_q,
input wire sha256su1_v1_q,
input wire sha256su1_dup_x_v1_q,
input wire sha256su1_dup_y_v1_q,
input wire sha256su1_dup_z_v1_q,
input wire [127:0] opa_v1,
input wire [127:0] opb_v1,
input wire [127:0] opc_v1,
output wire [127:0] cryptout_v2,
output wire [127:0] cryptout_v4,
output wire crypt_active
);
wire block_opa_passthrough;
wire [63:0] carry1c_v1;
wire [63:0] carry4c_v3;
wire [31:0] carry4c_v4;
wire [63:0] carry_2c4c_v2;
wire [31:0] carry_sha1cpm_v1;
wire [31:0] carry_sha1cpm_v2;
wire [31:0] carry_sha1cpm_v3;
wire [31:0] carry_sha1cpm_v4;
wire [63:0] carry_sha256h32_v1;
wire [63:0] carry_sha256h32_v2;
wire [63:0] carry_sha256h32_v3;
wire [31:0] carry_sha256h32_v4;
wire [31:0] carry_sha256su0_v1;
wire [63:0] carry_sha256su1_v1;
wire [63:0] carry_sha256su1_v2;
wire ival_en;
wire ival_v1_or_v2;
wire ival_v2_4latency;
reg ival_v2_q;
reg ival_v3_q;
wire [127:0] newa_v1;
wire [127:0] newa_v2;
wire [127:0] newa_v3;
wire [127:0] newb_v1;
wire [127:0] newb_v2;
wire [127:0] newb_v3;
wire [95:0] newc_v1;
wire [127:0] newx_v4;
wire [127:0] newy_v4;
reg [127:0] opa_v2_q;
reg [127:0] opa_v3_q;
reg [127:0] opa_v4_q;
reg [127:0] opb_v2_q;
reg [127:0] opb_v3_q;
reg [127:0] opb_v4_q;
reg [95:0] opc_v2_q;
reg [63:0] opc_v3_q;
reg [31:0] opc_v4_q;
wire [127:0] sha1_out_v1;
wire sha1_v1;
wire [127:0] sha1_xin_v1;
wire [31:0] sha1_yin_v1;
wire [31:0] sha1_zin_v1;
reg sha1c_v2_q;
reg sha1c_v3_q;
reg sha1c_v4_q;
reg sha1cpm_h_v4_q;
reg sha1cpm_l_v4_q;
reg sha1cpm_v2_q;
reg sha1cpm_v3_q;
reg sha1cpm_v4_q;
wire [127:0] sha1cpm_x_v1;
wire [127:0] sha1cpm_x_v2;
wire [127:0] sha1cpm_x_v3;
wire [127:0] sha1cpm_x_v4;
wire [127:0] sha1cpm_y_v1;
wire [127:0] sha1cpm_y_v2;
wire [127:0] sha1cpm_y_v3;
wire [31:0] sha1cpm_y_v4;
wire [31:0] sha1h_qnin_v1;
reg sha1m_v2_q;
reg sha1m_v3_q;
reg sha1m_v4_q;
reg sha1p_v2_q;
reg sha1p_v3_q;
reg sha1p_v4_q;
wire [127:0] sha1su0_q_v1;
reg sha1su0_v2_q;
wire [127:0] sha1su1_qdin_v1;
wire [127:0] sha1su1_qnin_v1;
wire [127:0] sha256_xin_v1;
wire [127:0] sha256_yin_v1;
wire [31:0] sha256_zin_v1;
reg sha256h2_h_v4_q;
reg sha256h2_l_v4_q;
reg sha256h2_v2_q;
reg sha256h2_v3_q;
reg sha256h2_v4_q;
reg sha256h_h_v4_q;
reg sha256h_l_v4_q;
reg sha256h_v2_q;
reg sha256h_v3_q;
reg sha256h_v4_q;
wire [127:0] sha256h_x_v1;
wire [127:0] sha256h_x_v2;
wire [127:0] sha256h_x_v3;
wire [127:0] sha256h_x_v4;
wire [127:0] sha256h_y_v1;
wire [127:0] sha256h_y_v2;
wire [127:0] sha256h_y_v3;
wire [127:0] sha256h_y_v4;
wire sha256hh2_v2;
wire sha256hh2_v3;
wire sha256hh2_v4;
wire [127:0] sha256su0_out_v1;
wire [127:0] sha256su0_qdin_v1;
wire [127:0] sha256su0_qnin_v1;
reg sha256su1_dup_x_v2_q;
reg sha256su1_dup_y_v2_q;
reg sha256su1_dup_z_v2_q;
reg sha256su1_h_v2_q;
reg sha256su1_l_v2_q;
reg sha256su1_v2_q;
wire [63:0] sha256su1_x_v1;
wire [63:0] sha256su1_x_v2;
reg sha_inst_h_v2_q;
reg sha_inst_l_v2_q;
wire sha_inst_v1;
reg sha_inst_v2_q;
wire short_pipe_out_v3_en;
wire [31:0] sigma0_v3;
wire [31:0] sigma0_v4;
wire [31:0] sigma1_v3;
wire [63:0] sum1c_v1;
wire [63:0] sum4c_v3;
wire [31:0] sum4c_v4;
wire [63:0] sum_2c4c_v2;
wire [31:0] sum_sha1cpm_v1;
wire [31:0] sum_sha1cpm_v2;
wire [31:0] sum_sha1cpm_v3;
wire [31:0] sum_sha1cpm_v4;
wire [63:0] sum_sha256h32_v1;
wire [63:0] sum_sha256h32_v2;
wire [63:0] sum_sha256h32_v3;
wire [31:0] sum_sha256h32_v4;
wire [31:0] sum_sha256su0_v1;
wire [63:0] sum_sha256su1_v1;
wire [63:0] sum_sha256su1_v2;
wire [63:0] sumnr1c_v1;
wire [63:0] sumnr4c_v3;
wire [31:0] sumnr4c_v4;
wire [63:0] sumnr_2c4c_v2;
wire [63:0] sumres_sha256su1_v2;
wire [31:0] tchoose_v3;
wire [31:0] tmajority_v3;
wire [31:0] tmajority_v4;
wire unused_cout1c2_v1;
wire unused_cout1c_v1;
wire unused_cout2_2c4c_v2;
wire unused_cout2_4c_v3;
wire unused_cout4c_v3;
wire unused_cout4c_v4;
wire unused_cout_2c4c_v2;
wire unused_cout_sha256su1h_v2;
wire unused_cout_sha256su1l_v2;
wire [32:0] x_fa2_c_v4;
wire [31:0] x_fa2_s_v4;
wire [127:0] x_v1;
wire [127:0] x_v2;
wire [127:0] x_v3;
wire [127:0] x_v4;
wire xprime_carry;
wire [127:96] xprime_v4;
wire [32:0] xy_fa0_c_v3;
wire [31:0] xy_fa0_s_v3;
wire [32:0] xy_fa1_c_v3;
wire [31:0] xy_fa1_c_v4;
wire [31:0] xy_fa1_s_v3;
wire [31:0] xy_fa1_s_v4;
wire [32:0] y_fa2_c_v4;
wire [31:0] y_fa2_s_v4;
wire [32:0] y_fa3_c_v4;
wire [31:0] y_fa3_s_v4;
wire [127:0] y_v1;
wire [127:0] y_v2;
wire [127:0] y_v3;
wire [127:0] y_v4;
wire [127:96] yprime_v4;
wire [127:0] z_v1;
wire [95:0] z_v2;
wire [63:0] z_v3;
wire [31:0] z_v4;
assign ival_en = ival_v1_q | ival_v2_q | ival_v3_q;
assign short_pipe_out_v3_en = sha_inst_v2_q | sha1su0_v2_q | sha256su1_v2_q;
assign ival_v2_4latency = ~short_pipe_out_v3_en & ival_v2_q;
assign ival_v1_or_v2 = ival_v1_q | ival_v2_q;
always_ff @(posedge clk or posedge reset)
begin: u_ival_v2_q
if (reset == 1'b1)
ival_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_en == 1'b1)
ival_v2_q <= `HERCULESAE_DFF_DELAY ival_v1_q;
else if (reset == 1'b0 && ival_en == 1'b0)
begin
end
else
ival_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
`else
else if (ival_en == 1'b1)
ival_v2_q <= `HERCULESAE_DFF_DELAY ival_v1_q;
`endif
end
always_ff @(posedge clk or posedge reset)
begin: u_ival_v3_q
if (reset == 1'b1)
ival_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_en == 1'b1)
ival_v3_q <= `HERCULESAE_DFF_DELAY ival_v2_4latency;
else if (reset == 1'b0 && ival_en == 1'b0)
begin
end
else
ival_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
`else
else if (ival_en == 1'b1)
ival_v3_q <= `HERCULESAE_DFF_DELAY ival_v2_4latency;
`endif
end
always_ff @(posedge clk or posedge reset)
begin: u_sha1c_v2_q_grp
if (reset == 1'b1) begin
sha1c_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1p_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1m_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h2_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha_inst_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1su0_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256su1_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
sha1c_v2_q <= `HERCULESAE_DFF_DELAY sha1c_v1_q;
sha1p_v2_q <= `HERCULESAE_DFF_DELAY sha1p_v1_q;
sha1m_v2_q <= `HERCULESAE_DFF_DELAY sha1m_v1_q;
sha256h_v2_q <= `HERCULESAE_DFF_DELAY sha256h_v1_q;
sha256h2_v2_q <= `HERCULESAE_DFF_DELAY sha256h2_v1_q;
sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY sha1cpm_v1_q;
sha_inst_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
sha1su0_v2_q <= `HERCULESAE_DFF_DELAY sha1su0_v1_q;
sha256su1_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
end
else if (reset == 1'b0 && ival_v1_q == 1'b0)
begin
end
else begin
sha1c_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1p_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1m_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h2_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha_inst_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1su0_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256su1_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
end
`else
else if (ival_v1_q == 1'b1) begin
sha1c_v2_q <= `HERCULESAE_DFF_DELAY sha1c_v1_q;
sha1p_v2_q <= `HERCULESAE_DFF_DELAY sha1p_v1_q;
sha1m_v2_q <= `HERCULESAE_DFF_DELAY sha1m_v1_q;
sha256h_v2_q <= `HERCULESAE_DFF_DELAY sha256h_v1_q;
sha256h2_v2_q <= `HERCULESAE_DFF_DELAY sha256h2_v1_q;
sha1cpm_v2_q <= `HERCULESAE_DFF_DELAY sha1cpm_v1_q;
sha_inst_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
sha_inst_h_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
sha_inst_l_v2_q <= `HERCULESAE_DFF_DELAY sha_inst_v1;
sha1su0_v2_q <= `HERCULESAE_DFF_DELAY sha1su0_v1_q;
sha256su1_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_h_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_l_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_dup_x_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_dup_y_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
sha256su1_dup_z_v2_q <= `HERCULESAE_DFF_DELAY sha256su1_v1_q;
end
`endif
end
always_ff @(posedge clk or posedge reset)
begin: u_sha1c_v3_q_grp
if (reset == 1'b1) begin
sha1c_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1p_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1m_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h2_v3_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v2_4latency == 1'b1) begin
sha1c_v3_q <= `HERCULESAE_DFF_DELAY sha1c_v2_q;
sha1p_v3_q <= `HERCULESAE_DFF_DELAY sha1p_v2_q;
sha1m_v3_q <= `HERCULESAE_DFF_DELAY sha1m_v2_q;
sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY sha1cpm_v2_q;
sha256h_v3_q <= `HERCULESAE_DFF_DELAY sha256h_v2_q;
sha256h2_v3_q <= `HERCULESAE_DFF_DELAY sha256h2_v2_q;
end
else if (reset == 1'b0 && ival_v2_4latency == 1'b0)
begin
end
else begin
sha1c_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1p_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1m_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h2_v3_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
end
`else
else if (ival_v2_4latency == 1'b1) begin
sha1c_v3_q <= `HERCULESAE_DFF_DELAY sha1c_v2_q;
sha1p_v3_q <= `HERCULESAE_DFF_DELAY sha1p_v2_q;
sha1m_v3_q <= `HERCULESAE_DFF_DELAY sha1m_v2_q;
sha1cpm_v3_q <= `HERCULESAE_DFF_DELAY sha1cpm_v2_q;
sha256h_v3_q <= `HERCULESAE_DFF_DELAY sha256h_v2_q;
sha256h2_v3_q <= `HERCULESAE_DFF_DELAY sha256h2_v2_q;
end
`endif
end
always_ff @(posedge clk or posedge reset)
begin: u_sha1c_v4_q_grp
if (reset == 1'b1) begin
sha1c_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1p_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1m_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h2_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v3_q == 1'b1) begin
sha1c_v4_q <= `HERCULESAE_DFF_DELAY sha1c_v3_q;
sha1p_v4_q <= `HERCULESAE_DFF_DELAY sha1p_v3_q;
sha1m_v4_q <= `HERCULESAE_DFF_DELAY sha1m_v3_q;
sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
sha256h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h2_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q;
sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q;
end
else if (reset == 1'b0 && ival_v3_q == 1'b0)
begin
end
else begin
sha1c_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1p_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1m_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h2_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY {1{1'bx}};
end
`else
else if (ival_v3_q == 1'b1) begin
sha1c_v4_q <= `HERCULESAE_DFF_DELAY sha1c_v3_q;
sha1p_v4_q <= `HERCULESAE_DFF_DELAY sha1p_v3_q;
sha1m_v4_q <= `HERCULESAE_DFF_DELAY sha1m_v3_q;
sha1cpm_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
sha1cpm_h_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
sha1cpm_l_v4_q <= `HERCULESAE_DFF_DELAY sha1cpm_v3_q;
sha256h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h2_v4_q <= `HERCULESAE_DFF_DELAY sha256h_v3_q;
sha256h2_h_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q;
sha256h2_l_v4_q <= `HERCULESAE_DFF_DELAY sha256h2_v3_q;
end
`endif
end
assign sha1_v1 = sha1h_v1_q | sha1su0_v1_q | sha1su1_v1_q;
assign sha1h_qnin_v1[ 31:0] = {32{sha1h_v1_q}} & opa_v1[ 31:0];
assign sha1su1_qdin_v1[127:0] = {128{sha1su0_v1_q | sha1su1_v1_q}} & opb_v1[127:0];
assign sha1su1_qnin_v1[127:0] = {128{sha1su0_v1_q | sha1su1_v1_q}} & opa_v1[127:0];
assign sha1su0_q_v1[127:0] = {128{sha1su0_v1_q}} & opc_v1[127:0];
herculesae_vx_sha1 u_sha1(
.sha1h_v1_i (sha1h_v1_q),
.sha1su0_v1_i (sha1su0_v1_q),
.sha1su1_v1_i (sha1su1_v1_q),
.sha1h_qn (sha1h_qnin_v1[31:0]),
.sha1su0_qd (sha1su0_q_v1[127:0]),
.sha1su1_qd (sha1su1_qdin_v1[127:0]),
.sha1su1_qn (sha1su1_qnin_v1[127:0]),
.sha1_v1_o (sha1_out_v1[127:0]));
assign sha256su0_qdin_v1[127:0] = {128{sha256su0_v1_q}} & opb_v1[127:0];
assign sha256su0_qnin_v1[127:0] = {128{sha256su0_v1_q}} & opa_v1[127:0];
herculesae_vx_sha256su0 u_sha256su0(
.qd (sha256su0_qdin_v1[127:0]),
.qn (sha256su0_qnin_v1[ 31:0]),
.sumd (sumnr1c_v1[31:0]),
.suma (sum_sha256su0_v1[31:0]),
.sumb (carry_sha256su0_v1[31:0]),
.d (sha256su0_out_v1[127:0]));
herculesae_vx_sha256su1 u_sha256su1_v1(
.sha256su1_x_op (sha256su1_dup_x_v1_q),
.sha256su1_y_op (sha256su1_dup_y_v1_q),
.sha256su1_z_op (sha256su1_dup_z_v1_q),
.x (opc_v1[63:0]),
.y (opa_v1[95:32]),
.z (opb_v1[127:64]),
.sumnr (sumnr1c_v1[63:0]),
.sum_3to2 (sum_sha256su1_v1[63:0]),
.carry_3to2 (carry_sha256su1_v1[63:0]),
.newx (sha256su1_x_v1[63:0]));
assign x_v1[127:0] = opc_v1[127:0];
assign y_v1[127:0] = opa_v1[127:0];
assign z_v1[127:0] = opb_v1[127:0];
assign sha1_xin_v1[127:0] = {128{sha1cpm_v1_q}} & x_v1[127:0];
assign sha1_yin_v1[31:0] = { 32{sha1cpm_v1_q}} & y_v1[31:0];
assign sha1_zin_v1[31:0] = { 32{sha1cpm_v1_q}} & z_v1[31:0];
herculesae_vx_sha1cpm u_sha1cpm_v1(
.choose (sha1c_v1_q),
.parity (sha1p_v1_q),
.majority (sha1m_v1_q),
.cpm (sha1cpm_v1_q),
.x (sha1_xin_v1[127:0]),
.y (sha1_yin_v1[31:0]),
.z (sha1_zin_v1[31:0]),
.t2 (sumnr1c_v1[31:0]),
.fa1_s (sum_sha1cpm_v1[31:0]),
.fa1_c (carry_sha1cpm_v1[31:0]),
.newx (sha1cpm_x_v1[127:0]),
.newy (sha1cpm_y_v1[31:0]));
assign sha1cpm_y_v1[127:32] = {96{sha1cpm_v1_q}} & y_v1[127:32];
assign sha256_xin_v1[127:0] = {128{sha256hh2_v1_q}} & x_v1[127:0];
assign sha256_yin_v1[127:0] = {128{sha256hh2_v1_q}} & y_v1[127:0];
assign sha256_zin_v1[ 31:0] = {32{ sha256hh2_v1_q}} & z_v1[31:0];
herculesae_vx_sha256h32 u_sha256h32_v1(
.x (sha256_xin_v1[127:0]),
.y (sha256_yin_v1[127:0]),
.z (sha256_zin_v1[31:0]),
.sumnr (sumnr1c_v1[63:0]),
.sum (sum_sha256h32_v1[63:0]),
.carry (carry_sha256h32_v1[63:0]),
.newx (sha256h_x_v1[127:0]),
.newy (sha256h_y_v1[127:0]));
assign sum1c_v1[31:0] = {32{sha256su0_v1_q}} & sum_sha256su0_v1[31:0]
| {32{sha1cpm_v1_q }} & sum_sha1cpm_v1[31:0]
| {32{sha256hh2_v1_q}} & sum_sha256h32_v1[31:0]
| {32{sha256su1_v1_q}} & sum_sha256su1_v1[31:0];
assign carry1c_v1[31:0] = {32{sha256su0_v1_q}} & carry_sha256su0_v1[31:0]
| {32{sha1cpm_v1_q }} & carry_sha1cpm_v1[31:0]
| {32{sha256hh2_v1_q}} & carry_sha256h32_v1[31:0]
| {32{sha256su1_v1_q}} & carry_sha256su1_v1[31:0];
assign {unused_cout1c_v1, sumnr1c_v1[31:0]} = sum1c_v1[31:0] + carry1c_v1[31:0] + {{31{1'b0}}, 1'b0};
assign sum1c_v1[63:32] = {32{sha256hh2_v1_q}} & sum_sha256h32_v1[63:32]
| {32{sha256su1_v1_q}} & sum_sha256su1_v1[63:32];
assign carry1c_v1[63:32] = {32{sha256hh2_v1_q}} & carry_sha256h32_v1[63:32]
| {32{sha256su1_v1_q}} & carry_sha256su1_v1[63:32];
assign {unused_cout1c2_v1, sumnr1c_v1[63:32]} = sum1c_v1[63:32] + carry1c_v1[63:32] + {{31{1'b0}}, 1'b0};
assign sha_inst_v1 = sha1h_v1_q | sha1su0_v1_q | sha1su1_v1_q | sha256su0_v1_q;
assign block_opa_passthrough = sha_inst_v1 | sha256su1_v1_q |
sha256hh2_v1_q | sha1cpm_v1_q;
assign newa_v1[127:0] = ({128{sha1cpm_v1_q }} & sha1cpm_y_v1[127:0])
| ({128{sha256hh2_v1_q}} & sha256h_y_v1[127:0])
| ({128{sha256su1_v1_q}} & {opb_v1[31:0],opa_v1[127:32]})
| ({128{sha256su0_v1_q}} & sha256su0_out_v1[127:0])
| ({128{sha1_v1}} & sha1_out_v1[127:0])
| ({128{~(block_opa_passthrough)}} & opa_v1[127:0]);
assign newb_v1[127:0] = ({128{sha1cpm_v1_q }} & sha1cpm_x_v1[127:0])
| ({128{sha256hh2_v1_q}} & sha256h_x_v1[127:0])
| ({128{sha256su1_v1_q}} & {opc_v1[127:64], sha256su1_x_v1[63:0]});
assign newc_v1[95:0] = opb_v1[127:32];
always_ff @(posedge clk or posedge reset)
begin: u_opa_v2_q_127_0_grp
if (reset == 1'b1) begin
opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY {96{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v1_q == 1'b1) begin
opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v1[127:0];
opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v1[127:0];
opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY newc_v1[95:0];
end
else if (reset == 1'b0 && ival_v1_q == 1'b0)
begin
end
else begin
opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY {96{1'bx}};
end
`else
else if (ival_v1_q == 1'b1) begin
opa_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v1[127:0];
opb_v2_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v1[127:0];
opc_v2_q[95:0] <= `HERCULESAE_DFF_DELAY newc_v1[95:0];
end
`endif
end
assign x_v2[127:0] = opb_v2_q[127:0];
assign y_v2[127:0] = opa_v2_q[127:0];
assign z_v2[95:0] = opc_v2_q[95:0];
herculesae_vx_sha256su1 u_sha256su1_v2(
.sha256su1_x_op (sha256su1_dup_x_v2_q),
.sha256su1_y_op (sha256su1_dup_y_v2_q),
.sha256su1_z_op (sha256su1_dup_z_v2_q),
.x (x_v2[127:64]),
.y (y_v2[127:64]),
.z (x_v2[63:0]),
.sumnr (sumres_sha256su1_v2[63:0]),
.sum_3to2 (sum_sha256su1_v2[63:0]),
.carry_3to2 (carry_sha256su1_v2[63:0]),
.newx (sha256su1_x_v2[63:0]));
herculesae_vx_sha1cpm u_sha1cpm_v2(
.choose (sha1c_v2_q),
.parity (sha1p_v2_q),
.majority (sha1m_v2_q),
.cpm (sha1cpm_v2_q),
.x (x_v2[127:0]),
.y (y_v2[31:0]),
.z (z_v2[31:0]),
.t2 (sumnr_2c4c_v2[31:0]),
.fa1_s (sum_sha1cpm_v2[31:0]),
.fa1_c (carry_sha1cpm_v2[31:0]),
.newx (sha1cpm_x_v2[127:0]),
.newy (sha1cpm_y_v2[31:0]));
assign sha1cpm_y_v2[127:32] = y_v2[127:32];
herculesae_vx_sha256h32 u_sha256h32_v2(
.x (x_v2[127:0]),
.y (y_v2[127:0]),
.z (z_v2[31:0]),
.sumnr (sumnr_2c4c_v2[63:0]),
.sum (sum_sha256h32_v2[63:0]),
.carry (carry_sha256h32_v2[63:0]),
.newx (sha256h_x_v2[127:0]),
.newy (sha256h_y_v2[127:0]));
assign sha256hh2_v2 = sha256h_v2_q | sha256h2_v2_q;
assign sum_2c4c_v2[31:0] = {32{sha1cpm_v2_q}} & sum_sha1cpm_v2[31:0] |
{32{sha256hh2_v2}} & sum_sha256h32_v2[31:0];
assign carry_2c4c_v2[31:0] = {32{sha1cpm_v2_q}} & carry_sha1cpm_v2[31:0] |
{32{sha256hh2_v2}} & carry_sha256h32_v2[31:0];
assign {unused_cout_2c4c_v2, sumnr_2c4c_v2[31:0]} = sum_2c4c_v2[31:0] + carry_2c4c_v2[31:0] + {{31{1'b0}}, 1'b0};
assign sum_2c4c_v2[63:32] = {32{sha256hh2_v2}} & sum_sha256h32_v2[63:32];
assign carry_2c4c_v2[63:32] = {32{sha256hh2_v2}} & carry_sha256h32_v2[63:32];
assign {unused_cout2_2c4c_v2, sumnr_2c4c_v2[63:32]} = sum_2c4c_v2[63:32] + carry_2c4c_v2[63:32] + {{31{1'b0}}, 1'b0};
assign {unused_cout_sha256su1l_v2, sumres_sha256su1_v2[31:0]} = sum_sha256su1_v2[31:0] + carry_sha256su1_v2[31:0] + {{31{1'b0}}, 1'b0};
assign {unused_cout_sha256su1h_v2, sumres_sha256su1_v2[63:32]} = sum_sha256su1_v2[63:32] + carry_sha256su1_v2[63:32] + {{31{1'b0}}, 1'b0};
assign newb_v2[127:0] = ({128{sha1cpm_v2_q}} & sha1cpm_x_v2[127:0])
| ({128{sha256hh2_v2}} & sha256h_x_v2[127:0]);
assign newa_v2[127:0] = ({128{sha1cpm_v2_q}} & sha1cpm_y_v2[127:0])
| ({128{sha256hh2_v2}} & sha256h_y_v2[127:0]);
assign cryptout_v2[127:64] = ({64{sha256su1_h_v2_q}} & sha256su1_x_v2[63:0])
| ({64{sha_inst_h_v2_q}} & opa_v2_q[127:64]);
assign cryptout_v2[63:0] = ({64{sha256su1_l_v2_q}} & opb_v2_q[63:0])
| ({64{sha_inst_l_v2_q}} & opa_v2_q[63:0]);
always_ff @(posedge clk or posedge reset)
begin: u_opa_v3_q_127_0_grp
if (reset == 1'b1) begin
opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY {64{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v2_4latency == 1'b1) begin
opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v2[127:0];
opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v2[127:0];
opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY opc_v2_q[95:32];
end
else if (reset == 1'b0 && ival_v2_4latency == 1'b0)
begin
end
else begin
opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY {64{1'bx}};
end
`else
else if (ival_v2_4latency == 1'b1) begin
opa_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v2[127:0];
opb_v3_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v2[127:0];
opc_v3_q[63:0] <= `HERCULESAE_DFF_DELAY opc_v2_q[95:32];
end
`endif
end
assign x_v3[127:0] = opb_v3_q[127:0];
assign y_v3[127:0] = opa_v3_q[127:0];
assign z_v3[63:0] = opc_v3_q[63:0];
herculesae_vx_sha1cpm u_sha1cpm_v3(
.choose (sha1c_v3_q),
.parity (sha1p_v3_q),
.majority (sha1m_v3_q),
.cpm (sha1cpm_v3_q),
.x (x_v3[127:0]),
.y (y_v3[31:0]),
.z (z_v3[31:0]),
.t2 (sumnr4c_v3[31:0]),
.fa1_s (sum_sha1cpm_v3[31:0]),
.fa1_c (carry_sha1cpm_v3[31:0]),
.newx (sha1cpm_x_v3[127:0]),
.newy (sha1cpm_y_v3[31:0]));
assign sha1cpm_y_v3[127:32] = y_v3[127:32];
herculesae_vx_sha256h32 u_sha256h32_v3(
.x (x_v3[127:0]),
.y (y_v3[127:0]),
.z (z_v3[31:0]),
.sumnr (sumnr4c_v3[63:0]),
.sum (sum_sha256h32_v3[63:0]),
.carry (carry_sha256h32_v3[63:0]),
.newx (sha256h_x_v3[127:0]),
.newy (sha256h_y_v3[127:0]));
assign tchoose_v3[31:0] = (sha256h_y_v3[31:0] & sha256h_y_v3[63:32]) |
(~sha256h_y_v3[31:0] & sha256h_y_v3[95:64]);
assign tmajority_v3[31:0] = (sha256h_x_v3[31:0] & sha256h_x_v3[63:32]) |
(sha256h_x_v3[31:0] & sha256h_x_v3[95:64]) |
(sha256h_x_v3[63:32] & sha256h_x_v3[95:64]);
assign sigma0_v3[31:0] = {sha256h_x_v3[1:0], sha256h_x_v3[31:2]}
^ {sha256h_x_v3[12:0], sha256h_x_v3[31:13]}
^ {sha256h_x_v3[21:0], sha256h_x_v3[31:22]};
assign sigma1_v3[31:0] = {sha256h_y_v3[5:0], sha256h_y_v3[31:6]}
^ {sha256h_y_v3[10:0], sha256h_y_v3[31:11]}
^ {sha256h_y_v3[24:0], sha256h_y_v3[31:25]};
assign xy_fa0_s_v3[31:0] = sha256h_y_v3[127:96] ^ z_v3[63:32] ^ tchoose_v3[31:0];
assign xy_fa0_c_v3[32:0] = {sha256h_y_v3[127:96] & z_v3[63:32] | tchoose_v3[31:0] &
(sha256h_y_v3[127:96] | z_v3[63:32]), 1'b0};
assign xy_fa1_s_v3[31:0] = xy_fa0_s_v3[31:0] ^ xy_fa0_c_v3[31:0] ^ sigma1_v3[31:0];
assign xy_fa1_c_v3[32:0] = {xy_fa0_s_v3[31:0] & xy_fa0_c_v3[31:0] | sigma1_v3[31:0] &
(xy_fa0_s_v3[31:0] | xy_fa0_c_v3[31:0]), 1'b0};
assign sha256hh2_v3 = sha256h_v3_q | sha256h2_v3_q;
assign sum4c_v3[31:0] = {32{sha1cpm_v3_q}} & sum_sha1cpm_v3[31:0] |
{32{sha256hh2_v3}} & sum_sha256h32_v3[31:0];
assign carry4c_v3[31:0] = {32{sha1cpm_v3_q}} & carry_sha1cpm_v3[31:0] |
{32{sha256hh2_v3}} & carry_sha256h32_v3[31:0];
assign {unused_cout4c_v3, sumnr4c_v3[31:0]} = sum4c_v3[31:0] + carry4c_v3[31:0] + {{31{1'b0}}, 1'b0};
assign sum4c_v3[63:32] = sum_sha256h32_v3[63:32];
assign carry4c_v3[63:32] = carry_sha256h32_v3[63:32];
assign {unused_cout2_4c_v3, sumnr4c_v3[63:32]} = sum4c_v3[63:32] + carry4c_v3[63:32] + {{31{1'b0}}, 1'b0};
assign newa_v3[127:0] = ({128{sha1cpm_v3_q}} & sha1cpm_y_v3[127:0])
| ({128{sha256h_v3_q}} & {sigma0_v3[31:0], tmajority_v3[31:0],
xy_fa1_s_v3[31:0], xy_fa1_c_v3[31:0]})
| ({128{sha256h2_v3_q}} & {sigma0_v3[31:0],tmajority_v3[31:0],
xy_fa1_s_v3[31:0],xy_fa1_c_v3[31:0]});
assign newb_v3[127:0] = ({128{sha1cpm_v3_q}} & sha1cpm_x_v3[127:0])
| ({128{sha256h_v3_q }} & sha256h_x_v3[127:0])
| ({128{sha256h2_v3_q }} & {sha256h_x_v3[127:96], sha256h_y_v3[95:0]});
always_ff @(posedge clk or posedge reset)
begin: u_opb_v4_q_127_0_grp
if (reset == 1'b1) begin
opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY {32{1'b0}};
end
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v3_q == 1'b1) begin
opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v3[127:0];
opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v3[127:0];
opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY opc_v3_q[63:32];
end
else if (reset == 1'b0 && ival_v3_q == 1'b0)
begin
end
else begin
opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY {32{1'bx}};
end
`else
else if (ival_v3_q == 1'b1) begin
opb_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newb_v3[127:0];
opa_v4_q[127:0] <= `HERCULESAE_DFF_DELAY newa_v3[127:0];
opc_v4_q[31:0] <= `HERCULESAE_DFF_DELAY opc_v3_q[63:32];
end
`endif
end
assign x_v4[127:0] = opb_v4_q[127:0];
assign y_v4[127:0] = opa_v4_q[127:0];
assign z_v4[31:0] = opc_v4_q[31:0];
herculesae_vx_sha1cpm u_sha1cpm_v4(
.choose (sha1c_v4_q),
.parity (sha1p_v4_q),
.majority (sha1m_v4_q),
.cpm (sha1cpm_v4_q),
.x (x_v4[127:0]),
.y (y_v4[31:0]),
.z (z_v4[31:0]),
.t2 (sumnr4c_v4[31:0]),
.fa1_s (sum_sha1cpm_v4[31:0]),
.fa1_c (carry_sha1cpm_v4[31:0]),
.newx (sha1cpm_x_v4[127:0]),
.newy (sha1cpm_y_v4[31:0]));
assign sigma0_v4[31:0] = y_v4[127:96];
assign tmajority_v4[31:0] = y_v4[95:64];
assign xy_fa1_s_v4[31:0] = y_v4[63:32];
assign xy_fa1_c_v4[31:0] = y_v4[31:0];
assign x_fa2_s_v4[31:0] = xy_fa1_s_v4[31:0] ^ xy_fa1_c_v4[31:0] ^ x_v4[127:96];
assign x_fa2_c_v4[32:0] = {xy_fa1_s_v4[31:0] & xy_fa1_c_v4[31:0] |
x_v4[127:96] & (xy_fa1_s_v4[31:0] |
xy_fa1_c_v4[31:0]), 1'b0};
assign y_fa2_s_v4[31:0] = sigma0_v4[31:0] ^ tmajority_v4[31:0] ^ xy_fa1_c_v4[31:0];
assign y_fa2_c_v4[32:0] = {sigma0_v4[31:0] & tmajority_v4[31:0] |
xy_fa1_c_v4[31:0] & (sigma0_v4[31:0] |
tmajority_v4[31:0]), 1'b0};
assign y_fa3_s_v4[31:0] = y_fa2_s_v4[31:0] ^ y_fa2_c_v4[31:0] ^ xy_fa1_s_v4[31:0];
assign y_fa3_c_v4[32:0] = {y_fa2_s_v4[31:0] & y_fa2_c_v4[31:0] |
xy_fa1_s_v4[31:0] & (y_fa2_s_v4[31:0] |
y_fa2_c_v4[31:0]), 1'b0};
assign {xprime_carry, xprime_v4[127:96]} = x_fa2_s_v4[31:0] + x_fa2_c_v4[31:0] + {{31{1'b0}}, 1'b0};
assign sha256hh2_v4 = sha256h_v4_q | sha256h2_v4_q;
assign sum_sha256h32_v4[31:0] = y_fa3_s_v4[31:0];
assign carry_sha256h32_v4[31:0] = y_fa3_c_v4[31:0];
assign sum4c_v4[31:0] = {32{sha1cpm_v4_q}} & sum_sha1cpm_v4[31:0] |
{32{sha256hh2_v4}} & sum_sha256h32_v4[31:0];
assign carry4c_v4[31:0] = {32{sha1cpm_v4_q}} & carry_sha1cpm_v4[31:0] |
{32{sha256hh2_v4}} & carry_sha256h32_v4[31:0];
assign {unused_cout4c_v4, sumnr4c_v4[31:0]} = sum4c_v4[31:0] + carry4c_v4[31:0] + {{31{1'b0}}, 1'b0};
assign yprime_v4[127:96] = sumnr4c_v4[31:0];
assign newx_v4[127:0] = {x_v4[95:0], yprime_v4[127:96]};
assign newy_v4[127:0] = {x_v4[95:0], xprime_v4[127:96]};
assign sha256h_x_v4[127:0] = newx_v4[127:0];
assign sha256h_y_v4[127:0] = newy_v4[127:0];
assign cryptout_v4[63:0] = ({64{sha1cpm_l_v4_q}} & sha1cpm_x_v4[63:0])
| ({64{sha256h_l_v4_q}} & sha256h_x_v4[63:0])
| ({64{sha256h2_l_v4_q}} & sha256h_y_v4[63:0]);
assign cryptout_v4[127:64] = ({64{sha1cpm_h_v4_q}} & sha1cpm_x_v4[127:64])
| ({64{sha256h_h_v4_q}} & sha256h_x_v4[127:64])
| ({64{sha256h2_h_v4_q}} & sha256h_y_v4[127:64]);
assign crypt_active = ival_v1_or_v2;
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

257
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@ -0,0 +1,257 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_pmull
(
input wire clk,
input wire reset,
input wire ival_v1_q,
input wire [63:0] opa_v1,
input wire [63:0] opb_v1,
output reg [127:0] pmullout_v2_q
);
wire [63:0] a_in;
wire [63:0] b_in;
wire [127:0] p_out;
wire [63:0] pp0;
wire [63:0] pp1;
wire [63:0] pp2;
wire [63:0] pp3;
wire [63:0] pp4;
wire [63:0] pp5;
wire [63:0] pp6;
wire [63:0] pp7;
wire [63:0] pp8;
wire [63:0] pp9;
wire [63:0] pp10;
wire [63:0] pp11;
wire [63:0] pp12;
wire [63:0] pp13;
wire [63:0] pp14;
wire [63:0] pp15;
wire [63:0] pp16;
wire [63:0] pp17;
wire [63:0] pp18;
wire [63:0] pp19;
wire [63:0] pp20;
wire [63:0] pp21;
wire [63:0] pp22;
wire [63:0] pp23;
wire [63:0] pp24;
wire [63:0] pp25;
wire [63:0] pp26;
wire [63:0] pp27;
wire [63:0] pp28;
wire [63:0] pp29;
wire [63:0] pp30;
wire [63:0] pp31;
wire [63:0] pp32;
wire [63:0] pp33;
wire [63:0] pp34;
wire [63:0] pp35;
wire [63:0] pp36;
wire [63:0] pp37;
wire [63:0] pp38;
wire [63:0] pp39;
wire [63:0] pp40;
wire [63:0] pp41;
wire [63:0] pp42;
wire [63:0] pp43;
wire [63:0] pp44;
wire [63:0] pp45;
wire [63:0] pp46;
wire [63:0] pp47;
wire [63:0] pp48;
wire [63:0] pp49;
wire [63:0] pp50;
wire [63:0] pp51;
wire [63:0] pp52;
wire [63:0] pp53;
wire [63:0] pp54;
wire [63:0] pp55;
wire [63:0] pp56;
wire [63:0] pp57;
wire [63:0] pp58;
wire [63:0] pp59;
wire [63:0] pp60;
wire [63:0] pp61;
wire [63:0] pp62;
wire [63:0] pp63;
wire [66:0] rednl0_0;
wire [66:0] rednl0_1;
wire [66:0] rednl0_2;
wire [66:0] rednl0_3;
wire [66:0] rednl0_4;
wire [66:0] rednl0_5;
wire [66:0] rednl0_6;
wire [66:0] rednl0_7;
wire [66:0] rednl0_8;
wire [66:0] rednl0_9;
wire [66:0] rednl0_10;
wire [66:0] rednl0_11;
wire [66:0] rednl0_12;
wire [66:0] rednl0_13;
wire [66:0] rednl0_14;
wire [66:0] rednl0_15;
wire [78:0] rednl1_0;
wire [78:0] rednl1_1;
wire [78:0] rednl1_2;
wire [78:0] rednl1_3;
assign a_in[63:0] = opa_v1[63:0];
assign b_in[63:0] = opb_v1[63:0];
assign pp0[63:0] = {64{a_in[ 0]}} & b_in[63:0];
assign pp1[63:0] = {64{a_in[ 1]}} & b_in[63:0];
assign pp2[63:0] = {64{a_in[ 2]}} & b_in[63:0];
assign pp3[63:0] = {64{a_in[ 3]}} & b_in[63:0];
assign pp4[63:0] = {64{a_in[ 4]}} & b_in[63:0];
assign pp5[63:0] = {64{a_in[ 5]}} & b_in[63:0];
assign pp6[63:0] = {64{a_in[ 6]}} & b_in[63:0];
assign pp7[63:0] = {64{a_in[ 7]}} & b_in[63:0];
assign pp8[63:0] = {64{a_in[ 8]}} & b_in[63:0];
assign pp9[63:0] = {64{a_in[ 9]}} & b_in[63:0];
assign pp10[63:0] = {64{a_in[10]}} & b_in[63:0];
assign pp11[63:0] = {64{a_in[11]}} & b_in[63:0];
assign pp12[63:0] = {64{a_in[12]}} & b_in[63:0];
assign pp13[63:0] = {64{a_in[13]}} & b_in[63:0];
assign pp14[63:0] = {64{a_in[14]}} & b_in[63:0];
assign pp15[63:0] = {64{a_in[15]}} & b_in[63:0];
assign pp16[63:0] = {64{a_in[16]}} & b_in[63:0];
assign pp17[63:0] = {64{a_in[17]}} & b_in[63:0];
assign pp18[63:0] = {64{a_in[18]}} & b_in[63:0];
assign pp19[63:0] = {64{a_in[19]}} & b_in[63:0];
assign pp20[63:0] = {64{a_in[20]}} & b_in[63:0];
assign pp21[63:0] = {64{a_in[21]}} & b_in[63:0];
assign pp22[63:0] = {64{a_in[22]}} & b_in[63:0];
assign pp23[63:0] = {64{a_in[23]}} & b_in[63:0];
assign pp24[63:0] = {64{a_in[24]}} & b_in[63:0];
assign pp25[63:0] = {64{a_in[25]}} & b_in[63:0];
assign pp26[63:0] = {64{a_in[26]}} & b_in[63:0];
assign pp27[63:0] = {64{a_in[27]}} & b_in[63:0];
assign pp28[63:0] = {64{a_in[28]}} & b_in[63:0];
assign pp29[63:0] = {64{a_in[29]}} & b_in[63:0];
assign pp30[63:0] = {64{a_in[30]}} & b_in[63:0];
assign pp31[63:0] = {64{a_in[31]}} & b_in[63:0];
assign pp32[63:0] = {64{a_in[32]}} & b_in[63:0];
assign pp33[63:0] = {64{a_in[33]}} & b_in[63:0];
assign pp34[63:0] = {64{a_in[34]}} & b_in[63:0];
assign pp35[63:0] = {64{a_in[35]}} & b_in[63:0];
assign pp36[63:0] = {64{a_in[36]}} & b_in[63:0];
assign pp37[63:0] = {64{a_in[37]}} & b_in[63:0];
assign pp38[63:0] = {64{a_in[38]}} & b_in[63:0];
assign pp39[63:0] = {64{a_in[39]}} & b_in[63:0];
assign pp40[63:0] = {64{a_in[40]}} & b_in[63:0];
assign pp41[63:0] = {64{a_in[41]}} & b_in[63:0];
assign pp42[63:0] = {64{a_in[42]}} & b_in[63:0];
assign pp43[63:0] = {64{a_in[43]}} & b_in[63:0];
assign pp44[63:0] = {64{a_in[44]}} & b_in[63:0];
assign pp45[63:0] = {64{a_in[45]}} & b_in[63:0];
assign pp46[63:0] = {64{a_in[46]}} & b_in[63:0];
assign pp47[63:0] = {64{a_in[47]}} & b_in[63:0];
assign pp48[63:0] = {64{a_in[48]}} & b_in[63:0];
assign pp49[63:0] = {64{a_in[49]}} & b_in[63:0];
assign pp50[63:0] = {64{a_in[50]}} & b_in[63:0];
assign pp51[63:0] = {64{a_in[51]}} & b_in[63:0];
assign pp52[63:0] = {64{a_in[52]}} & b_in[63:0];
assign pp53[63:0] = {64{a_in[53]}} & b_in[63:0];
assign pp54[63:0] = {64{a_in[54]}} & b_in[63:0];
assign pp55[63:0] = {64{a_in[55]}} & b_in[63:0];
assign pp56[63:0] = {64{a_in[56]}} & b_in[63:0];
assign pp57[63:0] = {64{a_in[57]}} & b_in[63:0];
assign pp58[63:0] = {64{a_in[58]}} & b_in[63:0];
assign pp59[63:0] = {64{a_in[59]}} & b_in[63:0];
assign pp60[63:0] = {64{a_in[60]}} & b_in[63:0];
assign pp61[63:0] = {64{a_in[61]}} & b_in[63:0];
assign pp62[63:0] = {64{a_in[62]}} & b_in[63:0];
assign pp63[63:0] = {64{a_in[63]}} & b_in[63:0];
assign rednl0_0[66:0] = { pp3[63:0], 3'b000} ^ {1'b0, pp2[63:0], 2'b00} ^ {2'b00, pp1[63:0], 1'b0} ^ {3'b000, pp0[63:0]};
assign rednl0_1[66:0] = { pp7[63:0], 3'b000} ^ {1'b0, pp6[63:0], 2'b00} ^ {2'b00, pp5[63:0], 1'b0} ^ {3'b000, pp4[63:0]};
assign rednl0_2[66:0] = {pp11[63:0], 3'b000} ^ {1'b0, pp10[63:0], 2'b00} ^ {2'b00, pp9[63:0], 1'b0} ^ {3'b000, pp8[63:0]};
assign rednl0_3[66:0] = {pp15[63:0], 3'b000} ^ {1'b0, pp14[63:0], 2'b00} ^ {2'b00, pp13[63:0], 1'b0} ^ {3'b000, pp12[63:0]};
assign rednl0_4[66:0] = {pp19[63:0], 3'b000} ^ {1'b0, pp18[63:0], 2'b00} ^ {2'b00, pp17[63:0], 1'b0} ^ {3'b000, pp16[63:0]};
assign rednl0_5[66:0] = {pp23[63:0], 3'b000} ^ {1'b0, pp22[63:0], 2'b00} ^ {2'b00, pp21[63:0], 1'b0} ^ {3'b000, pp20[63:0]};
assign rednl0_6[66:0] = {pp27[63:0], 3'b000} ^ {1'b0, pp26[63:0], 2'b00} ^ {2'b00, pp25[63:0], 1'b0} ^ {3'b000, pp24[63:0]};
assign rednl0_7[66:0] = {pp31[63:0], 3'b000} ^ {1'b0, pp30[63:0], 2'b00} ^ {2'b00, pp29[63:0], 1'b0} ^ {3'b000, pp28[63:0]};
assign rednl0_8[66:0] = {pp35[63:0], 3'b000} ^ {1'b0, pp34[63:0], 2'b00} ^ {2'b00, pp33[63:0], 1'b0} ^ {3'b000, pp32[63:0]};
assign rednl0_9[66:0] = {pp39[63:0], 3'b000} ^ {1'b0, pp38[63:0], 2'b00} ^ {2'b00, pp37[63:0], 1'b0} ^ {3'b000, pp36[63:0]};
assign rednl0_10[66:0] = {pp43[63:0], 3'b000} ^ {1'b0, pp42[63:0], 2'b00} ^ {2'b00, pp41[63:0], 1'b0} ^ {3'b000, pp40[63:0]};
assign rednl0_11[66:0] = {pp47[63:0], 3'b000} ^ {1'b0, pp46[63:0], 2'b00} ^ {2'b00, pp45[63:0], 1'b0} ^ {3'b000, pp44[63:0]};
assign rednl0_12[66:0] = {pp51[63:0], 3'b000} ^ {1'b0, pp50[63:0], 2'b00} ^ {2'b00, pp49[63:0], 1'b0} ^ {3'b000, pp48[63:0]};
assign rednl0_13[66:0] = {pp55[63:0], 3'b000} ^ {1'b0, pp54[63:0], 2'b00} ^ {2'b00, pp53[63:0], 1'b0} ^ {3'b000, pp52[63:0]};
assign rednl0_14[66:0] = {pp59[63:0], 3'b000} ^ {1'b0, pp58[63:0], 2'b00} ^ {2'b00, pp57[63:0], 1'b0} ^ {3'b000, pp56[63:0]};
assign rednl0_15[66:0] = {pp63[63:0], 3'b000} ^ {1'b0, pp62[63:0], 2'b00} ^ {2'b00, pp61[63:0], 1'b0} ^ {3'b000, pp60[63:0]};
assign rednl1_0[78:0] = { rednl0_3[66:0], 12'h000} ^ {4'h0, rednl0_2[66:0], 8'h00} ^ {8'h00, rednl0_1[66:0], 4'h0} ^ {12'h000, rednl0_0[66:0]};
assign rednl1_1[78:0] = { rednl0_7[66:0], 12'h000} ^ {4'h0, rednl0_6[66:0], 8'h00} ^ {8'h00, rednl0_5[66:0], 4'h0} ^ {12'h000, rednl0_4[66:0]};
assign rednl1_2[78:0] = {rednl0_11[66:0], 12'h000} ^ {4'h0, rednl0_10[66:0], 8'h00} ^ {8'h00, rednl0_9[66:0], 4'h0} ^ {12'h000, rednl0_8[66:0]};
assign rednl1_3[78:0] = {rednl0_15[66:0], 12'h000} ^ {4'h0, rednl0_14[66:0], 8'h00} ^ {8'h00, rednl0_13[66:0], 4'h0} ^ {12'h000, rednl0_12[66:0]};
assign p_out[15: 0] = rednl1_0[15: 0];
assign p_out[31: 16] = rednl1_1[15: 0] ^ rednl1_0[31:16];
assign p_out[47: 32] = rednl1_2[15: 0] ^ rednl1_1[31:16] ^ rednl1_0[47:32];
assign p_out[78: 48] = rednl1_3[30: 0] ^ rednl1_2[46:16] ^ rednl1_1[62:32] ^ rednl1_0[78:48];
assign p_out[94: 79] = rednl1_3[46:31] ^ rednl1_2[62:47] ^ rednl1_1[78:63];
assign p_out[110: 95] = rednl1_3[62:47] ^ rednl1_2[78:63];
assign p_out[127:111] = {1'b0, rednl1_3[78:63]};
always_ff @(posedge clk or posedge reset)
begin: u_pmullout_v2_q_127_0
if (reset == 1'b1)
pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'b0}};
`ifdef HERCULESAE_XPROP_FLOP
else if (reset == 1'b0 && ival_v1_q == 1'b1)
pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY p_out[127:0];
else if (reset == 1'b0 && ival_v1_q == 1'b0)
begin
end
else
pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY {128{1'bx}};
`else
else if (ival_v1_q == 1'b1)
pmullout_v2_q[127:0] <= `HERCULESAE_DFF_DELAY p_out[127:0];
`endif
end
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_sha1
(
input wire sha1h_v1_i,
input wire sha1su0_v1_i,
input wire sha1su1_v1_i,
input wire [31:0] sha1h_qn,
input wire [127:0] sha1su0_qd,
input wire [127:0] sha1su1_qd,
input wire [127:0] sha1su1_qn,
output wire [127:0] sha1_v1_o
);
wire [31:0] sha1h_v1;
wire [63:0] sha1su0_opa_v1;
wire [127:0] sha1su0_opb_v1;
wire [127:0] sha1su0_opc_v1;
wire [127:0] sha1su0_v1;
wire [127:0] sha1su1_v1;
wire [127:0] t;
assign sha1h_v1[31:0] = {sha1h_qn[1:0], sha1h_qn[31:2]};
assign sha1su0_opa_v1[63:0] = sha1su1_qn[63:0];
assign sha1su0_opb_v1[127:0] = sha1su1_qd[127:0];
assign sha1su0_opc_v1[127:0] = sha1su0_qd[127:0];
assign sha1su0_v1 [127:0] = sha1su0_opc_v1[127:0]
^ {sha1su0_opa_v1[63:0], sha1su0_opc_v1[127:64]}
^ sha1su0_opb_v1[127:0];
assign t[127:0] = sha1su1_qd[127:0] ^ {{32{1'b0}}, sha1su1_qn[127:32]};
assign sha1su1_v1[127:96] = {t[126:96], t[127]} ^ {t[29:0], t[31:30]};
assign sha1su1_v1[95:64] = {t[94:64], t[95]};
assign sha1su1_v1[63:32] = {t[62:32], t[63]};
assign sha1su1_v1[31:0] = {t[30:0], t[31]};
assign sha1_v1_o[127:0] = {128{sha1su0_v1_i}} & sha1su0_v1[127:0] |
{128{sha1su1_v1_i}} & sha1su1_v1[127:0] |
{128{sha1h_v1_i}} & {{96{1'b0}}, sha1h_v1[31:0]};
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_sha1cpm
(
input wire choose,
input wire parity,
input wire majority,
input wire cpm,
input wire [127:0] x,
input wire [31:0] y,
input wire [31:0] z,
input wire [31:0] t2,
output wire [31:0] fa1_s,
output wire [31:0] fa1_c,
output wire [127:0] newx,
output wire [31:0] newy
);
wire [32:0] fa0_c;
wire [31:0] fa0_s;
wire shacpm_nop;
wire [31:0] t1_nop;
wire [31:0] t1c;
wire [31:0] t1m;
wire [31:0] t1p;
wire [127:0] x1;
wire [127:0] x_nop;
wire [31:0] x_rol5_nop;
wire [31:0] y_nop;
wire [31:0] z_nop;
assign shacpm_nop = ~cpm;
assign t1c[31:0] = (x[63:32] & x[95:64]) | (~x[63:32] & x[127:96]);
assign t1p[31:0] = x[63:32] ^ x[95:64] ^ x[127:96];
assign t1m[31:0] = (x[63:32] & x[95:64])
| (x[63:32] & x[127:96])
| (x[95:64] & x[127:96]);
assign t1_nop[31:0] = ({32{choose}} & t1c[31:0])
| ({32{parity}} & t1p[31:0])
| ({32{majority}} & t1m[31:0]);
assign x_rol5_nop[31:0] = {32{~shacpm_nop}} & {x[26:0], x[31:27]};
assign y_nop[31:0] = {32{~shacpm_nop}} & y[31:0];
assign z_nop[31:0] = {32{~shacpm_nop}} & z[31:0];
assign fa0_s[31:0] = y_nop[31:0] ^ x_rol5_nop[31:0] ^ z_nop[31:0];
assign fa0_c[32:0] = {y_nop[31:0] & x_rol5_nop[31:0] | z_nop[31:0] & (y_nop[31:0] | x_rol5_nop[31:0]), 1'b0};
assign fa1_s[31:0] = fa0_s[31:0] ^ fa0_c[31:0] ^ t1_nop[31:0];
assign fa1_c[31:0] = {fa0_s[30:0] & fa0_c[30:0] | t1_nop[30:0] & (fa0_s[30:0] | fa0_c[30:0]), 1'b0};
assign x_nop[127:0] = {128{~shacpm_nop}} & x[127:0];
assign x1[127:64] = x_nop[127:64];
assign x1[63:32] = {x_nop[33:32], x_nop[63:34]};
assign x1[31:0] = x_nop[31:0];
assign newx[127:0] = {x1[95:0], t2[31:0]};
assign newy[31:0] = x1[127:96];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_sha256h32
(
input wire [127:0] x,
input wire [127:0] y,
input wire [31:0] z,
input wire [63:0] sumnr,
output wire [63:0] sum,
output wire [63:0] carry,
output wire [127:0] newx,
output wire [127:0] newy
);
wire [31:0] sigma0;
wire [31:0] sigma1;
wire [31:0] tchoose;
wire [31:0] tmajority;
wire [32:0] x_fa2_c;
wire [31:0] x_fa2_s;
wire [127:96] xprime;
wire [32:0] xy_fa0_c;
wire [31:0] xy_fa0_s;
wire [32:0] xy_fa1_c;
wire [31:0] xy_fa1_s;
wire [32:0] y_fa2_c;
wire [31:0] y_fa2_s;
wire [31:0] y_fa3_c;
wire [31:0] y_fa3_s;
wire [127:96] yprime;
assign tchoose[31:0] = (y[31:0] & y[63:32]) | (~y[31:0] & y[95:64]);
assign tmajority[31:0] = (x[31:0] & x[63:32]) | (x[31:0] & x[95:64]) | (x[63:32] & x[95:64]);
assign sigma0[31:0] = {x[1:0], x[31:2]}
^ {x[12:0], x[31:13]}
^ {x[21:0], x[31:22]};
assign sigma1[31:0] = {y[5:0], y[31:6]}
^ {y[10:0], y[31:11]}
^ {y[24:0], y[31:25]};
assign xy_fa0_s[31:0] = y[127:96] ^ z[31:0] ^ tchoose[31:0];
assign xy_fa0_c[32:0] = {y[127:96] & z[31:0] | tchoose[31:0] & (y[127:96] | z[31:0]), 1'b0};
assign xy_fa1_s[31:0] = xy_fa0_s[31:0] ^ xy_fa0_c[31:0] ^ sigma1[31:0];
assign xy_fa1_c[32:0] = {xy_fa0_s[31:0] & xy_fa0_c[31:0] | sigma1[31:0] & (xy_fa0_s[31:0] | xy_fa0_c[31:0]), 1'b0};
assign x_fa2_s[31:0] = xy_fa1_s[31:0] ^ xy_fa1_c[31:0] ^ x[127:96];
assign x_fa2_c[32:0] = {xy_fa1_s[31:0] & xy_fa1_c[31:0] | x[127:96] & (xy_fa1_s[31:0] | xy_fa1_c[31:0]), 1'b0};
assign y_fa2_s[31:0] = sigma0[31:0] ^ tmajority[31:0] ^ xy_fa1_c[31:0];
assign y_fa2_c[32:0] = {sigma0[31:0] & tmajority[31:0] | xy_fa1_c[31:0] & (sigma0[31:0] | tmajority[31:0]), 1'b0};
assign y_fa3_s[31:0] = y_fa2_s[31:0] ^ y_fa2_c[31:0] ^ xy_fa1_s[31:0];
assign y_fa3_c[31:0] = {y_fa2_s[30:0] & y_fa2_c[30:0] | xy_fa1_s[30:0] & (y_fa2_s[30:0] | y_fa2_c[30:0]), 1'b0};
assign sum[63:0] = {x_fa2_s[31:0], y_fa3_s[31:0]};
assign carry[63:0] = {x_fa2_c[31:0], y_fa3_c[31:0]};
assign xprime[127:96] = sumnr[63:32];
assign yprime[127:96] = sumnr[31:0];
assign newx[127:0] = {x[95:0], yprime[127:96]};
assign newy[127:0] = {y[95:0], xprime[127:96]};
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_sha256su0
(
input wire [127:0] qd,
input wire [31:0] qn,
input wire [31:0] sumd,
output wire [31:0] suma,
output wire [31:0] sumb,
output wire [127:0] d
);
wire d1_cout;
wire d2_cout;
wire d3_cout;
wire [127:0] t;
wire [127:0] t0;
assign t[127:0] = {qn[31:0], qd[127:32]};
assign t0[127:96] = {t[102:96], t[127:103]} ^ {t[113:96], t[127:114]} ^ {3'b000, t[127:99]};
assign t0[95:64] = {t[ 70:64], t[ 95: 71]} ^ {t[ 81:64], t[ 95: 82]} ^ {3'b000, t[ 95:67]};
assign t0[63:32] = {t[ 38:32], t[ 63: 39]} ^ {t[ 49:32], t[ 63: 50]} ^ {3'b000, t[ 63:35]};
assign t0[31:0] = {t[ 6: 0], t[ 31: 7]} ^ {t[ 17: 0], t[ 31: 18]} ^ {3'b000, t[ 31: 3]};
assign {d3_cout, d[127:96]} = t0[127:96] + qd[127:96] + {{31{1'b0}}, 1'b0};
assign {d2_cout, d[95:64]} = t0[95:64] + qd[95:64] + {{31{1'b0}}, 1'b0};
assign {d1_cout, d[63:32]} = t0[63:32] + qd[63:32] + {{31{1'b0}}, 1'b0};
assign suma[31:0] = t0[31:0];
assign sumb[31:0] = qd[31:0];
assign d[31:0] = sumd[31:0];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2015-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//-----------------------------------------------------------------------------
// SystemVerilog (IEEE Std 1800-2012)
//-----------------------------------------------------------------------------
`include "herculesae_header.sv"
module herculesae_vx_sha256su1
(
input wire sha256su1_x_op,
input wire sha256su1_y_op,
input wire sha256su1_z_op,
input wire [63:0] x,
input wire [63:0] y,
input wire [63:0] z,
input wire [63:0] sumnr,
output wire [63:0] sum_3to2,
output wire [63:0] carry_3to2,
output wire [63:0] newx
);
wire [63:0] carry;
wire [63:0] sum;
wire [63:0] x_nop;
wire [63:0] y_nop;
wire [63:0] z_nop;
wire [63:0] z_rot;
wire [63:0] zror17;
wire [63:0] zror19;
wire [63:0] zshr10;
assign x_nop[63:0] = x[63:0] & {64{sha256su1_x_op}};
assign y_nop[63:0] = y[63:0] & {64{sha256su1_y_op}};
assign z_nop[63:0] = z[63:0] & {64{sha256su1_z_op}};
assign zror17[63:0] = {z_nop[48:32], z_nop[63:49],
z_nop[16:0], z_nop[31:17]};
assign zror19[63:0] = {z_nop[50:32], z_nop[63:51],
z_nop[18:0], z_nop[31:19]};
assign zshr10[63:0] = {10'b00_0000_0000, z_nop[63:42],
10'b00_0000_0000, z_nop[31:10]};
assign z_rot[63:0] = zror17[63:0] ^ zror19[63:0] ^ zshr10[63:0];
assign sum[63:0] = (x_nop[63:0] ^ y_nop[63:0]) ^ z_rot[63:0];
assign carry[63:32] = {(x_nop[62:32] & y_nop[62:32])
| (y_nop[62:32] & z_rot[62:32])
| (x_nop[62:32] & z_rot[62:32]), 1'b0};
assign carry[31:0] = {(x_nop[30:0] & y_nop[30:0])
| (y_nop[30:0] & z_rot[30:0])
| (x_nop[30:0] & z_rot[30:0]), 1'b0};
assign sum_3to2[63:0] = sum[63:0];
assign carry_3to2[63:0] = carry[63:0];
assign newx[63:0] = sumnr[63:0];
endmodule
`define HERCULESAE_UNDEFINE
`include "herculesae_header.sv"
`undef HERCULESAE_UNDEFINE

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#-----------------------------------------------------------------------------
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from ARM Limited or its affiliates.
#
# (C) COPYRIGHT 2013-2020 ARM Limited or its affiliates.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from ARM Limited or its affiliates.
#
# Release Information : HERCULESAE-MP106-r0p1-00eac0
#
#-----------------------------------------------------------------------------
# Makefile include file for AArch32 crypto. This must be included from the
# top-level Makefile; it is not a standalone Makefile.
#-----------------------------------------------------------------------------
# Note these variables must only be used in places where Make reads their
# immediate values rather than their deferred values. This is because all
# the include files use the same variables and the deferred evaluation will
# yeild the last values set by the last include file. They can be used in the
# target and prerequisite sections of rule definitions, which are evaluated
# immediately, but not in the recipe, where evaluation is deferred.
srcdir := aarch32/crypto
common_srcdir := common/crypto
libdir := common/shared
dstdir := aarch32/crypto
target := $(dstdir)/crypto.elf
csrcs := $(wildcard $(common_srcdir)/*.c)
asmsrcs := $(wildcard $(srcdir)/*.s)
libsrcs := $(wildcard $(libdir)/*.c)
cobjs := $(patsubst $(common_srcdir)/%.c,$(dstdir)/%.o,$(csrcs)) \
$(patsubst $(libdir)/%.c,$(dstdir)/%.o,$(libsrcs))
asmobjs := $(patsubst %.s,%.o,$(asmsrcs))
# Find common C files (the source files are not in the build target directory)
vpath %.c $(common_srcdir) $(libdir)
# Change the CPU target to include crypto for all files that need compiling
$(asmobjs): ARCH = armv8-a+crypto
$(asmobjs): %.o: %.s
@echo " [ASM ] $<"
@$(ASM32) $(ASM_OPTS_AARCH32) $< -o $@
$(cobjs): $(dstdir)/%.o: %.c
@echo " [CC $(CC32) ] $<"
ifeq ($(strip $(GCC)), yes)
@$(CC32) $(subst -funroll-loops ,,$(CC_OPTS_AARCH32)) -O3 -mword-relocations -fno-inline-functions -fno-inline $(foreach inc,$(^D),-I$(inc)) -I$(common_shared) $< -o $@
else
@$(CC32) -mfpu=none $(subst -funroll-loops ,,$(CC_OPTS_AARCH32)) -O3 -fno-inline-functions -fno-inline $(foreach inc,$(^D),-I$(inc)) -I$(common_shared) $< -o $@
endif
# Link. For C-based tests this is done through GCC to make sure that all
# standard libraries are set up correctly.
$(target): $(asmobjs) $(cobjs) $(aarch32_bootobj) $(aarch32_c_bootobj)
@echo " [LINK] $<"
ifeq ($(strip $(GCC)), yes)
@$(CC32) $(LINK_OPTS_CSRC_AARCH32) $^ -o $@
else
@$(LD32) $(LINK_OPTS_CSRC_AARCH32) $^ -o $@
endif
# ex: syntax=make:

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2013-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//------------------------------------------------------------------------------
// Description:
//
// This file defines assembler functions that are called from C in the main
// crypto test
//------------------------------------------------------------------------------
.section testcode, "ax", %progbits
//------------------------------------------------------------------------------
// Macros
//------------------------------------------------------------------------------
.macro aes128_key_expand_step rcon
VTBL.8 d26, {d22, d23}, d28
VTBL.8 d27, {d22, d23}, d29
AESE.8 q13, q12
VMOV.I32 q15, #\rcon
VEOR q13, q13, q15
VEXT.8 q15, q12, q11, #12
VEOR q11, q11, q15
VEXT.8 q15, q12, q15, #12
VEOR q11, q11, q15
VEXT.8 q15, q12, q15, #12
VEOR q11, q11, q15
VEOR q11, q11, q13
.endm
//------------------------------------------------------------------------------
// Function: aes128_key_expand
//------------------------------------------------------------------------------
.global aes128_key_expand
.type aes128_key_expand, %function
aes128_key_expand:
// C arguments:
// r0: const unsigned char *key_in
// r1: unsigned char *key_out
// Return: void
VLD1.8 {d22-d23}, [r0]
MOV r2, #0
VDUP.8 q12, r2
LDR r2, =0x0c0f0e0d
VDUP.32 q14, r2
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x01
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x02
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x04
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x08
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x10
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x20
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x40
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x80
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x1B
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
aes128_key_expand_step 0x36
VST1.8 {d22}, [r1]
ADD r1, r1, #8
VST1.8 {d23}, [r1]
ADD r1, r1, #8
BX lr
//------------------------------------------------------------------------------
// Function: aes128_ecb_encrypt
//------------------------------------------------------------------------------
.global aes128_ecb_encrypt
.type aes128_ecb_encrypt, %function
aes128_ecb_encrypt:
// C arguments:
// r0: const unsigned char *key
// r1: const unsigned char *in_data
// r2: unsigned char *out_data
// r3: unsigned int size
// Return: void
VLD1.8 {d10-d13}, [r0]
ADD r0, r0, #32
VLD1.8 {d14-d17}, [r0]
ADD r0, r0, #32
VLD1.8 {d18-d21}, [r0]
ADD r0, r0, #32
VLD1.8 {d22-d25}, [r0]
ADD r0, r0, #32
VLD1.8 {d26-d29}, [r0]
ADD r0, r0, #32
VLD1.8 {d30-d31}, [r0]
aes128_ecb_enc_loop:
// Load data
VLD1.8 {d0-d3}, [r1]
ADD r1, r1, #32
// Round 1
AESE.8 q0, q5
AESMC.8 q0, q0
AESE.8 q1, q5
AESMC.8 q1, q1
// Round 2
AESE.8 q0, q6
AESMC.8 q0, q0
AESE.8 q1, q6
AESMC.8 q1, q1
// Round 3
AESE.8 q0, q7
AESMC.8 q0, q0
AESE.8 q1, q7
AESMC.8 q1, q1
// Round 4
AESE.8 q0, q8
AESMC.8 q0, q0
AESE.8 q1, q8
AESMC.8 q1, q1
// Round 5
AESE.8 q0, q9
AESMC.8 q0, q0
AESE.8 q1, q9
AESMC.8 q1, q1
// Round 6
AESE.8 q0, q10
AESMC.8 q0, q0
AESE.8 q1, q10
AESMC.8 q1, q1
// Round 7
AESE.8 q0, q11
AESMC.8 q0, q0
AESE.8 q1, q11
AESMC.8 q1, q1
// Round 8
AESE.8 q0, q12
AESMC.8 q0, q0
AESE.8 q1, q12
AESMC.8 q1, q1
// Round 9
AESE.8 q0, q13
AESMC.8 q0, q0
AESE.8 q1, q13
AESMC.8 q1, q1
// Round 10
AESE.8 q0, q14
PLD [r1, #64]
AESE.8 q1, q14
VEOR q0, q0, q15
SUBS r3, r3, #16
VST1.8 {d0-d1}, [r2]
ADD r2, r2, #16
BEQ aes128_ecb_enc_exit
VEOR q1, q1, q15
SUBS r3, r3, #16
VST1.8 {d2-d3}, [r2]
ADD r2, r2, #16
BGT aes128_ecb_enc_loop
aes128_ecb_enc_exit:
BX lr

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#-------------------------------------------------------------------------------
# The confidential and proprietary information contained in this file may
# only be used by a person authorised under and to the extent permitted
# by a subsisting licensing agreement from ARM Limited or its affiliates.
#
# (C) COPYRIGHT 2013-2020 ARM Limited or its affiliates.
# ALL RIGHTS RESERVED
#
# This entire notice must be reproduced on all copies of this file
# and copies of this file may only be made by a person if such person is
# permitted to do so under the terms of a subsisting license agreement
# from ARM Limited or its affiliates.
#
# Release Information : HERCULESAE-MP106-r0p1-00eac0
#
#-------------------------------------------------------------------------------
# Makefile include file for AArch64 crypto. This must be included from the
# top-level Makefile; it is not a standalone Makefile.
#-------------------------------------------------------------------------------
# Note these variables must only be used in places where Make reads their
# immediate values rather than their deferred values. This is because all
# the include files use the same variables and the deferred evaluation will
# yield the last values set by the last include file. They can be used in the
# target and prerequisite sections of rule definitions, which are evaluated
# immediately, but not in the recipe, where evaluation is deferred.
srcdir := aarch64/crypto
common_srcdir := common/crypto
libdir := common/shared
dstdir := aarch64/crypto
target := $(dstdir)/crypto.elf
asmsrcs := $(wildcard $(srcdir)/*.s)
csrcs := $(wildcard $(common_srcdir)/*.c)
libsrcs := $(wildcard $(libdir)/*.c)
asmobjs := $(patsubst %.s,%.o,$(asmsrcs))
cobjs := $(patsubst $(common_srcdir)/%.c,$(dstdir)/%.o,$(csrcs)) \
$(patsubst $(libdir)/%.c,$(dstdir)/%.o,$(libsrcs))
# Find common C files (the source files are not in the build target directory)
vpath %.c $(common_srcdir) $(libdir)
# Change the CPU target to include crypto for all files that need compiling
$(cobjs) $(asmobjs): ARCH = armv8-a+crypto
$(asmobjs): %.o: %.s
@echo " [ASM ] $<"
@$(ASM64) $(ASM_OPTS_AARCH64) $< -o $@
$(cobjs): $(dstdir)/%.o: %.c
@echo " [CC ] $<"
@$(CC64) $(CC_OPTS_AARCH64) -I$(common_shared) $< -o $@
# Link. For C-based tests this is done through GCC to make sure that all
# standard libraries are set up correctly.
$(target): $(asmobjs) $(cobjs) $(aarch64_bootobj)
@echo " [LINK] $<"
ifeq ($(strip $(GCC)), yes)
@$(CC64) $(LINK_OPTS_CSRC_AARCH64) $^ -o $@
else
@$(LD64) $(LINK_OPTS_CSRC_AARCH64) $^ -o $@
endif
# ex: syntax=make:

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//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2012-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//------------------------------------------------------------------------------
// Description:
//
// This file defines assembler functions that are called from C in the main
// crypto test
//------------------------------------------------------------------------------
.section .text, "ax", %progbits
//------------------------------------------------------------------------------
// Macros
//------------------------------------------------------------------------------
.macro aes128_key_expand_step rcon
TBL v18.16B, {v16.16B}, v19.16B
AESE v18.16B, v17.16B
MOVI v20.4S, #\rcon
EOR v18.16B, v18.16B, v20.16B
EXT v20.16B, v17.16B, v16.16B, #12
EOR v16.16B, v16.16B, v20.16B
EXT v20.16B, v17.16B, v20.16B, #12
EOR v16.16B, v16.16B, v20.16B
EXT v20.16B, v17.16B, v20.16B, #12
EOR v16.16B, v16.16B, v20.16B
EOR v16.16B, v16.16B, v18.16B
.endm
//------------------------------------------------------------------------------
// Function: aes128_key_expand
//------------------------------------------------------------------------------
.global aes128_key_expand
.type aes128_key_expand, %function
aes128_key_expand:
// C arguments:
// r0: const unsigned char *key_in
// r1: unsigned char *key_out
// Return: void
LD1 {v16.16B}, [x0]
MOVZ w2, #0x0e0d
DUP v17.16B, wzr
movk w2, #0xc0f, lsl #16
DUP v19.4S, w2
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x01
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x02
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x04
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x08
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x10
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x20
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x40
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x80
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x1B
ST1 {v16.16B}, [x1], #16
aes128_key_expand_step 0x36
ST1 {v16.16B}, [x1]
RET
//------------------------------------------------------------------------------
// Function: aes128_ecb_encrypt
//------------------------------------------------------------------------------
.global aes128_ecb_encrypt
.type aes128_ecb_encrypt, %function
aes128_ecb_encrypt:
// C arguments:
// r0: const unsigned char *key
// r1: const unsigned char *in_data
// r2: unsigned char *out_data
// r3: unsigned int size
// Return: void
LD1 {v16.16B-v19.16B}, [x0], #64
LD1 {v20.16B-v23.16B}, [x0], #64
LD1 {v24.16B-v26.16B}, [x0]
aes128_ecb_enc_loop:
// Load data
LD1 {v0.16B-v1.16B}, [x1], #32
// Round 1
AESE v0.16B, v16.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v16.16B
AESMC v1.16B, v1.16B
// Round 2
AESE v0.16B, v17.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v17.16B
AESMC v1.16B, v1.16B
// Round 3
AESE v0.16B, v18.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v18.16B
AESMC v1.16B, v1.16B
// Round 4
AESE v0.16B, v19.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v19.16B
AESMC v1.16B, v1.16B
// Round 5
AESE v0.16B, v20.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v20.16B
AESMC v1.16B, v1.16B
// Round 6
AESE v0.16B, v21.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v21.16B
AESMC v1.16B, v1.16B
// Round 7
AESE v0.16B, v22.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v22.16B
AESMC v1.16B, v1.16B
// Round 8
AESE v0.16B, v23.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v23.16B
AESMC v1.16B, v1.16B
// Round 9
AESE v0.16B, v24.16B
AESMC v0.16B, v0.16B
AESE v1.16B, v24.16B
AESMC v1.16B, v1.16B
// Round 10
AESE v0.16B, v25.16B
PRFM PLDL1KEEP, [x1, #64]
AESE v1.16B, v25.16B
EOR v0.16B, v0.16B, v26.16B
SUBS x3, x3, #16
ST1 {v0.16B}, [x2], #16
B.EQ aes128_ecb_enc_exit
EOR v1.16B, v1.16B, v26.16B
SUBS x3, x3, #16
ST1 {v1.16B}, [x2], #16
B.GT aes128_ecb_enc_loop
aes128_ecb_enc_exit:
RET

1586
Security Algo Accelerator/logical/testbench/execution_tb/tests/common/crypto/aesdata.c Normal file
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72
Security Algo Accelerator/logical/testbench/execution_tb/tests/common/crypto/crypto_aes.c Normal file
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@ -0,0 +1,72 @@
//-----------------------------------------------------------------------------
// The confidential and proprietary information contained in this file may
// only be used by a person authorised under and to the extent permitted
// by a subsisting licensing agreement from ARM Limited or its affiliates.
//
// (C) COPYRIGHT 2012-2020 ARM Limited or its affiliates.
// ALL RIGHTS RESERVED
//
// This entire notice must be reproduced on all copies of this file
// and copies of this file may only be made by a person if such person is
// permitted to do so under the terms of a subsisting license agreement
// from ARM Limited or its affiliates.
//
// Release Information : HERCULESAE-MP106-r0p1-00eac0
//
//------------------------------------------------------------------------------
#include <stdio.h>
#include <stdlib.h>
#include <stdint.h>
#include <string.h>
#include "benchmark.h"
static const uint8_t key[] = {0x00, 0x11, 0x22, 0x33, 0x44, 0x55, 0x66, 0x77,
0x88, 0x99, 0xaa, 0xbb, 0xcc, 0xdd, 0xee, 0xff};
extern const uint8_t aes128_ecb_encrypt_input[][4096];
extern const uint8_t aes128_ecb_encrypt_ref_output[][4096];
extern uint8_t aes128_ecb_encrypt_output[][4096];
// Function prototypes for asm functions
extern void aes128_key_expand(const unsigned char *key_in, unsigned char *key_out);
extern void aes128_ecb_encrypt(const unsigned char *key, const unsigned char *in_data, unsigned char *out_data, unsigned int size);
extern uint32_t have_crypto;
int main()
{
int bs;
int i;
int fail = 0;
uint8_t kv[176];
started();
if ( !have_crypto ) {
printf("Cryptographic extension not available on this PE.\n");
exit(144); // something gross
}
aes128_key_expand(key, kv);
for (i = 0, bs = 16; bs <= 4096; i++, bs*=2) {
uint32_t cmpres;
aes128_ecb_encrypt(kv, aes128_ecb_encrypt_input[i], aes128_ecb_encrypt_output[i], bs);
cmpres = (memcmp(aes128_ecb_encrypt_output[i], aes128_ecb_encrypt_ref_output[i], bs) != 0);
aes128_ecb_encrypt(kv, aes128_ecb_encrypt_input[i], aes128_ecb_encrypt_output[i], bs);
cmpres |= (memcmp(aes128_ecb_encrypt_output[i], aes128_ecb_encrypt_ref_output[i], bs) != 0);
if (cmpres != 0)
fail = 1;
}
return fail;
}