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Raziel K. Crowe b48c9cc972 Second batch of augmented kernel 
Github is super gay like T3Q.
2022-03-15 21:06:03 +05:00
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Adder.v QortalOS Titan 5.60.12 2022-03-05 21:17:59 +05:00
alignment.c Second batch of augmented kernel 2022-03-15 21:06:03 +05:00
ALU.v QortalOS Titan 5.60.12 2022-03-05 21:17:59 +05:00
ARM_TB.v QortalOS Titan 5.60.12 2022-03-05 21:17:59 +05:00
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Condition_Check.v QortalOS Titan 5.60.12 2022-03-05 21:17:59 +05:00
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fault.c Second batch of augmented kernel 2022-03-15 21:06:03 +05:00
fault.h Second batch of augmented kernel 2022-03-15 21:06:03 +05:00
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ioremap.c Second batch of augmented kernel 2022-03-15 21:06:03 +05:00
kasan_init.c Second batch of augmented kernel 2022-03-15 21:06:03 +05:00
Kconfig Second batch of augmented kernel 2022-03-15 21:06:03 +05:00
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pageattr.c Second batch of augmented kernel 2022-03-15 21:06:03 +05:00
PC.v QortalOS Titan 5.60.12 2022-03-05 21:17:59 +05:00
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README.md QortalOS Titan 5.60.12 2022-03-05 21:17:59 +05:00
Register_File.v QortalOS Titan 5.60.12 2022-03-05 21:17:59 +05:00
settings.h QortalOS Titan 5.60.12 2022-03-05 21:17:59 +05:00
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README.md

ARM-Processor

A pipelined implementation of ARM processor

Processor Specifications

This CPU has a 32-bit data bus and a 32-bit address bus.

All of the instructions are 32-bit.

Instructions:

Instruction Mnemonic Definition Bits 27:26 Bits 24:21
MOV Move 00 1101
MVN Move NOT 00 1111
ADD Add 00 0100
ADC Add with Carry 00 0101
SUB Subtract 00 0010
SBC Subtract with Carry 00 0110
AND Logical AND 00 0000
ORR Logical OR 00 1100
EOR Exclusive OR 00 0001
CMP Compare 00 1010
TST Test 00 1000
LDR Load Register 01 0100
STR Store Register 01 0100
B Branch 10 XXXX

Developers