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46 lines
1.1 KiB
Verilog
46 lines
1.1 KiB
Verilog
`include "settings.h"
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module EXE_Reg
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(
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input clk,
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input rst,
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input [`WORD_WIDTH-1:0] pc_in,
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input [`WORD_WIDTH-1:0] instruction_in,
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input [`REG_FILE_DEPTH-1:0] dst_in,
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input mem_read_in, mem_write_in, WB_en_in,
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input [`WORD_WIDTH-1:0] val_Rm_in,
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input [`WORD_WIDTH-1:0] ALU_res_in,
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output reg [`REG_FILE_DEPTH-1:0] dst_out,
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output reg [`WORD_WIDTH-1:0] ALU_res_out,
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output reg [`WORD_WIDTH-1:0] val_Rm_out,
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output reg mem_read_out, mem_write_out, WB_en_out,
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output reg [`WORD_WIDTH-1:0] pc,
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output reg [`WORD_WIDTH-1:0] instruction
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);
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always @(posedge clk, posedge rst) begin
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if(rst) begin
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pc <= 0;
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instruction <= 0;
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dst_out <= 0;
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ALU_res_out <= 0;
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val_Rm_out <= 0;
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mem_read_out <= 0;
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mem_write_out <= 0;
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WB_en_out <= 0;
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end
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else begin
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pc <= pc_in;
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instruction <= instruction_in;
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dst_out <= dst_in;
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ALU_res_out <= ALU_res_in;
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val_Rm_out <= val_Rm_in;
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mem_read_out <= mem_read_in;
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mem_write_out <= mem_write_in;
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WB_en_out <= WB_en_in;
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end
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end
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endmodule
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