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32 lines
1.5 KiB
Markdown
32 lines
1.5 KiB
Markdown
# ARM-Processor
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A pipelined implementation of ARM processor
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## Processor Specifications
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This CPU has a `32-bit` data bus and a `32-bit` address bus.
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All of the instructions are 32-bit.
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Instructions:
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| Instruction Mnemonic | Definition | Bits 27:26 | Bits 24:21 |
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|----------------------|---------------------|------------|------------|
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| MOV | Move | 00 | 1101 |
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| MVN | Move NOT | 00 | 1111 |
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| ADD | Add | 00 | 0100 |
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| ADC | Add with Carry | 00 | 0101 |
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| SUB | Subtract | 00 | 0010 |
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| SBC | Subtract with Carry | 00 | 0110 |
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| AND | Logical AND | 00 | 0000 |
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| ORR | Logical OR | 00 | 1100 |
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| EOR | Exclusive OR | 00 | 0001 |
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| CMP | Compare | 00 | 1010 |
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| TST | Test | 00 | 1000 |
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| LDR | Load Register | 01 | 0100 |
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| STR | Store Register | 01 | 0100 |
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| B | Branch | 10 | XXXX |
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## Developers
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* [**Mobina Shahbandeh**](https://github.com/mobinashb)
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* [**Ghazal Kalhor**](https://github.com/kalhorghazal)
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* [**Omid Bodaghi**](https://github.com/omigo2000)
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